summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAli Saidi <saidi@eecs.umich.edu>2008-02-14 16:13:50 -0500
committerAli Saidi <saidi@eecs.umich.edu>2008-02-14 16:13:50 -0500
commitfc38e9c630e62c97aa633c32933d43d027211989 (patch)
treeacc31cdd95dbeeb49c5d309216101e023dab52f9
parenta33a3f7c552919003950e8171f02634f7ae62f27 (diff)
downloadgem5-fc38e9c630e62c97aa633c32933d43d027211989.tar.xz
Configs: Change Simulation.py to return a subclass of the CPU models rather than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency.
--HG-- extra : convert_revision : f972207c616590a60a6e103daa5de469cf124b44
-rw-r--r--configs/common/Simulation.py10
1 files changed, 5 insertions, 5 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 1ff36c5d0..cea391c5d 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -37,14 +37,14 @@ def setCPUClass(options):
atomic = False
if options.timing:
- TmpClass = TimingSimpleCPU
+ class TmpClass(TimingSimpleCPU): pass
elif options.detailed:
if not options.caches:
print "O3 CPU must be used with caches"
sys.exit(1)
- TmpClass = DerivO3CPU
+ class TmpClass(DerivO3CPU): pass
else:
- TmpClass = AtomicSimpleCPU
+ class TmpClass(AtomicSimpleCPU): pass
atomic = True
CPUClass = None
@@ -53,7 +53,7 @@ def setCPUClass(options):
if not atomic:
if options.checkpoint_restore:
CPUClass = TmpClass
- TmpClass = AtomicSimpleCPU
+ class TmpClass(AtomicSimpleCPU): pass
else:
test_mem_mode = 'timing'