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author | Nathan Binkert <binkertn@umich.edu> | 2003-12-08 13:15:18 -0500 |
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committer | Nathan Binkert <binkertn@umich.edu> | 2003-12-08 13:15:18 -0500 |
commit | 0ff2457bfaa223c70d431d100c5b5a92540ff6e2 (patch) | |
tree | 1f2e356e9b17f5a1dd582c5fc233f4959327debb | |
parent | b6c77fe6f8fbd6f38718bed48e731145f763888c (diff) | |
download | gem5-0ff2457bfaa223c70d431d100c5b5a92540ff6e2.tar.xz |
move setStatus into the .cc file
--HG--
extra : convert_revision : 9ccf885274d72ea3151a0db76b580dd51763edab
-rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 57 | ||||
-rw-r--r-- | cpu/simple_cpu/simple_cpu.hh | 56 |
2 files changed, 58 insertions, 55 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 476f28ea0..4b9a7c6bd 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -212,6 +212,63 @@ SimpleCPU::execCtxStatusChg(int thread_num) { setStatus(Idle); } +void +SimpleCPU::setStatus(Status new_status) +{ + Status old_status = status(); + + // We should never even get here if the CPU has been switched out. + assert(old_status != SwitchedOut); + + _status = new_status; + + switch (status()) { + case IcacheMissStall: + assert(old_status == Running); + lastIcacheStall = curTick; + if (tickEvent.scheduled()) + tickEvent.squash(); + break; + + case IcacheMissComplete: + assert(old_status == IcacheMissStall); + if (tickEvent.squashed()) + tickEvent.reschedule(curTick + 1); + else if (!tickEvent.scheduled()) + tickEvent.schedule(curTick + 1); + break; + + case DcacheMissStall: + assert(old_status == Running); + lastDcacheStall = curTick; + if (tickEvent.scheduled()) + tickEvent.squash(); + break; + + case Idle: + assert(old_status == Running); + idleFraction++; + if (tickEvent.scheduled()) + tickEvent.squash(); + break; + + case Running: + assert(old_status == Idle || + old_status == DcacheMissStall || + old_status == IcacheMissComplete); + if (old_status == Idle && curTick != 0) + idleFraction--; + + if (tickEvent.squashed()) + tickEvent.reschedule(curTick + 1); + else if (!tickEvent.scheduled()) + tickEvent.schedule(curTick + 1); + break; + + default: + panic("can't get here"); + } +} void SimpleCPU::regStats() diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index b0189349f..e497559ce 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -174,61 +174,7 @@ class SimpleCPU : public BaseCPU virtual void execCtxStatusChg(int thread_num); - void setStatus(Status new_status) { - Status old_status = status(); - - // We should never even get here if the CPU has been switched out. - assert(old_status != SwitchedOut); - - _status = new_status; - - switch (status()) { - case IcacheMissStall: - assert(old_status == Running); - lastIcacheStall = curTick; - if (tickEvent.scheduled()) - tickEvent.squash(); - break; - - case IcacheMissComplete: - assert(old_status == IcacheMissStall); - if (tickEvent.squashed()) - tickEvent.reschedule(curTick + 1); - else if (!tickEvent.scheduled()) - tickEvent.schedule(curTick + 1); - break; - - case DcacheMissStall: - assert(old_status == Running); - lastDcacheStall = curTick; - if (tickEvent.scheduled()) - tickEvent.squash(); - break; - - case Idle: - assert(old_status == Running); - idleFraction++; - if (tickEvent.scheduled()) - tickEvent.squash(); - break; - - case Running: - assert(old_status == Idle || - old_status == DcacheMissStall || - old_status == IcacheMissComplete); - if (old_status == Idle && curTick != 0) - idleFraction--; - - if (tickEvent.squashed()) - tickEvent.reschedule(curTick + 1); - else if (!tickEvent.scheduled()) - tickEvent.schedule(curTick + 1); - break; - - default: - panic("can't get here"); - } - } + void setStatus(Status new_status); // statistics virtual void regStats(); |