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authorGabe Black <gblack@eecs.umich.edu>2009-02-25 10:16:04 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-25 10:16:04 -0800
commit15940d06b5f6aabbe917a2a8c4cc4bb1cab991e2 (patch)
tree1d03fcd57fea0d42cf4f718da19fba69d2d15eeb
parent1b336a8fe713dad2e77c5f973d9eb2f5fbcfb585 (diff)
downloadgem5-15940d06b5f6aabbe917a2a8c4cc4bb1cab991e2.tar.xz
SPARC: Adjust a few instructions to not write registers in initiateAcc.
-rw-r--r--src/arch/sparc/isa/decoder.isa18
-rw-r--r--src/arch/sparc/isa/formats/mem/basicmem.isa10
-rw-r--r--src/arch/sparc/isa/formats/mem/util.isa14
3 files changed, 27 insertions, 15 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index c35b231ff..e34ca033f 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1231,16 +1231,14 @@ decode OP default Unknown::unknown()
0x23: Load::lddf({{Frd.udw = Mem.udw;}});
0x24: Store::stf({{Mem.uw = Frds.uw;}});
0x25: decode RD {
- 0x0: Store::stfsr({{fault = checkFpEnableFault(xc);
- if (fault)
- return fault;
- Mem.uw = Fsr<31:0>;
- Fsr = insertBits(Fsr,16,14,0);}});
- 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc);
- if (fault)
- return fault;
- Mem.udw = Fsr;
- Fsr = insertBits(Fsr,16,14,0);}});
+ 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc);
+ if (fault)
+ return fault;
+ Mem.uw = Fsr<31:0>;}});
+ 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc);
+ if (fault)
+ return fault;
+ Mem.udw = Fsr;}});
default: FailUnimpl::stfsrOther();
}
0x26: stqf({{fault = new FpDisabled;}});
diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index e3c043cf3..c7bb3e435 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -108,6 +108,16 @@ def format Store(code, *opt_flags) {{
StoreFuncs, '', name, Name, 0, opt_flags)
}};
+def format StoreFsr(code, *opt_flags) {{
+ code = filterDoubles(code)
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doMemFormat(code,
+ StoreFuncs, '', name, Name, 0, opt_flags,
+ 'Fsr = insertBits(Fsr,16,14,0);')
+}};
+
def format TwinLoad(code, *opt_flags) {{
(header_output,
decoder_output,
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index f2a2327ee..31efb9cf6 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -264,11 +264,6 @@ def template StoreInitiateAcc {{
fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
- if(fault == NoFault)
- {
- //Write the resulting state to the execution context
- %(op_wb)s;
- }
return fault;
}
}};
@@ -277,6 +272,15 @@ def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
Trace::InstRecord * traceData) const
{
+ Fault fault = NoFault;
+ %(op_decl)s;
+
+ %(op_rd)s;
+ %(postacc_code)s;
+ if (fault == NoFault)
+ {
+ %(op_wb)s;
+ }
return NoFault;
}
}};