Merge stever@zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5

--HG--
extra : convert_revision : 25f6c41b709b4dabe1a2e0a180508db05aa4263f

3 files changed, 29 insertions, 16 deletions

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 3a0c1bffe..89ec05c0e 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2388,27 +2388,39 @@ decode OPCODE default Unknown::unknown() {
 	0x1e: hw_rei({{ xc->hwrei(); }});
 
 	// M5 special opcodes use the reserved 0x01 opcode space
-	0x01: decode M5FUNC{
+	0x01: decode M5FUNC {
 	    0x00: arm({{
-		Annotate::ARM(xc);
-		xc->kernelStats.arm();
+		if (!xc->misspeculating()) {
+		    Annotate::ARM(xc);
+		    xc->kernelStats.arm();
+		}
 	    }});
 	    0x01: quiesce({{
-		Annotate::QUIESCE(xc);
-		xc->setStatus(ExecContext::Suspended);
-		xc->kernelStats.quiesce();
+		if (!xc->misspeculating()) {
+		    Annotate::QUIESCE(xc);
+		    xc->setStatus(ExecContext::Suspended);
+		    xc->kernelStats.quiesce();
+		}
 	    }});
 	    0x10: ivlb({{
-		Annotate::BeginInterval(xc);
-		xc->kernelStats.ivlb();
+		if (!xc->misspeculating()) {
+		    Annotate::BeginInterval(xc);
+		    xc->kernelStats.ivlb();
+		}
+	    }}, No_OpClass);
+	    0x11: ivle({{
+		if (!xc->misspeculating())
+		    Annotate::EndInterval(xc);
 	    }}, No_OpClass);
-	    0x11: ivle({{ Annotate::EndInterval(xc); }}, No_OpClass);
 	    0x20: m5exit({{
 		if (!xc->misspeculating())
 		    m5_exit();
 	    }}, No_OpClass);
             0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
-            0x40: resetstats({{ Statistics::reset(); }});
+            0x40: resetstats({{
+		if (!xc->misspeculating())
+		    Statistics::reset();
+	    }});
 	}
     }
 
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index d3d9bc2ca..3d0818672 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -261,7 +261,7 @@ SimpleCPU::serialize()
     for (int i = 0; i < NumFloatRegs; i++) {
         stringstream buf;
         ccprintf(buf, "F%02d", i);
-        paramOut(buf.str(), xc->regs.floatRegFile.d[i]);
+        paramOut(buf.str(), xc->regs.floatRegFile.q[i]);
     }
     // CPUTraitsType::serializeSpecialRegs(getProxy(), xc->regs);
 }
@@ -281,7 +281,7 @@ SimpleCPU::unserialize(IniFile &db, const string &category, ConfigNode *node)
         stringstream buf;
         ccprintf(buf, "F%02d", i);
         db.findDefault(category, buf.str(), data);
-        xc->regs.floatRegFile.d[i] = strtod(data.c_str(),NULL);
+        to_number(data.c_str(), xc->regs.floatRegFile.q[i]);
     }
 
     // Read in Special registers
diff --git a/sim/serialize.cc b/sim/serialize.cc
index 6144c97d0..c90f1694e 100644
--- a/sim/serialize.cc
+++ b/sim/serialize.cc
@@ -100,8 +100,9 @@ Serializeable::childOut(const string &name, Serializeable *child)
 void
 Serializeable::setName(const string &name)
 {
-    if (objName != "")
-        panic("Cannot change object name");
+    if (objName != "") {
+        cprintf("Renaming object '%s' to '%s'.\n", objName, name);
+    }
 
     objName = name;
 }
@@ -160,7 +161,7 @@ Serializer::serialize(const string &f)
     add_objects();
     while (!objects.empty()) {
         Serializeable *serial = objects.front();
-        DPRINTF(Serialize, "Name Children of %s\n", serial->name());
+        DPRINTF(Serialize, "Naming children of %s\n", serial->name());
         serial->nameChildren();
         objects.pop_front();
         list.push_back(serial);
@@ -174,7 +175,7 @@ Serializer::serialize(const string &f)
     add_objects();
     while (!objects.empty()) {
         Serializeable *serial = objects.front();
-        DPRINTF(Serialize, "Name Children of %s\n", serial->name());
+        DPRINTF(Serialize, "Serializing %s\n", serial->name());
         serial->serialize();
         objects.pop_front();
         list.push_back(serial);