diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
| commit | 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch) | |
| tree | 81108e7ff1951b652258f53bd5615a617b734ce2 | |
| parent | ddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff) | |
| download | gem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz | |
update stats for preceeding changes
162 files changed, 31224 insertions, 30178 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 028711e47..158e17e5b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -11,14 +11,15 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +clock=1000 +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -34,18 +35,17 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -93,6 +93,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -111,7 +112,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -145,16 +145,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -437,16 +439,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -460,6 +464,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=AlphaInterrupts +[system.cpu0.isa] +type=AlphaISA + [system.cpu0.itb] type=AlphaTLB size=48 @@ -469,7 +476,7 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -517,6 +524,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -535,7 +543,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -569,16 +576,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -861,16 +870,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -884,6 +895,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=AlphaInterrupts +[system.cpu1.isa] +type=AlphaISA + [system.cpu1.itb] type=AlphaTLB size=48 @@ -908,7 +922,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -928,7 +942,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -951,16 +965,18 @@ type=BaseCache addr_ranges=0:8589934591 assoc=8 block_size=64 +clock=1000 forward_snoops=false hash_delay=1 +hit_latency=50 is_top_level=true -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -976,20 +992,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -1010,9 +1028,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1000 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -1025,14 +1044,28 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[1] @@ -1044,7 +1077,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -1057,7 +1090,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 @@ -1072,10 +1105,11 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor +clock=1000 cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal @@ -1083,8 +1117,9 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip +clock=1000 pio_addr=8803072344064 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[0] @@ -1140,12 +1175,10 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami rss=false rx_delay=1000000 @@ -1162,9 +1195,10 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake +clock=1000 fake_mem=false pio_addr=8796093677568 -pio_latency=1000 +pio_latency=100000 pio_size=393216 ret_bad_addr=false ret_data16=65535 @@ -1178,9 +1212,10 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848432 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1194,9 +1229,10 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848304 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1210,9 +1246,10 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848569 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1226,9 +1263,10 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848451 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1242,9 +1280,10 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848515 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1258,9 +1297,10 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848579 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1274,9 +1314,10 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848643 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1290,9 +1331,10 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848707 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1306,9 +1348,10 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848771 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1322,9 +1365,10 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848835 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1338,9 +1382,10 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848899 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1354,9 +1399,10 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615850617 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1370,9 +1416,10 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848891 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1386,9 +1433,10 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848816 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1402,9 +1450,10 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848696 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1418,9 +1467,10 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848936 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1434,9 +1484,10 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848680 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1450,9 +1501,10 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848944 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1466,9 +1518,10 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice +clock=1000 devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -1512,16 +1565,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami system=system config=system.iobus.master[26] @@ -1530,9 +1582,10 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO +clock=1000 frequency=976562500 pio_addr=8804615847936 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1541,8 +1594,9 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip +clock=1000 pio_addr=8802535473152 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[1] @@ -1550,7 +1604,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1000 +pio_latency=30000 platform=system.tsunami size=16777216 system=system @@ -1558,8 +1613,9 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 +clock=1000 pio_addr=8804615848952 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index acdd4bc1c..200b08796 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:20:05 -gem5 started Jul 26 2012 22:30:48 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:40:49 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 112168000 -Exiting @ tick 1900530295500 because m5_exit instruction encountered +info: Launching CPU 1 @ 107840000 +Exiting @ tick 1897857556000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 763ec5c7a..59d7770e6 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.896908 # Number of seconds simulated -sim_ticks 1896907607500 # Number of ticks simulated -final_tick 1896907607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.897858 # Number of seconds simulated +sim_ticks 1897857556000 # Number of ticks simulated +final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91997 # Simulator instruction rate (inst/s) -host_op_rate 91997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3111116066 # Simulator tick rate (ticks/s) -host_mem_usage 330780 # Number of bytes of host memory used -host_seconds 609.72 # Real time elapsed on the host -sim_insts 56092592 # Number of instructions simulated -sim_ops 56092592 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 788928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24066944 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 193664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1095360 # Number of bytes read from this memory -system.physmem.bytes_read::total 28794304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 788928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 193664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7762048 # Number of bytes written to this memory -system.physmem.bytes_written::total 7762048 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12327 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 376046 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 17115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449911 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121282 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121282 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 415902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12687462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1396698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 102095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 577445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15179603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 415902 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 102095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517997 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4091948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4091948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4091948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 415902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12687462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1396698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 102095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 577445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19271551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449911 # Total number of read requests seen -system.physmem.writeReqs 121282 # Total number of write requests seen -system.physmem.cpureqs 578344 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28794304 # Total number of bytes read from memory -system.physmem.bytesWritten 7762048 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28794304 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7762048 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 53 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3357 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27975 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28585 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28175 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28316 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27281 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7339 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7422 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7694 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7599 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7607 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7795 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7764 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8092 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7767 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6820 # Track writes on a per bank basis +host_inst_rate 131170 # Simulator instruction rate (inst/s) +host_op_rate 131170 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4437782045 # Simulator tick rate (ticks/s) +host_mem_usage 332328 # Number of bytes of host memory used +host_seconds 427.66 # Real time elapsed on the host +sim_insts 56096024 # Number of instructions simulated +sim_ops 56096024 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24264832 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 217920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 955136 # Number of bytes read from this memory +system.physmem.bytes_read::total 28851328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 762816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 217920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 980736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7805952 # Number of bytes written to this memory +system.physmem.bytes_written::total 7805952 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 379138 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3405 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14924 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450802 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121968 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121968 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 401935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12785381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1396640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 503271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15202051 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 401935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4113034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4113034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4113034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 401935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12785381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1396640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 503271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19315085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450802 # Total number of read requests seen +system.physmem.writeReqs 121968 # Total number of write requests seen +system.physmem.cpureqs 580318 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28851328 # Total number of bytes read from memory +system.physmem.bytesWritten 7805952 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28851328 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7805952 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 52 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3354 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28406 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28166 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28066 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27814 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7745 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7549 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7514 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7617 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7558 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7855 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7634 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7378 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 313 # Number of times wr buffer was full causing retry -system.physmem.totGap 1896888917000 # Total gap between requests +system.physmem.numWrRetry 525 # Number of times wr buffer was full causing retry +system.physmem.totGap 1897852967000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 449911 # Categorize read packet sizes +system.physmem.readPktSize::6 450802 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 121595 # categorize write packet sizes +system.physmem.writePktSize::6 122493 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,31 +116,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3357 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3354 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 322755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 322811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 1259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 178 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6417421318 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13706967318 # Sum of mem lat for all requests -system.physmem.totBusLat 1799432000 # Total cycles spent in databus access -system.physmem.totBankLat 5490114000 # Total cycles spent in bank access -system.physmem.avgQLat 14265.44 # Average queueing delay per request -system.physmem.avgBankLat 12204.10 # Average bank access latency per request +system.physmem.totQLat 6654880960 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13976960960 # Sum of mem lat for all requests +system.physmem.totBusLat 1803000000 # Total cycles spent in databus access +system.physmem.totBankLat 5519080000 # Total cycles spent in bank access +system.physmem.avgQLat 14764.02 # Average queueing delay per request +system.physmem.avgBankLat 12244.22 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30469.54 # Average memory access latency -system.physmem.avgRdBW 15.18 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.18 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31008.23 # Average memory access latency +system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.19 # Average write queue length over time -system.physmem.readRowHits 429697 # Number of row buffer hits during reads -system.physmem.writeRowHits 77704 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.07 # Row buffer hit rate for writes -system.physmem.avgGap 3320924.66 # Average gap between requests -system.l2c.replacements 342985 # number of replacements -system.l2c.tagsinuse 65321.507443 # Cycle average of tags in use -system.l2c.total_refs 2664537 # Total number of references to valid blocks. -system.l2c.sampled_refs 407990 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.530888 # Average number of references to valid blocks. +system.physmem.avgWrQLen 7.39 # Average write queue length over time +system.physmem.readRowHits 429728 # Number of row buffer hits during reads +system.physmem.writeRowHits 77127 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes +system.physmem.avgGap 3313464.33 # Average gap between requests +system.l2c.replacements 343886 # number of replacements +system.l2c.tagsinuse 65330.449226 # Cycle average of tags in use +system.l2c.total_refs 2612992 # Total number of references to valid blocks. +system.l2c.sampled_refs 408910 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.390140 # Average number of references to valid blocks. system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53803.345548 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4275.017757 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5362.992247 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1295.991254 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 584.160637 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820974 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.065232 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.081833 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.019775 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.008914 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996727 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 631150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 433289 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 452366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 409982 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1926787 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 859408 # number of Writeback hits -system.l2c.Writeback_hits::total 859408 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 132 # number of UpgradeReq hits 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accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164369 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164369 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average 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overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38476.029428 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 91899.539403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40824.378350 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -505,39 +508,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # 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-system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41724 # number of demand (read+write) misses +system.iocache.demand_misses::total 41724 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41724 # number of overall misses +system.iocache.overall_misses::total 41724 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 20816998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20816998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9540304806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9540304806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9561121804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9561121804 # number of demand (read+write) miss cycles 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+system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41724 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -546,40 +549,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229206.002262 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229206.002262 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228748.964820 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228748.964820 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228748.964820 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228748.964820 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 193065 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121029.058140 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121029.058140 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229599.172266 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229599.172266 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 229151.610680 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 229151.610680 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 192730 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23193 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23021 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.324279 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.371921 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41523 # number of writebacks system.iocache.writebacks::total 41523 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 172 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 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+system.iocache.demand_mshr_miss_latency::tsunami.ide 7389390046 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7389390046 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7389390046 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7389390046 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -588,14 +591,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177156.274572 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177156.274572 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69023.255814 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69023.255814 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177549.048084 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177549.048084 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -613,22 +616,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7007258 # DTB read hits -system.cpu0.dtb.read_misses 29214 # DTB read misses -system.cpu0.dtb.read_acv 555 # DTB read access violations -system.cpu0.dtb.read_accesses 627494 # DTB read accesses -system.cpu0.dtb.write_hits 4619142 # DTB write hits -system.cpu0.dtb.write_misses 6985 # DTB write misses -system.cpu0.dtb.write_acv 345 # DTB write access violations -system.cpu0.dtb.write_accesses 208744 # DTB write accesses -system.cpu0.dtb.data_hits 11626400 # DTB hits -system.cpu0.dtb.data_misses 36199 # DTB misses -system.cpu0.dtb.data_acv 900 # DTB access violations -system.cpu0.dtb.data_accesses 836238 # DTB accesses -system.cpu0.itb.fetch_hits 888386 # ITB hits -system.cpu0.itb.fetch_misses 27286 # ITB misses -system.cpu0.itb.fetch_acv 998 # ITB acv -system.cpu0.itb.fetch_accesses 915672 # ITB accesses +system.cpu0.dtb.read_hits 7996955 # DTB read hits +system.cpu0.dtb.read_misses 29938 # DTB read misses +system.cpu0.dtb.read_acv 553 # DTB read access violations +system.cpu0.dtb.read_accesses 624438 # DTB read accesses +system.cpu0.dtb.write_hits 5309744 # DTB write hits +system.cpu0.dtb.write_misses 7955 # DTB write misses +system.cpu0.dtb.write_acv 319 # DTB write access violations +system.cpu0.dtb.write_accesses 207916 # DTB write accesses +system.cpu0.dtb.data_hits 13306699 # DTB hits +system.cpu0.dtb.data_misses 37893 # DTB misses +system.cpu0.dtb.data_acv 872 # DTB access violations +system.cpu0.dtb.data_accesses 832354 # DTB accesses +system.cpu0.itb.fetch_hits 944692 # ITB hits +system.cpu0.itb.fetch_misses 28693 # ITB misses +system.cpu0.itb.fetch_acv 988 # ITB acv +system.cpu0.itb.fetch_accesses 973385 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -641,277 +644,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 83155415 # number of cpu cycles simulated +system.cpu0.numCycles 92901317 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 9804849 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 8272695 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 286303 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 6905955 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 4307856 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11220993 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9498823 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 301088 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 7731310 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 4807164 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 619842 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 27789 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 19011041 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 50915714 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 9804849 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4927698 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 9659436 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1473505 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 28455218 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 194299 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 211367 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 143 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6349535 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 190370 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 58504859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.870282 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.201063 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 696053 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31347 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 22682478 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 57580156 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11220993 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5503217 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10836671 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1573403 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32658351 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 28974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 198560 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 186652 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 190 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6976582 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 207142 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 67595352 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.851836 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.189286 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 48845423 83.49% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 638375 1.09% 84.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1232766 2.11% 86.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 545499 0.93% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2228588 3.81% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 432839 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 448017 0.77% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 658155 1.12% 94.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3475197 5.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 56758681 83.97% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 707820 1.05% 85.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1385949 2.05% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 615643 0.91% 87.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2401218 3.55% 91.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 457628 0.68% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 501258 0.74% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 784291 1.16% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3982864 5.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 58504859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.117910 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.612296 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20221803 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 27858596 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8736076 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 771700 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 916683 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 397847 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 27467 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 49800366 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 84499 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 916683 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21025049 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 10730618 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14396247 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8233599 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3202661 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 46975607 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6729 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 282251 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1314603 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 31610949 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 57450568 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 57189305 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 261263 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 27436892 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4174049 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1166690 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 177857 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8656888 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7389019 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4877617 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 925746 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 640404 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 41641305 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1430691 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 40525941 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 100515 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 4996937 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2778091 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 970759 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 58504859 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.692694 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328093 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 67595352 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.120784 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.619799 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 23783356 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 32156359 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9819480 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 864593 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 971563 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 447466 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32236 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56434658 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 99123 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 971563 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24717335 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12372612 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16597679 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9220139 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3716022 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53261468 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6752 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 462341 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1402867 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 35633564 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 64862965 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 64519168 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 343797 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31292257 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4341299 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1345733 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 201778 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10181749 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8375667 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5571987 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1008121 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 649590 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47223004 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1661663 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 46145441 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96356 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5312296 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2839377 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1124463 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 67595352 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.682672 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.326673 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 40198625 68.71% 68.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8496961 14.52% 83.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3824833 6.54% 89.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2421122 4.14% 93.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1801555 3.08% 96.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 974491 1.67% 98.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 509636 0.87% 99.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 241631 0.41% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 36005 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 46917740 69.41% 69.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9524699 14.09% 83.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4257234 6.30% 89.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2757377 4.08% 93.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128651 3.15% 97.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1105682 1.64% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 579516 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 281591 0.42% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 42862 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 58504859 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 67595352 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 54985 10.35% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 255079 48.00% 58.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 221355 41.65% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67879 11.08% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 286167 46.73% 57.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 258352 42.19% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 27833265 68.68% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 41848 0.10% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 13219 0.03% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7301690 18.02% 86.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4678009 11.54% 98.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 652246 1.61% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 31627354 68.54% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48263 0.10% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14877 0.03% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8323640 18.04% 86.73% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5371898 11.64% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 753768 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 40525941 # Type of FU issued -system.cpu0.iq.rate 0.487352 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 531419 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013113 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 139814106 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 47896052 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 39650626 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 374568 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 182665 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 177037 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 40857986 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 195589 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 455505 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 46145441 # Type of FU issued +system.cpu0.iq.rate 0.496715 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 612398 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 160102230 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 53968976 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 45199549 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 492757 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 238910 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 232575 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 46496253 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 257824 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 502915 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1004949 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2086 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10010 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 405892 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1032397 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11166 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 416538 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 11959 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 139790 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13927 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 141497 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 916683 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7413565 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 614240 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 45518060 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 556785 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7389019 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4877617 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1263664 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 539342 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5760 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10010 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149941 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 281478 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 431419 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 40181745 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7054742 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 344195 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 971563 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8614462 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 715502 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51740003 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 598208 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8375667 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5571987 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1467274 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 578076 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5429 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11166 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 147373 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 320873 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 468246 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 45797277 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8048095 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 348163 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2446064 # number of nop insts executed -system.cpu0.iew.exec_refs 11690884 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6330042 # Number of branches executed -system.cpu0.iew.exec_stores 4636142 # Number of stores executed -system.cpu0.iew.exec_rate 0.483213 # Inst execution rate -system.cpu0.iew.wb_sent 39909560 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 39827663 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 19855593 # num instructions producing a value -system.cpu0.iew.wb_consumers 26361633 # num instructions consuming a value +system.cpu0.iew.exec_nop 2855336 # number of nop insts executed +system.cpu0.iew.exec_refs 13377753 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7249094 # Number of branches executed +system.cpu0.iew.exec_stores 5329658 # Number of stores executed +system.cpu0.iew.exec_rate 0.492967 # Inst execution rate +system.cpu0.iew.wb_sent 45516467 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 45432124 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22555336 # num instructions producing a value +system.cpu0.iew.wb_consumers 30242853 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.478955 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.753200 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.489036 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.745807 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5375485 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 459932 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 404147 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 57588176 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.695477 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.605159 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5732411 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 537200 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 438547 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 66623789 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.689159 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608194 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 42371011 73.58% 73.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6488229 11.27% 84.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3374360 5.86% 90.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1907115 3.31% 94.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1044719 1.81% 95.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 416558 0.72% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 355194 0.62% 97.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 347785 0.60% 97.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1283205 2.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 49353923 74.08% 74.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7278183 10.92% 85.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3860099 5.79% 90.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2143933 3.22% 94.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1188584 1.78% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 481737 0.72% 96.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 414393 0.62% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 388678 0.58% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1514259 2.27% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 57588176 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 40051259 # Number of instructions committed -system.cpu0.commit.committedOps 40051259 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 66623789 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 45914377 # Number of instructions committed +system.cpu0.commit.committedOps 45914377 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10855795 # Number of memory references committed -system.cpu0.commit.loads 6384070 # Number of loads committed -system.cpu0.commit.membars 151085 # Number of memory barriers committed -system.cpu0.commit.branches 6007416 # Number of branches committed -system.cpu0.commit.fp_insts 174841 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 37190024 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489523 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1283205 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12498719 # Number of memory references committed +system.cpu0.commit.loads 7343270 # Number of loads committed +system.cpu0.commit.membars 179286 # Number of memory barriers committed +system.cpu0.commit.branches 6902899 # Number of branches committed +system.cpu0.commit.fp_insts 230540 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 42546523 # Number of committed integer instructions. +system.cpu0.commit.function_calls 573621 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1514259 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 101537476 # The number of ROB reads -system.cpu0.rob.rob_writes 91770556 # The number of ROB writes -system.cpu0.timesIdled 793139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24650556 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3710654942 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 37835874 # Number of Instructions Simulated -system.cpu0.committedOps 37835874 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 37835874 # Number of Instructions Simulated -system.cpu0.cpi 2.197793 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.197793 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.455002 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.455002 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 52969279 # number of integer regfile reads -system.cpu0.int_regfile_writes 28937240 # number of integer regfile writes -system.cpu0.fp_regfile_reads 87038 # number of floating regfile reads -system.cpu0.fp_regfile_writes 87248 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1306578 # number of misc regfile reads -system.cpu0.misc_regfile_writes 663412 # number of misc regfile writes +system.cpu0.rob.rob_reads 116563585 # The number of ROB reads +system.cpu0.rob.rob_writes 104266102 # The number of ROB writes +system.cpu0.timesIdled 937015 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25305965 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3702808960 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 43304295 # Number of Instructions Simulated +system.cpu0.committedOps 43304295 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 43304295 # Number of Instructions Simulated +system.cpu0.cpi 2.145314 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.145314 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.466132 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.466132 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 60234005 # number of integer regfile reads +system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes +system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads +system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1561000 # number of misc regfile reads +system.cpu0.misc_regfile_writes 765601 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -943,245 +946,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 642913 # number of replacements -system.cpu0.icache.tagsinuse 510.325206 # Cycle average of tags in use -system.cpu0.icache.total_refs 5670885 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 643421 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.813646 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20341529000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.325206 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996729 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996729 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5670885 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5670885 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5670885 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5670885 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5670885 # number of overall hits -system.cpu0.icache.overall_hits::total 5670885 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 678650 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 678650 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 678650 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 678650 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 678650 # number of overall misses -system.cpu0.icache.overall_misses::total 678650 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9582412994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9582412994 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9582412994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9582412994 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9582412994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9582412994 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6349535 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6349535 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6349535 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6349535 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6349535 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6349535 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.106882 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.106882 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.106882 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.106882 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.106882 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.106882 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14119.815802 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14119.815802 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14119.815802 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14119.815802 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2234 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.406897 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.replacements 790851 # number of replacements +system.cpu0.icache.tagsinuse 510.328171 # Cycle average of tags in use +system.cpu0.icache.total_refs 6144778 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 791359 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.764843 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20315369000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.328171 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6144778 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6144778 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6144778 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6144778 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6144778 # number of overall hits +system.cpu0.icache.overall_hits::total 6144778 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 831804 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 831804 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 831804 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 831804 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 831804 # number of overall misses +system.cpu0.icache.overall_misses::total 831804 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11563264492 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11563264492 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11563264492 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11563264492 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11563264492 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11563264492 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6976582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6976582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6976582 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6976582 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6976582 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6976582 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119228 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.119228 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119228 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.119228 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119228 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.119228 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13901.429293 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13901.429293 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13901.429293 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13901.429293 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2068 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1976 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.031008 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 988 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 35068 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 35068 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 35068 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 35068 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 35068 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 35068 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 643582 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 643582 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 643582 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 643582 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 643582 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 643582 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7877266496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7877266496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7877266496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7877266496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7877266496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7877266496 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.101359 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.101359 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.101359 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12239.724691 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40285 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 40285 # number of ReadReq MSHR hits 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miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9521125993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9521125993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9521125993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9521125993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9521125993 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113454 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113454 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12028.929177 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 932591 # number of replacements -system.cpu0.dcache.tagsinuse 478.331784 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8251917 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 933103 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.843522 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21811000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 478.331784 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.934242 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.934242 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5164945 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5164945 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2787881 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2787881 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136688 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 136688 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 157014 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 157014 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7952826 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7952826 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7952826 # number of overall hits -system.cpu0.dcache.overall_hits::total 7952826 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1127907 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1127907 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1514074 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1514074 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12708 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12708 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 640 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2641981 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2641981 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2641981 # number of overall misses -system.cpu0.dcache.overall_misses::total 2641981 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26996447000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26996447000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62901501244 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 62901501244 # number of WriteReq miss cycles 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# miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249366 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23934.993754 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23934.993754 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41544.535633 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41544.535633 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.956878 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.956878 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6181.250000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6181.250000 # average StoreCondReq miss latency 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# Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 467.302243 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.912700 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.912700 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5816576 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5816576 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3291002 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3291002 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156681 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156681 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 180603 # number of StoreCondReq hits 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miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4105000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4105000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263114 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 98980263114 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263114 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 98980263114 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4961759 # number of WriteReq accesses(hits+misses) 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22493.148628 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.533997 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.533997 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6108.630952 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6108.630952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32280.621866 # average overall miss latency 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system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 453711 # number of writebacks -system.cpu0.dcache.writebacks::total 453711 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 427154 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 427154 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1285155 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1285155 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3146 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3146 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1712309 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1712309 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1712309 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1712309 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 700753 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 700753 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 228919 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 228919 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 929672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 929672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 929672 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 929672 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 17299108000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 17299108000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9077949457 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9077949457 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117930500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117930500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26377057457 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26377057457 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26377057457 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26377057457 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998607000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998607000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1686748998 # number of WriteReq MSHR uncacheable cycles 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1116427 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2761000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2761000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275728787 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 29275728787 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275728787 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 29275728787 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1684532498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2683011498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2683011498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051967 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051967 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075952 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075952 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003707 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003707 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091707 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.378365 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.378365 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4108.630952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4108.630952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1193,22 +1196,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3713266 # DTB read hits -system.cpu1.dtb.read_misses 14359 # DTB read misses -system.cpu1.dtb.read_acv 33 # DTB read access violations -system.cpu1.dtb.read_accesses 328215 # DTB read accesses -system.cpu1.dtb.write_hits 2351870 # DTB write hits -system.cpu1.dtb.write_misses 2326 # DTB write misses -system.cpu1.dtb.write_acv 62 # DTB write access violations -system.cpu1.dtb.write_accesses 130566 # DTB write accesses -system.cpu1.dtb.data_hits 6065136 # DTB hits -system.cpu1.dtb.data_misses 16685 # DTB misses -system.cpu1.dtb.data_acv 95 # DTB access violations -system.cpu1.dtb.data_accesses 458781 # DTB accesses -system.cpu1.itb.fetch_hits 552396 # ITB hits -system.cpu1.itb.fetch_misses 7861 # ITB misses -system.cpu1.itb.fetch_acv 226 # ITB acv -system.cpu1.itb.fetch_accesses 560257 # ITB accesses +system.cpu1.dtb.read_hits 2657978 # DTB read hits +system.cpu1.dtb.read_misses 12789 # DTB read misses +system.cpu1.dtb.read_acv 27 # DTB read access violations +system.cpu1.dtb.read_accesses 325192 # DTB read accesses +system.cpu1.dtb.write_hits 1642917 # DTB write hits +system.cpu1.dtb.write_misses 2443 # DTB write misses +system.cpu1.dtb.write_acv 63 # DTB write access violations +system.cpu1.dtb.write_accesses 132832 # DTB write accesses +system.cpu1.dtb.data_hits 4300895 # DTB hits +system.cpu1.dtb.data_misses 15232 # DTB misses +system.cpu1.dtb.data_acv 90 # DTB access violations +system.cpu1.dtb.data_accesses 458024 # DTB accesses +system.cpu1.itb.fetch_hits 468004 # ITB hits +system.cpu1.itb.fetch_misses 6860 # ITB misses +system.cpu1.itb.fetch_acv 223 # ITB acv +system.cpu1.itb.fetch_accesses 474864 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1221,516 +1224,516 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 34615367 # number of cpu cycles simulated +system.cpu1.numCycles 24425153 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 5312293 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 4360790 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 184753 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 3627578 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1933378 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3729082 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 3054181 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 119454 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2320080 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1316503 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 383381 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 19114 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 12153279 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 25592027 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 5312293 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2316759 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 4666723 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 848042 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 13957627 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25440 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65073 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 147747 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2992364 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 115997 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 31571084 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.810616 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.170872 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17895154 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3257696 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 9888413 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2125846 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 78174 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 26904361 85.22% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 276998 0.88% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 593564 1.88% 87.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 353090 1.12% 89.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 710175 2.25% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 234476 0.74% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 277213 0.88% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 377383 1.20% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1843824 5.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 18634782 85.12% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 494265 2.26% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1306901 5.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 31571084 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.153466 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.739326 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 12173556 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 14265063 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 4322746 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 271541 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 538177 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 245868 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 17179 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 25069869 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 51217 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 538177 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 12622413 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 4307697 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 8552551 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 4022106 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1528138 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 23469307 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 403073 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 318746 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 15460907 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 27951432 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 27722595 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 228837 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 13017644 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2443263 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 711049 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 79879 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4546986 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3946391 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2480141 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 398992 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 247125 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 20556503 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 873226 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 19920635 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 45889 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3011838 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1481780 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 622079 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 31571084 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.630977 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.308978 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 21892478 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.152674 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.732653 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8206589 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 10101487 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3024410 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 183126 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 376865 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 172901 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 11788 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8509917 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2827279 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6300793 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2835389 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 16406077 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 10874639 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 19629758 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 19484069 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1710467 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2820928 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1739172 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 303279 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 178063 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 14428831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 617828 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 13962547 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 36109 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2150385 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1081456 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 443630 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 21892478 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.637778 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.318020 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 22947759 72.69% 72.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 3816292 12.09% 84.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1671768 5.30% 90.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1218822 3.86% 93.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 1072376 3.40% 97.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 425454 1.35% 98.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 262904 0.83% 99.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 135529 0.43% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 20180 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 15854245 72.42% 72.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2672796 12.21% 84.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1184242 5.41% 90.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 847687 3.87% 93.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 726248 3.32% 97.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 300582 1.37% 98.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 191038 0.87% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 101044 0.46% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 14596 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 31571084 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 21892478 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28274 8.56% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 166109 50.30% 58.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 135868 41.14% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17685 7.13% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 130361 52.59% 59.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 99827 40.27% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 13189448 66.21% 66.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 28632 0.14% 66.37% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.37% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 12556 0.06% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3884810 19.50% 85.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 2385812 11.98% 97.92% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 414088 2.08% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 9165178 65.64% 65.67% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 22201 0.16% 65.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10896 0.08% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2775695 19.88% 85.80% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1670228 11.96% 97.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 313060 2.24% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 19920635 # Type of FU issued -system.cpu1.iq.rate 0.575485 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 330251 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.016578 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 71458593 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 24286363 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 19388343 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 329901 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 159417 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 155652 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 20074577 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 172783 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 184439 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 13962547 # Type of FU issued +system.cpu1.iq.rate 0.571646 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 247873 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017753 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 49890568 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 17097827 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 13608739 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 210986 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 102380 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 99816 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 14096605 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 110289 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 133191 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 581301 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1183 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4340 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 230089 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 414475 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 850 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3253 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 172072 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 6918 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 18073 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4939 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 538177 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 3253999 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229517 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 22699099 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 268114 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3946391 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 2480141 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 779721 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 89744 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2529 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4340 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 96593 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 181110 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 277703 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 19708494 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3738657 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 212141 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2193720 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 185768 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 45814 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2212 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3253 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 57900 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 130435 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 188335 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 13825969 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2678414 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 136578 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 1269370 # number of nop insts executed -system.cpu1.iew.exec_refs 6100523 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3128191 # Number of branches executed -system.cpu1.iew.exec_stores 2361866 # Number of stores executed -system.cpu1.iew.exec_rate 0.569357 # Inst execution rate -system.cpu1.iew.wb_sent 19587937 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 19543995 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 9462232 # num instructions producing a value -system.cpu1.iew.wb_consumers 13383566 # num instructions consuming a value +system.cpu1.iew.exec_nop 825136 # number of nop insts executed +system.cpu1.iew.exec_refs 4329493 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2168898 # Number of branches executed +system.cpu1.iew.exec_stores 1651079 # Number of stores executed +system.cpu1.iew.exec_rate 0.566055 # Inst execution rate +system.cpu1.iew.wb_sent 13745874 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 13708555 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 6651311 # num instructions producing a value +system.cpu1.iew.wb_consumers 9340604 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.564605 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.707004 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.561247 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712086 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3264810 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 251147 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260251 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 31032907 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.624350 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.557822 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2293261 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 174198 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 176022 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 21515613 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.628195 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.562431 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 23883562 76.96% 76.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2995086 9.65% 86.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1581522 5.10% 91.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 799862 2.58% 94.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 502768 1.62% 95.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 236983 0.76% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 224339 0.72% 97.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 194617 0.63% 98.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 614168 1.98% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 16491806 76.65% 76.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2174989 10.11% 86.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1058158 4.92% 91.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 548223 2.55% 94.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 352308 1.64% 95.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 166690 0.77% 96.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 160522 0.75% 97.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 129128 0.60% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 433789 2.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 31032907 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 19375400 # Number of instructions committed -system.cpu1.commit.committedOps 19375400 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 21515613 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 13515996 # Number of instructions committed +system.cpu1.commit.committedOps 13515996 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 5615142 # Number of memory references committed -system.cpu1.commit.loads 3365090 # Number of loads committed -system.cpu1.commit.membars 85627 # Number of memory barriers committed -system.cpu1.commit.branches 2912516 # Number of branches committed -system.cpu1.commit.fp_insts 154287 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17850043 # Number of committed integer instructions. -system.cpu1.commit.function_calls 300496 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 614168 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3973553 # Number of memory references committed +system.cpu1.commit.loads 2406453 # Number of loads committed +system.cpu1.commit.membars 57533 # Number of memory barriers committed +system.cpu1.commit.branches 2017672 # Number of branches committed +system.cpu1.commit.fp_insts 98521 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 12496541 # Number of committed integer instructions. +system.cpu1.commit.function_calls 216490 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 433789 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 52972716 # The number of ROB reads -system.cpu1.rob.rob_writes 45818344 # The number of ROB writes -system.cpu1.timesIdled 377037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 3044283 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3758611040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 18256718 # Number of Instructions Simulated -system.cpu1.committedOps 18256718 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 18256718 # Number of Instructions Simulated -system.cpu1.cpi 1.896034 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.896034 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.527417 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.527417 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 25482349 # number of integer regfile reads -system.cpu1.int_regfile_writes 13944369 # number of integer regfile writes -system.cpu1.fp_regfile_reads 81651 # number of floating regfile reads -system.cpu1.fp_regfile_writes 82372 # number of floating regfile writes -system.cpu1.misc_regfile_reads 840995 # number of misc regfile reads -system.cpu1.misc_regfile_writes 357443 # number of misc regfile writes -system.cpu1.icache.replacements 454861 # number of replacements -system.cpu1.icache.tagsinuse 506.121737 # Cycle average of tags in use -system.cpu1.icache.total_refs 2515591 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 455373 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.524243 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 42848278000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 506.121737 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.988519 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.988519 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 2515591 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2515591 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2515591 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2515591 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2515591 # number of overall hits -system.cpu1.icache.overall_hits::total 2515591 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 476773 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 476773 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 476773 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 476773 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 476773 # number of overall misses -system.cpu1.icache.overall_misses::total 476773 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6462749000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6462749000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6462749000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6462749000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6462749000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6462749000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2992364 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2992364 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2992364 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2992364 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2992364 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2992364 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.159330 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.159330 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.159330 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.159330 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.159330 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.159330 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13555.190835 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13555.190835 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13555.190835 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13555.190835 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 884 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.808511 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 36803153 # The number of ROB reads +system.cpu1.rob.rob_writes 31994561 # The number of ROB writes +system.cpu1.timesIdled 237566 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2532675 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3770663279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 12791729 # Number of Instructions Simulated +system.cpu1.committedOps 12791729 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 12791729 # Number of Instructions Simulated +system.cpu1.cpi 1.909449 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.909449 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.523711 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.523711 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 17892474 # number of integer regfile reads +system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes +system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads +system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes +system.cpu1.misc_regfile_reads 586782 # number of misc regfile reads +system.cpu1.misc_regfile_writes 255768 # number of misc regfile writes +system.cpu1.icache.replacements 297472 # number of replacements +system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use +system.cpu1.icache.total_refs 1814154 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 6.088092 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1814154 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1814154 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1814154 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1814154 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1814154 # number of overall hits +system.cpu1.icache.overall_hits::total 1814154 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 311692 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 311692 # number of overall misses +system.cpu1.icache.overall_misses::total 311692 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4307826496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4307826496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125846 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2125846 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2125846 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2125846 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2125846 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2125846 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.146620 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146620 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.146620 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13820.779795 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13820.779795 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13820.779795 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13820.779795 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 806 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 423 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.744186 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 423 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21323 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 21323 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 21323 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 21323 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 21323 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 21323 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455450 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 455450 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 455450 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 455450 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 455450 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 455450 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5356907000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5356907000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5356907000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5356907000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5356907000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5356907000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152204 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.152204 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.152204 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11761.789439 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 13650 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 13650 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 13650 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 13650 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 13650 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 13650 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 298042 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 298042 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 298042 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 298042 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 298042 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 298042 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3567181997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3567181997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3567181997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3567181997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3567181997 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3567181997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140199 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.140199 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.140199 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11968.722519 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 520860 # number of replacements -system.cpu1.dcache.tagsinuse 498.284346 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4488456 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 521257 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 8.610831 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 31290571500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 498.284346 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.973212 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.973212 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2711578 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2711578 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1652227 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1652227 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59380 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 59380 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 66046 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 66046 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4363805 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4363805 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4363805 # number of overall hits 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-system.cpu1.dcache.overall_misses::total 1259140 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 11275775500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 11275775500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16995132775 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 16995132775 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 186282500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 186282500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5003500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5003500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 28270908275 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 28270908275 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 28270908275 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 28270908275 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3447051 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3447051 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2175894 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2175894 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 66735 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 66735 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5622945 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5622945 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5622945 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5622945 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.213363 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.213363 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.240668 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.240668 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177334 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177334 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.010324 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.010324 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.223929 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.223929 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.223929 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.223929 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15331.324875 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15331.324875 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32454.083941 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32454.083941 # average WriteReq miss latency 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-system.cpu1.dcache.blocked::no_mshrs 10411 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 52.958217 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.replacements 296647 # number of replacements +system.cpu1.dcache.tagsinuse 497.527759 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3293413 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 297044 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 11.087290 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 36352469000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 497.527759 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.971734 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.971734 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2035773 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2035773 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1175370 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1175370 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40064 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 40064 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 42523 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 42523 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3211143 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3211143 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3211143 # number of overall hits +system.cpu1.dcache.overall_hits::total 3211143 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 433262 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 433262 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 341345 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 719 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 719 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses +system.cpu1.dcache.overall_misses::total 774607 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736451500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6736451500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 20256376174 # number of demand (read+write) miss cycles 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0.149366 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016627 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016627 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.216783 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.216783 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency 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-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10368 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 689 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 689 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 517084 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 517084 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 517084 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 517084 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5584148500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5584148500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2607634127 # number of WriteReq MSHR miss cycles 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-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 485715000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 485715000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 920480500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 920480500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1406195500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1406195500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.123263 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.123263 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042369 # mshr miss rate for WriteReq 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13142.481754 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13142.481754 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28285.126824 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28285.126824 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12153.549383 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12153.549383 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5261.973875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5261.973875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 225448 # number of writebacks +system.cpu1.dcache.writebacks::total 225448 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 193837 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 193837 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 283225 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 283225 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1368 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1368 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 477062 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 477062 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 477062 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 477062 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 239425 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 239425 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58120 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 58120 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5667 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5667 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 718 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 718 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123298500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123298500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152410804 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5152410804 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152410804 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5152410804 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 925465000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1412353000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1412353000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096971 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096971 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.997390 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.997390 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1739,170 +1742,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4859 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 144961 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 48033 39.13% 39.13% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.11% 39.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.57% 40.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 40.82% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 72639 59.18% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 122745 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 47372 48.94% 48.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.14% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.99% 51.06% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.02% 51.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 47357 48.92% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 96802 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866486525500 98.40% 98.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63938000 0.00% 98.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 572947000 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8827500 0.00% 98.43% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 29774513500 1.57% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1896906751500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.986239 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 169372 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 58506 39.88% 39.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 135 0.09% 39.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.31% 41.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.29% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 86127 58.71% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 146709 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 57513 49.12% 49.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 135 0.12% 49.23% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.64% 50.88% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.89% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 57499 49.11% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 117088 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866028984500 98.32% 98.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63917500 0.00% 98.33% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 571228500 0.03% 98.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8802500 0.00% 98.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 31183758000 1.64% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897856691000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983027 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.651950 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.788643 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.667607 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.798097 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.91% 13.40% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.88% 27.27% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 27.75% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.31% 32.06% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.35% 35.41% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.91% 37.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.48% 37.80% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.44% 39.23% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.35% 42.58% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.96% 43.54% # number of syscalls executed +system.cpu0.kern.syscall::45 37 17.70% 61.24% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.44% 62.68% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.83% 66.51% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.31% 70.81% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.39% 73.68% # number of syscalls executed +system.cpu0.kern.syscall::71 27 12.92% 86.60% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.44% 88.04% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.35% 91.39% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.96% 92.82% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.35% 96.17% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.96% 97.13% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.96% 98.09% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.48% 98.56% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 209 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 97 0.07% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2435 1.87% 1.95% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.04% 1.98% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.99% # number of callpals executed -system.cpu0.kern.callpal::swpipl 116655 89.61% 91.60% # number of callpals executed -system.cpu0.kern.callpal::rdps 6417 4.93% 96.53% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.53% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.54% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rti 4017 3.09% 99.63% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.27% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 130177 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5807 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches +system.cpu0.kern.callpal::wripir 100 0.06% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3082 1.99% 2.06% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed +system.cpu0.kern.callpal::swpipl 140299 90.69% 92.78% # number of callpals executed +system.cpu0.kern.callpal::rdps 6336 4.10% 96.88% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.88% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.88% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.89% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.89% # number of callpals executed +system.cpu0.kern.callpal::rti 4335 2.80% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 342 0.22% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 154704 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6439 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1272 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1286 -system.cpu0.kern.mode_good::user 1287 +system.cpu0.kern.mode_good::kernel 1271 +system.cpu0.kern.mode_good::user 1272 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.221457 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.197391 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.362701 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1894993254500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1913489000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.329789 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1895973773500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1882909500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2436 # number of times the context was actually changed +system.cpu0.kern.swap_context 3083 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3786 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 92502 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 33560 40.13% 40.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 2.30% 42.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 97 0.12% 42.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 48058 57.46% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 83636 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 32844 48.58% 48.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 2.84% 51.42% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 97 0.14% 51.56% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 32747 48.44% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 67609 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1867334401000 98.46% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533283000 0.03% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 45472500 0.00% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28701925000 1.51% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1896615081500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978665 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3800 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 68195 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 23112 38.67% 38.67% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.22% 41.89% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 100 0.17% 42.06% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 34629 57.94% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 59765 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 22728 47.97% 47.97% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 4.06% 52.03% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 100 0.21% 52.24% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22629 47.76% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 47381 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870052426500 98.55% 98.55% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533448500 0.03% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 47034500 0.00% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 26913191500 1.42% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897546101000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.983385 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.681406 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.808372 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.653470 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.792788 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.11% 23.08% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.85% 23.93% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.13% 29.06% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.56% 31.62% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.71% 33.33% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.56% 35.90% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.56% 38.46% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.42% 41.88% # number of syscalls executed +system.cpu1.kern.syscall::45 17 14.53% 56.41% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.56% 58.97% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.71% 60.68% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.85% 61.54% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.71% 63.25% # number of syscalls executed +system.cpu1.kern.syscall::71 27 23.08% 86.32% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.69% 94.02% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.85% 94.87% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.71% 96.58% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.56% 99.15% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 117 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1813 2.11% 2.13% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 78432 91.18% 93.32% # number of callpals executed -system.cpu1.kern.callpal::rdps 2336 2.72% 96.04% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.05% # number of callpals executed -system.cpu1.kern.callpal::rti 3185 3.70% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.20% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.03% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1165 1.89% 1.92% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 1.93% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 54867 89.09% 91.04% # number of callpals executed +system.cpu1.kern.callpal::rdps 2419 3.93% 94.96% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.96% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.97% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 94.97% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.98% # number of callpals executed +system.cpu1.kern.callpal::rti 2874 4.67% 99.64% # number of callpals executed +system.cpu1.kern.callpal::callsys 175 0.28% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 86022 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2264 # number of protection mode switches -system.cpu1.kern.mode_switch::user 459 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 518 -system.cpu1.kern.mode_good::user 459 -system.cpu1.kern.mode_good::idle 59 -system.cpu1.kern.mode_switch_good::kernel 0.228799 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 61585 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1629 # number of protection mode switches +system.cpu1.kern.mode_switch::user 476 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 537 +system.cpu1.kern.mode_good::user 476 +system.cpu1.kern.mode_good::idle 61 +system.cpu1.kern.mode_switch_good::kernel 0.329650 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.028964 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.217647 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 42822911000 2.26% 2.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 817792500 0.04% 2.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1852963538500 97.70% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1814 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.029814 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.258733 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 37752222500 1.99% 1.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 817466500 0.04% 2.03% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1858966004500 97.97% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1166 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 353ee4820..4e3852a72 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,17 +8,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +clock=1000 +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -34,18 +35,17 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -93,6 +93,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -111,7 +112,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -145,16 +145,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -163,7 +165,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -437,16 +439,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -455,15 +459,55 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + [system.cpu.tracer] type=ExeTracer @@ -484,7 +528,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -504,7 +548,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -527,16 +571,18 @@ type=BaseCache addr_ranges=0:8589934591 assoc=8 block_size=64 +clock=1000 forward_snoops=false hash_delay=1 +hit_latency=50 is_top_level=true -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -547,31 +593,6 @@ write_buffers=8 cpu_side=system.iobus.master[29] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -582,13 +603,14 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1000 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -601,14 +623,28 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[1] @@ -620,7 +656,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -630,16 +666,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -648,10 +674,11 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor +clock=1000 cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal @@ -659,8 +686,9 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip +clock=1000 pio_addr=8803072344064 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[0] @@ -716,12 +744,10 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami rss=false rx_delay=1000000 @@ -738,9 +764,10 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake +clock=1000 fake_mem=false pio_addr=8796093677568 -pio_latency=1000 +pio_latency=100000 pio_size=393216 ret_bad_addr=false ret_data16=65535 @@ -754,9 +781,10 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848432 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -770,9 +798,10 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848304 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -786,9 +815,10 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848569 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -802,9 +832,10 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848451 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -818,9 +849,10 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848515 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -834,9 +866,10 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848579 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -850,9 +883,10 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848643 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -866,9 +900,10 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848707 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -882,9 +917,10 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848771 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -898,9 +934,10 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848835 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -914,9 +951,10 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848899 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -930,9 +968,10 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615850617 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -946,9 +985,10 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848891 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -962,9 +1002,10 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848816 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -978,9 +1019,10 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848696 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -994,9 +1036,10 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848936 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1010,9 +1053,10 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848680 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1026,9 +1070,10 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848944 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1042,9 +1087,10 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice +clock=1000 devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -1088,16 +1134,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami system=system config=system.iobus.master[26] @@ -1106,9 +1151,10 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO +clock=1000 frequency=976562500 pio_addr=8804615847936 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1117,8 +1163,9 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip +clock=1000 pio_addr=8802535473152 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[1] @@ -1126,7 +1173,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1000 +pio_latency=30000 platform=system.tsunami size=16777216 system=system @@ -1134,8 +1182,9 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 +clock=1000 pio_addr=8804615848952 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f67dea3de..6a7037f2d 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:20:05 -gem5 started Jul 26 2012 22:30:38 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:34:06 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1864423957500 because m5_exit instruction encountered +Exiting @ tick 1854349611000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index e834f19f3..cbfa90061 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854370 # Number of seconds simulated -sim_ticks 1854370484500 # Number of ticks simulated -final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854350 # Number of seconds simulated +sim_ticks 1854349611000 # Number of ticks simulated +final_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120780 # Simulator instruction rate (inst/s) -host_op_rate 120780 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4226353954 # Simulator tick rate (ticks/s) -host_mem_usage 326684 # Number of bytes of host memory used -host_seconds 438.76 # Real time elapsed on the host -sim_insts 52993965 # Number of instructions simulated -sim_ops 52993965 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24876288 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28497728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7507712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7507712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388692 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445277 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117308 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117308 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 522597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13414950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15367872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 522597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 522597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 522597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13414950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19416530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445277 # Total number of read requests seen -system.physmem.writeReqs 117308 # Total number of write requests seen -system.physmem.cpureqs 564090 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28497728 # Total number of bytes read from memory -system.physmem.bytesWritten 7507712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28497728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7507712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q +host_inst_rate 135035 # Simulator instruction rate (inst/s) +host_op_rate 135035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4724741522 # Simulator tick rate (ticks/s) +host_mem_usage 327760 # Number of bytes of host memory used +host_seconds 392.48 # Real time elapsed on the host +sim_insts 52998188 # Number of instructions simulated +sim_ops 52998188 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 28499904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7518592 # Number of bytes written to this memory +system.physmem.bytes_written::total 7518592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445311 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117478 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117478 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 521567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13417345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15369218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 521567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 521567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054571 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054571 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 521567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13417345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19423789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445311 # Total number of read requests seen +system.physmem.writeReqs 117478 # Total number of write requests seen +system.physmem.cpureqs 564077 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28499904 # Total number of bytes read from memory +system.physmem.bytesWritten 7518592 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28499904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7518592 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28080 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28123 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27692 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28145 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27734 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7584 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7291 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7583 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7405 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7380 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7215 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6854 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7671 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7427 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7315 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7174 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 28171 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28126 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27859 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27508 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27634 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27843 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27902 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6891 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7793 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7306 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7055 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7397 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7475 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7210 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7329 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854365055000 # Total gap between requests +system.physmem.numWrRetry 554 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854344226000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445277 # Categorize read packet sizes +system.physmem.readPktSize::6 445311 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 118080 # categorize write packet sizes +system.physmem.writePktSize::6 118032 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -109,29 +109,29 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 175 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 331917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 331896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 65179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2003 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1608 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -142,47 +142,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6175504423 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13385770423 # Sum of mem lat for all requests -system.physmem.totBusLat 1780884000 # Total cycles spent in databus access -system.physmem.totBankLat 5429382000 # Total cycles spent in bank access -system.physmem.avgQLat 13870.65 # Average queueing delay per request -system.physmem.avgBankLat 12194.80 # Average bank access latency per request +system.physmem.totQLat 6253510302 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13461286302 # Sum of mem lat for all requests +system.physmem.totBusLat 1781012000 # Total cycles spent in databus access +system.physmem.totBankLat 5426764000 # Total cycles spent in bank access +system.physmem.avgQLat 14044.85 # Average queueing delay per request +system.physmem.avgBankLat 12188.05 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30065.45 # Average memory access latency +system.physmem.avgMemAccLat 30232.89 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s @@ -190,21 +190,21 @@ system.physmem.avgConsumedWrBW 4.05 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.01 # Average write queue length over time -system.physmem.readRowHits 425232 # Number of row buffer hits during reads -system.physmem.writeRowHits 76485 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.20 # Row buffer hit rate for writes -system.physmem.avgGap 3296150.90 # Average gap between requests +system.physmem.avgWrQLen 11.07 # Average write queue length over time +system.physmem.readRowHits 425296 # Number of row buffer hits during reads +system.physmem.writeRowHits 76454 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.08 # Row buffer hit rate for writes +system.physmem.avgGap 3294919.10 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265505 # Cycle average of tags in use +system.iocache.tagsinuse 1.265413 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704471567000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265505 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079094 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079094 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704469740000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079088 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -213,14 +213,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20930998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20930998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9501230806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9501230806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9522161804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9522161804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9522161804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9522161804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9494924806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9494924806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9515852804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9515852804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9515852804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9515852804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -237,19 +237,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120988.427746 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120988.427746 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228658.808385 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228658.808385 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228212.385956 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228212.385956 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 190847 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228507.046737 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228507.046737 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228061.181642 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228061.181642 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 189089 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22837 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 22862 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.356921 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.270886 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11934000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11934000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338470481 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7338470481 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7350404481 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7350404481 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7350404481 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7350404481 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7332138561 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7332138561 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7344069561 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7344069561 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7344069561 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7344069561 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68982.658960 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68982.658960 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176609.320394 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176609.320394 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176456.934949 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176456.934949 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10013236 # DTB read hits -system.cpu.dtb.read_misses 44959 # DTB read misses -system.cpu.dtb.read_acv 558 # DTB read access violations -system.cpu.dtb.read_accesses 947796 # DTB read accesses -system.cpu.dtb.write_hits 6616814 # DTB write hits -system.cpu.dtb.write_misses 10390 # DTB write misses -system.cpu.dtb.write_acv 394 # DTB write access violations -system.cpu.dtb.write_accesses 338465 # DTB write accesses -system.cpu.dtb.data_hits 16630050 # DTB hits -system.cpu.dtb.data_misses 55349 # DTB misses -system.cpu.dtb.data_acv 952 # DTB access violations -system.cpu.dtb.data_accesses 1286261 # DTB accesses -system.cpu.itb.fetch_hits 1329992 # ITB hits -system.cpu.itb.fetch_misses 37108 # ITB misses -system.cpu.itb.fetch_acv 1110 # ITB acv -system.cpu.itb.fetch_accesses 1367100 # ITB accesses +system.cpu.dtb.read_hits 9959916 # DTB read hits +system.cpu.dtb.read_misses 41524 # DTB read misses +system.cpu.dtb.read_acv 557 # DTB read access violations +system.cpu.dtb.read_accesses 942700 # DTB read accesses +system.cpu.dtb.write_hits 6603148 # DTB write hits +system.cpu.dtb.write_misses 10669 # DTB write misses +system.cpu.dtb.write_acv 409 # DTB write access violations +system.cpu.dtb.write_accesses 338186 # DTB write accesses +system.cpu.dtb.data_hits 16563064 # DTB hits +system.cpu.dtb.data_misses 52193 # DTB misses +system.cpu.dtb.data_acv 966 # DTB access violations +system.cpu.dtb.data_accesses 1280886 # DTB accesses +system.cpu.itb.fetch_hits 1308562 # ITB hits +system.cpu.itb.fetch_misses 36917 # ITB misses +system.cpu.itb.fetch_acv 1051 # ITB acv +system.cpu.itb.fetch_accesses 1345479 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,147 +332,147 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 109331520 # number of cpu cycles simulated +system.cpu.numCycles 108866981 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14034298 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11727409 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 442398 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10070774 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5936443 # Number of BTB hits +system.cpu.BPredUnit.lookups 13878911 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11630816 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 403232 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9482716 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5833581 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 932889 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 42550 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28466944 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71882691 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14034298 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37395098 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81356873 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 911561 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 38998 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 28184398 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70994195 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13878911 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6745142 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13311939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2031019 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37417570 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 255429 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 315513 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8617973 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269432 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80827249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.878345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221663 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67855366 83.40% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2811672 3.46% 91.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 591009 0.73% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671901 0.83% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1016398 1.25% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67515310 83.53% 83.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 859289 1.06% 84.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1709305 2.11% 86.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 824937 1.02% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2774546 3.43% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 565272 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 652347 0.81% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007085 1.25% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4919158 6.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81356873 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37116941 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 610220 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43308 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70446207 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129922 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19830185 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6758 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 499961 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1485755 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44416415 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80669752 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80190207 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479545 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38187514 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6228893 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1695379 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 248206 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12171415 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10595299 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6961029 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1313529 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 845283 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58768050 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2080813 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57151750 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119190 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81356873 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80827249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127485 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.652119 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29306094 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37119542 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12159527 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 975132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1266953 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 590499 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43097 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69660736 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 130298 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1266953 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30443941 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13656496 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19805604 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11392846 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4261407 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65802441 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6765 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 504009 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1491914 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43932847 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79894315 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79415060 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479255 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38191269 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5741570 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1687796 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 244874 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12188114 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10482106 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6925475 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1313213 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 855117 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58302952 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2055207 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56888280 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 110464 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6988476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3659625 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1390229 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80827249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.703826 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364551 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56509823 69.46% 69.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2660699 3.27% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1462898 1.80% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 750627 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 334208 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56119293 69.43% 69.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10851228 13.43% 82.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5175866 6.40% 89.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3389461 4.19% 93.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2645582 3.27% 96.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1466047 1.81% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 750476 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332850 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96446 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81356873 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80827249 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 375615 47.50% 58.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326165 41.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91026 11.51% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373270 47.20% 58.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326472 41.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38947584 68.15% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61688 0.11% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38768679 68.15% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61732 0.11% 68.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued @@ -495,114 +495,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10460697 18.30% 86.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6696198 11.72% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949053 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10391331 18.27% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6681118 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948891 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57151750 # Type of FU issued -system.cpu.iq.rate 0.522738 # Inst issue rate -system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195876834 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336801 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327935 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57573031 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362154 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597795 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56888280 # Type of FU issued +system.cpu.iq.rate 0.522549 # Inst issue rate +system.cpu.iq.fu_busy_cnt 790768 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013900 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194812399 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67023826 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55617934 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692641 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336620 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327880 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57310327 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361435 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598219 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1500833 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3663 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13623 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 580148 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1386761 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3497 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 544022 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17973 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 208284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17955 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 206298 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1354175 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9957840 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684465 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64406962 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 718774 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10595299 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6961029 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1833098 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512595 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19043 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13623 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 239398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 420347 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 659745 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56634449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10087078 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 517300 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1266953 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9965004 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 682330 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63888752 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 694377 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10482106 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6925475 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1810071 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 511236 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18909 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 204344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411597 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615941 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56420713 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10029634 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467566 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3558099 # number of nop insts executed -system.cpu.iew.exec_refs 16729501 # number of memory reference insts executed -system.cpu.iew.exec_branches 8966109 # Number of branches executed -system.cpu.iew.exec_stores 6642423 # Number of stores executed -system.cpu.iew.exec_rate 0.518007 # Inst execution rate -system.cpu.iew.wb_sent 56249945 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56126682 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27860065 # num instructions producing a value -system.cpu.iew.wb_consumers 37718288 # num instructions consuming a value +system.cpu.iew.exec_nop 3530593 # number of nop insts executed +system.cpu.iew.exec_refs 16658677 # number of memory reference insts executed +system.cpu.iew.exec_branches 8937468 # Number of branches executed +system.cpu.iew.exec_stores 6629043 # Number of stores executed +system.cpu.iew.exec_rate 0.518254 # Inst execution rate +system.cpu.iew.wb_sent 56060470 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55945814 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27785553 # num instructions producing a value +system.cpu.iew.wb_consumers 37633865 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.513362 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738635 # average fanout of values written-back +system.cpu.iew.wb_rate 0.513891 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738313 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80002698 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7580888 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 664978 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 571532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79560296 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.706241 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.634825 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59120920 73.90% 73.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1525301 1.91% 95.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 612184 0.77% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 529748 0.66% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 518714 0.65% 97.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58754657 73.85% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8628270 10.84% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4624578 5.81% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2529268 3.18% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1515738 1.91% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 609533 0.77% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 524421 0.66% 97.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 524312 0.66% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1849519 2.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80002698 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56184240 # Number of instructions committed -system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79560296 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56188709 # Number of instructions committed +system.cpu.commit.committedOps 56188709 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15475347 # Number of memory references committed -system.cpu.commit.loads 9094466 # Number of loads committed -system.cpu.commit.membars 226347 # Number of memory barriers committed -system.cpu.commit.branches 8447798 # Number of branches committed +system.cpu.commit.refs 15476798 # Number of memory references committed +system.cpu.commit.loads 9095345 # Number of loads committed +system.cpu.commit.membars 226320 # Number of memory barriers committed +system.cpu.commit.branches 8447896 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52030338 # Number of committed integer instructions. -system.cpu.commit.function_calls 740415 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52034633 # Number of committed integer instructions. +system.cpu.commit.function_calls 740447 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1849519 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 142220969 # The number of ROB reads -system.cpu.rob.rob_writes 129940455 # The number of ROB writes -system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27974647 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52993965 # Number of Instructions Simulated -system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52993965 # Number of Instructions Simulated -system.cpu.cpi 2.063094 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.063094 # CPI: Total CPI of All Threads -system.cpu.ipc 0.484709 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.484709 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74218754 # number of integer regfile reads -system.cpu.int_regfile_writes 40498790 # number of integer regfile writes -system.cpu.fp_regfile_reads 166070 # number of floating regfile reads -system.cpu.fp_regfile_writes 167447 # number of floating regfile writes -system.cpu.misc_regfile_reads 1994018 # number of misc regfile reads -system.cpu.misc_regfile_writes 947042 # number of misc regfile writes +system.cpu.rob.rob_reads 141230883 # The number of ROB reads +system.cpu.rob.rob_writes 128808067 # The number of ROB writes +system.cpu.timesIdled 1177683 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28039732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599825806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52998188 # Number of Instructions Simulated +system.cpu.committedOps 52998188 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52998188 # Number of Instructions Simulated +system.cpu.cpi 2.054164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.054164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.486816 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.486816 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73962724 # number of integer regfile reads +system.cpu.int_regfile_writes 40347354 # number of integer regfile writes +system.cpu.fp_regfile_reads 166024 # number of floating regfile reads +system.cpu.fp_regfile_writes 167429 # number of floating regfile writes +system.cpu.misc_regfile_reads 1993125 # number of misc regfile reads +system.cpu.misc_regfile_writes 947074 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -634,355 +634,189 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1020188 # number of replacements -system.cpu.icache.tagsinuse 510.304097 # Cycle average of tags in use -system.cpu.icache.total_refs 7717774 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1020696 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.561286 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20124452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.304097 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996688 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7717775 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7717775 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7717775 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7717775 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7717775 # number of overall hits -system.cpu.icache.overall_hits::total 7717775 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1079494 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079494 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1079494 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079494 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1079494 # number of overall misses -system.cpu.icache.overall_misses::total 1079494 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14680685994 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14680685994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14680685994 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14680685994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14680685994 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14680685994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8797269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8797269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8797269 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8797269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8797269 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8797269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122708 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122708 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122708 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122708 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122708 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122708 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13599.599436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13599.599436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13599.599436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13599.599436 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3410 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 686 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.icache.replacements 1012720 # number of replacements +system.cpu.icache.tagsinuse 510.299473 # Cycle average of tags in use +system.cpu.icache.total_refs 7548318 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1013228 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.449772 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 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accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15212789 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15212789 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15212789 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15212789 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315902 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.315902 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.246054 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.246054 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.246054 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.535074 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.535074 # 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ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.145811 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.145811 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 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ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20300279500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21216496500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20300279500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21216496500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 841139 # number of Writeback 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# miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.537313 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.537313 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383388 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383388 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014836 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277427 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166828 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014836 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277427 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166828 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60500.330164 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43102.806554 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 300911 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 300911 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1013328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1401377 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2414705 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1013328 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1401377 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2414705 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014915 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248845 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136702 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.580645 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.580645 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383522 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383522 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014915 # miss rate for demand accesses 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73670.415427 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.415427 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52473.218658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52473.218658 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74530.267057 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74530.267057 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52679.480965 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52679.480965 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -991,80 +825,72 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75796 # number of writebacks -system.cpu.l2cache.writebacks::total 75796 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75966 # number of writebacks +system.cpu.l2cache.writebacks::total 75966 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 289002 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273846 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288959 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115327 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115327 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389186 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389186 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404329 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725022440 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8259922361 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8984944801 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115406 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115406 # number of ReadExReq MSHR misses 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system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067947103 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067947103 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327869464 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16052891904 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327869464 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16052891904 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333831000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333831000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882540500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882540500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216371500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216371500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.537313 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.537313 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383388 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383388 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.166828 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.166828 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47878.388694 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30161.222969 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31089.559245 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7172240815 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7172240815 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 718571789 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15419461076 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16138032865 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 718571789 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15419461076 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16138032865 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333809500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333809500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882195500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882195500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216005000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216005000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248845 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.580645 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.580645 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383522 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383522 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167459 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167459 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47546.601535 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30116.270681 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31027.903786 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.143774 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.143774 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62147.902319 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62147.902319 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1072,29 +898,191 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1400783 # number of replacements +system.cpu.dcache.tagsinuse 511.995190 # Cycle average of tags in use +system.cpu.dcache.total_refs 11827578 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401295 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.440463 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21532000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995190 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7213661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7213661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203894 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203894 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 190181 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 190181 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 219613 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219613 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11417555 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11417555 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11417555 # number of overall hits +system.cpu.dcache.overall_hits::total 11417555 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1801125 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1801125 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1943246 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1943246 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3744371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3744371 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3744371 # number of overall misses +system.cpu.dcache.overall_misses::total 3744371 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33805478000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33805478000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 71113991647 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 71113991647 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303653500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 303653500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104919469647 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104919469647 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104919469647 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104919469647 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9014786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9014786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147140 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147140 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 212866 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 212866 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 219615 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219615 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15161926 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15161926 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15161926 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15161926 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199797 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199797 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316122 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.106569 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.106569 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246959 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246959 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246959 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246959 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18769.090430 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18769.090430 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36595.465344 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36595.465344 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13385.651311 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13385.651311 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28020.586007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28020.586007 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2640119 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 587 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95652 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.601294 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.375000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 840489 # number of writebacks +system.cpu.dcache.writebacks::total 840489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717559 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 717559 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642936 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642936 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2360495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2360495 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2360495 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2360495 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083566 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083566 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300310 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300310 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17562 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17562 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383876 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383876 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383876 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383876 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21170477000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21170477000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10817290277 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10817290277 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199800500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199800500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31987767277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31987767277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31987767277 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31987767277 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423886500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423886500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997350998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997350998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421237498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421237498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120199 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120199 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082503 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082503 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19537.782655 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19537.782655 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36020.413163 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36020.413163 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11376.864822 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.864822 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211013 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 210973 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74651 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105569 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105545 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182205 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73284 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818451122500 98.06% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64044500 0.00% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561305000 0.03% 98.10% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35293166500 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854369638500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73284 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148577 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818516202000 98.07% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64252000 0.00% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 558035000 0.03% 98.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35210286000 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854348775000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694295 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694339 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1133,29 +1121,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175126 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175092 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191972 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 191934 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326778 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29748704000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2690261500 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1821930665000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394590 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29709775500 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2660669000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1821978322500 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index f66d752af..219ef17ea 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -8,13 +8,14 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -39,7 +40,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +70,7 @@ read_only=true [system.cpu] type=DerivO3CPU -children=checker dcache dtb fuPool icache interrupts itb tracer +children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -167,7 +168,7 @@ icache_port=system.cpu.icache.cpu_side type=O3Checker children=dtb itb tracer checker=Null -clock=1 +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -200,10 +201,10 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[5] +port=system.cpu.toL2Bus.slave[5] [system.cpu.checker.itb] type=ArmTLB @@ -213,10 +214,10 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[4] +port=system.cpu.toL2Bus.slave[4] [system.cpu.checker.tracer] type=ExeTracer @@ -226,10 +227,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -237,7 +238,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -246,7 +247,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -256,10 +257,10 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -529,10 +530,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -540,7 +541,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -549,7 +550,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -562,10 +563,47 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -589,18 +627,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -611,33 +649,6 @@ write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -hit_latency=10000 -is_top_level=false -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -648,11 +659,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -668,15 +679,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -691,7 +715,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -700,7 +724,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -747,7 +771,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -778,7 +802,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -787,7 +811,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -804,7 +828,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -818,7 +842,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -828,7 +852,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -838,7 +862,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -848,7 +872,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -862,7 +886,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -875,7 +899,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -904,7 +928,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -914,7 +938,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -926,7 +950,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -938,7 +962,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -951,7 +975,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -961,7 +985,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -971,7 +995,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -981,7 +1005,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -991,7 +1015,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1005,7 +1029,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1018,7 +1042,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -1033,7 +1057,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1043,7 +1067,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1053,7 +1077,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1063,7 +1087,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1077,16 +1101,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port - [system.vncserver] type=VncServer frame_capture=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 3e85e4166..2082cdfd9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,34 +10,27 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 6471379000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 -warn: 6479236500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6488789500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6527432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6543641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 7089434000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 -warn: 12809896500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 12854316500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 13169361500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 14424922500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 14474529500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 15519752500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 15669382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 5946987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 5954355500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5963229500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5999905500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6015449500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 warn: LCD dual screen mode not supported -warn: 54391557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 51801575500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: 816692532000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -warn: 2486377425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2500398254500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2501706856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2523057678500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2523647855500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2529994034500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2530576345500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2531219324500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2531220454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2473940227500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2487729164500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2488940395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2503139484500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2510001697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2510516362000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2516240346500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2516753495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2517315503000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2517316610000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2517867351500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 5011d2336..a3de8bb34 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:35:22 +gem5 compiled Nov 1 2012 15:18:10 +gem5 started Nov 2 2012 01:09:00 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2537929870500 because m5_exit instruction encountered +Exiting @ tick 2523500318000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 3725b6e15..a24f5a985 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523629 # Number of seconds simulated -sim_ticks 2523629285500 # Number of ticks simulated -final_tick 2523629285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523500 # Number of seconds simulated +sim_ticks 2523500318000 # Number of ticks simulated +final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68763 # Simulator instruction rate (inst/s) -host_op_rate 88448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2863680529 # Simulator tick rate (ticks/s) -host_mem_usage 399792 # Number of bytes of host memory used -host_seconds 881.25 # Real time elapsed on the host -sim_insts 60597236 # Number of instructions simulated -sim_ops 77945371 # Number of ops (including micro ops) simulated +host_inst_rate 54734 # Simulator instruction rate (inst/s) +host_op_rate 70403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2279341302 # Simulator tick rate (ticks/s) +host_mem_usage 401036 # Number of bytes of host memory used +host_seconds 1107.12 # Real time elapsed on the host +sim_insts 60596849 # Number of instructions simulated +sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory -system.physmem.bytes_read::total 129436176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800520 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12488 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096906 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59132 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813150 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47367363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51289695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47367363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096906 # Total number of read requests seen -system.physmem.writeReqs 813150 # Total number of write requests seen -system.physmem.cpureqs 218484 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966201984 # Total number of bytes read from memory -system.physmem.bytesWritten 52041600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129436176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 390 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943634 # Track reads on a per bank basis +system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096860 # Total number of read requests seen +system.physmem.writeReqs 813144 # Total number of write requests seen +system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966199040 # Total number of bytes read from memory +system.physmem.bytesWritten 52041216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50102 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1156336 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523628152000 # Total gap between requests +system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523499110500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154662 # Categorize read packet sizes +system.physmem.readPktSize::6 154616 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1910354 # categorize write packet sizes +system.physmem.writePktSize::2 1907897 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59132 # categorize write packet sizes +system.physmem.writePktSize::6 59126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +117,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4690 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14955823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -176,37 +176,37 @@ system.physmem.wrQLenPdf::19 35354 # Wh system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 46839255594 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 317495505594 # Sum of mem lat for all requests -system.physmem.totBusLat 60386064000 # Total cycles spent in databus access -system.physmem.totBankLat 210270186000 # Total cycles spent in bank access -system.physmem.avgQLat 3102.65 # Average queueing delay per request -system.physmem.avgBankLat 13928.39 # Average bank access latency per request +system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests +system.physmem.totBusLat 60386104000 # Total cycles spent in databus access +system.physmem.totBankLat 210282128000 # Total cycles spent in bank access +system.physmem.avgQLat 3116.78 # Average queueing delay per request +system.physmem.avgBankLat 13929.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21031.04 # Average memory access latency -system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 21045.95 # Average memory access latency +system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 13.20 # Average write queue length over time -system.physmem.readRowHits 15050623 # Number of row buffer hits during reads -system.physmem.writeRowHits 784578 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.49 # Row buffer hit rate for writes -system.physmem.avgGap 158618.43 # Average gap between requests +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 15049962 # Number of row buffer hits during reads +system.physmem.writeRowHits 784769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes +system.physmem.avgGap 158610.84 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048943 # DTB read hits -system.cpu.checker.dtb.read_misses 7309 # DTB read misses -system.cpu.checker.dtb.write_hits 11294215 # DTB write hits +system.cpu.checker.dtb.read_hits 15048842 # DTB read hits +system.cpu.checker.dtb.read_misses 7308 # DTB read misses +system.cpu.checker.dtb.write_hits 11294147 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15056252 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296404 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056150 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296336 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26343158 # DTB hits -system.cpu.checker.dtb.misses 9498 # DTB misses -system.cpu.checker.dtb.accesses 26352656 # DTB accesses -system.cpu.checker.itb.inst_hits 61775988 # ITB inst hits +system.cpu.checker.dtb.hits 26342989 # DTB hits +system.cpu.checker.dtb.misses 9497 # DTB misses +system.cpu.checker.dtb.accesses 26352486 # DTB accesses +system.cpu.checker.itb.inst_hits 61775601 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -263,36 +263,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61780459 # ITB inst accesses -system.cpu.checker.itb.hits 61775988 # DTB hits +system.cpu.checker.itb.inst_accesses 61780072 # ITB inst accesses +system.cpu.checker.itb.hits 61775601 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61780459 # DTB accesses -system.cpu.checker.numCycles 78235930 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61780072 # DTB accesses +system.cpu.checker.numCycles 78235487 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51393832 # DTB read hits -system.cpu.dtb.read_misses 77273 # DTB read misses -system.cpu.dtb.write_hits 11807513 # DTB write hits -system.cpu.dtb.write_misses 17284 # DTB write misses +system.cpu.dtb.read_hits 51279526 # DTB read hits +system.cpu.dtb.read_misses 73667 # DTB read misses +system.cpu.dtb.write_hits 11753863 # DTB write hits +system.cpu.dtb.write_misses 17234 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7715 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2923 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 497 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7683 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51471105 # DTB read accesses -system.cpu.dtb.write_accesses 11824797 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51353193 # DTB read accesses +system.cpu.dtb.write_accesses 11771097 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63201345 # DTB hits -system.cpu.dtb.misses 94557 # DTB misses -system.cpu.dtb.accesses 63295902 # DTB accesses -system.cpu.itb.inst_hits 11866090 # ITB inst hits -system.cpu.itb.inst_misses 12256 # ITB inst misses +system.cpu.dtb.hits 63033389 # DTB hits +system.cpu.dtb.misses 90901 # DTB misses +system.cpu.dtb.accesses 63124290 # DTB accesses +system.cpu.itb.inst_hits 11603865 # ITB inst hits +system.cpu.itb.inst_misses 11359 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -301,538 +301,538 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5202 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5142 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3056 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11878346 # ITB inst accesses -system.cpu.itb.hits 11866090 # DTB hits -system.cpu.itb.misses 12256 # DTB misses -system.cpu.itb.accesses 11878346 # DTB accesses -system.cpu.numCycles 471617242 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11615224 # ITB inst accesses +system.cpu.itb.hits 11603865 # DTB hits +system.cpu.itb.misses 11359 # DTB misses +system.cpu.itb.accesses 11615224 # DTB accesses +system.cpu.numCycles 470951029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14707934 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11701482 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783806 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9735591 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7867248 # Number of BTB hits +system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454059 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82839 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30177247 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91949952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14707934 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9321307 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20604105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4981007 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133002 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96623906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 100214 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208761 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11862293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 731589 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6461 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.758817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.115765 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130696614 86.39% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382439 0.91% 87.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755242 1.16% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2339470 1.55% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2142585 1.42% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1134296 0.75% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2618835 1.73% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 784869 0.52% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8429565 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.194967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32009474 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96255861 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18724959 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031397 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3262224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2019817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174593 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 109260478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576218 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3262224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33806773 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36827261 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53335707 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17902220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6149730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 104066052 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21507 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4119258 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31916 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107817309 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 475022232 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 474932056 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90176 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 29086099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 892462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797997 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12333143 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20063520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13521808 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973034 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2429271 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 96511584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2058662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123961862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189585 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20013916 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 50091772 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151283915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531663 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106904579 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13863783 9.16% 79.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7099546 4.69% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5863279 3.88% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12474907 8.25% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2771705 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1719952 1.14% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 458027 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128137 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151283915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57031 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8373952 94.62% 95.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 418898 4.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58283800 47.02% 47.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95201 0.08% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52766411 42.57% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12450621 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123961862 # Type of FU issued -system.cpu.iq.rate 0.262844 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8849884 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071392 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408318037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118600535 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86285351 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12408 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10278 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132435732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12348 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 629942 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued +system.cpu.iq.rate 0.261997 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4347483 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7997 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29897 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1723272 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34108218 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 695964 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3262224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27920683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98794824 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232558 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20063520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13521808 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467094 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29897 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 410015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293518 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703533 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121755337 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081116 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2206525 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224578 # number of nop insts executed -system.cpu.iew.exec_refs 64400589 # number of memory reference insts executed -system.cpu.iew.exec_branches 11599904 # Number of branches executed -system.cpu.iew.exec_stores 12319473 # Number of stores executed -system.cpu.iew.exec_rate 0.258166 # Inst execution rate -system.cpu.iew.wb_sent 120729614 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86295629 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47354389 # num instructions producing a value -system.cpu.iew.wb_consumers 88420573 # num instructions consuming a value +system.cpu.iew.exec_nop 220747 # number of nop insts executed +system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed +system.cpu.iew.exec_branches 11527542 # Number of branches executed +system.cpu.iew.exec_stores 12265452 # Number of stores executed +system.cpu.iew.exec_rate 0.257499 # Inst execution rate +system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47162688 # num instructions producing a value +system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182978 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535558 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19868776 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544514 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612308 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148104118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.512767 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120332893 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13565443 9.16% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3964002 2.68% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135941 1.44% 94.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1954116 1.32% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973664 0.66% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1592335 1.08% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730104 0.49% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2855620 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148104118 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747617 # Number of instructions committed -system.cpu.commit.committedOps 78095752 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747230 # Number of instructions committed +system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514573 # Number of memory references committed -system.cpu.commit.loads 15716037 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023091 # Number of branches committed +system.cpu.commit.refs 27514399 # Number of memory references committed +system.cpu.commit.loads 15715935 # Number of loads committed +system.cpu.commit.membars 413101 # Number of memory barriers committed +system.cpu.commit.branches 10023041 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134185 # Number of committed integer instructions. -system.cpu.commit.function_calls 995980 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2855620 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. +system.cpu.commit.function_calls 995976 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 241297904 # The number of ROB reads -system.cpu.rob.rob_writes 199283253 # The number of ROB writes -system.cpu.timesIdled 1774711 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320333327 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575553300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597236 # Number of Instructions Simulated -system.cpu.committedOps 77945371 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597236 # Number of Instructions Simulated -system.cpu.cpi 7.782818 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.782818 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551506178 # number of integer regfile reads -system.cpu.int_regfile_writes 88407138 # number of integer regfile writes -system.cpu.fp_regfile_reads 8339 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 124072221 # number of misc regfile reads -system.cpu.misc_regfile_writes 912903 # number of misc regfile writes -system.cpu.icache.replacements 990875 # number of replacements -system.cpu.icache.tagsinuse 510.405236 # Cycle average of tags in use -system.cpu.icache.total_refs 10787830 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991387 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.881553 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.405236 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996885 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996885 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10787830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10787830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10787830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10787830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10787830 # number of overall hits -system.cpu.icache.overall_hits::total 10787830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1074333 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1074333 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1074333 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1074333 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1074333 # number of overall misses -system.cpu.icache.overall_misses::total 1074333 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14125562486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14125562486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14125562486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14125562486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11862163 # number of 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(read+write) accesses -system.cpu.dcache.overall_accesses::total 24890517 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 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# average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29089 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14501 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2531 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.493086 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57.543651 # average number of cycles each access was blocked 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731455 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses +system.cpu.dcache.overall_misses::total 3692032 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses 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13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked 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LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3055404 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3055404 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387237 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387237 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249136 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249136 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636373 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636373 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks +system.cpu.dcache.writebacks::total 607749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits 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misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses 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11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average 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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963877530 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166968222685 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18087556027 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18087556027 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185051433557 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185055778712 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.091162 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.091162 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40728.085356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42384.203091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41521.299263 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.246744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.246744 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37865.660886 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37865.660886 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38490.213011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38490.213011 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1117,16 +1117,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1068163777856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88030 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index f00ea7875..966a7a822 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,9 +12,10 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -23,7 +24,6 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +39,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +69,7 @@ read_only=true [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -117,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -168,10 +169,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -179,7 +180,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -198,7 +199,7 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -471,10 +472,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -482,7 +483,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -496,6 +497,23 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=ArmInterrupts +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu0.itb] type=ArmTLB children=walker @@ -504,7 +522,7 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -514,7 +532,7 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -562,6 +580,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -613,10 +632,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -624,7 +643,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -643,7 +662,7 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -916,10 +935,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -927,7 +946,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -941,6 +960,23 @@ mem_side=system.toL2Bus.slave[4] [system.cpu1.interrupts] type=ArmInterrupts +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu1.itb] type=ArmTLB children=walker @@ -949,7 +985,7 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -976,18 +1012,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -1003,22 +1039,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -1039,7 +1075,7 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1055,15 +1091,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -1078,7 +1127,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -1087,7 +1136,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1134,7 +1183,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -1165,7 +1214,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1174,7 +1223,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1191,7 +1240,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -1205,7 +1254,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1215,7 +1264,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1225,7 +1274,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1235,7 +1284,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1249,7 +1298,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1262,7 +1311,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1291,7 +1340,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1301,7 +1350,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -1313,7 +1362,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1325,7 +1374,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1338,7 +1387,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1348,7 +1397,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1358,7 +1407,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1368,7 +1417,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1378,7 +1427,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1392,7 +1441,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1405,7 +1454,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -1420,7 +1469,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1430,7 +1479,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1440,7 +1489,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1450,7 +1499,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1467,7 +1516,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 04178bb32..e8e271d58 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 4c598b20c..ac731cab9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:18:35 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 21:14:52 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2616878893500 because m5_exit instruction encountered +Exiting @ tick 2593146078000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 30d23f9d7..2681ab283 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,131 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603317 # Number of seconds simulated -sim_ticks 2603316759000 # Number of ticks simulated -final_tick 2603316759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.593146 # Number of seconds simulated +sim_ticks 2593146078000 # Number of ticks simulated +final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64170 # Simulator instruction rate (inst/s) -host_op_rate 82590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2648964509 # Simulator tick rate (ticks/s) -host_mem_usage 407980 # Number of bytes of host memory used -host_seconds 982.77 # Real time elapsed on the host -sim_insts 63063787 # Number of instructions simulated -sim_ops 81167171 # Number of ops (including micro ops) simulated +host_inst_rate 66425 # Simulator instruction rate (inst/s) +host_op_rate 85503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2731005239 # Simulator tick rate (ticks/s) +host_mem_usage 409388 # Number of bytes of host memory used +host_seconds 949.52 # Real time elapsed on the host +sim_insts 63072130 # Number of instructions simulated +sim_ops 81187111 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 396352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4375860 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5260720 # Number of bytes read from this memory -system.physmem.bytes_read::total 131570852 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 396352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4284288 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 395328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4376500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 426752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5261232 # Number of bytes read from this memory +system.physmem.bytes_read::total 131572388 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 426752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4282048 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7313424 # Number of bytes written to this memory +system.physmem.bytes_written::total 7311184 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6193 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6647 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302357 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66942 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82233 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302381 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66907 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824226 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46521626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 320 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 824191 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46704090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 152249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1680879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2020776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50539702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 152249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163410 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1645704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1157038 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2809272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1645704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46521626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 152451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1687718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2028899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50738518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 152451 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164569 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1651295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1161576 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2819426 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1651295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46704090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 152249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1687409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3177814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53348973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302357 # Total number of read requests seen -system.physmem.writeReqs 824226 # Total number of write requests seen -system.physmem.cpureqs 284853 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979350848 # Total number of bytes read from memory -system.physmem.bytesWritten 52750464 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131570852 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7313424 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 375 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14171 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956419 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956561 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956521 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955968 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 957003 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 956395 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 956361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 956664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 956494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956128 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955882 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50798 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51080 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50753 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50993 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51530 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51645 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51480 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 152451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1694274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3190475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53557944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302381 # Total number of read requests seen +system.physmem.writeReqs 824191 # Total number of write requests seen +system.physmem.cpureqs 284713 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 979352384 # Total number of bytes read from memory +system.physmem.bytesWritten 52748224 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131572388 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7311184 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 335 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 14131 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956528 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956655 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 956404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956499 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956473 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 956086 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956080 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 957009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 956354 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 956393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 956606 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956350 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 956542 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955941 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50933 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51869 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51569 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51383 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51546 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52151 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51788 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51735 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51546 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1152088 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603315545500 # Total gap between requests +system.physmem.numWrRetry 1150487 # Number of times wr buffer was full causing retry +system.physmem.totGap 2593144762500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163436 # Categorize read packet sizes +system.physmem.readPktSize::6 163460 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1909372 # categorize write packet sizes +system.physmem.writePktSize::2 1907771 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66942 # categorize write packet sizes +system.physmem.writePktSize::6 66907 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,29 +138,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 14171 # categorize neither packet sizes +system.physmem.neitherpktsize::6 14131 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 15151636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 94017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15151641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 94331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -170,60 +174,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31249 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 48061683883 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 322412499883 # Sum of mem lat for all requests -system.physmem.totBusLat 61207928000 # Total cycles spent in databus access -system.physmem.totBankLat 213142888000 # Total cycles spent in bank access -system.physmem.avgQLat 3140.88 # Average queueing delay per request -system.physmem.avgBankLat 13929.10 # Average bank access latency per request +system.physmem.totQLat 47868619345 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 322210199345 # Sum of mem lat for all requests +system.physmem.totBusLat 61208184000 # Total cycles spent in databus access +system.physmem.totBankLat 213133396000 # Total cycles spent in bank access +system.physmem.avgQLat 3128.25 # Average queueing delay per request +system.physmem.avgBankLat 13928.42 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21069.98 # Average memory access latency -system.physmem.avgRdBW 376.19 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 21056.67 # Average memory access latency +system.physmem.avgRdBW 377.67 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.34 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.82 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.48 # Data bus utilization in percentage +system.physmem.busUtil 2.49 # Data bus utilization in percentage system.physmem.avgRdQLen 0.12 # Average read queue length over time -system.physmem.avgWrQLen 11.94 # Average write queue length over time -system.physmem.readRowHits 15253098 # Number of row buffer hits during reads -system.physmem.writeRowHits 789391 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.88 # Average write queue length over time +system.physmem.readRowHits 15253448 # Number of row buffer hits during reads +system.physmem.writeRowHits 789566 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 95.77 # Row buffer hit rate for writes -system.physmem.avgGap 161430.08 # Average gap between requests +system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes +system.physmem.avgGap 160799.50 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -235,244 +239,258 @@ system.realview.nvmem.num_reads::cpu1.inst 6 # system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 173 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 173 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 73153 # number of replacements -system.l2c.tagsinuse 53083.361452 # Cycle average of tags in use -system.l2c.total_refs 1922203 # Total number of references to valid blocks. -system.l2c.sampled_refs 138333 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.895477 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::total 173 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 73184 # number of replacements +system.l2c.tagsinuse 53096.266008 # Cycle average of tags in use +system.l2c.total_refs 1906265 # Total number of references to valid blocks. +system.l2c.sampled_refs 138351 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.778469 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37742.975736 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 6.244346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.876765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4208.985983 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2954.129199 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.276001 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4048.165548 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4110.707874 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575912 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000095 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064224 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000172 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061770 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062724 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809988 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 35828 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5516 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 398518 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165446 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 53941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6316 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 614017 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 202060 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1481642 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 584379 # number of Writeback hits -system.l2c.Writeback_hits::total 584379 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1214 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1952 # number of UpgradeReq hits +system.l2c.occ_blocks::writebacks 37733.790025 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 7.219153 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4206.047810 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2960.317078 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.178862 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.966447 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4058.933416 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4117.812877 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575772 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000110 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.064179 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.045171 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000171 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061934 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062833 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.810185 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 33579 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 393016 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 165084 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 53008 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6038 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 608232 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 201468 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1465388 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 583960 # number of Writeback hits +system.l2c.Writeback_hits::total 583960 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1107 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 848 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1955 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 156 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47923 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58901 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106824 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 35828 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5516 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 398518 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 213369 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 53941 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6316 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 614017 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260961 # number of demand (read+write) hits -system.l2c.demand_hits::total 1588466 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 35828 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5516 # number of overall hits -system.l2c.overall_hits::cpu0.inst 398518 # number of overall hits -system.l2c.overall_hits::cpu0.data 213369 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 53941 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6316 # number of overall hits -system.l2c.overall_hits::cpu1.inst 614017 # number of overall hits -system.l2c.overall_hits::cpu1.data 260961 # number of overall hits -system.l2c.overall_hits::total 1588466 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 368 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47823 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59123 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106946 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 33579 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 393016 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 212907 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 53008 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6038 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 608232 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260591 # number of demand (read+write) hits +system.l2c.demand_hits::total 1572334 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 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overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -665,27 +695,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9063545 # DTB read hits -system.cpu0.dtb.read_misses 36220 # DTB read misses -system.cpu0.dtb.write_hits 5280653 # DTB write hits -system.cpu0.dtb.write_misses 6480 # DTB write misses +system.cpu0.dtb.read_hits 9014303 # DTB read hits +system.cpu0.dtb.read_misses 34965 # DTB read misses +system.cpu0.dtb.write_hits 5253714 # DTB write hits +system.cpu0.dtb.write_misses 6399 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2158 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1224 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 336 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2155 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1094 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 321 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 569 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9099765 # DTB read accesses -system.cpu0.dtb.write_accesses 5287133 # DTB write accesses +system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9049268 # DTB read accesses +system.cpu0.dtb.write_accesses 5260113 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14344198 # DTB hits -system.cpu0.dtb.misses 42700 # DTB misses -system.cpu0.dtb.accesses 14386898 # DTB accesses -system.cpu0.itb.inst_hits 4425189 # ITB inst hits -system.cpu0.itb.inst_misses 5562 # ITB inst misses +system.cpu0.dtb.hits 14268017 # DTB hits +system.cpu0.dtb.misses 41364 # DTB misses +system.cpu0.dtb.accesses 14309381 # DTB accesses +system.cpu0.itb.inst_hits 4294311 # ITB inst hits +system.cpu0.itb.inst_misses 5261 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -694,542 +724,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1395 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1385 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1364 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4430751 # ITB inst accesses -system.cpu0.itb.hits 4425189 # DTB hits -system.cpu0.itb.misses 5562 # DTB misses -system.cpu0.itb.accesses 4430751 # DTB accesses -system.cpu0.numCycles 69436793 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4299572 # ITB inst accesses +system.cpu0.itb.hits 4294311 # DTB hits +system.cpu0.itb.misses 5261 # DTB misses +system.cpu0.itb.accesses 4299572 # DTB accesses +system.cpu0.numCycles 69013505 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6232893 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4743306 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 327822 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3788300 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3047807 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6123831 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4675790 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 298271 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3798227 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2989296 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 701189 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 31986 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12165372 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33223009 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6232893 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3748996 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7801748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1579515 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 70495 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21773574 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 55458 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 92257 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4423471 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 173760 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2652 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 43098147 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.994806 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.374305 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 685728 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 28375 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11998527 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32710943 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6123831 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3675024 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7667644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1480146 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66638 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21758305 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5862 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 53793 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 221 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4292744 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 155269 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2401 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42704543 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.988603 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.369673 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35304381 81.92% 81.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 609582 1.41% 83.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 823952 1.91% 85.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 710643 1.65% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 795409 1.85% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 570879 1.32% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 720960 1.67% 91.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 375620 0.87% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3186721 7.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35044149 82.06% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 606065 1.42% 83.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 793528 1.86% 85.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 689319 1.61% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 781424 1.83% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 567584 1.33% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 711320 1.67% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364019 0.85% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3147135 7.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 43098147 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.089764 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.478464 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12694368 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21733151 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7021973 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 580158 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1068497 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 974425 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66014 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41440720 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 216131 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1068497 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13283568 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5811502 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13763022 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6961604 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2209954 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40230567 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2204 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 441496 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1232571 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 70 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40628697 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 181762207 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 181727693 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34514 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31673882 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8954814 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 460934 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 417253 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5454618 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7893877 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5899231 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1129288 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1250491 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37987189 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 942287 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38211306 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88088 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6766776 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14417426 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 253739 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 43098147 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.886611 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.498890 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42704543 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088734 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.473979 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12497333 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21726841 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6896095 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 584636 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 999638 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 951812 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64726 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40836330 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213865 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 999638 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13071648 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5812993 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13759259 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6855374 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2205631 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39711904 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2173 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 427558 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1242268 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 68 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40116309 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 179435830 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 179401258 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34572 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31681024 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8435284 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 457771 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 414521 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5443309 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7819363 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5820332 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1146243 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1242216 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37575405 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 946067 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37951575 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82274 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6366228 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13456450 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257591 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42704543 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.888701 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.500077 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27429044 63.64% 63.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6069688 14.08% 77.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3249267 7.54% 85.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2519397 5.85% 91.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2120550 4.92% 96.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 959758 2.23% 98.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 504062 1.17% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 191517 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54864 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27159670 63.60% 63.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6000291 14.05% 77.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3232720 7.57% 85.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2489147 5.83% 91.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2132528 4.99% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 950123 2.22% 98.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 497063 1.16% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188710 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54291 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 43098147 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42704543 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25519 2.38% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 839951 78.37% 80.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 205830 19.20% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 24659 2.31% 2.31% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 467 0.04% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 838061 78.41% 80.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 205631 19.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52084 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22953142 60.07% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 49969 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 683 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9542960 24.97% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5612439 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22793341 60.06% 60.20% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48224 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9480747 24.98% 85.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5576214 14.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38211306 # Type of FU issued -system.cpu0.iq.rate 0.550303 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1071764 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028048 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 120714498 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45704259 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35275992 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8506 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4731 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3909 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39226540 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4446 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323503 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37951575 # Type of FU issued +system.cpu0.iq.rate 0.549915 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1068818 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028163 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119791525 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44895833 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35071497 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8304 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3884 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38963714 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4335 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 318123 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1474665 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3677 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13402 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 626328 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1396327 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2506 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13403 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 544501 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149439 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149359 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5385 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1068497 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4177933 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 101495 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39049116 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 95858 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7893877 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5899231 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 616112 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40709 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3360 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13402 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 173604 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 128122 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 301726 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37794024 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9381421 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 417282 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 999638 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4184428 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 103741 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38639126 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85944 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7819363 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5820332 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 614711 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 41414 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3290 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13403 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151339 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 119425 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 270764 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37563861 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9331167 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 387714 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119640 # number of nop insts executed -system.cpu0.iew.exec_refs 14935051 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4997979 # Number of branches executed -system.cpu0.iew.exec_stores 5553630 # Number of stores executed -system.cpu0.iew.exec_rate 0.544294 # Inst execution rate -system.cpu0.iew.wb_sent 37576425 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35279901 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18742857 # num instructions producing a value -system.cpu0.iew.wb_consumers 36023721 # num instructions consuming a value +system.cpu0.iew.exec_nop 117654 # number of nop insts executed +system.cpu0.iew.exec_refs 14857557 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4958494 # Number of branches executed +system.cpu0.iew.exec_stores 5526390 # Number of stores executed +system.cpu0.iew.exec_rate 0.544297 # Inst execution rate +system.cpu0.iew.wb_sent 37365472 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35075381 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18655901 # num instructions producing a value +system.cpu0.iew.wb_consumers 35819655 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.508087 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520292 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.508239 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520829 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6624150 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 688548 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 263048 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 42066039 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.760422 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.715065 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6205381 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 688476 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 234604 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41741265 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.766601 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.727877 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29990291 71.29% 71.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5984334 14.23% 85.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1979513 4.71% 90.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1007903 2.40% 92.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 802639 1.91% 94.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 528288 1.26% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 397543 0.95% 96.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 220589 0.52% 97.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1154939 2.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29720457 71.20% 71.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5963123 14.29% 85.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1948324 4.67% 90.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1002440 2.40% 92.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 789371 1.89% 94.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 520489 1.25% 95.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 393953 0.94% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 216687 0.52% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1186421 2.84% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 42066039 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24262669 # Number of instructions committed -system.cpu0.commit.committedOps 31987958 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41741265 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24264310 # Number of instructions committed +system.cpu0.commit.committedOps 31998915 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11692115 # Number of memory references committed -system.cpu0.commit.loads 6419212 # Number of loads committed -system.cpu0.commit.membars 234468 # Number of memory barriers committed -system.cpu0.commit.branches 4346825 # Number of branches committed +system.cpu0.commit.refs 11698867 # Number of memory references committed +system.cpu0.commit.loads 6423036 # Number of loads committed +system.cpu0.commit.membars 234373 # Number of memory barriers committed +system.cpu0.commit.branches 4346960 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28256367 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500017 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1154939 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28266871 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499893 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1186421 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 78638973 # The number of ROB reads -system.cpu0.rob.rob_writes 78294863 # The number of ROB writes -system.cpu0.timesIdled 365151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26338646 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5137152930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24181927 # Number of Instructions Simulated -system.cpu0.committedOps 31907216 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24181927 # Number of Instructions Simulated -system.cpu0.cpi 2.871433 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.871433 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348258 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348258 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176324047 # number of integer regfile reads -system.cpu0.int_regfile_writes 35061690 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads -system.cpu0.fp_regfile_writes 912 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47470625 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527597 # number of misc regfile writes -system.cpu0.icache.replacements 404775 # number of replacements -system.cpu0.icache.tagsinuse 511.602715 # Cycle average of tags in use -system.cpu0.icache.total_refs 3985323 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 405287 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.833335 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6841145000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.602715 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3985323 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3985323 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3985323 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3985323 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3985323 # number of overall hits -system.cpu0.icache.overall_hits::total 3985323 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 438012 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 438012 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 438012 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 438012 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 438012 # number of overall misses -system.cpu0.icache.overall_misses::total 438012 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5943655997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5943655997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5943655997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5943655997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5943655997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5943655997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4423335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4423335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4423335 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4423335 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4423335 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4423335 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099023 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099023 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099023 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099023 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099023 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099023 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13569.619090 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13569.619090 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13569.619090 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13569.619090 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2262 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77875275 # The number of ROB reads +system.cpu0.rob.rob_writes 77410136 # The number of ROB writes +system.cpu0.timesIdled 364830 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26308962 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5117234895 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24183568 # Number of Instructions Simulated +system.cpu0.committedOps 31918173 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24183568 # Number of Instructions Simulated +system.cpu0.cpi 2.853735 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.853735 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.350418 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.350418 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 175323075 # number of integer regfile reads +system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads +system.cpu0.fp_regfile_writes 906 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46878729 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes +system.cpu0.icache.replacements 399233 # number of replacements +system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use +system.cpu0.icache.total_refs 3861943 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 399745 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.661016 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6802423000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.592262 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999204 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999204 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3861943 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3861943 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3861943 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3861943 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3861943 # number of overall hits +system.cpu0.icache.overall_hits::total 3861943 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 430668 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 430668 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 430668 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 430668 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 430668 # number of overall misses +system.cpu0.icache.overall_misses::total 430668 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5857521993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5857521993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5857521993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5857521993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5857521993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5857521993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4292611 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4292611 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4292611 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4292611 # number of demand (read+write) accesses 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overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13601.015151 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13601.015151 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2687 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 131 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 157 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.267176 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.114650 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32710 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 32710 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 32710 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 32710 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 32710 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 32710 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405302 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 405302 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 405302 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 405302 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 405302 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 405302 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4852452498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4852452498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4852452498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4852452498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4852452498 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4852452498 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7399000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7399000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.091628 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.091628 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11972.436598 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30901 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30901 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30901 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30901 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30901 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30901 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399767 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 399767 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 399767 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 399767 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 399767 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 399767 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4790784994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4790784994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4790784994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4790784994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4790784994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4790784994 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093129 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093129 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093129 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11983.943132 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 274922 # number of replacements -system.cpu0.dcache.tagsinuse 477.004191 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9558639 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275434 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.703918 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 36505000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 477.004191 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.931649 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.931649 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5930824 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5930824 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3236437 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3236437 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174250 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174250 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171562 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171562 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9167261 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9167261 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9167261 # number of overall hits -system.cpu0.dcache.overall_hits::total 9167261 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 390293 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 390293 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1580955 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1580955 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7756 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7756 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1971248 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1971248 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1971248 # number of overall misses -system.cpu0.dcache.overall_misses::total 1971248 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5368045500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5368045500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61391771868 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 61391771868 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88103500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88103500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50615000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 50615000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66759817368 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66759817368 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66759817368 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66759817368 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6321117 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6321117 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4817392 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4817392 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183153 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183153 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179318 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179318 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11138509 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11138509 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11138509 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11138509 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.061744 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.061744 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328177 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.328177 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048610 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048610 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043253 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043253 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.176976 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.176976 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.176976 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.176976 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13753.886183 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13753.886183 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38832.080526 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38832.080526 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9895.933955 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9895.933955 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6525.915420 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6525.915420 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33866.777477 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33866.777477 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7897 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2466 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 585 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 72 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.499145 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 34.250000 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 274937 # number of replacements +system.cpu0.dcache.tagsinuse 481.181813 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9516256 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 275449 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.548160 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 481.181813 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.939808 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.939808 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5887183 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5887183 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3238358 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3238358 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173666 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 173666 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171542 # number of StoreCondReq hits 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cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 50475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66258676847 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66258676847 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66258676847 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66258676847 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6277949 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6277949 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820379 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4820379 # number of WriteReq accesses(hits+misses) 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13760.831290 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13760.831290 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38483.314600 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38483.314600 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9943.924707 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9943.924707 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6518.855741 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6518.855741 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33586.330834 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33586.330834 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8283 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3369 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 596 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.897651 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 41.085366 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255626 # number of writebacks -system.cpu0.dcache.writebacks::total 255626 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201523 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 201523 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449784 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1449784 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1651307 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1651307 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1651307 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1651307 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188770 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188770 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131171 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131171 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7755 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7755 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319941 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319941 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319941 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319941 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2338858500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2338858500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4087753491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4087753491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66408500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66408500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 35107000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 35107000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426611991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6426611991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426611991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6426611991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431962000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431962000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199718891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199718891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631680891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631680891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046054 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046054 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043247 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043247 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12389.990465 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12389.990465 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31163.545990 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31163.545990 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7872.969769 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7872.969769 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4527.014829 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4527.014829 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255577 # number of writebacks +system.cpu0.dcache.writebacks::total 255577 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202032 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202032 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450989 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1450989 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 498 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 498 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653021 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1653021 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653021 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1653021 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188734 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188734 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131032 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131032 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8374 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8374 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7739 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7739 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319766 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319766 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319766 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319766 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2333622500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2333622500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054127491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054127491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66245000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66245000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34997500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34997500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6387749991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6387749991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6387749991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6387749991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431600500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431600500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199905877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199905877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631506377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631506377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027183 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027183 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045875 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045875 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043166 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043166 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028812 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028812 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12364.611040 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12364.611040 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30939.980241 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30939.980241 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7910.795319 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7910.795319 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4522.225094 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4522.225094 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1239,27 +1265,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43093620 # DTB read hits -system.cpu1.dtb.read_misses 44212 # DTB read misses -system.cpu1.dtb.write_hits 7019560 # DTB write hits -system.cpu1.dtb.write_misses 11765 # DTB write misses +system.cpu1.dtb.read_hits 43030291 # DTB read hits +system.cpu1.dtb.read_misses 42638 # DTB read misses +system.cpu1.dtb.write_hits 6991861 # DTB write hits +system.cpu1.dtb.write_misses 11867 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3591 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2362 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2846 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43137832 # DTB read accesses -system.cpu1.dtb.write_accesses 7031325 # DTB write accesses +system.cpu1.dtb.perms_faults 690 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43072929 # DTB read accesses +system.cpu1.dtb.write_accesses 7003728 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50113180 # DTB hits -system.cpu1.dtb.misses 55977 # DTB misses -system.cpu1.dtb.accesses 50169157 # DTB accesses -system.cpu1.itb.inst_hits 7945263 # ITB inst hits -system.cpu1.itb.inst_misses 6054 # ITB inst misses +system.cpu1.dtb.hits 50022152 # DTB hits +system.cpu1.dtb.misses 54505 # DTB misses +system.cpu1.dtb.accesses 50076657 # DTB accesses +system.cpu1.itb.inst_hits 7786412 # ITB inst hits +system.cpu1.itb.inst_misses 5635 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1268,538 +1294,538 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1580 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1618 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7951317 # ITB inst accesses -system.cpu1.itb.hits 7945263 # DTB hits -system.cpu1.itb.misses 6054 # DTB misses -system.cpu1.itb.accesses 7951317 # DTB accesses -system.cpu1.numCycles 409430571 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7792047 # ITB inst accesses +system.cpu1.itb.hits 7786412 # DTB hits +system.cpu1.itb.misses 5635 # DTB misses +system.cpu1.itb.accesses 7792047 # DTB accesses +system.cpu1.numCycles 409024249 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9152257 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7432560 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 466867 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6195424 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5148293 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9020667 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7346445 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 421687 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 5902094 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5066087 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 835215 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50625 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 19713770 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 62254744 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9152257 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5983508 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13632356 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3573599 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 74747 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78115877 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 48120 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142516 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7943235 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 563949 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3459 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114180028 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.668662 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.999663 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 810235 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 44717 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 19548819 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61628162 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9020667 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5876322 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13445282 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3432135 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 71958 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78159434 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 48212 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 140837 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7784486 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 545452 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3066 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113770833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.663645 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.994153 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100555609 88.07% 88.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 838988 0.73% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1011000 0.89% 89.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1744900 1.53% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1443541 1.26% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 605100 0.53% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1974563 1.73% 94.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 445551 0.39% 95.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5560776 4.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100333102 88.19% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 820750 0.72% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 967014 0.85% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1722421 1.51% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1420935 1.25% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 598048 0.53% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1962596 1.73% 94.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 435893 0.38% 95.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5510074 4.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114180028 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022354 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.152052 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21120325 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77740288 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12430171 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 543608 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2345636 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1176073 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102892 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 72257305 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 341492 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2345636 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22356190 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32102348 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41268894 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11643477 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4463483 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 68190005 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19565 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 695237 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3171764 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33722 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 71496605 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 312933263 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 312874076 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59187 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50205657 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 21290948 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 480351 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 419670 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8129610 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13049293 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8227563 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1078580 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1518105 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 62664777 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1204533 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89464326 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 109059 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 14241211 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 38124625 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 284346 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114180028 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.783537 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.520062 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113770833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022054 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.150671 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20932611 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77783544 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12260401 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 543319 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2250958 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1146967 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100968 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71503765 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 336196 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2250958 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22152530 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32126143 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41276446 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11489660 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4475096 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67542275 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19496 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 697256 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3178756 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 32684 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70870880 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 310023883 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 309964693 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59190 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50213421 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20657459 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 473589 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 413624 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8131877 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12919526 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8160199 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1076421 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1515550 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 62172086 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1201080 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89161848 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 100982 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13762748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36926540 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 280453 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113770833 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.783697 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.520241 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83489742 73.12% 73.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8670086 7.59% 80.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4385231 3.84% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3749968 3.28% 87.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10493751 9.19% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1975559 1.73% 98.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1067200 0.93% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 270053 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 78438 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83205809 73.13% 73.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8622127 7.58% 80.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4341809 3.82% 84.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3750529 3.30% 87.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10472490 9.20% 97.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1973623 1.73% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1061651 0.93% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 265825 0.23% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 76970 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114180028 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113770833 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28685 0.36% 0.36% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 990 0.01% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7576734 95.92% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 292663 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29803 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 992 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7572506 95.90% 96.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 293239 3.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37676817 42.11% 42.46% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61442 0.07% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44006207 49.19% 91.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7404070 8.28% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37491969 42.05% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61148 0.07% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43923048 49.26% 91.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7369892 8.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89464326 # Type of FU issued -system.cpu1.iq.rate 0.218509 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7899072 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088293 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 301157769 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 78119517 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54662771 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14827 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8100 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 97041573 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7763 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 356788 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89161848 # Type of FU issued +system.cpu1.iq.rate 0.217987 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7896540 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088564 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300131429 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 77144913 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54450273 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14948 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8092 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6814 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96736439 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7887 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 357826 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3051550 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4387 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17666 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1202172 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2919371 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4089 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1133342 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965367 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 692896 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965401 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 692354 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2345636 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24201399 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 366318 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63975423 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 133542 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13049293 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8227563 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 893848 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67557 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17666 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 244185 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 171619 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 415804 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87650825 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43476570 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1813501 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2250958 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24192691 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 367138 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63477454 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 113697 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12919526 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8160199 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 893697 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 68960 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3858 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17660 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 208465 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 159370 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 367835 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87401818 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43412086 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1760030 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 106113 # number of nop insts executed -system.cpu1.iew.exec_refs 50801692 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7123929 # Number of branches executed -system.cpu1.iew.exec_stores 7325122 # Number of stores executed -system.cpu1.iew.exec_rate 0.214080 # Inst execution rate -system.cpu1.iew.wb_sent 86821194 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54669578 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30455976 # num instructions producing a value -system.cpu1.iew.wb_consumers 54432612 # num instructions consuming a value +system.cpu1.iew.exec_nop 104288 # number of nop insts executed +system.cpu1.iew.exec_refs 50709476 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7088545 # Number of branches executed +system.cpu1.iew.exec_stores 7297390 # Number of stores executed +system.cpu1.iew.exec_rate 0.213684 # Inst execution rate +system.cpu1.iew.wb_sent 86601126 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54457087 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30364436 # num instructions producing a value +system.cpu1.iew.wb_consumers 54295656 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.133526 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.559517 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.133139 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.559242 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14216299 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 920187 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 365862 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111882823 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.440904 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.409715 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13692554 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 920627 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 322274 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111568344 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.442227 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.413238 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94662436 84.61% 84.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8450873 7.55% 92.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2228797 1.99% 94.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1285384 1.15% 95.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1281795 1.15% 96.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 596967 0.53% 96.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1010034 0.90% 97.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 539540 0.48% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1826997 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94375668 84.59% 84.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8446118 7.57% 92.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2197127 1.97% 94.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1290727 1.16% 95.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1277171 1.14% 96.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 591366 0.53% 96.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1009730 0.91% 97.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 541366 0.49% 98.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1839071 1.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111882823 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38951499 # Number of instructions committed -system.cpu1.commit.committedOps 49329594 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111568344 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38958201 # Number of instructions committed +system.cpu1.commit.committedOps 49338577 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17023134 # Number of memory references committed -system.cpu1.commit.loads 9997743 # Number of loads committed -system.cpu1.commit.membars 202380 # Number of memory barriers committed -system.cpu1.commit.branches 6138522 # Number of branches committed +system.cpu1.commit.refs 17027012 # Number of memory references committed +system.cpu1.commit.loads 10000155 # Number of loads committed +system.cpu1.commit.membars 202531 # Number of memory barriers committed +system.cpu1.commit.branches 6139960 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43719778 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556453 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1826997 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43727423 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556605 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1839071 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172487010 # The number of ROB reads -system.cpu1.rob.rob_writes 129525616 # The number of ROB writes -system.cpu1.timesIdled 1423460 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295250543 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796554837 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38881860 # Number of Instructions Simulated -system.cpu1.committedOps 49259955 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38881860 # Number of Instructions Simulated -system.cpu1.cpi 10.530118 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.530118 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.094966 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.094966 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 392568937 # number of integer regfile reads -system.cpu1.int_regfile_writes 56802865 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4926 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes -system.cpu1.misc_regfile_reads 81929191 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429868 # number of misc regfile writes -system.cpu1.icache.replacements 620724 # number of replacements -system.cpu1.icache.tagsinuse 498.809985 # Cycle average of tags in use -system.cpu1.icache.total_refs 7273497 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 621236 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 11.708106 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74643061500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.809985 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974238 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974238 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7273497 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7273497 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7273497 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7273497 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7273497 # number of overall hits -system.cpu1.icache.overall_hits::total 7273497 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 669686 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 669686 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 669686 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 669686 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 669686 # number of overall misses -system.cpu1.icache.overall_misses::total 669686 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8966780496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8966780496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8966780496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8966780496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8966780496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8966780496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7943183 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7943183 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7943183 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7943183 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7943183 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7943183 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084310 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084310 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084310 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084310 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084310 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084310 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13389.529565 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13389.529565 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13389.529565 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13389.529565 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2782 # number of cycles access was blocked +system.cpu1.rob.rob_reads 171645222 # The number of ROB reads +system.cpu1.rob.rob_writes 128401309 # The number of ROB writes +system.cpu1.timesIdled 1423775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295253416 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4776625618 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38888562 # Number of Instructions Simulated +system.cpu1.committedOps 49268938 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38888562 # Number of Instructions Simulated +system.cpu1.cpi 10.517855 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.517855 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.095076 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.095076 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391481129 # number of integer regfile reads +system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes +system.cpu1.misc_regfile_reads 81326805 # number of misc regfile reads +system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes +system.cpu1.icache.replacements 614989 # number of replacements +system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use +system.cpu1.icache.total_refs 7122851 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 615501 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 11.572444 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74507010000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.619037 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.973865 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.973865 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7122851 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7122851 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7122851 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7122851 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7122851 # number of overall hits +system.cpu1.icache.overall_hits::total 7122851 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661583 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661583 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661583 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661583 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 661583 # number of overall misses +system.cpu1.icache.overall_misses::total 661583 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8883357995 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8883357995 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8883357995 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8883357995 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8883357995 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8883357995 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7784434 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7784434 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7784434 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7784434 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7784434 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7784434 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084988 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084988 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084988 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084988 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084988 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084988 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.427844 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13427.427844 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13427.427844 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13427.427844 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3547 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 195 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 182 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.266667 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.489011 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48404 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 48404 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 48404 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 48404 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 48404 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 48404 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 621282 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 621282 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 621282 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 621282 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 621282 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 621282 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328304997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328304997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328304997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7328304997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328304997 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7328304997 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2925000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2925000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2925000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2925000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078216 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for demand accesses 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overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363973 # number of replacements -system.cpu1.dcache.tagsinuse 487.193831 # Cycle average of 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LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14285 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10913 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10913 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1965918 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1965918 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1965918 # number of overall misses -system.cpu1.dcache.overall_misses::total 1965918 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6004176000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6004176000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64721170014 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 64721170014 # number of WriteReq miss cycles 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# miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.132198 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14966.960978 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14966.960978 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41361.828946 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41361.828946 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9294.189709 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9294.189709 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5374.919820 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5374.919820 # average StoreCondReq miss latency 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accesses +system.cpu1.dcache.overall_accesses::total 14810427 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044876 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044876 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267271 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.267271 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120811 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120811 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097843 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097843 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132823 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.132823 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132823 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.132823 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14998.048790 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14998.048790 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41277.190277 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41277.190277 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9254.903339 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9254.903339 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5381.191738 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5381.191738 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 35909.547784 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 35909.547784 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 28351 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 15005 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3227 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.785559 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 89.315476 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328753 # number of writebacks -system.cpu1.dcache.writebacks::total 328753 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169362 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 169362 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401575 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1401575 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1448 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1448 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1570937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1570937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570937 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1570937 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231800 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231800 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163181 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163181 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12837 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12837 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10908 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10908 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394981 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394981 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394981 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394981 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870952500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870952500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5312418211 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5312418211 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91073000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91073000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36840500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36840500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8183370711 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8183370711 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8183370711 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8183370711 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263287500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263287500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26961622519 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26961622519 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196224910019 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196224910019 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027869 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027869 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097634 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097634 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026561 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12385.472390 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12385.472390 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32555.372323 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32555.372323 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7094.570382 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7094.570382 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3377.383572 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3377.383572 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 328383 # number of writebacks +system.cpu1.dcache.writebacks::total 328383 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170419 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170419 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402227 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1402227 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572646 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1572646 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572646 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1572646 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231383 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231383 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163131 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163131 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10936 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10936 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394514 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394514 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394514 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394514 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870368000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870368000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5301094210 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5301094210 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90117500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90117500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37009000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37009000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8171462210 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8171462210 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8171462210 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8171462210 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263515000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263515000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26947906394 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26947906394 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196211421394 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196211421394 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025842 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025842 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108496 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108496 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097790 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097790 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026638 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026638 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12405.267457 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12405.267457 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32495.934004 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32495.934004 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7054.207436 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7054.207436 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3384.144111 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3384.144111 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1821,18 +1847,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1082331782222 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1082331782222 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1082174693399 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1082174693399 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43796 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43757 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53969 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index e428e398a..fbd26bc50 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -8,13 +8,14 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -23,7 +24,6 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +39,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +69,7 @@ read_only=true [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -117,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -168,10 +169,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -179,7 +180,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -188,7 +189,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -198,10 +199,10 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -471,10 +472,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -482,7 +483,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -491,11 +492,28 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -504,10 +522,47 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -531,18 +586,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -553,33 +608,6 @@ write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -hit_latency=10000 -is_top_level=false -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -590,11 +618,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -610,15 +638,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -633,7 +674,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -642,7 +683,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -689,7 +730,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -720,7 +761,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -729,7 +770,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -746,7 +787,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -760,7 +801,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -770,7 +811,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -780,7 +821,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -790,7 +831,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -804,7 +845,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -817,7 +858,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -846,7 +887,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -856,7 +897,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -868,7 +909,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -880,7 +921,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -893,7 +934,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -903,7 +944,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -913,7 +954,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -923,7 +964,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -933,7 +974,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -947,7 +988,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -960,7 +1001,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -975,7 +1016,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -985,7 +1026,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -995,7 +1036,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1005,7 +1046,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1019,16 +1060,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - [system.vncserver] type=VncServer frame_capture=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index affb69ad6..3ee89fc27 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -11,8 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 304caa505..e4320499c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:10:34 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 21:11:31 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2537929870500 because m5_exit instruction encountered +Exiting @ tick 2523500318000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 68a4a5e77..6a79df0e0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523629 # Number of seconds simulated -sim_ticks 2523629285500 # Number of ticks simulated -final_tick 2523629285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523500 # Number of seconds simulated +sim_ticks 2523500318000 # Number of ticks simulated +final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77702 # Simulator instruction rate (inst/s) -host_op_rate 99947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3235958193 # Simulator tick rate (ticks/s) -host_mem_usage 399788 # Number of bytes of host memory used -host_seconds 779.87 # Real time elapsed on the host -sim_insts 60597236 # Number of instructions simulated -sim_ops 77945371 # Number of ops (including micro ops) simulated +host_inst_rate 66325 # Simulator instruction rate (inst/s) +host_op_rate 85314 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2762063576 # Simulator tick rate (ticks/s) +host_mem_usage 400896 # Number of bytes of host memory used +host_seconds 913.63 # Real time elapsed on the host +sim_insts 60596849 # Number of instructions simulated +sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory -system.physmem.bytes_read::total 129436176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800520 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12488 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096906 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59132 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813150 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47367363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51289695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47367363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096906 # Total number of read requests seen -system.physmem.writeReqs 813150 # Total number of write requests seen -system.physmem.cpureqs 218484 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966201984 # Total number of bytes read from memory -system.physmem.bytesWritten 52041600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129436176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 390 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943634 # Track reads on a per bank basis +system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096860 # Total number of read requests seen +system.physmem.writeReqs 813144 # Total number of write requests seen +system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966199040 # Total number of bytes read from memory +system.physmem.bytesWritten 52041216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50102 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1156336 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523628152000 # Total gap between requests +system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523499110500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154662 # Categorize read packet sizes +system.physmem.readPktSize::6 154616 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1910354 # categorize write packet sizes +system.physmem.writePktSize::2 1907897 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59132 # categorize write packet sizes +system.physmem.writePktSize::6 59126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +117,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4690 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14955823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -176,37 +176,37 @@ system.physmem.wrQLenPdf::19 35354 # Wh system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 46839255594 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 317495505594 # Sum of mem lat for all requests -system.physmem.totBusLat 60386064000 # Total cycles spent in databus access -system.physmem.totBankLat 210270186000 # Total cycles spent in bank access -system.physmem.avgQLat 3102.65 # Average queueing delay per request -system.physmem.avgBankLat 13928.39 # Average bank access latency per request +system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests +system.physmem.totBusLat 60386104000 # Total cycles spent in databus access +system.physmem.totBankLat 210282128000 # Total cycles spent in bank access +system.physmem.avgQLat 3116.78 # Average queueing delay per request +system.physmem.avgBankLat 13929.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21031.04 # Average memory access latency -system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 21045.95 # Average memory access latency +system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 13.20 # Average write queue length over time -system.physmem.readRowHits 15050623 # Number of row buffer hits during reads -system.physmem.writeRowHits 784578 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.49 # Row buffer hit rate for writes -system.physmem.avgGap 158618.43 # Average gap between requests +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 15049962 # Number of row buffer hits during reads +system.physmem.writeRowHits 784769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes +system.physmem.avgGap 158610.84 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -227,27 +227,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51393832 # DTB read hits -system.cpu.dtb.read_misses 77273 # DTB read misses -system.cpu.dtb.write_hits 11807513 # DTB write hits -system.cpu.dtb.write_misses 17284 # DTB write misses +system.cpu.dtb.read_hits 51279526 # DTB read hits +system.cpu.dtb.read_misses 73667 # DTB read misses +system.cpu.dtb.write_hits 11753863 # DTB write hits +system.cpu.dtb.write_misses 17234 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4230 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2923 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 497 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4224 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51471105 # DTB read accesses -system.cpu.dtb.write_accesses 11824797 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51353193 # DTB read accesses +system.cpu.dtb.write_accesses 11771097 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63201345 # DTB hits -system.cpu.dtb.misses 94557 # DTB misses -system.cpu.dtb.accesses 63295902 # DTB accesses -system.cpu.itb.inst_hits 11866090 # ITB inst hits -system.cpu.itb.inst_misses 12256 # ITB inst misses +system.cpu.dtb.hits 63033389 # DTB hits +system.cpu.dtb.misses 90901 # DTB misses +system.cpu.dtb.accesses 63124290 # DTB accesses +system.cpu.itb.inst_hits 11603865 # ITB inst hits +system.cpu.itb.inst_misses 11359 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -256,688 +256,526 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2603 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2573 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3056 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11878346 # ITB inst accesses -system.cpu.itb.hits 11866090 # DTB hits -system.cpu.itb.misses 12256 # DTB misses -system.cpu.itb.accesses 11878346 # DTB accesses -system.cpu.numCycles 471617242 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11615224 # ITB inst accesses +system.cpu.itb.hits 11603865 # DTB hits +system.cpu.itb.misses 11359 # DTB misses +system.cpu.itb.accesses 11615224 # DTB accesses +system.cpu.numCycles 470951029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14707934 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11701482 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783806 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9735591 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7867248 # Number of BTB hits +system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454059 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82839 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30177247 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91949952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14707934 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9321307 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20604105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4981007 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133002 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96623906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 100214 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208761 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11862293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 731589 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6461 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.758817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.115765 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130696614 86.39% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382439 0.91% 87.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755242 1.16% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2339470 1.55% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2142585 1.42% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1134296 0.75% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2618835 1.73% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 784869 0.52% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8429565 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.194967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32009474 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96255861 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18724959 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031397 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3262224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2019817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174593 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 109260478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576218 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3262224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33806773 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36827261 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53335707 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17902220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6149730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 104066052 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21507 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4119258 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31916 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107817309 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 475022232 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 474932056 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90176 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 29086099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 892462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797997 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12333143 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20063520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13521808 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973034 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2429271 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 96511584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2058662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123961862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189585 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20013916 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 50091772 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151283915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531663 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106904579 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13863783 9.16% 79.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7099546 4.69% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5863279 3.88% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12474907 8.25% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2771705 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1719952 1.14% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 458027 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128137 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151283915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57031 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8373952 94.62% 95.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 418898 4.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58283800 47.02% 47.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95201 0.08% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52766411 42.57% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12450621 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123961862 # Type of FU issued -system.cpu.iq.rate 0.262844 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8849884 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071392 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408318037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118600535 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86285351 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12408 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10278 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132435732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12348 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 629942 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued +system.cpu.iq.rate 0.261997 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4347483 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7997 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29897 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1723272 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34108218 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 695964 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3262224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27920683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98794824 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232558 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20063520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13521808 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467094 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29897 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 410015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293518 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703533 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121755337 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081116 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2206525 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224578 # number of nop insts executed -system.cpu.iew.exec_refs 64400589 # number of memory reference insts executed -system.cpu.iew.exec_branches 11599904 # Number of branches executed -system.cpu.iew.exec_stores 12319473 # Number of stores executed -system.cpu.iew.exec_rate 0.258166 # Inst execution rate -system.cpu.iew.wb_sent 120729614 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86295629 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47354389 # num instructions producing a value -system.cpu.iew.wb_consumers 88420573 # num instructions consuming a value +system.cpu.iew.exec_nop 220747 # number of nop insts executed +system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed +system.cpu.iew.exec_branches 11527542 # Number of branches executed +system.cpu.iew.exec_stores 12265452 # Number of stores executed +system.cpu.iew.exec_rate 0.257499 # Inst execution rate +system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47162688 # num instructions producing a value +system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182978 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535558 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19868776 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544514 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612308 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148104118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.512767 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120332893 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13565443 9.16% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3964002 2.68% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135941 1.44% 94.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1954116 1.32% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973664 0.66% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1592335 1.08% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730104 0.49% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2855620 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148104118 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747617 # Number of instructions committed -system.cpu.commit.committedOps 78095752 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747230 # Number of instructions committed +system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514573 # Number of memory references committed -system.cpu.commit.loads 15716037 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023091 # Number of branches committed +system.cpu.commit.refs 27514399 # Number of memory references committed +system.cpu.commit.loads 15715935 # Number of loads committed +system.cpu.commit.membars 413101 # Number of memory barriers committed +system.cpu.commit.branches 10023041 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134185 # Number of committed integer instructions. -system.cpu.commit.function_calls 995980 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2855620 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. +system.cpu.commit.function_calls 995976 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 241297904 # The number of ROB reads -system.cpu.rob.rob_writes 199283253 # The number of ROB writes -system.cpu.timesIdled 1774711 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320333327 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575553300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597236 # Number of Instructions Simulated -system.cpu.committedOps 77945371 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597236 # Number of Instructions Simulated -system.cpu.cpi 7.782818 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.782818 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551506175 # number of integer regfile reads -system.cpu.int_regfile_writes 88407137 # number of integer regfile writes -system.cpu.fp_regfile_reads 8339 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 124072221 # number of misc regfile reads -system.cpu.misc_regfile_writes 912903 # number of misc regfile writes -system.cpu.icache.replacements 990875 # number of replacements -system.cpu.icache.tagsinuse 510.405236 # Cycle average of tags in use -system.cpu.icache.total_refs 10787830 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991387 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.881553 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.405236 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996885 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996885 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10787830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10787830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10787830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10787830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10787830 # number of overall hits -system.cpu.icache.overall_hits::total 10787830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1074333 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1074333 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1074333 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1074333 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1074333 # number of overall misses -system.cpu.icache.overall_misses::total 1074333 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14125562486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14125562486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14125562486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14125562486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11862163 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11862163 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11862163 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11862163 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.090568 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.090568 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.090568 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.090568 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13148.216136 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13148.216136 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4400 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 296 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.864865 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.rob.rob_reads 239806361 # The number of ROB reads +system.cpu.rob.rob_writes 197293644 # The number of ROB writes +system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60596849 # Number of Instructions Simulated +system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated +system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 549353817 # number of integer regfile reads +system.cpu.int_regfile_writes 87979071 # number of integer regfile writes +system.cpu.fp_regfile_reads 8318 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads +system.cpu.misc_regfile_writes 912865 # number of misc regfile writes +system.cpu.icache.replacements 980837 # number of replacements +system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use +system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits +system.cpu.icache.overall_hits::total 10539450 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses +system.cpu.icache.overall_misses::total 1060605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq 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ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 8 # 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uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7052500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7052500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7052500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.083580 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.083580 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.083580 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 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overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645101 # number of replacements -system.cpu.dcache.tagsinuse 511.994184 # Cycle average of tags in use -system.cpu.dcache.total_refs 21772820 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645613 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724259 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35202000 # Cycle when the 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accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24890517 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24890517 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24890517 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24890517 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288923 # miss rate for WriteReq accesses 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WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636373 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636373 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4781839500 # number of ReadReq MSHR miss cycles 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accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 643459 # number of replacements +system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use +system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits +system.cpu.dcache.overall_hits::total 21094791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses 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+system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses 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rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency 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cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks +system.cpu.dcache.writebacks::total 607749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1072,16 +1072,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1068163777856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88030 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 97b29a376..f7ba63a28 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -8,15 +8,15 @@ time_sync_spin_threshold=100000000 [system] type=LinuxX86System -children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus +children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table acpi_description_table_pointer=system.acpi_description_table_pointer boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 -clock=1 +clock=1000 e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -52,7 +52,7 @@ oem_table_id= [system.apicbridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=11529215046068469760:11529215046068473855 req_size=16 @@ -62,7 +62,7 @@ slave=system.iobus.master[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 @@ -72,7 +72,7 @@ slave=system.membus.master[1] [system.cpu] type=DerivO3CPU -children=dcache dtb dtb_walker_cache fuPool icache interrupts itb itb_walker_cache tracer +children=dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -120,6 +120,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -171,17 +172,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -190,7 +192,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -200,7 +202,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -209,17 +211,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -is_top_level=false -latency=1000 +hit_latency=2 +is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=1024 subblock_size=0 system=system @@ -228,7 +231,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port -mem_side=system.toL2Bus.slave[3] +mem_side=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -498,17 +501,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -517,11 +521,11 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -530,6 +534,9 @@ int_master=system.membus.slave[4] int_slave=system.membus.master[3] pio=system.membus.master[2] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -538,7 +545,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -547,17 +554,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -is_top_level=false -latency=1000 +hit_latency=2 +is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=1024 subblock_size=0 system=system @@ -566,7 +574,44 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port -mem_side=system.toL2Bus.slave[2] +mem_side=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[3] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side [system.cpu.tracer] type=ExeTracer @@ -950,17 +995,18 @@ type=BaseCache addr_ranges=0:134217727 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -is_top_level=false -latency=50000 +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -971,32 +1017,6 @@ write_buffers=8 cpu_side=system.iobus.master[18] mem_side=system.membus.slave[2] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[3] - [system.membus] type=CoherentBus children=badaddr_responder @@ -1007,11 +1027,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master +slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1034,7 +1054,7 @@ system=system [system.pc.behind_pci] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -1052,7 +1072,7 @@ pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 children=terminal -clock=1 +clock=1000 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -1076,7 +1096,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -1093,7 +1113,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -1110,7 +1130,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -1127,7 +1147,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -1144,7 +1164,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -1162,7 +1182,7 @@ pio=system.iobus.master[11] [system.pc.pciconfig] type=PciConfigAll bus=0 -clock=1 +clock=1000 pio_latency=30000 platform=system.pc size=16777216 @@ -1185,7 +1205,7 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos children=int_pin -clock=1 +clock=1000 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -1198,7 +1218,7 @@ type=X86IntSourcePin [system.pc.south_bridge.dma1] type=I8237 -clock=1 +clock=1000 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -1245,7 +1265,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 @@ -1277,7 +1297,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/projects/pd/randd/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1297,7 +1317,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1380,7 +1400,7 @@ number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 -clock=1 +clock=1000 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1392,7 +1412,7 @@ pio=system.iobus.master[10] [system.pc.south_bridge.keyboard] type=I8042 children=keyboard_int_pin mouse_int_pin -clock=1 +clock=1000 command_port=9223372036854775908 data_port=9223372036854775904 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin @@ -1411,7 +1431,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pic1] type=I8259 children=output -clock=1 +clock=1000 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1426,7 +1446,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pic2] type=I8259 children=output -clock=1 +clock=1000 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1441,7 +1461,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pit] type=I8254 children=int_pin -clock=1 +clock=1000 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1453,7 +1473,7 @@ type=X86IntSourcePin [system.pc.south_bridge.speaker] type=PcSpeaker -clock=1 +clock=1000 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1461,15 +1481,28 @@ system=system pio=system.iobus.master[9] [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] @@ -1494,13 +1527,3 @@ starting_addr_segment=0 vendor= version= -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side - diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 54a312ff8..8ce3a2233 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -5,9 +5,6 @@ warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc warn: instruction 'fxsave' unimplemented warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index a7e5df44c..334789158 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:31:43 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 18:26:17 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5167941639500 because m5_exit instruction encountered +Exiting @ tick 5132789913000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 46e54af4f..87b53a299 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.132866 # Number of seconds simulated -sim_ticks 5132866386000 # Number of ticks simulated -final_tick 5132866386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.132790 # Number of seconds simulated +sim_ticks 5132789913000 # Number of ticks simulated +final_tick 5132789913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195837 # Simulator instruction rate (inst/s) -host_op_rate 387119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2464119438 # Simulator tick rate (ticks/s) -host_mem_usage 403620 # Number of bytes of host memory used -host_seconds 2083.04 # Real time elapsed on the host -sim_insts 407937545 # Number of instructions simulated -sim_ops 806384911 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2474752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1081536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10883712 # Number of bytes read from this memory -system.physmem.bytes_read::total 14443712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1081536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1081536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9597376 # Number of bytes written to this memory -system.physmem.bytes_written::total 9597376 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 170058 # Number of read requests responded to by this memory -system.physmem.num_reads::total 225683 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149959 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149959 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210708 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2120397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2813966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210708 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210708 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1869789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1869789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1869789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2120397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4683755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 225683 # Total number of read requests seen -system.physmem.writeReqs 149959 # Total number of write requests seen -system.physmem.cpureqs 389568 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14443712 # Total number of bytes read from memory -system.physmem.bytesWritten 9597376 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14443712 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9597376 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 89 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3846 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13634 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 15197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 14751 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14175 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 14847 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 14685 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 14758 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 10128 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8462 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 10559 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9080 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 10102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8151 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9598 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8927 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 10197 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9975 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 9903 # Track writes on a per bank basis +host_inst_rate 148899 # Simulator instruction rate (inst/s) +host_op_rate 294332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1873578722 # Simulator tick rate (ticks/s) +host_mem_usage 406892 # Number of bytes of host memory used +host_seconds 2739.56 # Real time elapsed on the host +sim_insts 407917143 # Number of instructions simulated +sim_ops 806342485 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2491072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1075264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10835456 # Number of bytes read from this memory +system.physmem.bytes_read::total 14405312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1075264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1075264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9578880 # Number of bytes written to this memory +system.physmem.bytes_written::total 9578880 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16801 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169304 # Number of read requests responded to by this memory +system.physmem.num_reads::total 225083 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149670 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149670 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 485325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 209489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2111027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2806527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 209489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 209489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1866213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1866213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1866213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 485325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 209489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2111027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4672740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 225083 # Total number of read requests seen +system.physmem.writeReqs 149670 # Total number of write requests seen +system.physmem.cpureqs 388719 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14405312 # Total number of bytes read from memory +system.physmem.bytesWritten 9578880 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14405312 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9578880 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4102 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 13654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14948 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 15106 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 14545 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14098 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 14962 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14549 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 14901 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 10390 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 10526 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8491 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 9845 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8546 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9654 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8818 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 10118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9236 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 10295 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9932 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 10206 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132866305000 # Total gap between requests +system.physmem.numWrRetry 49 # Number of times wr buffer was full causing retry +system.physmem.totGap 5132789860500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 225683 # Categorize read packet sizes +system.physmem.readPktSize::6 225083 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 149959 # categorize write packet sizes +system.physmem.writePktSize::6 149719 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -114,31 +114,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3846 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4102 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 177236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 176543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -150,47 +150,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3339090244 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7604182244 # Sum of mem lat for all requests -system.physmem.totBusLat 902376000 # Total cycles spent in databus access -system.physmem.totBankLat 3362716000 # Total cycles spent in bank access -system.physmem.avgQLat 14801.33 # Average queueing delay per request -system.physmem.avgBankLat 14906.05 # Average bank access latency per request +system.physmem.totQLat 3269589754 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7518085754 # Sum of mem lat for all requests +system.physmem.totBusLat 900032000 # Total cycles spent in databus access +system.physmem.totBankLat 3348464000 # Total cycles spent in bank access +system.physmem.avgQLat 14530.99 # Average queueing delay per request +system.physmem.avgBankLat 14881.53 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33707.38 # Average memory access latency +system.physmem.avgMemAccLat 33412.53 # Average memory access latency system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s @@ -198,45 +198,45 @@ system.physmem.avgConsumedWrBW 1.87 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 10.11 # Average write queue length over time -system.physmem.readRowHits 199074 # Number of row buffer hits during reads -system.physmem.writeRowHits 88511 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.02 # Row buffer hit rate for writes -system.physmem.avgGap 13664250.28 # Average gap between requests -system.iocache.replacements 47575 # number of replacements -system.iocache.tagsinuse 0.103977 # Cycle average of tags in use +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 198566 # Number of row buffer hits during reads +system.physmem.writeRowHits 87960 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.77 # Row buffer hit rate for writes +system.physmem.avgGap 13696461.03 # Average gap between requests +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.103964 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991894063000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.103977 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006499 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.warmup_cycle 4991828572000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.103964 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006498 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006498 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143902932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143902932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9034164160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9034164160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 9178067092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9178067092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 9178067092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9178067092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146267932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 146267932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8962382160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 8962382160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 9108650092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9108650092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 9108650092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9108650092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158135.090110 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158135.090110 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 193368.239726 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 193368.239726 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 192695.089062 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 192695.089062 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 60674 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160557.554336 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160557.554336 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191831.809932 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 191831.809932 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 191233.652285 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 191233.652285 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51554 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7530 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7256 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.057636 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.105017 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96552990 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 96552990 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6602427338 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 6602427338 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6698980328 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6698980328 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98865990 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 98865990 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6530591975 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 6530591975 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6629457965 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6629457965 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,14 +287,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106102.186813 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 106102.186813 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 141319.078296 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 141319.078296 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108524.687157 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 108524.687157 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139781.506314 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 139781.506314 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -308,409 +308,409 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 448858777 # number of cpu cycles simulated +system.cpu.numCycles 447650408 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86511552 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86511552 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1187540 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 81908216 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79448034 # Number of BTB hits +system.cpu.BPredUnit.lookups 86252473 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86252473 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1112360 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81440812 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79250759 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28014488 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427358956 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86511552 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79448034 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164036376 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5076610 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125788 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 62760738 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36372 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 61645 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9269515 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 518863 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3783 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 258886753 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.258580 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418024 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27455337 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426133339 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86252473 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79250759 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163637491 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4749598 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 117040 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 62764723 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36355 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 51011 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 275 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9043493 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 487667 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3497 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257661797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.265027 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418216 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95280988 36.80% 36.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1593075 0.62% 37.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71954141 27.79% 65.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971709 0.38% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1620643 0.63% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2451488 0.95% 67.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1122205 0.43% 67.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1426657 0.55% 68.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82465847 31.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94448905 36.66% 36.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1567012 0.61% 37.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71922195 27.91% 65.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 935544 0.36% 65.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1602565 0.62% 66.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2433530 0.94% 67.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1078893 0.42% 67.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1381790 0.54% 68.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82291363 31.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 258886753 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192737 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952101 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31742461 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60237035 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159788942 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3267328 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3850987 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840289565 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1231 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3850987 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34512001 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37373607 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10738522 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159961860 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12449776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836423195 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19229 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5893988 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4723761 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7727 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998196840 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816454110 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816453462 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 648 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964349930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33846903 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 467065 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 474165 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28825004 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17330743 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10271430 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1207742 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 944493 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829965735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1256270 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824405499 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167750 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23821216 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36350655 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 203504 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 258886753 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.184425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.385403 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257661797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192678 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.951933 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31146269 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60227421 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159444515 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3244027 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3599565 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838112106 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3599565 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33887749 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37302672 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10848429 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159621170 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12402212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834448767 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20383 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5810954 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4749020 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7935 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 996003699 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1811552283 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1811551779 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964308271 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31695421 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 457655 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 465271 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28736743 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17096853 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10140380 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1243307 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 975146 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 828306292 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1248163 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823283697 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 148415 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22289625 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33892420 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 195525 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257661797 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.195211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.383294 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72013044 27.82% 27.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15598777 6.03% 33.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10365143 4.00% 37.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7553925 2.92% 40.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75959659 29.34% 70.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3903196 1.51% 71.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72545029 28.02% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 793969 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 154011 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71201357 27.63% 27.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15459797 6.00% 33.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10286150 3.99% 37.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7472850 2.90% 40.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75924697 29.47% 69.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3857138 1.50% 71.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72522119 28.15% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 785654 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152035 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 258886753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257661797 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 353413 33.31% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 554407 52.25% 85.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153287 14.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 364358 34.12% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 552545 51.74% 85.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150975 14.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 307308 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796584719 96.63% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18039231 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9474241 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 312887 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795710532 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17869782 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9390496 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824405499 # Type of FU issued -system.cpu.iq.rate 1.836670 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1061107 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1909060731 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 855053110 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819712115 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 306 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825159176 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1650601 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823283697 # Type of FU issued +system.cpu.iq.rate 1.839122 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1067878 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905576298 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851854038 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818789401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 824038596 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1642479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3355072 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26592 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11367 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1855422 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3121524 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22243 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11430 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1726583 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932171 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11828 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932632 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11779 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3850987 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26145840 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2117101 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831222005 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 328364 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17330743 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10271430 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 725551 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1616789 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12654 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11367 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 710665 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 625080 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1335745 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822377334 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17606524 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2028164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3599565 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26096083 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2112224 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829554455 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 302739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17096853 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10140380 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 717341 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1614771 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11695 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11430 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 654771 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 594016 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1248787 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821389011 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17449263 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1894685 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26829889 # number of memory reference insts executed -system.cpu.iew.exec_branches 83279279 # Number of branches executed -system.cpu.iew.exec_stores 9223365 # Number of stores executed -system.cpu.iew.exec_rate 1.832152 # Inst execution rate -system.cpu.iew.wb_sent 821869918 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819712181 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640562059 # num instructions producing a value -system.cpu.iew.wb_consumers 1046574799 # num instructions consuming a value +system.cpu.iew.exec_refs 26607287 # number of memory reference insts executed +system.cpu.iew.exec_branches 83217289 # Number of branches executed +system.cpu.iew.exec_stores 9158024 # Number of stores executed +system.cpu.iew.exec_rate 1.834889 # Inst execution rate +system.cpu.iew.wb_sent 820925784 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818789455 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639951171 # num instructions producing a value +system.cpu.iew.wb_consumers 1045809475 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.826214 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612056 # average fanout of values written-back +system.cpu.iew.wb_rate 1.829082 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24730610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052764 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1192382 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255051171 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.161659 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.853306 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 23105687 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052636 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1116569 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254077625 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.173607 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.854352 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 83143291 32.60% 32.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11860450 4.65% 37.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3961812 1.55% 38.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74971665 29.39% 68.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2481439 0.97% 69.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1489878 0.58% 69.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 950647 0.37% 70.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70929098 27.81% 97.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5262891 2.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82352974 32.41% 32.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11796837 4.64% 37.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3872314 1.52% 38.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74949594 29.50% 68.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2433419 0.96% 69.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1479159 0.58% 69.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 902635 0.36% 69.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70918587 27.91% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5372106 2.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255051171 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407937545 # Number of instructions committed -system.cpu.commit.committedOps 806384911 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254077625 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407917143 # Number of instructions committed +system.cpu.commit.committedOps 806342485 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22391676 # Number of memory references committed -system.cpu.commit.loads 13975668 # Number of loads committed -system.cpu.commit.membars 473465 # Number of memory barriers committed -system.cpu.commit.branches 82190309 # Number of branches committed +system.cpu.commit.refs 22389123 # Number of memory references committed +system.cpu.commit.loads 13975326 # Number of loads committed +system.cpu.commit.membars 473463 # Number of memory barriers committed +system.cpu.commit.branches 82187715 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735319938 # Number of committed integer instructions. +system.cpu.commit.int_insts 735283087 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5262891 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5372106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080825517 # The number of ROB reads -system.cpu.rob.rob_writes 1666103017 # The number of ROB writes -system.cpu.timesIdled 1222907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 189972024 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9816871415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407937545 # Number of Instructions Simulated -system.cpu.committedOps 806384911 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407937545 # Number of Instructions Simulated -system.cpu.cpi 1.100312 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.100312 # CPI: Total CPI of All Threads -system.cpu.ipc 0.908833 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.908833 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508250980 # number of integer regfile reads -system.cpu.int_regfile_writes 977858997 # number of integer regfile writes -system.cpu.fp_regfile_reads 66 # number of floating regfile reads -system.cpu.misc_regfile_reads 265171411 # number of misc regfile reads -system.cpu.misc_regfile_writes 402390 # number of misc regfile writes -system.cpu.icache.replacements 1072344 # number of replacements -system.cpu.icache.tagsinuse 510.326715 # Cycle average of tags in use -system.cpu.icache.total_refs 8127499 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1072855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.575580 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56079311000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.326715 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996732 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996732 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8127499 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8127499 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8127499 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8127499 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8127499 # number of overall hits -system.cpu.icache.overall_hits::total 8127499 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1142014 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1142014 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1142014 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1142014 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1142014 # number of overall misses -system.cpu.icache.overall_misses::total 1142014 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15424181989 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15424181989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15424181989 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15424181989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15424181989 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15424181989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9269513 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9269513 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9269513 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9269513 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9269513 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9269513 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123201 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123201 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123201 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123201 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123201 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123201 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.123383 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13506.123383 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.123383 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13506.123383 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.123383 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13506.123383 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7378 # number of cycles access was blocked +system.cpu.rob.rob_reads 1078075497 # The number of ROB reads +system.cpu.rob.rob_writes 1662514782 # The number of ROB writes +system.cpu.timesIdled 1218897 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189988611 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9817926834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407917143 # Number of Instructions Simulated +system.cpu.committedOps 806342485 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407917143 # Number of Instructions Simulated +system.cpu.cpi 1.097405 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.097405 # CPI: Total CPI of All Threads +system.cpu.ipc 0.911240 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.911240 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1506960736 # number of integer regfile reads +system.cpu.int_regfile_writes 976968921 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.misc_regfile_reads 264713842 # number of misc regfile reads +system.cpu.misc_regfile_writes 402218 # number of misc regfile writes +system.cpu.icache.replacements 1046081 # number of replacements +system.cpu.icache.tagsinuse 510.992308 # Cycle average of tags in use +system.cpu.icache.total_refs 7932749 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1046593 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.579593 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 55992087000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.992308 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998032 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998032 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7932749 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7932749 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7932749 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7932749 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7932749 # number of overall hits +system.cpu.icache.overall_hits::total 7932749 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1110744 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1110744 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1110744 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1110744 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1110744 # number of overall misses +system.cpu.icache.overall_misses::total 1110744 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15035266490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15035266490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15035266490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15035266490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15035266490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15035266490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9043493 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9043493 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9043493 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9043493 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9043493 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9043493 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122822 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122822 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122822 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122822 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122822 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122822 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13536.212206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13536.212206 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13536.212206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13536.212206 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5934 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 254 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 274 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 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-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075078 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1075078 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1075078 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1075078 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1075078 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1075078 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12692625989 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12692625989 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12692625989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12692625989 # number of demand (read+write) MSHR miss cycles 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of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1049065 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1049065 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1049065 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1049065 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1049065 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12388903990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12388903990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12388903990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12388903990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12388903990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12388903990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11809.472235 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11809.472235 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11809.472235 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11809.472235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11809.472235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11809.472235 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10190 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.008148 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 29715 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10203 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.912379 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5103977180500 # Cycle when the warmup percentage was hit. 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was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.006130 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375383 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375383 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26219 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26219 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 29722 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 29722 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 29722 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 29722 # number of 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overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37036 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 37036 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40794 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 40794 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40794 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 40794 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.271432 # miss rate for ReadReq accesses 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11309.654986 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11309.654986 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37039 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 37039 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37039 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 37039 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.292067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.292067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.292044 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.292044 # miss rate for demand accesses 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system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -719,78 +719,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1966 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1966 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11072 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11072 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11072 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 11072 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11072 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 11072 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 103076500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 103076500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 103076500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 103076500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 103076500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 103076500 # number of overall MSHR miss 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overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10817 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10817 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10817 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10817 # number of demand (read+write) MSHR misses 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accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.292067 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.292044 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.292044 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8773.550892 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 112521 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.957581 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 137445 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 112536 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.221343 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100518873000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.957581 # Average occupied blocks per requestor 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demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 113500 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 113500 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 113500 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1432388500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1432388500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1432388500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1432388500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1432388500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1432388500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 250952 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 250952 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 250952 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 250952 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 250952 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 250952 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.452278 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.452278 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.452278 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.452278 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.452278 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.452278 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12620.162996 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12620.162996 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12620.162996 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12620.162996 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 113923 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.921985 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 130116 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 113938 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.141990 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100448688500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.921985 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.807624 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.807624 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130138 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 130138 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130138 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 130138 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130138 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 130138 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 114896 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 114896 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 114896 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 114896 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 114896 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 114896 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1427497500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1427497500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1427497500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1427497500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1427497500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1427497500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245034 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 245034 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245034 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 245034 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245034 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 245034 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.468898 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.468898 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.468898 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.468898 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.468898 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.468898 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.257589 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.257589 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.257589 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,146 +799,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 37324 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 37324 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 113500 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 113500 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 113500 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 113500 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 113500 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 113500 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1205388500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1205388500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1205388500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.452278 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.452278 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.452278 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10620.162996 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35555 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35555 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 114896 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 114896 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 114896 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 114896 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 114896 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 114896 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1197705500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1197705500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1197705500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.468898 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.468898 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.468898 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10424.257589 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1671903 # number of replacements -system.cpu.dcache.tagsinuse 511.996701 # Cycle average of tags in use -system.cpu.dcache.total_refs 19219910 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1672415 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.492309 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.996701 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11126974 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11126974 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8088054 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8088054 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19215028 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19215028 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19215028 # number of overall hits -system.cpu.dcache.overall_hits::total 19215028 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2267052 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2267052 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318719 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318719 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2585771 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2585771 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2585771 # number of overall misses -system.cpu.dcache.overall_misses::total 2585771 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32362735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32362735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9617362993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9617362993 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41980097993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41980097993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41980097993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41980097993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13394026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13394026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8406773 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8406773 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21800799 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21800799 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21800799 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21800799 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169258 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169258 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037912 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037912 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118609 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118609 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118609 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118609 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14275.250413 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14275.250413 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30175.053866 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30175.053866 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16235.040919 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16235.040919 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16235.040919 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16235.040919 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 395929 # number of cycles access was blocked +system.cpu.dcache.replacements 1657882 # number of replacements +system.cpu.dcache.tagsinuse 511.998105 # Cycle average of tags in use +system.cpu.dcache.total_refs 19102953 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1658394 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.518947 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27815000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.998105 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11010989 # number of ReadReq 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rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037806 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117865 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117865 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117865 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117865 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14242.699040 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14242.699040 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30100.225944 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30100.225944 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16217.309874 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16217.309874 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 396326 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42571 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42512 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.300439 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.322685 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1571444 # number of writebacks -system.cpu.dcache.writebacks::total 1571444 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 884224 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 884224 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24733 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24733 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 908957 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 908957 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 908957 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 908957 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1382828 # number of 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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8776924993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26243078993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26243078993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26243078993 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26243078993 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296687500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296687500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470134500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470134500 # number of WriteReq MSHR uncacheable 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for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12630.749450 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12630.749450 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29854.908033 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29854.908033 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15650.560523 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15650.560523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15650.560523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15650.560523 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1559612 # number of writebacks +system.cpu.dcache.writebacks::total 1559612 # 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uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103551 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103551 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034681 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034681 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076815 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076815 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076815 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076815 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12612.557591 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12612.557591 # average ReadReq mshr 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per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 12.458733 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.160012 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3172.410316 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11431.254363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.766187 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000190 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.048330 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.175742 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989259 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 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for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016054 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102691 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.066391 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 57543.583333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46264.696387 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51709.813276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50008.328830 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10269.863411 # average UpgradeReq mshr miss latency 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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46264.696387 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40987.240013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41465.951256 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 0e8616cf5..8c8aecb35 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 282b60660..5289b243e 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:09:56 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:21:21 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 274137499500 because target called exit() +Exiting @ tick 269661304500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 01d17fd64..e8752c3e3 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.269731 # Number of seconds simulated -sim_ticks 269730745500 # Number of ticks simulated -final_tick 269730745500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269661 # Number of seconds simulated +sim_ticks 269661304500 # Number of ticks simulated +final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168515 # Simulator instruction rate (inst/s) -host_op_rate 168515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75522303 # Simulator tick rate (ticks/s) -host_mem_usage 218132 # Number of bytes of host memory used -host_seconds 3571.54 # Real time elapsed on the host +host_inst_rate 125304 # Simulator instruction rate (inst/s) +host_op_rate 125304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56142087 # Simulator tick rate (ticks/s) +host_mem_usage 214336 # Number of bytes of host memory used +host_seconds 4803.19 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6039326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6238873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240595 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240595 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6039326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6479469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 26294 # Total number of read requests seen system.physmem.writeReqs 1014 # Total number of write requests seen system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 74 # Tr system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269730693500 # Total gap between requests +system.physmem.totGap 269661252500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,9 +105,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 17613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 44 # Wh system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 360576187 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1020404187 # Sum of mem lat for all requests +system.physmem.totQLat 364261179 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests system.physmem.totBusLat 105120000 # Total cycles spent in databus access -system.physmem.totBankLat 554708000 # Total cycles spent in bank access -system.physmem.avgQLat 13720.56 # Average queueing delay per request -system.physmem.avgBankLat 21107.61 # Average bank access latency per request +system.physmem.totBankLat 554778000 # Total cycles spent in bank access +system.physmem.avgQLat 13860.78 # Average queueing delay per request +system.physmem.avgBankLat 21110.27 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38828.17 # Average memory access latency +system.physmem.avgMemAccLat 38971.05 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -187,31 +187,31 @@ system.physmem.peakBW 16000.00 # Th system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.19 # Average write queue length over time -system.physmem.readRowHits 17405 # Number of row buffer hits during reads +system.physmem.readRowHits 17406 # Number of row buffer hits during reads system.physmem.writeRowHits 51 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes -system.physmem.avgGap 9877350.72 # Average gap between requests +system.physmem.avgGap 9874807.84 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517567 # DTB read hits +system.cpu.dtb.read_hits 114517568 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520198 # DTB read accesses -system.cpu.dtb.write_hits 39453373 # DTB write hits +system.cpu.dtb.read_accesses 114520199 # DTB read accesses +system.cpu.dtb.write_hits 39453362 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39455675 # DTB write accesses -system.cpu.dtb.data_hits 153970940 # DTB hits +system.cpu.dtb.write_accesses 39455664 # DTB write accesses +system.cpu.dtb.data_hits 153970930 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153975873 # DTB accesses -system.cpu.itb.fetch_hits 25065868 # ITB hits +system.cpu.dtb.data_accesses 153975863 # DTB accesses +system.cpu.itb.fetch_hits 24997854 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25065890 # ITB accesses +system.cpu.itb.fetch_accesses 24997876 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539461492 # number of cpu cycles simulated +system.cpu.numCycles 539322610 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86297721 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81352852 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36357676 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52914836 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34319624 # Number of BTB hits +system.cpu.branch_predictor.lookups 86405274 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81476244 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36343014 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 44773910 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34660000 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.858226 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36896934 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49400787 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541636673 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 77.411153 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005491519 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 254989713 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155053642 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33759621 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2593068 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36352689 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26195221 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.119750 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334808 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 154928367 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36338027 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26209890 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.096302 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412128439 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535900413 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 295985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50743768 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488717724 # Number of cycles cpu stages are processed. -system.cpu.activity 90.593626 # Percentage of cycles cpu is active +system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed. +system.cpu.activity 90.582759 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -272,72 +272,72 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896328 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896328 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115663 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115663 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200698192 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338763300 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.796568 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 228822575 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310638917 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.583149 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197865765 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341595727 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.321615 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 428073840 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111387652 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.647934 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192651610 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346809882 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.288163 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.083311 # Cycle average of tags in use -system.cpu.icache.total_refs 25064833 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use +system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29315.594152 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.083311 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355998 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355998 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25064833 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25064833 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25064833 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25064833 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25064833 # number of overall hits -system.cpu.icache.overall_hits::total 25064833 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1035 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1035 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1035 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1035 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1035 # number of overall misses -system.cpu.icache.overall_misses::total 1035 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 52854000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 52854000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 52854000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 52854000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 52854000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 52854000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25065868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25065868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25065868 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25065868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25065868 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25065868 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits +system.cpu.icache.overall_hits::total 24996820 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses +system.cpu.icache.overall_misses::total 1034 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51066.666667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51066.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51066.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51066.666667 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -346,158 +346,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 180 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 180 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 180 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 180 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 179 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 179 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 179 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 179 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 179 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43286500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43286500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43286500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43286500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43286500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43286500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50627.485380 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50627.485380 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.419858 # Cycle average of tags in use -system.cpu.dcache.total_refs 151786041 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.306341 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.419858 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37665413 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37665413 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151786041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151786041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151786041 # number of overall hits -system.cpu.dcache.overall_hits::total 151786041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1785908 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1785908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2179322 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2179322 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2179322 # number of overall misses -system.cpu.dcache.overall_misses::total 2179322 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991589500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5991589500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22875440000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22875440000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28867029500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28867029500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28867029500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28867029500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15229.731275 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15229.731275 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12808.856895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12808.856895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13245.876240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13245.876240 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 165761 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 544 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5600 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.600179 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 60.444444 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks -system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531745 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1531745 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1723927 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1723927 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1723927 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1723927 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645854500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645854500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3731128500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3731128500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6376983000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6376983000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6376983000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6376983000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13148.279101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13148.279101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14680.061614 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14680.061614 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22878.552216 # Cycle average of tags in use -system.cpu.l2cache.total_refs 531848 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22879.132168 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.846686 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.756059 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.203653 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.592503 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.661766 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021918 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014514 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.698198 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21684.623478 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.963213 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.545477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014512 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits @@ -522,17 +414,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses system.cpu.l2cache.overall_misses::total 26294 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42280500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472681500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 514962000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1146890000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1146890000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42280500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1619571500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1661852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42280500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1619571500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1661852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42639500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472401500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 515041000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1150527000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1150527000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42639500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1622928500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1665568000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42639500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1622928500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1665568000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -557,17 +449,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50274.078478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114589.454545 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 103697.543294 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53773.912228 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53773.912228 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 63202.707842 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 63202.707842 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50700.951249 # average ReadReq miss latency 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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -589,17 +481,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31666859 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 419253922 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450920781 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 877062534 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 877062534 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31666859 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1296316456 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1327983315 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31666859 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1296316456 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1327983315 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32024355 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418973423 # number of ReadReq MSHR miss cycles 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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -611,17 +503,125 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37653.815696 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101637.314424 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90801.607128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41122.586928 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41122.586928 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38078.900119 # average ReadReq mshr miss latency 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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 451299 # number of replacements +system.cpu.dcache.tagsinuse 4093.419207 # Cycle average of tags in use +system.cpu.dcache.total_refs 151786016 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 333.306286 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.419207 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37665388 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37665388 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151786016 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151786016 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151786016 # number of overall hits +system.cpu.dcache.overall_hits::total 151786016 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1785933 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1785933 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2179347 # number of demand (read+write) misses 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cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15228.581088 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15228.581088 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12819.022606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12819.022606 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13253.994201 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13253.994201 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 167214 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 552 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5590 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.913059 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.333333 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks +system.cpu.dcache.writebacks::total 436887 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531770 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1531770 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1723952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1723952 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1723952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1723952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 5bc85930f..ba863cc04 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index ddf76222f..396a60755 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:10:10 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:21:56 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 135504709500 because target called exit() +Exiting @ tick 133778696500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 82eaca8c6..759350e06 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.135739 # Number of seconds simulated -sim_ticks 135738546500 # Number of ticks simulated -final_tick 135738546500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133779 # Number of seconds simulated +sim_ticks 133778696500 # Number of ticks simulated +final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149707 # Simulator instruction rate (inst/s) -host_op_rate 149707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35931284 # Simulator tick rate (ticks/s) -host_mem_usage 219152 # Number of bytes of host memory used -host_seconds 3777.73 # Real time elapsed on the host +host_inst_rate 208111 # Simulator instruction rate (inst/s) +host_op_rate 208111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49227708 # Simulator tick rate (ticks/s) +host_mem_usage 215496 # Number of bytes of host memory used +host_seconds 2717.55 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory -system.physmem.bytes_written::total 67072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26528 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 454049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12053761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12507810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 454049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 454049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 494126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 494126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 494126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 454049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12053761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13001937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26528 # Total number of read requests seen -system.physmem.writeReqs 1048 # Total number of write requests seen -system.physmem.cpureqs 27576 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697792 # Total number of bytes read from memory -system.physmem.bytesWritten 67072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697792 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636416 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67008 # Number of bytes written to this memory +system.physmem.bytes_written::total 67008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25569 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26520 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1047 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1047 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 454960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12232262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12687222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 454960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 500887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 500887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 500887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 454960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12232262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13188109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26520 # Total number of read requests seen +system.physmem.writeReqs 1047 # Total number of write requests seen +system.physmem.cpureqs 27567 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697280 # Total number of bytes read from memory +system.physmem.bytesWritten 67008 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697280 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67008 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1612 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1569 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1630 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1568 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1615 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1704 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis @@ -65,26 +65,26 @@ system.physmem.perBankWrReqs::2 55 # Tr system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 78 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 84 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 57 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 80 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 78 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 135738512500 # Total gap between requests +system.physmem.totGap 133778628000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26528 # Categorize read packet sizes +system.physmem.readPktSize::6 26520 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1048 # categorize write packet sizes +system.physmem.writePktSize::6 1047 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4903 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,7 +150,7 @@ system.physmem.wrQLenPdf::8 46 # Wh system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 656768415 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1272742415 # Sum of mem lat for all requests -system.physmem.totBusLat 106052000 # Total cycles spent in databus access -system.physmem.totBankLat 509922000 # Total cycles spent in bank access -system.physmem.avgQLat 24771.56 # Average queueing delay per request -system.physmem.avgBankLat 19232.90 # Average bank access latency per request +system.physmem.totQLat 650833420 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1266537420 # Sum of mem lat for all requests +system.physmem.totBusLat 106020000 # Total cycles spent in databus access +system.physmem.totBankLat 509684000 # Total cycles spent in bank access +system.physmem.avgQLat 24555.12 # Average queueing delay per request +system.physmem.avgBankLat 19229.73 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 48004.47 # Average memory access latency -system.physmem.avgRdBW 12.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.49 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 12.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.49 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 47784.85 # Average memory access latency +system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.08 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.03 # Average write queue length over time -system.physmem.readRowHits 18053 # Number of row buffer hits during reads -system.physmem.writeRowHits 56 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 5.34 # Row buffer hit rate for writes -system.physmem.avgGap 4922342.34 # Average gap between requests +system.physmem.avgWrQLen 10.37 # Average write queue length over time +system.physmem.readRowHits 18044 # Number of row buffer hits during reads +system.physmem.writeRowHits 53 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes +system.physmem.avgGap 4852854.06 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123922794 # DTB read hits -system.cpu.dtb.read_misses 28366 # DTB read misses +system.cpu.dtb.read_hits 122603551 # DTB read hits +system.cpu.dtb.read_misses 28565 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123951160 # DTB read accesses -system.cpu.dtb.write_hits 40833980 # DTB write hits -system.cpu.dtb.write_misses 25612 # DTB write misses +system.cpu.dtb.read_accesses 122632116 # DTB read accesses +system.cpu.dtb.write_hits 40753368 # DTB write hits +system.cpu.dtb.write_misses 25574 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40859592 # DTB write accesses -system.cpu.dtb.data_hits 164756774 # DTB hits -system.cpu.dtb.data_misses 53978 # DTB misses +system.cpu.dtb.write_accesses 40778942 # DTB write accesses +system.cpu.dtb.data_hits 163356919 # DTB hits +system.cpu.dtb.data_misses 54139 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164810752 # DTB accesses -system.cpu.itb.fetch_hits 66580671 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.dtb.data_accesses 163411058 # DTB accesses +system.cpu.itb.fetch_hits 65475592 # ITB hits +system.cpu.itb.fetch_misses 42 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66580711 # ITB accesses +system.cpu.itb.fetch_accesses 65475634 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 271477094 # number of cpu cycles simulated +system.cpu.numCycles 267557394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78553522 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72909571 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3050106 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42863354 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41672348 # Number of BTB hits +system.cpu.BPredUnit.lookups 76440222 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 70864810 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2706098 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 43060392 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41933015 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1629524 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 245 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68542455 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 711581178 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78553522 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43301872 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119313775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13045820 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73380337 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1305 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66580671 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 946763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 271202747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.623798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454049 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1604413 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43537428 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117782486 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11617306 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73490715 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1303 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65475592 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 928038 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267274328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.615488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444547 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151888972 56.01% 56.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10373570 3.83% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11841110 4.37% 64.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10622549 3.92% 68.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7004922 2.58% 70.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2671761 0.99% 71.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3503178 1.29% 72.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3113300 1.15% 74.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70183385 25.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149491842 55.93% 55.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10342090 3.87% 59.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11847639 4.43% 64.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10563390 3.95% 68.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7011808 2.62% 70.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2869024 1.07% 71.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3576964 1.34% 73.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3101400 1.16% 74.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68470171 25.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 271202747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289356 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.621146 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 86023061 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57429003 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104152322 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13634796 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9963565 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3909126 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702760367 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4141 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9963565 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 94304341 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12784998 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1531 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104174044 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49974268 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690768624 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 416 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38037873 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5669894 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527681051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 907529781 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 907526811 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2970 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267274328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285697 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.612721 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84240613 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57793701 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102635866 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13724657 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8879491 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3873839 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 920 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691093913 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3105 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8879491 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92211740 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12790279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1241 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103054645 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50336932 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 680961604 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 408 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38688874 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5430085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520709674 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 896990234 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 896987596 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2638 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63826162 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 100 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112138467 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129142032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42466663 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14842304 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10368291 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626932339 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608621790 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 344229 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60678365 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33855512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 271202747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.244158 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.828491 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 56854785 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 64 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 69 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112289485 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 126970724 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42377686 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14852387 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10147583 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621083354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604563100 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299815 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 54897951 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29938787 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267274328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.261957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823661 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55518105 20.47% 20.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55264401 20.38% 40.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53914091 19.88% 60.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 37013789 13.65% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31720099 11.70% 86.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23689667 8.74% 94.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10003906 3.69% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3493839 1.29% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 584850 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52499760 19.64% 19.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55875325 20.91% 40.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53442699 20.00% 60.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36269586 13.57% 74.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31423380 11.76% 85.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23799839 8.90% 94.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9996979 3.74% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3415050 1.28% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 551710 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 271202747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267274328 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2803923 71.85% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 36 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 717323 18.38% 90.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 381401 9.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2734710 70.93% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 35 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 729519 18.92% 89.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 391400 10.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441148473 72.48% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7331 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126212456 20.74% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41253487 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439055623 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7072 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124323040 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41177317 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608621790 # Type of FU issued -system.cpu.iq.rate 2.241890 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3902683 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006412 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1492689315 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 687613743 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598990581 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2505 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1722 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612522503 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1970 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12211500 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604563100 # Type of FU issued +system.cpu.iq.rate 2.259564 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3855664 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006378 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480552206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 675984537 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596489873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3801 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2284 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1738 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608416848 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1916 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12282855 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14627990 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32965 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5519 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3015342 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12456682 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 35904 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5518 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2926365 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6777 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 53391 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6461 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 52889 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9963565 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1456092 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 187737 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670933978 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1716868 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129142032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42466663 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 140012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7404 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5519 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1345446 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2210203 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3555649 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602801961 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123951309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5819829 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8879491 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1456554 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 192142 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 663913486 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1691538 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 126970724 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42377686 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 144242 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7408 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5518 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1333964 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1804152 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3138116 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599464075 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122632263 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5099025 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 44001547 # number of nop insts executed -system.cpu.iew.exec_refs 164826908 # number of memory reference insts executed -system.cpu.iew.exec_branches 67037045 # Number of branches executed -system.cpu.iew.exec_stores 40875599 # Number of stores executed -system.cpu.iew.exec_rate 2.220452 # Inst execution rate -system.cpu.iew.wb_sent 600240253 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598992303 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417488059 # num instructions producing a value -system.cpu.iew.wb_consumers 532706701 # num instructions consuming a value +system.cpu.iew.exec_nop 42830076 # number of nop insts executed +system.cpu.iew.exec_refs 163429760 # number of memory reference insts executed +system.cpu.iew.exec_branches 66623337 # Number of branches executed +system.cpu.iew.exec_stores 40797497 # Number of stores executed +system.cpu.iew.exec_rate 2.240506 # Inst execution rate +system.cpu.iew.wb_sent 597426155 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596491611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415927297 # num instructions producing a value +system.cpu.iew.wb_consumers 530215795 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.206419 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.783711 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229397 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784449 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 68955725 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61932723 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3049050 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 261239182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.303854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.691353 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2705240 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258394837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.691172 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82351408 31.52% 31.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72672063 27.82% 59.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25867656 9.90% 69.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8932880 3.42% 72.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10297113 3.94% 76.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20861196 7.99% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6530231 2.50% 87.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3837950 1.47% 88.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29888685 11.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79550578 30.79% 30.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72525012 28.07% 58.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25515345 9.87% 68.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9289171 3.59% 72.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10288497 3.98% 76.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21029047 8.14% 84.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6874256 2.66% 87.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3694459 1.43% 88.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29628472 11.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 261239182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258394837 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,368 +475,368 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29888685 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29628472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 902098796 # The number of ROB reads -system.cpu.rob.rob_writes 1351611788 # The number of ROB writes -system.cpu.timesIdled 34221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 274347 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892491662 # The number of ROB reads +system.cpu.rob.rob_writes 1336472901 # The number of ROB writes +system.cpu.timesIdled 34286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 283066 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.480021 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.480021 # CPI: Total CPI of All Threads -system.cpu.ipc 2.083242 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.083242 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848885274 # number of integer regfile reads -system.cpu.int_regfile_writes 492863541 # number of integer regfile writes -system.cpu.fp_regfile_reads 396 # number of floating regfile reads -system.cpu.fp_regfile_writes 49 # number of floating regfile writes +system.cpu.cpi 0.473090 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473090 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113761 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113761 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 844970192 # number of integer regfile reads +system.cpu.int_regfile_writes 490533624 # number of integer regfile writes +system.cpu.fp_regfile_reads 397 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 43 # number of replacements -system.cpu.icache.tagsinuse 832.109405 # Cycle average of tags in use -system.cpu.icache.total_refs 66579220 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 984 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67661.808943 # Average number of references to valid blocks. +system.cpu.icache.replacements 36 # number of replacements +system.cpu.icache.tagsinuse 825.012562 # Cycle average of tags in use +system.cpu.icache.total_refs 65474211 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67848.923316 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 832.109405 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.406303 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.406303 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66579220 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66579220 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66579220 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66579220 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66579220 # number of overall hits -system.cpu.icache.overall_hits::total 66579220 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1449 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1449 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1449 # number of overall misses -system.cpu.icache.overall_misses::total 1449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 74643000 # number of ReadReq miss cycles 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system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 28500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 28500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41310977656 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41310977656 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41310977656 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41310977656 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 111659183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 111659183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 41308508616 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41308508616 # number of demand (read+write) miss cycles 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accesses -system.cpu.dcache.overall_miss_rate::total 0.018716 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.004347 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.004347 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14366.481581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14366.481581 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 149720800 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149720800 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149720800 # number of overall (read+write) accesses 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-system.cpu.dcache.blocked_cycles::no_mshrs 279576 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 531 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17250 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.207304 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.250000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14599.230682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14599.230682 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 277266 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17305 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.022306 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 83.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445038 # number of writebacks -system.cpu.dcache.writebacks::total 445038 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 815637 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 815637 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1547591 # 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2363228 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2363228 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210381 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210381 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254515 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254515 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464896 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464896 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464896 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464896 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2700521500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2700521500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4051961986 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4051961986 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6752483486 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6752483486 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6752483486 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6752483486 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses 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+system.cpu.dcache.overall_mshr_miss_rate::total 0.003107 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12841.751321 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12841.751321 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15894.703311 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15894.703311 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1080 # number of replacements -system.cpu.l2cache.tagsinuse 22929.630995 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547178 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23523 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.261404 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21483.752454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 824.475298 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 621.403243 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655632 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025161 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018964 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699757 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 206090 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 206111 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 445038 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 445038 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233241 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 233241 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 439331 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 439352 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 439331 # number of overall hits -system.cpu.l2cache.overall_hits::total 439352 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4290 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5253 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21275 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21275 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25565 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26528 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25565 # number of overall misses -system.cpu.l2cache.overall_misses::total 26528 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50946500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 423158500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 474105000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1457229500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1457229500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50946500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1880388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1931334500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50946500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1880388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1931334500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211364 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 445038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 445038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 464896 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 465880 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 464896 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 465880 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.978659 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020392 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024853 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083590 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083590 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.978659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.054991 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.056942 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.978659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.054991 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.056942 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52903.946002 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 98638.344988 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 90254.140491 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68494.923619 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68494.923619 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52903.946002 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73553.217289 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72803.622587 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52903.946002 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73553.217289 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72803.622587 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks -system.cpu.l2cache.writebacks::total 1049 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5253 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21275 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21275 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25565 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26528 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25565 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26528 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38838509 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 367821283 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 406659792 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1190995676 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1190995676 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38838509 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1558816959 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1597655468 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38838509 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1558816959 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1597655468 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020392 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024853 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083590 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083590 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056942 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40330.746625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85739.226807 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77414.770988 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55980.995347 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55980.995347 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 9953e7dde..c4518abcc 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 21a8a9bfd..5bcc38f1b 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:54:44 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 18:59:47 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164735271500 because target called exit() +Exiting @ tick 164568389500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index ec201586b..d2efc8854 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.165181 # Number of seconds simulated -sim_ticks 165180822000 # Number of ticks simulated -final_tick 165180822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164568 # Number of seconds simulated +sim_ticks 164568389500 # Number of ticks simulated +final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196230 # Simulator instruction rate (inst/s) -host_op_rate 207352 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56860513 # Simulator tick rate (ticks/s) -host_mem_usage 233444 # Number of bytes of host memory used -host_seconds 2905.02 # Real time elapsed on the host +host_inst_rate 155967 # Simulator instruction rate (inst/s) +host_op_rate 164807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45026221 # Simulator tick rate (ticks/s) +host_mem_usage 230908 # Number of bytes of host memory used +host_seconds 3654.95 # Real time elapsed on the host sim_insts 570052720 # Number of instructions simulated sim_ops 602360926 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1702592 # Number of bytes read from this memory -system.physmem.bytes_read::total 1749568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1702080 # Number of bytes read from this memory +system.physmem.bytes_read::total 1749184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47104 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory system.physmem.bytes_written::total 162368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26603 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 736 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26595 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27331 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 284391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10307444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10591835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 284391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 284391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 982971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 982971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 982971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 284391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10307444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11574806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27339 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 286228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10342691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10628919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 286228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 286228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 986629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 986629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 986629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 286228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10342691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11615548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27332 # Total number of read requests seen system.physmem.writeReqs 2537 # Total number of write requests seen -system.physmem.cpureqs 29876 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1749568 # Total number of bytes read from memory +system.physmem.cpureqs 29869 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1749184 # Total number of bytes read from memory system.physmem.bytesWritten 162368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1749568 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1749184 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1705 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1698 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1679 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1720 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1696 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1745 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1718 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 164 # Tr system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 165180805000 # Total gap between requests +system.physmem.totGap 164568371500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27339 # Categorize read packet sizes +system.physmem.readPktSize::6 27332 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 783 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 952476989 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1656324989 # Sum of mem lat for all requests -system.physmem.totBusLat 109352000 # Total cycles spent in databus access -system.physmem.totBankLat 594496000 # Total cycles spent in bank access -system.physmem.avgQLat 34839.50 # Average queueing delay per request -system.physmem.avgBankLat 21745.35 # Average bank access latency per request -system.physmem.avgBusLat 3999.85 # Average bus latency per request -system.physmem.avgMemAccLat 60584.70 # Average memory access latency -system.physmem.avgRdBW 10.59 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.59 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.98 # Average consumed write bandwidth in MB/s +system.physmem.totQLat 953340995 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1657962995 # Sum of mem lat for all requests +system.physmem.totBusLat 109328000 # Total cycles spent in databus access +system.physmem.totBankLat 595294000 # Total cycles spent in bank access +system.physmem.avgQLat 34880.03 # Average queueing delay per request +system.physmem.avgBankLat 21780.11 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 60660.14 # Average memory access latency +system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 5.90 # Average write queue length over time -system.physmem.readRowHits 17775 # Number of row buffer hits during reads -system.physmem.writeRowHits 1102 # Number of row buffer hits during writes -system.physmem.readRowHitRate 65.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.44 # Row buffer hit rate for writes -system.physmem.avgGap 5528879.54 # Average gap between requests +system.physmem.avgWrQLen 6.05 # Average write queue length over time +system.physmem.readRowHits 17765 # Number of row buffer hits during reads +system.physmem.writeRowHits 1091 # Number of row buffer hits during writes +system.physmem.readRowHitRate 65.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.00 # Row buffer hit rate for writes +system.physmem.avgGap 5509671.28 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,246 +235,247 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 330361645 # number of cpu cycles simulated +system.cpu.numCycles 329136780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85614942 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80408346 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2411110 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47313103 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46933261 # Number of BTB hits +system.cpu.BPredUnit.lookups 85146783 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 79928286 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2342158 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47212748 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46871026 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1438558 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1082 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68875257 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669940715 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85614942 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48371819 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130120406 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13468606 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119373897 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 577 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67426910 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 785892 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 329401870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.167030 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.195227 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1427560 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1061 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68501011 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666829693 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85146783 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48298586 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129620938 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13095502 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119329475 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 67084220 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755001 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328178874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.165282 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193965 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199281685 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20931796 6.35% 66.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4976114 1.51% 68.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14405737 4.37% 72.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8916437 2.71% 75.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9491769 2.88% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4395407 1.33% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5797990 1.76% 81.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61204935 18.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198558185 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20911289 6.37% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4967188 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14345258 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8890662 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9436402 2.88% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4398507 1.34% 79.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5788329 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60883054 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 329401870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259155 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.027901 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93386530 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96217512 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108381185 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20386445 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11030198 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4725688 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1634 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 706212594 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6047 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11030198 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107646383 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14427218 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 44142 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114436491 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81817438 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697478243 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59322145 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20349848 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 693 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 724191424 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3242851069 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3242850941 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 328178874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258697 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.025996 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92947684 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96199178 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107899614 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20406722 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10725676 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4737184 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1561 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703240498 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5895 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10725676 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107135136 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14450172 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 44143 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114043084 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81780663 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694816427 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59310091 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20339427 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721301804 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230529001 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230528873 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96772235 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2137 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2090 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170767366 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172981751 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80655031 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21643688 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28602277 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 682247714 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3351 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646916263 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1413678 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79713119 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 198676272 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 420 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 329401870 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.963912 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726446 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 93882615 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2064 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2020 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170675831 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172202980 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80458110 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21583677 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28704390 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 679987725 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3320 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645601186 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1370428 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77447824 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193234107 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328178874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967223 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.725262 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68982651 20.94% 20.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85413517 25.93% 46.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75907397 23.04% 69.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40996794 12.45% 82.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28857883 8.76% 91.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14995240 4.55% 95.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5624116 1.71% 97.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6449034 1.96% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2175238 0.66% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68164683 20.77% 20.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85309693 25.99% 46.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75934594 23.14% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40814180 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28810425 8.78% 91.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14904242 4.54% 95.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5586841 1.70% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6537919 1.99% 99.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2116297 0.64% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 329401870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328178874 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 209715 5.57% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2699537 71.67% 77.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 857291 22.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 216945 5.75% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2691247 71.35% 77.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 863918 22.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403968416 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6570 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166149452 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76791822 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403371869 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165559477 25.64% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76663269 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646916263 # Type of FU issued -system.cpu.iq.rate 1.958206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3766543 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005822 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1628414581 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761976266 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638610282 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645601186 # Type of FU issued +system.cpu.iq.rate 1.961498 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3772110 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005843 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624523748 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757451010 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637563052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650682786 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649373276 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30415737 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30369655 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 24028931 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 122816 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12363 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10433791 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23250160 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123060 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12375 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10236870 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12786 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32242 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12923 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 32784 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11030198 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 797335 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 96405 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682254196 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 711562 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172981751 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80655031 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2002 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 33535 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20290 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12363 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1389918 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1519621 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2909539 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642699172 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163997886 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4217091 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10725676 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 798492 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 92069 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 679994152 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 690727 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172202980 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80458110 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1965 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 32845 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16029 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12375 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1358556 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460812 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2819368 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641523461 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163490704 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4077725 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3131 # number of nop insts executed -system.cpu.iew.exec_refs 239992833 # number of memory reference insts executed -system.cpu.iew.exec_branches 74738268 # Number of branches executed -system.cpu.iew.exec_stores 75994947 # Number of stores executed -system.cpu.iew.exec_rate 1.945441 # Inst execution rate -system.cpu.iew.wb_sent 640075541 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638610298 # cumulative count of insts written-back -system.cpu.iew.wb_producers 419218635 # num instructions producing a value -system.cpu.iew.wb_consumers 650818648 # num instructions consuming a value +system.cpu.iew.exec_nop 3107 # number of nop insts executed +system.cpu.iew.exec_refs 239380202 # number of memory reference insts executed +system.cpu.iew.exec_branches 74672586 # Number of branches executed +system.cpu.iew.exec_stores 75889498 # Number of stores executed +system.cpu.iew.exec_rate 1.949109 # Inst execution rate +system.cpu.iew.wb_sent 638973087 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637563068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418509904 # num instructions producing a value +system.cpu.iew.wb_consumers 649810327 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.933064 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644140 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937076 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644049 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79903729 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 77641136 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2409576 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 318371673 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.892006 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.234894 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2340694 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317453199 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897480 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237382 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93985379 29.52% 29.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104446341 32.81% 62.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43081844 13.53% 75.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8825548 2.77% 78.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25971107 8.16% 86.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12926353 4.06% 90.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7575563 2.38% 93.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1171571 0.37% 93.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20387967 6.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93244159 29.37% 29.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104350587 32.87% 62.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42987524 13.54% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8793922 2.77% 78.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25958876 8.18% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12900336 4.06% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7627072 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1171824 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20418899 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 318371673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 317453199 # Number of insts commited each cycle system.cpu.commit.committedInsts 570052771 # Number of instructions committed system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -485,317 +486,191 @@ system.cpu.commit.branches 70892751 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533523539 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20387967 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20418899 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 980247800 # The number of ROB reads -system.cpu.rob.rob_writes 1375591081 # The number of ROB writes -system.cpu.timesIdled 40973 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 959775 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 977035801 # The number of ROB reads +system.cpu.rob.rob_writes 1370761733 # The number of ROB writes +system.cpu.timesIdled 41126 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 957906 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570052720 # Number of Instructions Simulated system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated -system.cpu.cpi 0.579528 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.579528 # CPI: Total CPI of All Threads -system.cpu.ipc 1.725541 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.725541 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210576810 # number of integer regfile reads -system.cpu.int_regfile_writes 664235164 # number of integer regfile writes +system.cpu.cpi 0.577380 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577380 # CPI: Total CPI of All Threads +system.cpu.ipc 1.731963 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.731963 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204362065 # number of integer regfile reads +system.cpu.int_regfile_writes 663044095 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905305467 # number of misc regfile reads +system.cpu.misc_regfile_reads 901644614 # number of misc regfile reads system.cpu.misc_regfile_writes 3110 # number of misc regfile writes -system.cpu.icache.replacements 62 # number of replacements -system.cpu.icache.tagsinuse 692.874511 # Cycle average of tags in use -system.cpu.icache.total_refs 67425756 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 825 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 81728.189091 # Average number of references to valid blocks. +system.cpu.icache.replacements 60 # number of replacements +system.cpu.icache.tagsinuse 685.359263 # Cycle average of tags in use +system.cpu.icache.total_refs 67083066 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 820 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 81808.617073 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 692.874511 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.338318 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.338318 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67425756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67425756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67425756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67425756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67425756 # number of overall hits -system.cpu.icache.overall_hits::total 67425756 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 685.359263 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.334648 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.334648 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67083066 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67083066 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67083066 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67083066 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67083066 # number of overall hits +system.cpu.icache.overall_hits::total 67083066 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses system.cpu.icache.overall_misses::total 1154 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50922500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50922500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50922500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50922500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50922500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50922500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67426910 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67426910 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67426910 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67426910 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67426910 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67426910 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51351999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51351999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51351999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51351999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51351999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51351999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67084220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67084220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67084220 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67084220 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67084220 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67084220 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44126.949740 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44126.949740 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44126.949740 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44126.949740 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44126.949740 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44126.949740 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 247 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44499.132582 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44499.132582 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44499.132582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44499.132582 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38.428571 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 826 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 826 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 826 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 826 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 826 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38439500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38439500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38439500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38439500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38439500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38439500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 334 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38657999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38657999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38657999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38657999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38657999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38657999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46536.924939 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46536.924939 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46536.924939 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 46536.924939 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46536.924939 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 46536.924939 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47143.901220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47143.901220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440454 # number of replacements -system.cpu.dcache.tagsinuse 4091.536568 # Cycle average of tags in use -system.cpu.dcache.total_refs 198063046 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444550 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 445.536039 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 319624000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.536568 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998910 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 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hits -system.cpu.dcache.ReadReq_misses::cpu.data 341827 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341827 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3341748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3341748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3683575 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3683575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3683575 # number of overall misses -system.cpu.dcache.overall_misses::total 3683575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5150660000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5150660000 # number of ReadReq miss cycles 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hits +system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060483756 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060483756 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.145796 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.629975 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index ca675ac92..48dcd7446 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts +[system.cpu.isa] +type=SparcISA + [system.cpu.itb] type=SparcTLB size=64 @@ -451,22 +459,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -494,7 +504,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -516,14 +526,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 5518ac66c..10b614f5f 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:42 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:11:57 +gem5 started Oct 30 2012 14:00:44 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 389171398000 because target called exit() +Exiting @ tick 387281648500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index ef06efc76..c74d8b444 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.389228 # Number of seconds simulated -sim_ticks 389227542000 # Number of ticks simulated -final_tick 389227542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387282 # Number of seconds simulated +sim_ticks 387281648500 # Number of ticks simulated +final_tick 387281648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219415 # Simulator instruction rate (inst/s) -host_op_rate 220107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60950012 # Simulator tick rate (ticks/s) -host_mem_usage 227096 # Number of bytes of host memory used -host_seconds 6386.01 # Real time elapsed on the host +host_inst_rate 171377 # Simulator instruction rate (inst/s) +host_op_rate 171918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47367883 # Simulator tick rate (ticks/s) +host_mem_usage 224920 # Number of bytes of host memory used +host_seconds 8176.04 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 76608 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1678464 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76992 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76608 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1203 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1197 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 26226 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27429 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4312295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4510102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 416497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 416497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 416497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4312295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4926599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27430 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4333962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197810 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197810 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4333962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4950361 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27424 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29963 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755456 # Total number of bytes read from memory +system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755072 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755456 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1721 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 1715 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1769 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1667 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1745 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1621 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 158 # Tr system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 389227514000 # Total gap between requests +system.physmem.totGap 387281620500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27430 # Categorize read packet sizes +system.physmem.readPktSize::6 27424 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -171,265 +171,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 723930803 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1405746803 # Sum of mem lat for all requests -system.physmem.totBusLat 109720000 # Total cycles spent in databus access -system.physmem.totBankLat 572096000 # Total cycles spent in bank access -system.physmem.avgQLat 26391.94 # Average queueing delay per request -system.physmem.avgBankLat 20856.58 # Average bank access latency per request +system.physmem.totQLat 722664308 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1404176308 # Sum of mem lat for all requests +system.physmem.totBusLat 109696000 # Total cycles spent in databus access +system.physmem.totBankLat 571816000 # Total cycles spent in bank access +system.physmem.avgQLat 26351.53 # Average queueing delay per request +system.physmem.avgBankLat 20850.93 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 51248.52 # Average memory access latency -system.physmem.avgRdBW 4.51 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 51202.46 # Average memory access latency +system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.21 # Average write queue length over time -system.physmem.readRowHits 18327 # Number of row buffer hits during reads -system.physmem.writeRowHits 1092 # Number of row buffer hits during writes +system.physmem.avgWrQLen 17.43 # Average write queue length over time +system.physmem.readRowHits 18322 # Number of row buffer hits during reads +system.physmem.writeRowHits 1102 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.11 # Row buffer hit rate for writes -system.physmem.avgGap 12990271.80 # Average gap between requests +system.physmem.writeRowHitRate 43.51 # Row buffer hit rate for writes +system.physmem.avgGap 12927917.36 # Average gap between requests system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 778455085 # number of cpu cycles simulated +system.cpu.numCycles 774563298 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98229199 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88445613 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3785118 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66042302 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65687206 # Number of BTB hits +system.cpu.BPredUnit.lookups 97756783 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88046378 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3616115 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 65822232 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65492473 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1416 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 222 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165941423 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1649243289 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98229199 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65688622 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330524246 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21752869 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264030512 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3232 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162872893 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 756309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 778243541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.125156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146469 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1334 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 164852368 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642212446 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97756783 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65493807 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329195647 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20823123 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263322100 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2527 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 161933661 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 734964 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774355546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126740 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146682 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 447719295 57.53% 57.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74411347 9.56% 67.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37980792 4.88% 71.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9095898 1.17% 73.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28164996 3.62% 76.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18829907 2.42% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11517848 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3875799 0.50% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146647659 18.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445159899 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74061304 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37898461 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077519 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28105677 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18773272 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11484924 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3792333 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146002157 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 778243541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126185 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.118611 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217164629 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 215069073 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285415505 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42850333 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17744001 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642995255 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17744001 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241214952 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36881220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52262769 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303103685 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 127036914 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631617640 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 159 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927214 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 74044181 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3148431 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1361239803 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2756565281 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2722455578 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34109703 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774355546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126209 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.120178 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215883064 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214466469 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284208572 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42814616 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16982825 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636500589 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16982825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239715972 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36727743 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52434063 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302057850 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126437093 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625611071 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30924044 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73480825 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3128707 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356294088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746297990 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712224165 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34073825 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116469364 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2680762 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2695576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 273321719 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438834936 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180276836 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255914047 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82184887 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1517277053 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2635551 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1461048176 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 49743 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113961410 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136888972 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 391880 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 778243541 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.877366 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.430181 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111523649 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2645349 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2664178 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271657434 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436922066 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179745095 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254298230 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83339884 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512454597 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2610820 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459325981 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53748 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109158045 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130052751 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 367149 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774355546 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884568 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.432012 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147640445 18.97% 18.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 185782276 23.87% 42.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210767336 27.08% 69.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131005887 16.83% 86.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70732163 9.09% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20418483 2.62% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7758324 1.00% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3966460 0.51% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 172167 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145671235 18.81% 18.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184692846 23.85% 42.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209497548 27.05% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131299597 16.96% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70722781 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20304331 2.62% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8026000 1.04% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3959195 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182013 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 778243541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774355546 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 96825 5.83% 5.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95727 5.76% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1146892 69.00% 80.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 322714 19.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90752 5.46% 5.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95014 5.72% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1160014 69.81% 80.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 315922 19.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867232738 59.36% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2645576 0.18% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419895345 28.74% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171274517 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866438962 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644873 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419117163 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171124983 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1461048176 # Type of FU issued -system.cpu.iq.rate 1.876856 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1662158 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001138 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3684211603 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624908064 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444562282 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17840191 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9203552 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8548837 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453579294 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9131040 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215356561 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459325981 # Type of FU issued +system.cpu.iq.rate 1.884063 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1661702 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676896998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615267495 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443201042 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17825960 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9193607 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8546616 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451866721 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9120962 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215450617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36322093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55076 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245947 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13428694 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34409223 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 57798 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 244556 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12896953 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3648 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 92141 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 91608 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17744001 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3080372 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 245510 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1614123458 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4140274 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438834936 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180276836 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2549819 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 147701 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1738 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245947 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2356068 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1563417 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3919485 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455490088 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417172237 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5558088 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16982825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3082295 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247112 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608751818 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125389 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436922066 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179745095 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2527727 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 148822 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1680 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 244556 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2270064 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1474247 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3744311 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454009970 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416570645 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5316011 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94210854 # number of nop insts executed -system.cpu.iew.exec_refs 587755640 # number of memory reference insts executed -system.cpu.iew.exec_branches 89119477 # Number of branches executed -system.cpu.iew.exec_stores 170583403 # Number of stores executed -system.cpu.iew.exec_rate 1.869716 # Inst execution rate -system.cpu.iew.wb_sent 1454027442 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1453111119 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154511485 # num instructions producing a value -system.cpu.iew.wb_consumers 1205709259 # num instructions consuming a value +system.cpu.iew.exec_nop 93686401 # number of nop insts executed +system.cpu.iew.exec_refs 587021920 # number of memory reference insts executed +system.cpu.iew.exec_branches 89037548 # Number of branches executed +system.cpu.iew.exec_stores 170451275 # Number of stores executed +system.cpu.iew.exec_rate 1.877200 # Inst execution rate +system.cpu.iew.wb_sent 1452636193 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451747658 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153420359 # num instructions producing a value +system.cpu.iew.wb_consumers 1204679279 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.866660 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957537 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874279 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957450 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 124505734 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119133058 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3785118 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 760500151 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.958610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504084 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3616115 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757373332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966696 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509453 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 241986025 31.82% 31.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276568961 36.37% 68.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42982436 5.65% 73.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54874417 7.22% 81.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19672131 2.59% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13330795 1.75% 85.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30549094 4.02% 89.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10561201 1.39% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69975091 9.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 239955150 31.68% 31.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275777678 36.41% 68.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42556583 5.62% 73.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54728215 7.23% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19718156 2.60% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13293088 1.76% 85.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30577311 4.04% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10491345 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70275806 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 760500151 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757373332 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -440,374 +441,374 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69975091 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70275806 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2304489206 # The number of ROB reads -system.cpu.rob.rob_writes 3245826636 # The number of ROB writes -system.cpu.timesIdled 25902 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 211544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295688996 # The number of ROB reads +system.cpu.rob.rob_writes 3234318218 # The number of ROB writes +system.cpu.timesIdled 25993 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 207752 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.555568 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555568 # CPI: Total CPI of All Threads -system.cpu.ipc 1.799961 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.799961 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980833855 # number of integer regfile reads -system.cpu.int_regfile_writes 1276392600 # number of integer regfile writes -system.cpu.fp_regfile_reads 16967472 # number of floating regfile reads -system.cpu.fp_regfile_writes 10493116 # number of floating regfile writes -system.cpu.misc_regfile_reads 593429000 # number of misc regfile reads +system.cpu.cpi 0.552790 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552790 # CPI: Total CPI of All Threads +system.cpu.ipc 1.809005 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.809005 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979115545 # number of integer regfile reads +system.cpu.int_regfile_writes 1275157860 # number of integer regfile writes +system.cpu.fp_regfile_reads 16963296 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491838 # number of floating regfile writes +system.cpu.misc_regfile_reads 592677531 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 221 # number of replacements -system.cpu.icache.tagsinuse 1044.865694 # Cycle average of tags in use -system.cpu.icache.total_refs 162870916 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1368 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119057.687135 # Average number of references to valid blocks. +system.cpu.icache.replacements 190 # number of replacements +system.cpu.icache.tagsinuse 1035.892325 # Cycle average of tags in use +system.cpu.icache.total_refs 161931728 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1331 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121661.703982 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1044.865694 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.510188 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.510188 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162870916 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162870916 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162870916 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162870916 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162870916 # number of overall hits -system.cpu.icache.overall_hits::total 162870916 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1977 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1977 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1977 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1977 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1977 # number of overall misses -system.cpu.icache.overall_misses::total 1977 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82311500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82311500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82311500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82311500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82311500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82311500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162872893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162872893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162872893 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162872893 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162872893 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162872893 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.892325 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505807 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505807 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161931728 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161931728 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161931728 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161931728 # number of demand (read+write) hits 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+system.cpu.icache.overall_miss_latency::cpu.inst 80019500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 80019500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161933661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161933661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161933661 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161933661 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161933661 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161933661 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for 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+system.cpu.dcache.occ_blocks::cpu.data 4093.828969 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999470 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999470 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200081459 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200081459 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955943 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955943 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365739456 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365739456 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365739456 # number of overall hits -system.cpu.dcache.overall_hits::total 365739456 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 929575 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 929575 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1888210 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1888210 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365037402 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365037402 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365037402 # number of overall hits +system.cpu.dcache.overall_hits::total 365037402 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 927524 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 927524 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1890873 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1890873 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2817785 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2817785 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2817785 # number of overall misses -system.cpu.dcache.overall_misses::total 2817785 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14994299000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14994299000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31871156950 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31871156950 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2818397 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2818397 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2818397 # number of overall misses +system.cpu.dcache.overall_misses::total 2818397 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988914500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14988914500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31918196457 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31918196457 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46865455950 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46865455950 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46865455950 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46865455950 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201710425 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201710425 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46907110957 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46907110957 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46907110957 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46907110957 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201008983 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201008983 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368557241 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368557241 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368557241 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368557241 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004608 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004608 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011317 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011317 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 367855799 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 367855799 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 367855799 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 367855799 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004614 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004614 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011333 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011333 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007645 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007645 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007645 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007645 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16130.273512 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16130.273512 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16879.031967 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16879.031967 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.007662 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007662 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007662 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007662 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16160.136557 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16160.136557 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16880.137617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16880.137617 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16632.019813 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16632.019813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16632.019813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16632.019813 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 577430 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35655 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16643.187939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16643.187939 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 574305 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35651 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.194924 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.109085 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 442964 # number of writebacks -system.cpu.dcache.writebacks::total 442964 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 729519 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 729519 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1626163 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1626163 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2355682 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2355682 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2355682 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2355682 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200056 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200056 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262047 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262047 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443776 # number of writebacks +system.cpu.dcache.writebacks::total 443776 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726784 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 726784 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628507 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628507 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2355291 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2355291 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2355291 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2355291 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200740 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200740 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262366 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262366 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 462103 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 462103 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 462103 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 462103 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2627957000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2627957000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4314187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4314187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 463106 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463106 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463106 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463106 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2634282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2634282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319277500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319277500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942144000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6942144000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942144000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6942144000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6953560000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6953560000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6953560000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6953560000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001572 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13136.106890 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13136.106890 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16463.409236 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16463.409236 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13122.857926 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13122.857926 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16462.794341 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16462.794341 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15022.936445 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15022.936445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15022.936445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15022.936445 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22458.024259 # Cycle average of tags in use -system.cpu.l2cache.total_refs 548899 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24278 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.608905 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20744.377954 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1070.274135 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 643.372169 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633068 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032662 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019634 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685365 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 165 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 195629 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 195794 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 442964 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 442964 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240255 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240255 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 165 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 435884 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 436049 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 165 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 435884 # number of overall hits -system.cpu.l2cache.overall_hits::total 436049 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1204 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4426 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5630 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21800 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21800 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26226 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27430 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1204 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26226 # number of overall misses -system.cpu.l2cache.overall_misses::total 27430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57312000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 469280500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 526592500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1549286000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1549286000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57312000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2018566500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2075878500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57312000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2018566500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2075878500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1369 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 200055 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 201424 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 442964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 442964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 262055 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 262055 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1369 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 462110 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 463479 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1369 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 462110 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.879474 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022124 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.027951 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083189 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083189 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.879474 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.056753 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059183 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.879474 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.056753 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059183 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47601.328904 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 106028.129236 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 93533.303730 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71068.165138 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71068.165138 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47601.328904 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76968.142302 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75679.128691 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47601.328904 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76968.142302 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75679.128691 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks -system.cpu.l2cache.writebacks::total 2533 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1204 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4426 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5630 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21800 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21800 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26226 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27430 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1204 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26226 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27430 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42159963 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413894207 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 456054170 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1275808135 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1275808135 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42159963 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1689702342 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1731862305 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42159963 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1689702342 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1731862305 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022124 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027951 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083189 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083189 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056753 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059183 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056753 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059183 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35016.580565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93514.280840 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81004.293073 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58523.308945 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58523.308945 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35016.580565 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64428.519103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63137.524790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35016.580565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64428.519103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63137.524790 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index abf2e74d2..f6f519501 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,17 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -430,17 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -462,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -470,30 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -503,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -521,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index dbf6b4770..48eb9aa0f 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:44:55 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 16:17:19 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,10 +18,10 @@ Uncompressing Data info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly -info: Increasing stack size by one page. Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 @@ -42,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 609566727000 because target called exit() +Exiting @ tick 607235830000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 43ee6670c..74f46e926 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.610645 # Number of seconds simulated -sim_ticks 610645123000 # Number of ticks simulated -final_tick 610645123000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.607236 # Number of seconds simulated +sim_ticks 607235830000 # Number of ticks simulated +final_tick 607235830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90668 # Simulator instruction rate (inst/s) -host_op_rate 167061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62914134 # Simulator tick rate (ticks/s) -host_mem_usage 229848 # Number of bytes of host memory used -host_seconds 9706.01 # Real time elapsed on the host +host_inst_rate 71722 # Simulator instruction rate (inst/s) +host_op_rate 132152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49489751 # Simulator tick rate (ticks/s) +host_mem_usage 226812 # Number of bytes of host memory used +host_seconds 12269.93 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493925 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1693312 # Number of bytes read from this memory -system.physmem.bytes_read::total 1751360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory -system.physmem.bytes_written::total 162176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26458 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27365 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2772989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2868049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 265581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 265581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 265581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2772989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3133630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27367 # Total number of read requests seen -system.physmem.writeReqs 2534 # Total number of write requests seen -system.physmem.cpureqs 29901 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1751360 # Total number of bytes read from memory -system.physmem.bytesWritten 162176 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1751360 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 57472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693120 # Number of bytes read from this memory +system.physmem.bytes_read::total 1750592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 57472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory +system.physmem.bytes_written::total 162112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27353 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2788241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2882887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94645 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94645 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 266967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 266967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 266967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2788241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3149854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27355 # Total number of read requests seen +system.physmem.writeReqs 2533 # Total number of write requests seen +system.physmem.cpureqs 29888 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1750592 # Total number of bytes read from memory +system.physmem.bytesWritten 162112 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1750592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1748 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1747 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1672 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1756 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1779 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1777 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1808 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1660 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1691 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis @@ -72,19 +72,19 @@ system.physmem.perBankWrReqs::9 158 # Tr system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 154 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 156 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 610645109000 # Total gap between requests +system.physmem.totGap 607235813000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27367 # Categorize read packet sizes +system.physmem.readPktSize::6 27355 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2534 # categorize write packet sizes +system.physmem.writePktSize::6 2533 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 26902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 26898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -141,7 +141,7 @@ system.physmem.rdQLenPdf::32 0 # Wh system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see @@ -171,264 +171,264 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 68648669 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 822368669 # Sum of mem lat for all requests -system.physmem.totBusLat 109468000 # Total cycles spent in databus access -system.physmem.totBankLat 644252000 # Total cycles spent in bank access -system.physmem.avgQLat 2508.45 # Average queueing delay per request -system.physmem.avgBankLat 23541.20 # Average bank access latency per request +system.physmem.totQLat 67414668 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 820820668 # Sum of mem lat for all requests +system.physmem.totBusLat 109420000 # Total cycles spent in databus access +system.physmem.totBankLat 643986000 # Total cycles spent in bank access +system.physmem.avgQLat 2464.44 # Average queueing delay per request +system.physmem.avgBankLat 23541.80 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30049.65 # Average memory access latency -system.physmem.avgRdBW 2.87 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 30006.24 # Average memory access latency +system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.42 # Average write queue length over time -system.physmem.readRowHits 17709 # Number of row buffer hits during reads -system.physmem.writeRowHits 1083 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 42.74 # Row buffer hit rate for writes -system.physmem.avgGap 20422230.33 # Average gap between requests +system.physmem.avgWrQLen 4.32 # Average write queue length over time +system.physmem.readRowHits 17706 # Number of row buffer hits during reads +system.physmem.writeRowHits 1086 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 42.87 # Row buffer hit rate for writes +system.physmem.avgGap 20317044.06 # Average gap between requests system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1221290247 # number of cpu cycles simulated +system.cpu.numCycles 1214471661 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 153796448 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 153796448 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26699295 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 76444965 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 76044325 # Number of BTB hits +system.cpu.BPredUnit.lookups 158566645 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 158566645 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26386333 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 83466743 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83279512 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180218290 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1484873312 # Number of instructions fetch has processed -system.cpu.fetch.Branches 153796448 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 76044325 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 400561886 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 92153015 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574855756 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 434 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 186235545 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9536973 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1220934154 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.078258 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.273787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 179036467 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1457944289 # Number of instructions fetch has processed +system.cpu.fetch.Branches 158566645 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83279512 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 399021545 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88092537 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 574509498 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 50 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 341 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186960601 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10940939 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214117357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.059847 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.253407 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 827594377 67.78% 67.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24117068 1.98% 69.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15648261 1.28% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17796387 1.46% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26716755 2.19% 74.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18183763 1.49% 76.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28386980 2.33% 78.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39418545 3.23% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 223072018 18.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 822311931 67.73% 67.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26973525 2.22% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13085420 1.08% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20645432 1.70% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26636403 2.19% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18254688 1.50% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31306986 2.58% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39069186 3.22% 82.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215833786 17.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1220934154 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125929 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215823 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 289407961 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 498246191 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 275145699 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92836570 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 65297733 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2356719721 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 65297733 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 337924282 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 123917110 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2381 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 305534064 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 388258584 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2260509367 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 337 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242606329 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120880984 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2627145665 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5770220684 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5770216108 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4576 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1214117357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130564 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.200476 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 288149545 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497851788 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274001581 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92564987 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 61549456 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2343342483 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 61549456 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 336776305 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124136399 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2472 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303957244 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387695481 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2247540252 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 338 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242690737 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120190709 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2617793255 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5721514338 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5721508630 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5708 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 740250408 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 92 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731279841 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542420235 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220423040 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 348990798 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 145234295 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2013682993 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 521 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784560921 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 286575 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 391758246 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 817229320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 471 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1220934154 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.461636 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.419528 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 730897998 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 87 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 731315186 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 531685334 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219218078 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 341957322 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144669482 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1993566712 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1783999852 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 259167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 371673921 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 759176081 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 236 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1214117357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.469380 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.421908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 365719162 29.95% 29.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 365027224 29.90% 59.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234751927 19.23% 79.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141361627 11.58% 90.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60962306 4.99% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39637127 3.25% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10977510 0.90% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1933125 0.16% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 564146 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360157334 29.66% 29.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364096004 29.99% 59.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234218772 19.29% 78.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141579875 11.66% 90.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60576135 4.99% 95.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39770363 3.28% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11069235 0.91% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2042198 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 607441 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1220934154 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214117357 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 457693 15.95% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2209699 77.01% 92.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 202113 7.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 448044 15.51% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2239769 77.53% 93.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 201121 6.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812464 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065891237 59.73% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479189352 26.85% 89.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192667868 10.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812236 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065749303 59.74% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478900937 26.84% 89.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192537376 10.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784560921 # Type of FU issued -system.cpu.iq.rate 1.461210 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2869505 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001608 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4793211641 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2405618854 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1725377736 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1480 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 90 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740617772 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 190 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209954463 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1783999852 # Type of FU issued +system.cpu.iq.rate 1.468951 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2888934 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001619 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4785264711 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2365417546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1724692001 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 451 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1804 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740076331 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 219 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209988104 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123378114 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 38587 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 183844 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 32236983 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 112643213 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 39222 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 182717 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31032021 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2078 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2338 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 61 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 65297733 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1143885 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 111744 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2013683514 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63490304 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542420235 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220423040 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 55193 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2862 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 183844 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2121921 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24727534 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26849455 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766386720 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474113432 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18174201 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 61549456 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1140639 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 111456 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1993566998 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 62891461 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 531685334 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219218078 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 82 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 54713 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2863 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 182717 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2045566 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24470672 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26516238 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766182455 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474610807 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17817397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665931472 # number of memory reference insts executed -system.cpu.iew.exec_branches 110216269 # Number of branches executed -system.cpu.iew.exec_stores 191818040 # Number of stores executed -system.cpu.iew.exec_rate 1.446328 # Inst execution rate -system.cpu.iew.wb_sent 1726595079 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1725377826 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1268018973 # num instructions producing a value -system.cpu.iew.wb_consumers 1829950696 # num instructions consuming a value +system.cpu.iew.exec_refs 666317556 # number of memory reference insts executed +system.cpu.iew.exec_branches 110350315 # Number of branches executed +system.cpu.iew.exec_stores 191706749 # Number of stores executed +system.cpu.iew.exec_rate 1.454281 # Inst execution rate +system.cpu.iew.wb_sent 1725793430 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1724692117 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267138729 # num instructions producing a value +system.cpu.iew.wb_consumers 1828924593 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.412750 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692925 # average fanout of values written-back +system.cpu.iew.wb_rate 1.420117 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692833 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 392192006 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 372074312 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26699352 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1155636421 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.403118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.832114 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26386383 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1152567901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.406853 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.830346 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 422545803 36.56% 36.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 413097230 35.75% 72.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87361742 7.56% 79.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122290747 10.58% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24514270 2.12% 92.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22708378 1.97% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18848985 1.63% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12046038 1.04% 97.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32223228 2.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 417955350 36.26% 36.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 415054079 36.01% 72.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86939331 7.54% 79.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122127082 10.60% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24184880 2.10% 92.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25402622 2.20% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16383099 1.42% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12042950 1.04% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32478508 2.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1155636421 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1152567901 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -439,148 +439,290 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32223228 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32478508 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3137099124 # The number of ROB reads -system.cpu.rob.rob_writes 4092706915 # The number of ROB writes -system.cpu.timesIdled 59218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 356093 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3113657630 # The number of ROB reads +system.cpu.rob.rob_writes 4048721682 # The number of ROB writes +system.cpu.timesIdled 59087 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 354304 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.387790 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.387790 # CPI: Total CPI of All Threads -system.cpu.ipc 0.720570 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.720570 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3541569732 # number of integer regfile reads -system.cpu.int_regfile_writes 1975385267 # number of integer regfile writes -system.cpu.fp_regfile_reads 90 # number of floating regfile reads -system.cpu.misc_regfile_reads 910403293 # number of misc regfile reads -system.cpu.icache.replacements 20 # number of replacements -system.cpu.icache.tagsinuse 822.205718 # Cycle average of tags in use -system.cpu.icache.total_refs 186234150 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 202648.694233 # Average number of references to valid blocks. +system.cpu.cpi 1.380042 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.380042 # CPI: Total CPI of All Threads +system.cpu.ipc 0.724616 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.724616 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3542913524 # number of integer regfile reads +system.cpu.int_regfile_writes 1974599259 # number of integer regfile writes +system.cpu.fp_regfile_reads 116 # number of floating regfile reads +system.cpu.misc_regfile_reads 910763104 # number of misc regfile reads +system.cpu.icache.replacements 26 # number of replacements +system.cpu.icache.tagsinuse 814.074374 # Cycle average of tags in use +system.cpu.icache.total_refs 186959214 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 915 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 204327.009836 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 822.205718 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.401468 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.401468 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 186234151 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 186234151 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 186234151 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 186234151 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 186234151 # number of overall hits -system.cpu.icache.overall_hits::total 186234151 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1394 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1394 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1394 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1394 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1394 # number of overall misses -system.cpu.icache.overall_misses::total 1394 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 63295000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 63295000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 63295000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 63295000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 63295000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 63295000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 186235545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 186235545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 186235545 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 186235545 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 186235545 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 186235545 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 814.074374 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.397497 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.397497 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186959220 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186959220 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186959220 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186959220 # number of demand (read+write) hits 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46195.872556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46195.872556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46195.872556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46195.872556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46195.872556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46195.872556 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 249 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.333333 # average number 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-system.cpu.l2cache.tagsinuse 22261.498307 # Cycle average of tags in use -system.cpu.l2cache.total_refs 530423 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24197 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.921023 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20782.532445 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 804.542121 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 674.423741 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.634233 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024553 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020582 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.679367 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 198746 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 198758 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428512 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428512 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224294 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224294 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 423040 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 423052 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 423040 # number of overall hits -system.cpu.l2cache.overall_hits::total 423052 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 907 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4543 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5450 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21917 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21917 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 907 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26460 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27367 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 907 # number of overall misses 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ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089017 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986942 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.058865 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060759 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986942 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058865 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060759 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49611.356119 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71620.074840 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67957.339450 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 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-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2534 # number of writebacks -system.cpu.l2cache.writebacks::total 2534 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4543 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5450 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21917 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21917 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26460 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27367 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26460 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27367 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33582421 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267466906 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301049327 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 797222639 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 797222639 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33582421 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064689545 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1098271966 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33582421 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064689545 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1098271966 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022347 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026688 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058865 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060759 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058865 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060759 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37025.822492 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58874.511556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55238.408624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36374.624219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36374.624219 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37025.822492 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40237.700113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40131.251727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37025.822492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40237.700113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40131.251727 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 9dfc48f3b..31bcf2795 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:268435455 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 62518a9bb..15ba3aa9f 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:53:48 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 19:23:29 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 28505597000 because target called exit() +Exiting @ tick 26786364500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 7f5474242..c26c8db9e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.027092 # Number of seconds simulated -sim_ticks 27092156000 # Number of ticks simulated -final_tick 27092156000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026786 # Number of seconds simulated +sim_ticks 26786364500 # Number of ticks simulated +final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163409 # Simulator instruction rate (inst/s) -host_op_rate 164582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48864627 # Simulator tick rate (ticks/s) -host_mem_usage 366512 # Number of bytes of host memory used -host_seconds 554.43 # Real time elapsed on the host -sim_insts 90599363 # Number of instructions simulated -sim_ops 91249916 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory -system.physmem.bytes_read::total 993280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45696 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 714 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1686687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34976323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36663011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1686687 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1686687 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1686687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34976323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36663011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15520 # Total number of read requests seen +host_inst_rate 151377 # Simulator instruction rate (inst/s) +host_op_rate 152464 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44755705 # Simulator tick rate (ticks/s) +host_mem_usage 363280 # Number of bytes of host memory used +host_seconds 598.50 # Real time elapsed on the host +sim_insts 90599358 # Number of instructions simulated +sim_ops 91249911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory +system.physmem.bytes_read::total 992768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15512 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1689218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35373221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37062439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1689218 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1689218 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1689218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35373221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 37062439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15512 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 993280 # Total number of bytes read from memory +system.physmem.cpureqs 15514 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 992768 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 993280 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 992768 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 965 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 903 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 938 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 942 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1013 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1012 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 977 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 933 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1021 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 978 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 27092026500 # Total gap between requests +system.physmem.totGap 26786185500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15520 # Categorize read packet sizes +system.physmem.readPktSize::6 15512 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,16 +95,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 2 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 41952001 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 275602001 # Sum of mem lat for all requests -system.physmem.totBusLat 62080000 # Total cycles spent in databus access -system.physmem.totBankLat 171570000 # Total cycles spent in bank access -system.physmem.avgQLat 2703.09 # Average queueing delay per request -system.physmem.avgBankLat 11054.77 # Average bank access latency per request +system.physmem.totQLat 45050979 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 279102979 # Sum of mem lat for all requests +system.physmem.totBusLat 62048000 # Total cycles spent in databus access +system.physmem.totBankLat 172004000 # Total cycles spent in bank access +system.physmem.avgQLat 2904.27 # Average queueing delay per request +system.physmem.avgBankLat 11088.45 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 17757.86 # Average memory access latency -system.physmem.avgRdBW 36.66 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 17992.71 # Average memory access latency +system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 36.66 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15093 # Number of row buffer hits during reads +system.physmem.readRowHits 15087 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.25 # Row buffer hit rate for reads +system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1745620.26 # Average gap between requests +system.physmem.avgGap 1726804.12 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,569 +228,451 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 54184313 # number of cpu cycles simulated +system.cpu.numCycles 53572730 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26986209 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22240935 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 891955 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11647054 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11461257 # Number of BTB hits +system.cpu.BPredUnit.lookups 26681190 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22001511 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 842165 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11371976 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11281654 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 72758 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 485 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14421407 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 129482789 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26986209 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11534015 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24364148 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4949387 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11145499 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14072424 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 353920 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53972527 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.416768 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.215873 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14169802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11256916 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13841949 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329938 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53360207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29646325 54.93% 54.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3454402 6.40% 61.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2035756 3.77% 65.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1585198 2.94% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1689643 3.13% 71.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2992855 5.55% 76.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1501294 2.78% 79.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1109449 2.06% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9957605 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29366337 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1666559 3.12% 71.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2918525 5.47% 76.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1512890 2.84% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090822 2.04% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53972527 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.498045 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.389673 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17207234 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9007840 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22744655 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 980413 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4032385 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4494708 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 9020 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 127545337 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43010 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4032385 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19020781 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3479230 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 185856 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21813074 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5441201 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124457435 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 413531 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4571711 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1235 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145128165 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 542105971 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 542097092 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8879 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429490 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37698675 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6572 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6570 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12467133 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29726886 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5575716 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2113972 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1267479 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119141743 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10445 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105694934 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 87169 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27699731 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68149614 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 314 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53972527 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.958310 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906959 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 53360207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9104448 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4441470 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126048465 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42747 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3892391 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21547168 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123140443 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143600920 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536395589 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536390601 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36171438 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29470902 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5524793 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2121904 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1282766 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118150173 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 10438 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105160593 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79722 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53360207 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15655199 29.01% 29.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11785517 21.84% 50.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8331092 15.44% 66.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6816137 12.63% 78.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4950230 9.17% 88.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2999113 5.56% 93.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2477964 4.59% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 523647 0.97% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 433628 0.80% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15336122 28.74% 28.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4978396 9.33% 88.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2962958 5.55% 93.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2475458 4.64% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 518730 0.97% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53972527 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53360207 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 46062 6.88% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 347309 51.84% 58.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276528 41.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340422 51.49% 58.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275350 41.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74789995 70.76% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10964 0.01% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 273 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 352 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25743831 24.36% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5149514 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74420683 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25610261 24.35% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5118329 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105694934 # Type of FU issued -system.cpu.iq.rate 1.950656 # Inst issue rate -system.cpu.iq.fu_busy_cnt 669926 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006338 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 266118166 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146855539 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 103065096 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1324 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1913 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 572 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106364200 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 660 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 431890 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105160593 # Type of FU issued +system.cpu.iq.rate 1.962950 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264421445 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1049 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 331 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105821300 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 443954 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7151007 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8111 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6407 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 828959 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6895024 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7123 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6272 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 778037 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30712 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31249 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4032385 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 880978 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 122273 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119164915 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 339993 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29726886 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5575716 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6543 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65097 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6980 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6407 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 480710 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 474427 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 955137 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104665581 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25412111 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1029353 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3892391 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309093 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66339 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6977 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6272 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446356 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445453 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 891809 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104181304 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25288567 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 979289 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12727 # number of nop insts executed -system.cpu.iew.exec_refs 30497033 # number of memory reference insts executed -system.cpu.iew.exec_branches 21398144 # Number of branches executed -system.cpu.iew.exec_stores 5084922 # Number of stores executed -system.cpu.iew.exec_rate 1.931658 # Inst execution rate -system.cpu.iew.wb_sent 103359257 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 103065668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62382767 # num instructions producing a value -system.cpu.iew.wb_consumers 104584630 # num instructions consuming a value +system.cpu.iew.exec_nop 12695 # number of nop insts executed +system.cpu.iew.exec_refs 30349931 # number of memory reference insts executed +system.cpu.iew.exec_branches 21325057 # Number of branches executed +system.cpu.iew.exec_stores 5061364 # Number of stores executed +system.cpu.iew.exec_rate 1.944670 # Inst execution rate +system.cpu.iew.wb_sent 102965645 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102686542 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62242061 # num instructions producing a value +system.cpu.iew.wb_consumers 104289210 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.902131 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596481 # average fanout of values written-back +system.cpu.iew.wb_rate 1.916769 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596822 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27905407 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10131 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 883062 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49940143 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.827438 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.524426 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 26913567 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 833602 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49467817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.844887 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.541636 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20246507 40.54% 40.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13253757 26.54% 67.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4242903 8.50% 75.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3506121 7.02% 82.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1547134 3.10% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 741508 1.48% 87.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 927602 1.86% 89.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253977 0.51% 89.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5220634 10.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19986876 40.40% 40.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13133000 26.55% 66.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4163273 8.42% 75.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3434953 6.94% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1533681 3.10% 85.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 739386 1.49% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 948988 1.92% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 248747 0.50% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5278913 10.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49940143 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611972 # Number of instructions committed -system.cpu.commit.committedOps 91262525 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 49467817 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611967 # Number of instructions committed +system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322636 # Number of memory references committed -system.cpu.commit.loads 22575879 # Number of loads committed +system.cpu.commit.refs 27322634 # Number of memory references committed +system.cpu.commit.loads 22575878 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18734217 # Number of branches committed +system.cpu.commit.branches 18734216 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533326 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5220634 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5278913 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 163881707 # The number of ROB reads -system.cpu.rob.rob_writes 242387570 # The number of ROB writes -system.cpu.timesIdled 40508 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 211786 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599363 # Number of Instructions Simulated -system.cpu.committedOps 91249916 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599363 # Number of Instructions Simulated -system.cpu.cpi 0.598065 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.598065 # CPI: Total CPI of All Threads -system.cpu.ipc 1.672059 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.672059 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 497610089 # number of integer regfile reads -system.cpu.int_regfile_writes 120987803 # number of integer regfile writes -system.cpu.fp_regfile_reads 263 # number of floating regfile reads -system.cpu.fp_regfile_writes 760 # number of floating regfile writes -system.cpu.misc_regfile_reads 183141130 # number of misc regfile reads -system.cpu.misc_regfile_writes 11610 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 641.121517 # Cycle average of tags in use -system.cpu.icache.total_refs 14071405 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 743 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18938.633917 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 162359257 # The number of ROB reads +system.cpu.rob.rob_writes 240263976 # The number of ROB writes +system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 212523 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599358 # Number of Instructions Simulated +system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated +system.cpu.cpi 0.591315 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.591315 # CPI: Total CPI of All Threads +system.cpu.ipc 1.691147 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.691147 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495578845 # number of integer regfile reads +system.cpu.int_regfile_writes 120555497 # number of integer regfile writes +system.cpu.fp_regfile_reads 176 # number of floating regfile reads +system.cpu.fp_regfile_writes 427 # number of floating regfile writes +system.cpu.misc_regfile_reads 181219036 # number of misc regfile reads +system.cpu.misc_regfile_writes 11608 # number of misc regfile writes +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 632.599736 # Cycle average of tags in use +system.cpu.icache.total_refs 13840965 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 735 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 18831.244898 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 641.121517 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.313048 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.313048 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14071405 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14071405 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14071405 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14071405 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14071405 # number of overall hits -system.cpu.icache.overall_hits::total 14071405 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1017 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1017 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1017 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1017 # number of overall misses -system.cpu.icache.overall_misses::total 1017 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47244499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47244499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47244499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47244499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47244499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47244499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14072422 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14072422 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14072422 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14072422 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14072422 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14072422 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46454.767945 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46454.767945 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46454.767945 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46454.767945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46454.767945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46454.767945 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 632.599736 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.308887 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.308887 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13840965 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13840965 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13840965 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits +system.cpu.icache.overall_hits::total 13840965 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses +system.cpu.icache.overall_misses::total 983 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48291499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48291499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48291499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48291499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48291499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48291499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13841948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13841948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13841948 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13841948 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13841948 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13841948 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49126.652085 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49126.652085 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49126.652085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49126.652085 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 274 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 274 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 274 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 274 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 274 # number of overall MSHR hits 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36064499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36064499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses 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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48539.029610 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48539.029610 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48539.029610 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48539.029610 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48539.029610 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48539.029610 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49748.307172 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49748.307172 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943610 # number of replacements -system.cpu.dcache.tagsinuse 3668.756958 # Cycle average of tags in use -system.cpu.dcache.total_refs 28277834 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947706 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.838192 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8133068000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3668.756958 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.895693 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.895693 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23721969 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23721969 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4544209 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4544209 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 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demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19138646929 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19138646929 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24904938 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24904938 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5800 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5800 # number of StoreCondReq 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0.046348 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046348 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046348 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046348 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11773.240465 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11773.240465 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27316.736361 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27316.736361 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13931.772386 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13931.772386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13931.772386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13931.772386 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 151113 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23634 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.393882 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942971 # number of writebacks -system.cpu.dcache.writebacks::total 942971 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 275787 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 275787 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150248 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 150248 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 426035 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 426035 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 426035 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 426035 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907182 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 907182 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40524 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 40524 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947706 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947706 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947706 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947706 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10023226500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10023226500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 922752968 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 922752968 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945979468 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10945979468 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945979468 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10945979468 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036426 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036426 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008558 # mshr miss rate for WriteReq accesses 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overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11549.973798 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11549.973798 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10724.733108 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1834762 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15503 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.348836 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15495 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.204389 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 9870.615236 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 623.470728 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 230.647144 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.301227 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.019027 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007039 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.327293 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 906888 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 906916 # number of ReadReq hits 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-system.cpu.l2cache.Writeback_accesses::writebacks 942971 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942971 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 40539 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 40539 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 743 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947706 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948449 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 743 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947706 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948449 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 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+system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses +system.cpu.dcache.overall_misses::total 1370806 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks +system.cpu.dcache.writebacks::total 942892 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index b61f2399d..b0792be17 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,17 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -430,17 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -462,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -470,30 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -503,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -521,9 +528,9 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:268435455 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 70c115e37..d71b96b19 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 23:05:45 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 16:29:18 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,7 +16,6 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 -info: Increasing stack size by one page. flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 @@ -26,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 64346039000 because target called exit() +Exiting @ tick 66000220500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 973686ac9..80c10d75b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.067525 # Number of seconds simulated -sim_ticks 67525253000 # Number of ticks simulated -final_tick 67525253000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066000 # Number of seconds simulated +sim_ticks 66000220500 # Number of ticks simulated +final_tick 66000220500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116144 # Simulator instruction rate (inst/s) -host_op_rate 204512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49640781 # Simulator tick rate (ticks/s) -host_mem_usage 364964 # Number of bytes of host memory used -host_seconds 1360.28 # Real time elapsed on the host +host_inst_rate 92408 # Simulator instruction rate (inst/s) +host_op_rate 162716 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38603772 # Simulator tick rate (ticks/s) +host_mem_usage 361664 # Number of bytes of host memory used +host_seconds 1709.68 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 66944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1886080 # Number of bytes read from this memory -system.physmem.bytes_read::total 1953024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 13568 # Number of bytes written to this memory -system.physmem.bytes_written::total 13568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1046 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29470 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 212 # Number of write requests responded to by this memory -system.physmem.num_writes::total 212 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 991392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 27931476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 28922868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 991392 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 991392 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 991392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 27931476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29123801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30518 # Total number of read requests seen -system.physmem.writeReqs 212 # Total number of write requests seen -system.physmem.cpureqs 30733 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1953024 # Total number of bytes read from memory -system.physmem.bytesWritten 13568 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1953024 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 13568 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 63 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1916 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 2002 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1862 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1826 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1914 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1771 # Track reads on a per bank basis +system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1881344 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9344 # Number of bytes written to this memory +system.physmem.bytes_written::total 9344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29396 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30409 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 146 # Number of write requests responded to by this memory +system.physmem.num_writes::total 146 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 982300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28505117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29487417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 982300 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 982300 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 141575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 141575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 141575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 982300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28505117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29628992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30411 # Total number of read requests seen +system.physmem.writeReqs 146 # Total number of write requests seen +system.physmem.cpureqs 30558 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1946176 # Total number of bytes read from memory +system.physmem.bytesWritten 9344 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1946176 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9344 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 46 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 2026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1920 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1870 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1859 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1922 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1899 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1824 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1881 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1910 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1876 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1770 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 23 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 17 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 93 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 12 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 10 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 11 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 67525239000 # Total gap between requests +system.physmem.totGap 66000206500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30518 # Categorize read packet sizes +system.physmem.readPktSize::6 30411 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 212 # categorize write packet sizes +system.physmem.writePktSize::6 146 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,13 +102,13 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3 # categorize neither packet sizes +system.physmem.neitherpktsize::6 1 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 29919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,29 +138,29 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -171,266 +171,265 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 11553430 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 574779430 # Sum of mem lat for all requests -system.physmem.totBusLat 121820000 # Total cycles spent in databus access -system.physmem.totBankLat 441406000 # Total cycles spent in bank access -system.physmem.avgQLat 379.36 # Average queueing delay per request -system.physmem.avgBankLat 14493.71 # Average bank access latency per request +system.physmem.totQLat 10043842 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 570319842 # Sum of mem lat for all requests +system.physmem.totBusLat 121460000 # Total cycles spent in databus access +system.physmem.totBankLat 438816000 # Total cycles spent in bank access +system.physmem.avgQLat 330.77 # Average queueing delay per request +system.physmem.avgBankLat 14451.37 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18873.07 # Average memory access latency -system.physmem.avgRdBW 28.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.20 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 28.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.20 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 18782.15 # Average memory access latency +system.physmem.avgRdBW 29.49 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.49 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.14 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.18 # Data bus utilization in percentage +system.physmem.busUtil 0.19 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 2.27 # Average write queue length over time -system.physmem.readRowHits 29673 # Number of row buffer hits during reads -system.physmem.writeRowHits 71 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.49 # Row buffer hit rate for writes -system.physmem.avgGap 2197371.92 # Average gap between requests +system.physmem.avgWrQLen 11.23 # Average write queue length over time +system.physmem.readRowHits 29628 # Number of row buffer hits during reads +system.physmem.writeRowHits 33 # Number of row buffer hits during writes +system.physmem.readRowHitRate 97.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 22.60 # Row buffer hit rate for writes +system.physmem.avgGap 2159904.65 # Average gap between requests system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 135050507 # number of cpu cycles simulated +system.cpu.numCycles 132000442 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 35279612 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 35279612 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1097690 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25134949 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25035866 # Number of BTB hits +system.cpu.BPredUnit.lookups 34554509 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 34554509 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 911394 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 24765022 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24662055 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27689493 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 190877273 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35279612 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25035866 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 58050662 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7148119 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43215578 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26932643 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266231 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 134969887 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.491492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.329843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 26596332 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 185596643 # Number of instructions fetch has processed +system.cpu.fetch.Branches 34554509 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24662055 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 56507097 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6124499 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43643381 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 161 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25948459 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 189220 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131924094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.485407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326719 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79660068 59.02% 59.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2061386 1.53% 60.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3001296 2.22% 62.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4024404 2.98% 65.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7960578 5.90% 71.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4856128 3.60% 75.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2895673 2.15% 77.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1440638 1.07% 78.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29069716 21.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77963907 59.10% 59.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1995685 1.51% 60.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2954745 2.24% 62.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3921734 2.97% 65.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7794021 5.91% 71.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4758298 3.61% 75.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2730030 2.07% 77.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1578417 1.20% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28227257 21.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 134969887 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261233 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.413377 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38714097 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35595607 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46068800 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8577479 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6013904 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 332373669 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 6013904 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44296876 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8440142 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9061 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48816518 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27393386 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 327323595 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 229 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 40548 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25654370 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 357 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 329853596 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 868074055 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 868071866 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2189 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131924094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261776 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.406030 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37436709 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35891345 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44770440 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8648508 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5177092 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 324637130 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 5177092 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43002137 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8530644 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9064 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 47590207 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27614950 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 320247590 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 56685 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25740543 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 371 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 322254877 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 849337194 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 849335025 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2169 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 50640852 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 483 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 61788867 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104142858 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36158946 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40039032 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6050954 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 321707041 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1738 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307032101 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 190555 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42805778 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 61072777 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1292 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 134969887 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.274819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.710764 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 43042133 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 470 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 464 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62360742 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 102568175 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 35245114 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39579817 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6021711 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 315893152 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1659 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 302191539 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115107 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 37070468 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 54283440 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1213 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131924094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290647 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.699813 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26262527 19.46% 19.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23269182 17.24% 36.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26059494 19.31% 56.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 26258264 19.45% 75.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19354972 14.34% 89.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8435024 6.25% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4232889 3.14% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 903483 0.67% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 194052 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24546585 18.61% 18.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23206107 17.59% 36.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25921610 19.65% 55.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25807341 19.56% 75.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18909357 14.33% 89.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8337371 6.32% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4135132 3.13% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 899614 0.68% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 160977 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 134969887 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131924094 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 32987 1.63% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1843971 90.87% 92.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 152228 7.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 38482 1.96% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1831710 93.52% 95.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 88409 4.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31299 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174160366 56.72% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 56 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99035655 32.26% 88.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33804725 11.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31296 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 171161443 56.64% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97760077 32.35% 89.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33238688 11.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307032101 # Type of FU issued -system.cpu.iq.rate 2.273461 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2029186 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006609 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 751253230 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 364547081 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 303801599 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 600 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1091 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 195 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 309029699 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 289 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54104965 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 302191539 # Type of FU issued +system.cpu.iq.rate 2.289322 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1958601 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006481 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 738380204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 352997189 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 299552936 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1019 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 193 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 304118533 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 311 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 53992044 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13363474 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 46851 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34646 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4719195 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11788791 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25892 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34061 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3805363 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3287 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8523 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3223 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8493 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6013904 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1728221 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 160274 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 321708779 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 372174 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104142858 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36158946 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3195 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73111 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34646 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 603719 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 587627 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1191346 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 304994543 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98411821 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2037558 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5177092 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1727451 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 159578 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 315894811 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 195834 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 102568175 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 35245114 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3211 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73329 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34061 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 522882 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446154 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 969036 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 300573249 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97290254 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1618290 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131928718 # number of memory reference insts executed -system.cpu.iew.exec_branches 31180940 # Number of branches executed -system.cpu.iew.exec_stores 33516897 # Number of stores executed -system.cpu.iew.exec_rate 2.258374 # Inst execution rate -system.cpu.iew.wb_sent 304306961 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 303801794 # cumulative count of insts written-back -system.cpu.iew.wb_producers 222946371 # num instructions producing a value -system.cpu.iew.wb_consumers 302902430 # num instructions consuming a value +system.cpu.iew.exec_refs 130308372 # number of memory reference insts executed +system.cpu.iew.exec_branches 30889144 # Number of branches executed +system.cpu.iew.exec_stores 33018118 # Number of stores executed +system.cpu.iew.exec_rate 2.277062 # Inst execution rate +system.cpu.iew.wb_sent 299980860 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 299553129 # cumulative count of insts written-back +system.cpu.iew.wb_producers 219502976 # num instructions producing a value +system.cpu.iew.wb_consumers 298002309 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.249542 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736034 # average fanout of values written-back +system.cpu.iew.wb_rate 2.269334 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736581 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43529723 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 37715212 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1097716 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 128955983 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.157267 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.943706 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 911415 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126747002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.194864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.965405 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59867865 46.43% 46.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19620961 15.22% 61.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11973021 9.28% 70.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9656574 7.49% 78.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1838556 1.43% 79.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2079674 1.61% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1347744 1.05% 82.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 756025 0.59% 83.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 21815563 16.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58171175 45.90% 45.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19282988 15.21% 61.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11825828 9.33% 70.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9598483 7.57% 78.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1735999 1.37% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2077835 1.64% 81.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1295284 1.02% 82.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 717786 0.57% 82.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22041624 17.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 128955983 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126747002 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,307 +440,197 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 21815563 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22041624 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 428862605 # The number of ROB reads -system.cpu.rob.rob_writes 649464240 # The number of ROB writes -system.cpu.timesIdled 14220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 420613052 # The number of ROB reads +system.cpu.rob.rob_writes 636997439 # The number of ROB writes +system.cpu.timesIdled 13642 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76348 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.854812 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.854812 # CPI: Total CPI of All Threads -system.cpu.ipc 1.169848 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.169848 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 599211234 # number of integer regfile reads -system.cpu.int_regfile_writes 304304879 # number of integer regfile writes -system.cpu.fp_regfile_reads 178 # number of floating regfile reads -system.cpu.fp_regfile_writes 115 # number of floating regfile writes -system.cpu.misc_regfile_reads 195413561 # number of misc regfile reads -system.cpu.icache.replacements 78 # number of replacements -system.cpu.icache.tagsinuse 851.671106 # Cycle average of tags in use -system.cpu.icache.total_refs 26931242 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1068 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25216.518727 # Average number of references to valid blocks. +system.cpu.cpi 0.835506 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835506 # CPI: Total CPI of All Threads +system.cpu.ipc 1.196879 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.196879 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 592880828 # number of integer regfile reads +system.cpu.int_regfile_writes 300217894 # number of integer regfile writes +system.cpu.fp_regfile_reads 180 # number of floating regfile reads +system.cpu.fp_regfile_writes 79 # number of floating regfile writes +system.cpu.misc_regfile_reads 192706911 # number of misc regfile reads +system.cpu.icache.replacements 61 # number of replacements +system.cpu.icache.tagsinuse 834.549611 # Cycle average of tags in use +system.cpu.icache.total_refs 25947121 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25215.861030 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 851.671106 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.415855 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.415855 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 26931243 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26931243 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26931243 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26931243 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26931243 # number of overall hits -system.cpu.icache.overall_hits::total 26931243 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1400 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1400 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1400 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1400 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1400 # number of overall misses -system.cpu.icache.overall_misses::total 1400 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66418500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66418500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66418500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66418500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66418500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66418500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26932643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26932643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26932643 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26932643 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26932643 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26932643 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 834.549611 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.407495 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.407495 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25947121 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25947121 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25947121 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25947121 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25947121 # number of overall hits +system.cpu.icache.overall_hits::total 25947121 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1338 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1338 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1338 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1338 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1338 # number of overall misses +system.cpu.icache.overall_misses::total 1338 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65589000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65589000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65589000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65589000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65589000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65589000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25948459 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25948459 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25948459 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25948459 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25948459 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25948459 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47441.785714 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47441.785714 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47441.785714 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47441.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47441.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47441.785714 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49020.179372 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49020.179372 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49020.179372 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49020.179372 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49020.179372 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49020.179372 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1072 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1072 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1072 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1072 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1072 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52640000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 52640000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52640000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 52640000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52640000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 52640000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 308 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 308 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 308 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 308 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 308 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1030 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1030 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51699000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51699000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49104.477612 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49104.477612 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49104.477612 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49104.477612 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49104.477612 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49104.477612 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50193.203883 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50193.203883 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50193.203883 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50193.203883 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50193.203883 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50193.203883 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072134 # number of replacements -system.cpu.dcache.tagsinuse 4072.225954 # Cycle average of tags in use -system.cpu.dcache.total_refs 72984548 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076230 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 35.152439 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 22141542000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.225954 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994196 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994196 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 41643096 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 41643096 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341442 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341442 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 72984538 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 72984538 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 72984538 # number of overall hits -system.cpu.dcache.overall_hits::total 72984538 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2617976 # number of ReadReq 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33381730998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33381730998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33381730998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33381730998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 44261072 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 44261072 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 75700823 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 75700823 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 75700823 # number of overall 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latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21266.226876 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21266.226876 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12289.480300 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12289.480300 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12289.480300 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12289.480300 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32223 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9490 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.395469 # average number of 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+system.cpu.dcache.sampled_refs 2076183 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.664148 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21167717000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.565599 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40627633 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40627633 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341474 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341474 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71969107 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71969107 # number of demand (read+write) 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+system.cpu.dcache.overall_miss_rate::total 0.036463 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.182756 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.182756 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21246.710807 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21246.710807 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12266.364142 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12266.364142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12266.364142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12266.364142 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32155 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9466 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.396894 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2066445 # number of writebacks +system.cpu.dcache.writebacks::total 2066445 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631206 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631206 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16138 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16138 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647344 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647344 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647344 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647344 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994048 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994048 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82139 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82139 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076187 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076187 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076187 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076187 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982292500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982292500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812892498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812892498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23795184998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23795184998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23795184998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23795184998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046102 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046102 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027796 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027796 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.953536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.953536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22071.032007 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22071.032007 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.002789 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.002789 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.002789 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.002789 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 0d4631b4b..b3fd6699b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index b4d96e4ea..374965c0a 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] +warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7] hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index ccc3391a2..c76d776a9 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:11:01 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 19:35:49 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 205972871500 because target called exit() +Exiting @ tick 206019870500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c7236dc45..7f8080346 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.209792 # Number of seconds simulated -sim_ticks 209791572500 # Number of ticks simulated -final_tick 209791572500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.206020 # Number of seconds simulated +sim_ticks 206019870500 # Number of ticks simulated +final_tick 206019870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156369 # Simulator instruction rate (inst/s) -host_op_rate 176151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64455547 # Simulator tick rate (ticks/s) -host_mem_usage 260364 # Number of bytes of host memory used -host_seconds 3254.83 # Real time elapsed on the host -sim_insts 508955223 # Number of instructions simulated -sim_ops 573341783 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9263872 # Number of bytes read from this memory -system.physmem.bytes_read::total 9481024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6251520 # Number of bytes written to this memory -system.physmem.bytes_written::total 6251520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3393 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144748 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148141 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97680 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97680 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1035084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44157503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 45192588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1035084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1035084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 29798718 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 29798718 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 29798718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1035084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44157503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 74991306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148142 # Total number of read requests seen -system.physmem.writeReqs 97680 # Total number of write requests seen -system.physmem.cpureqs 245829 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9481024 # Total number of bytes read from memory -system.physmem.bytesWritten 6251520 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9481024 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6251520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9201 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9489 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10287 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 9703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9133 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8953 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8749 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6110 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6121 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6032 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6371 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5972 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6670 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6298 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6055 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6063 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5907 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5779 # Track writes on a per bank basis +host_inst_rate 121571 # Simulator instruction rate (inst/s) +host_op_rate 136951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49210675 # Simulator tick rate (ticks/s) +host_mem_usage 259828 # Number of bytes of host memory used +host_seconds 4186.49 # Real time elapsed on the host +sim_insts 508955243 # Number of instructions simulated +sim_ops 573341803 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 217536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9265600 # Number of bytes read from this memory +system.physmem.bytes_read::total 9483136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6247936 # Number of bytes written to this memory +system.physmem.bytes_written::total 6247936 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144775 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148174 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97624 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97624 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1055898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44974303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46030201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1055898 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1055898 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30326861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30326861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30326861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1055898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44974303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 76357062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148175 # Total number of read requests seen +system.physmem.writeReqs 97624 # Total number of write requests seen +system.physmem.cpureqs 245816 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9483136 # Total number of bytes read from memory +system.physmem.bytesWritten 6247936 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9483136 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6247936 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 95 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 17 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9343 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8790 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9223 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8971 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9143 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10294 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 9679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8730 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6116 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5942 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6022 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6372 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6671 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6280 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6315 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6059 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5764 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 209791554000 # Total gap between requests +system.physmem.totGap 206019849500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148142 # Categorize read packet sizes +system.physmem.readPktSize::6 148175 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 97680 # categorize write packet sizes +system.physmem.writePktSize::6 97624 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 7 # categorize neither packet sizes +system.physmem.neitherpktsize::6 17 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 138253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 138261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9196 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1634133662 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4706663662 # Sum of mem lat for all requests -system.physmem.totBusLat 592276000 # Total cycles spent in databus access -system.physmem.totBankLat 2480254000 # Total cycles spent in bank access -system.physmem.avgQLat 11036.30 # Average queueing delay per request -system.physmem.avgBankLat 16750.66 # Average bank access latency per request +system.physmem.totQLat 1627412180 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4699930180 # Sum of mem lat for all requests +system.physmem.totBusLat 592320000 # Total cycles spent in databus access +system.physmem.totBankLat 2480198000 # Total cycles spent in bank access +system.physmem.avgQLat 10990.09 # Average queueing delay per request +system.physmem.avgBankLat 16749.04 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31786.96 # Average memory access latency -system.physmem.avgRdBW 45.19 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 29.80 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 45.19 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 29.80 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31739.13 # Average memory access latency +system.physmem.avgRdBW 46.03 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 30.33 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 46.03 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 30.33 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.47 # Data bus utilization in percentage +system.physmem.busUtil 0.48 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.47 # Average write queue length over time -system.physmem.readRowHits 128571 # Number of row buffer hits during reads -system.physmem.writeRowHits 35065 # Number of row buffer hits during writes +system.physmem.avgWrQLen 8.48 # Average write queue length over time +system.physmem.readRowHits 128585 # Number of row buffer hits during reads +system.physmem.writeRowHits 35174 # Number of row buffer hits during writes system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.90 # Row buffer hit rate for writes -system.physmem.avgGap 853428.72 # Average gap between requests +system.physmem.writeRowHitRate 36.03 # Row buffer hit rate for writes +system.physmem.avgGap 838163.90 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,576 +235,454 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 419583146 # number of cpu cycles simulated +system.cpu.numCycles 412039742 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 184787901 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 144275662 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7821695 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 98666438 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 90672892 # Number of BTB hits +system.cpu.BPredUnit.lookups 182071983 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142381295 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7268299 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 93564777 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 88700041 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12865720 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 116804 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 120063384 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 775942019 # Number of instructions fetch has processed -system.cpu.fetch.Branches 184787901 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103538612 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 174228692 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 37833268 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 88961490 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 89 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 441 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 115656461 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2629290 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 412465751 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.114116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.961632 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12685099 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 116083 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 117148048 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 763048101 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182071983 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 101385140 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170894035 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35686363 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 89221488 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 506 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 45 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 113043343 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2441081 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 404881843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.113466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.961359 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 238249907 57.76% 57.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14509257 3.52% 61.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 23515530 5.70% 66.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23126111 5.61% 72.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21084782 5.11% 77.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13401568 3.25% 80.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13317687 3.23% 84.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12258730 2.97% 87.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53002179 12.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 234000478 57.79% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14180958 3.50% 61.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22900692 5.66% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22746852 5.62% 72.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20902415 5.16% 77.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13082439 3.23% 80.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13044714 3.22% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11995563 2.96% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52027732 12.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 412465751 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.440408 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.849316 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 130727660 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83050170 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 164137621 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5414105 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 29136195 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26733440 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 78480 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 847595839 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 313311 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 29136195 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139084470 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9565310 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 58010596 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 161019235 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15649945 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 817254433 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1177 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3017136 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8708482 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 277 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 973333611 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3577975971 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3577974311 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672200291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 301133320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3043156 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3043152 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48850446 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173854149 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75418146 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27836757 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 16204833 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 768087050 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4468097 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 675015149 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1537645 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 197142364 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 504679775 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 746965 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 412465751 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.636536 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726020 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 404881843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.441880 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.851880 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127553544 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83254868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 161072807 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5457053 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27543571 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26128616 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76844 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 833018746 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 296404 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27543571 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135629156 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9608106 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57992007 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158279608 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15829395 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 804332023 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1038 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3062506 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8833795 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 960234545 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3519895125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3519893415 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1710 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672200323 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 288034222 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3037420 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3037417 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 49050394 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170961338 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74175754 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28008123 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15620624 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 757949088 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4467543 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 668974363 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1389643 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187239707 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479750925 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 746407 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 404881843 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.652271 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.728361 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 150311678 36.44% 36.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76712349 18.60% 55.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69700446 16.90% 71.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 54263544 13.16% 85.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31204898 7.57% 92.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16238502 3.94% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9395018 2.28% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3385462 0.82% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1253854 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145293299 35.89% 35.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75809300 18.72% 54.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69100310 17.07% 71.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53699574 13.26% 84.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30880132 7.63% 92.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16168967 3.99% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9289317 2.29% 98.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3363096 0.83% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1277848 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 412465751 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 404881843 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 459279 4.79% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6599656 68.89% 73.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2521285 26.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 478346 4.98% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6550639 68.20% 73.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2576691 26.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 453432070 67.17% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 386675 0.06% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 120 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 156063229 23.12% 90.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65133052 9.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 449945039 67.26% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383598 0.06% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 120 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 154114870 23.04% 90.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 64530733 9.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 675015149 # Type of FU issued -system.cpu.iq.rate 1.608776 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9580220 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014193 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1773613639 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 970503516 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 654104832 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 668974363 # Type of FU issued +system.cpu.iq.rate 1.623568 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9605676 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014359 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1753825613 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 950462588 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 649623996 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 376 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 684595230 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 678579900 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8576140 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 8555633 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47081094 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 45082 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810201 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17814169 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44188279 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 40573 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810259 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16571773 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19569 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4173 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19511 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4184 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 29136195 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4987646 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 377782 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 774132367 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1246249 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173854149 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75418146 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2979362 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 225001 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11770 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810201 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4778565 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4193502 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8972067 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 664703563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 152403506 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10311586 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27543571 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4982601 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 373964 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 763975241 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1120254 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170961338 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74175754 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2978807 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219858 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11158 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810259 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4340256 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4003229 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8343485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 659478369 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150829210 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9495994 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1577220 # number of nop insts executed -system.cpu.iew.exec_refs 216142633 # number of memory reference insts executed -system.cpu.iew.exec_branches 139998635 # Number of branches executed -system.cpu.iew.exec_stores 63739127 # Number of stores executed -system.cpu.iew.exec_rate 1.584200 # Inst execution rate -system.cpu.iew.wb_sent 659363122 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 654104848 # cumulative count of insts written-back -system.cpu.iew.wb_producers 377540372 # num instructions producing a value -system.cpu.iew.wb_consumers 650138040 # num instructions consuming a value +system.cpu.iew.exec_nop 1558610 # number of nop insts executed +system.cpu.iew.exec_refs 214064543 # number of memory reference insts executed +system.cpu.iew.exec_branches 139194602 # Number of branches executed +system.cpu.iew.exec_stores 63235333 # Number of stores executed +system.cpu.iew.exec_rate 1.600521 # Inst execution rate +system.cpu.iew.wb_sent 654596597 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 649624012 # cumulative count of insts written-back +system.cpu.iew.wb_producers 375406719 # num instructions producing a value +system.cpu.iew.wb_consumers 646267574 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.558940 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.580708 # average fanout of values written-back +system.cpu.iew.wb_rate 1.576605 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.580884 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 199474656 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721132 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7746281 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 383329557 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.499195 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.189163 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 189315872 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721136 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 7194171 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 377338273 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.522999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.206666 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 170483153 44.47% 44.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103125969 26.90% 71.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 34389586 8.97% 80.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19012192 4.96% 85.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16256916 4.24% 89.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7587599 1.98% 91.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6965408 1.82% 93.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3084029 0.80% 94.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22424705 5.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 165593996 43.88% 43.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102356552 27.13% 71.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 34023160 9.02% 80.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18860248 5.00% 85.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16133947 4.28% 89.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7612237 2.02% 91.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6942439 1.84% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3075088 0.81% 93.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22740606 6.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 383329557 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510299107 # Number of instructions committed -system.cpu.commit.committedOps 574685667 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 377338273 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510299127 # Number of instructions committed +system.cpu.commit.committedOps 574685687 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377032 # Number of memory references committed -system.cpu.commit.loads 126773055 # Number of loads committed +system.cpu.commit.refs 184377040 # Number of memory references committed +system.cpu.commit.loads 126773059 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 122291801 # Number of branches committed +system.cpu.commit.branches 122291805 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701693 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701709 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22424705 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22740606 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1135058037 # The number of ROB reads -system.cpu.rob.rob_writes 1577598411 # The number of ROB writes -system.cpu.timesIdled 306064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7117395 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508955223 # Number of Instructions Simulated -system.cpu.committedOps 573341783 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508955223 # Number of Instructions Simulated -system.cpu.cpi 0.824401 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824401 # CPI: Total CPI of All Threads -system.cpu.ipc 1.213002 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.213002 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3101759208 # number of integer regfile reads -system.cpu.int_regfile_writes 762565130 # number of integer regfile writes +system.cpu.rob.rob_reads 1118592088 # The number of ROB reads +system.cpu.rob.rob_writes 1555667472 # The number of ROB writes +system.cpu.timesIdled 306583 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7157899 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508955243 # Number of Instructions Simulated +system.cpu.committedOps 573341803 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508955243 # Number of Instructions Simulated +system.cpu.cpi 0.809580 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.809580 # CPI: Total CPI of All Threads +system.cpu.ipc 1.235209 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.235209 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3078155858 # number of integer regfile reads +system.cpu.int_regfile_writes 757766233 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1004803161 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464084 # number of misc regfile writes -system.cpu.icache.replacements 15462 # number of replacements -system.cpu.icache.tagsinuse 1099.228607 # Cycle average of tags in use -system.cpu.icache.total_refs 115634831 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17331 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6672.138422 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 990216760 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464092 # number of misc regfile writes +system.cpu.icache.replacements 14932 # number of replacements +system.cpu.icache.tagsinuse 1085.088818 # Cycle average of tags in use +system.cpu.icache.total_refs 113022367 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16785 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6733.533929 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1099.228607 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.536733 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.536733 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 115634831 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 115634831 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 115634831 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 115634831 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 115634831 # number of overall hits -system.cpu.icache.overall_hits::total 115634831 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21629 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21629 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21629 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21629 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21629 # number of overall misses -system.cpu.icache.overall_misses::total 21629 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 475311000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 475311000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 475311000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 475311000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 475311000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 475311000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115656460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115656460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115656460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115656460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115656460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115656460 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000187 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000187 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000187 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000187 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000187 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000187 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21975.634565 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21975.634565 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21975.634565 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21975.634565 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21975.634565 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21975.634565 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 436 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1085.088818 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.529829 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.529829 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 113022367 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113022367 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113022367 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113022367 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113022367 # number of overall hits +system.cpu.icache.overall_hits::total 113022367 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 20976 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 20976 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 20976 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 20976 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 20976 # number of overall misses +system.cpu.icache.overall_misses::total 20976 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 467556999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 467556999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 467556999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 467556999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 467556999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 467556999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 113043343 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 113043343 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 113043343 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 113043343 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 113043343 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 113043343 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22290.093392 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22290.093392 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22290.093392 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22290.093392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22290.093392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22290.093392 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 91.833333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4227 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4227 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4227 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4227 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4227 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4227 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17402 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17402 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17402 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17402 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17402 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17402 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 349731500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 349731500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 349731500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 349731500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 349731500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 349731500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000150 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000150 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000150 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20097.201471 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20097.201471 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20097.201471 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20097.201471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20097.201471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20097.201471 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4107 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4107 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4107 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4107 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4107 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4107 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16869 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16869 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16869 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16869 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16869 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16869 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 341781999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 341781999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 341781999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 341781999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 341781999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 341781999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20260.951983 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20260.951983 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20260.951983 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20260.951983 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20260.951983 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20260.951983 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1191468 # number of replacements -system.cpu.dcache.tagsinuse 4055.451159 # Cycle average of tags in use -system.cpu.dcache.total_refs 193136730 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1195564 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 161.544451 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4668381000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4055.451159 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990100 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990100 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137669566 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137669566 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51001637 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51001637 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233291 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2233291 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2232041 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2232041 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 188671203 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 188671203 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 188671203 # number of overall hits -system.cpu.dcache.overall_hits::total 188671203 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1694127 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1694127 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3237669 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3237669 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4931796 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4931796 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4931796 # number of overall misses -system.cpu.dcache.overall_misses::total 4931796 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25989593000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25989593000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58741692947 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58741692947 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 673500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 673500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84731285947 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84731285947 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84731285947 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84731285947 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 139363693 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 139363693 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233334 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2233334 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232041 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2232041 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 193602999 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 193602999 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 193602999 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 193602999 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012156 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012156 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059692 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059692 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000019 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000019 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025474 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025474 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025474 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025474 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15340.994506 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15340.994506 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18143.205172 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18143.205172 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15662.790698 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15662.790698 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17180.614516 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17180.614516 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17180.614516 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17180.614516 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15718 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14943 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1597 # number of cycles access was blocked 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+system.cpu.dcache.writebacks::writebacks 1110628 # number of writebacks +system.cpu.dcache.writebacks::total 1110628 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 845499 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 845499 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898153 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2898153 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 39 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 39 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3743652 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3743652 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3743652 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3743652 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348276 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348276 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196377 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196377 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196377 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196377 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11475197000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11475197000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257593997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257593997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19732790997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19732790997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19732790997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19732790997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006226 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006226 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13530.460405 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13530.460405 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23709.913968 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23709.913968 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16493.789998 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16493.789998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16493.789998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16493.789998 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 7d5241595..39d5d8c7f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,17 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -430,17 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -462,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -470,30 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -503,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -521,9 +528,9 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 31324de53..f635f915d 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,17 +1,15 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:33:09 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 16:49:35 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Reading the dictionary files: *********info: Increasing stack size by one page. +**************************************info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. @@ -24,7 +22,7 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -**************************************** +** 58924 words stored in 3784810 bytes @@ -82,4 +80,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 433562236500 because target called exit() +Exiting @ tick 434496110500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 0b91be0ea..05261b47d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.447151 # Number of seconds simulated -sim_ticks 447151291000 # Number of ticks simulated -final_tick 447151291000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434496 # Number of seconds simulated +sim_ticks 434496110500 # Number of ticks simulated +final_tick 434496110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99582 # Simulator instruction rate (inst/s) -host_op_rate 184139 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53851139 # Simulator tick rate (ticks/s) -host_mem_usage 337048 # Number of bytes of host memory used -host_seconds 8303.47 # Real time elapsed on the host +host_inst_rate 78440 # Simulator instruction rate (inst/s) +host_op_rate 145045 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41217689 # Simulator tick rate (ticks/s) +host_mem_usage 343084 # Number of bytes of host memory used +host_seconds 10541.50 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 207040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24466624 # Number of bytes read from this memory -system.physmem.bytes_read::total 24673664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 207040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 207040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18786368 # Number of bytes written to this memory -system.physmem.bytes_written::total 18786368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382291 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385526 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293537 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 463020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54716657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 55179677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 463020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 463020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42013449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42013449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42013449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 463020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54716657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 97193127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385528 # Total number of read requests seen -system.physmem.writeReqs 293537 # Total number of write requests seen -system.physmem.cpureqs 863596 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24673664 # Total number of bytes read from memory -system.physmem.bytesWritten 18786368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24673664 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18786368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 164 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 184531 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 23035 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 25301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24892 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 23920 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24683 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 23396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 24133 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 24155 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 19354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 17947 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18690 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18990 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 19041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18099 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18501 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 17450 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 17927 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 17723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17609 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 18279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18321 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18443 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 205760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24473920 # Number of bytes read from this memory +system.physmem.bytes_read::total 24679680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 205760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 205760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18793728 # Number of bytes written to this memory +system.physmem.bytes_written::total 18793728 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385620 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293652 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293652 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 473560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56327133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56800693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 473560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 473560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43254076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43254076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43254076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 473560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56327133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100054769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385622 # Total number of read requests seen +system.physmem.writeReqs 293652 # Total number of write requests seen +system.physmem.cpureqs 889960 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24679680 # Total number of bytes read from memory +system.physmem.bytesWritten 18793728 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24679680 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18793728 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 136 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 210686 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24775 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 22937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 25246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 24873 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 23841 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24700 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23587 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 23221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 23429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24164 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 24144 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24092 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24098 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 19149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 17956 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18934 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 19023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18089 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 17452 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 17936 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 17736 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18448 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 18286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18332 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18446 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 447151273000 # Total gap between requests +system.physmem.totGap 434496092500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385528 # Categorize read packet sizes +system.physmem.readPktSize::6 385622 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 293537 # categorize write packet sizes +system.physmem.writePktSize::6 293652 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 184531 # categorize neither packet sizes +system.physmem.neitherpktsize::6 210686 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 380682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 380872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,266 +171,267 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3526127005 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11592689005 # Sum of mem lat for all requests -system.physmem.totBusLat 1541456000 # Total cycles spent in databus access -system.physmem.totBankLat 6525106000 # Total cycles spent in bank access -system.physmem.avgQLat 9150.12 # Average queueing delay per request -system.physmem.avgBankLat 16932.32 # Average bank access latency per request +system.physmem.totQLat 3490991093 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11561975093 # Sum of mem lat for all requests +system.physmem.totBusLat 1541944000 # Total cycles spent in databus access +system.physmem.totBankLat 6529040000 # Total cycles spent in bank access +system.physmem.avgQLat 9056.08 # Average queueing delay per request +system.physmem.avgBankLat 16937.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30082.44 # Average memory access latency -system.physmem.avgRdBW 55.18 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 42.01 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 55.18 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 42.01 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29993.24 # Average memory access latency +system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.61 # Data bus utilization in percentage +system.physmem.busUtil 0.63 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 8.93 # Average write queue length over time -system.physmem.readRowHits 340552 # Number of row buffer hits during reads -system.physmem.writeRowHits 151633 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 51.66 # Row buffer hit rate for writes -system.physmem.avgGap 658480.81 # Average gap between requests +system.physmem.avgWrQLen 9.57 # Average write queue length over time +system.physmem.readRowHits 340592 # Number of row buffer hits during reads +system.physmem.writeRowHits 151278 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 51.52 # Row buffer hit rate for writes +system.physmem.avgGap 639647.76 # Average gap between requests system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 894302583 # number of cpu cycles simulated +system.cpu.numCycles 868992222 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 221834419 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 221834419 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14438837 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 157195941 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 152967077 # Number of BTB hits +system.cpu.BPredUnit.lookups 214993851 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 214993851 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 13132727 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 150483811 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 147870058 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 187305514 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1233712111 # Number of instructions fetch has processed -system.cpu.fetch.Branches 221834419 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 152967077 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 383213555 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 92482547 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 231997744 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 302541 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 179659779 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4113909 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 880638441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.600745 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.391861 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180595819 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1193570142 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214993851 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147870058 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371300946 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83432044 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 232898189 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 320539 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173489759 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3820168 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 855191197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.591382 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.388294 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 501847528 56.99% 56.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25496575 2.90% 59.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28121767 3.19% 63.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 29451767 3.34% 66.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18987914 2.16% 68.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25123088 2.85% 71.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31720196 3.60% 75.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30784274 3.50% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 189105332 21.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 488292980 57.10% 57.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24712697 2.89% 59.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27343487 3.20% 63.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28814936 3.37% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18484341 2.16% 68.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24598023 2.88% 71.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30669616 3.59% 75.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28863276 3.38% 78.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183411841 21.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 880638441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.248053 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.379524 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 244537844 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 188536263 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 324191261 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45585175 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 77787898 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2236907904 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 77787898 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 278585274 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54813178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15041 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 333395312 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136041738 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2184748951 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 34526 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20261515 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 101530735 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 116 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2284488026 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5524710294 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5524485031 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 225263 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 855191197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247406 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.373511 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 237057033 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 189447507 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313514348 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45129276 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70043033 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2167224659 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70043033 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270477979 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55455808 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15344 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322737561 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136461472 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2120443257 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31742 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21271807 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 100951250 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 96 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216845941 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5356850652 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5356713794 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136858 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 670447175 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1310 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1291 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 328673064 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528947917 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 211077156 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 202192665 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58804191 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2090539379 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34704 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1836706736 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 960329 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 555260187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 919296135 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 34151 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 880638441 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.085654 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.886104 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 602805090 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1368 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1337 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 329763590 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512746819 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204948217 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196647356 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55718334 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2034222855 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23204 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1808269086 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 840688 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499770877 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 818821894 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22651 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 855191197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.114462 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887618 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 249855133 28.37% 28.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 147643393 16.77% 45.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 139523467 15.84% 60.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 137737388 15.64% 76.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97163823 11.03% 87.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 59916022 6.80% 94.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34917189 3.96% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11990499 1.36% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1891527 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 234669237 27.44% 27.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145408124 17.00% 44.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138604269 16.21% 60.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 132699771 15.52% 76.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 96142027 11.24% 87.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58835818 6.88% 94.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34929865 4.08% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11989965 1.40% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1912121 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 880638441 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 855191197 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5040061 32.96% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7632140 49.91% 82.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2619273 17.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4982607 32.47% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7772291 50.65% 83.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2591536 16.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2704214 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1211533027 65.96% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 444457178 24.20% 90.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 178012317 9.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2719540 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190958422 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438908111 24.27% 90.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175683013 9.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1836706736 # Type of FU issued -system.cpu.iq.rate 2.053787 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15291474 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4570263035 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2646020420 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1794037475 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 40681 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 76210 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 9614 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1849275039 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 18957 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170130474 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1808269086 # Type of FU issued +system.cpu.iq.rate 2.080881 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15346434 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008487 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4487893952 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2534230949 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768791787 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22539 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 44036 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5119 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820885356 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 10624 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170553013 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144845761 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 503638 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 274982 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61917680 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128644663 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 472582 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 269715 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55788376 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10585 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 592 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12339 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1555 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 77787898 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17508647 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2908748 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2090574083 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2437552 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528947917 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 211077865 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5687 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1841603 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73588 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 274982 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10048689 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4929582 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 14978271 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1806703840 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 436137965 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30002896 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70043033 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17673850 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2842089 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2034246059 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2370262 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512746819 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204948561 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6149 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1800682 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76001 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 269715 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9110771 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4492681 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13603452 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780575608 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431395989 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27693478 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 608784008 # number of memory reference insts executed -system.cpu.iew.exec_branches 171260555 # Number of branches executed -system.cpu.iew.exec_stores 172646043 # Number of stores executed -system.cpu.iew.exec_rate 2.020238 # Inst execution rate -system.cpu.iew.wb_sent 1801373489 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1794047089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1362133405 # num instructions producing a value -system.cpu.iew.wb_consumers 1992639116 # num instructions consuming a value +system.cpu.iew.exec_refs 602081251 # number of memory reference insts executed +system.cpu.iew.exec_branches 169281204 # Number of branches executed +system.cpu.iew.exec_stores 170685262 # Number of stores executed +system.cpu.iew.exec_rate 2.049012 # Inst execution rate +system.cpu.iew.wb_sent 1775484026 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768796906 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341657182 # num instructions producing a value +system.cpu.iew.wb_consumers 1964610476 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.006085 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.683583 # average fanout of values written-back +system.cpu.iew.wb_rate 2.035458 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682913 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 561620004 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 505293245 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14469462 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 802850543 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.904450 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.430311 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 13164973 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 785148164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.947389 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.457160 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 304835163 37.97% 37.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 198905096 24.77% 62.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63436109 7.90% 70.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92154984 11.48% 82.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26044111 3.24% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29384573 3.66% 89.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9423573 1.17% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10229786 1.27% 91.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68437148 8.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 291743548 37.16% 37.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195452528 24.89% 62.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62380641 7.95% 70.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92170452 11.74% 81.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25089847 3.20% 84.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28355719 3.61% 88.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9376881 1.19% 89.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10764120 1.37% 91.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69814428 8.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 802850543 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 785148164 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,311 +442,203 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68437148 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69814428 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2825022098 # The number of ROB reads -system.cpu.rob.rob_writes 4259228710 # The number of ROB writes -system.cpu.timesIdled 301112 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13664142 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2749615680 # The number of ROB reads +system.cpu.rob.rob_writes 4138789024 # The number of ROB writes +system.cpu.timesIdled 344205 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13801025 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.081542 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.081542 # CPI: Total CPI of All Threads -system.cpu.ipc 0.924606 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.924606 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3392416402 # number of integer regfile reads -system.cpu.int_regfile_writes 1873878910 # number of integer regfile writes -system.cpu.fp_regfile_reads 9612 # number of floating regfile reads -system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.misc_regfile_reads 993805261 # number of misc regfile reads -system.cpu.icache.replacements 5664 # number of replacements -system.cpu.icache.tagsinuse 1040.414195 # Cycle average of tags in use -system.cpu.icache.total_refs 179444520 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7258 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24723.686966 # Average number of references to valid blocks. +system.cpu.cpi 1.050933 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.050933 # CPI: Total CPI of All Threads +system.cpu.ipc 0.951536 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.951536 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357495880 # number of integer regfile reads +system.cpu.int_regfile_writes 1848564966 # number of integer regfile writes +system.cpu.fp_regfile_reads 5116 # number of floating regfile reads +system.cpu.fp_regfile_writes 3 # number of floating regfile writes +system.cpu.misc_regfile_reads 980239891 # number of misc regfile reads +system.cpu.icache.replacements 5389 # number of replacements +system.cpu.icache.tagsinuse 1038.396160 # Cycle average of tags in use +system.cpu.icache.total_refs 173252420 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6992 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24778.664188 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1040.414195 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.508015 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.508015 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 179464097 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179464097 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179464097 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179464097 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179464097 # number of overall hits -system.cpu.icache.overall_hits::total 179464097 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 195682 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 195682 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 195682 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 195682 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 195682 # number of overall misses -system.cpu.icache.overall_misses::total 195682 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1231899498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1231899498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1231899498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1231899498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1231899498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1231899498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179659779 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179659779 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179659779 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179659779 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179659779 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179659779 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001089 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001089 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001089 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6295.415511 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6295.415511 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6295.415511 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6295.415511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6295.415511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6295.415511 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 959 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1038.396160 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.507029 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.507029 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173268230 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173268230 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173268230 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173268230 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173268230 # number of overall hits +system.cpu.icache.overall_hits::total 173268230 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 221529 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 221529 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 221529 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 221529 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 221529 # number of overall misses +system.cpu.icache.overall_misses::total 221529 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1367876999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1367876999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1367876999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1367876999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1367876999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1367876999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173489759 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173489759 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173489759 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173489759 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173489759 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173489759 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001277 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001277 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001277 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001277 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001277 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001277 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6174.708499 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6174.708499 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6174.708499 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6174.708499 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6174.708499 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6174.708499 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56.411765 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.555556 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2352 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2352 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2352 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2352 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2352 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2352 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 193330 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 193330 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 193330 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 193330 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 193330 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 193330 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 781617498 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 781617498 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 781617498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 781617498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 781617498 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 781617498 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001076 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001076 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4042.918833 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4042.918833 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4042.918833 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4042.918833 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4042.918833 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4042.918833 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2325 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2325 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2325 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2325 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2325 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2325 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 219204 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 219204 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 219204 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 219204 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 219204 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 219204 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 865886999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 865886999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 865886999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 865886999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 865886999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 865886999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001263 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001263 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001263 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3950.142329 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3950.142329 # average ReadReq mshr miss latency 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# number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 72922676000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 72922676000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 72922676000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264430051 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264430051 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 413590252 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 413590252 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 413590252 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 413590252 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010650 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010650 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006531 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006531 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009165 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009165 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009165 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009165 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17463.149605 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17463.149605 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24371.813665 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24371.813665 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19238.720224 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19238.720224 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19238.720224 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19238.720224 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6306 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.397914 # average number of cycles each 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overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1142960 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762404 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762404 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 983288 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 983288 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2745692 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2745692 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2745692 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2745692 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26902331000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26902331000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22198368000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 22198368000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49100699000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49100699000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49100699000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49100699000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006719 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006719 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15264.565332 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15264.565332 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22575.652301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22575.652301 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index d73c26c02..d18ed7c2f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index f78d992b7..063caa36a 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:12:34 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:24:52 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 141187061500 because target called exit() +Exiting @ tick 139846906500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index a158074c5..1ee5829a5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.141089 # Number of seconds simulated -sim_ticks 141089296500 # Number of ticks simulated -final_tick 141089296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139847 # Number of seconds simulated +sim_ticks 139846906500 # Number of ticks simulated +final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83115 # Simulator instruction rate (inst/s) -host_op_rate 83115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29414893 # Simulator tick rate (ticks/s) -host_mem_usage 223012 # Number of bytes of host memory used -host_seconds 4796.53 # Real time elapsed on the host +host_inst_rate 122154 # Simulator instruction rate (inst/s) +host_op_rate 122154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42850332 # Simulator tick rate (ticks/s) +host_mem_usage 220236 # Number of bytes of host memory used +host_seconds 3263.61 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1523688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1800392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3324079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1523688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1523688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1523688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1800392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3324079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1537224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1816386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3353610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1537224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1537224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1537224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1816386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3353610 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -37,7 +37,7 @@ system.physmem.bytesConsumedWr 0 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 465 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis @@ -48,7 +48,7 @@ system.physmem.perBankRdReqs::8 407 # Tr system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 528 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 141089244500 # Total gap between requests +system.physmem.totGap 139846854500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 39617295 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 175175295 # Sum of mem lat for all requests +system.physmem.totQLat 39390791 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 174626791 # Sum of mem lat for all requests system.physmem.totBusLat 29312000 # Total cycles spent in databus access -system.physmem.totBankLat 106246000 # Total cycles spent in bank access -system.physmem.avgQLat 5406.29 # Average queueing delay per request -system.physmem.avgBankLat 14498.64 # Average bank access latency per request +system.physmem.totBankLat 105924000 # Total cycles spent in bank access +system.physmem.avgQLat 5375.38 # Average queueing delay per request +system.physmem.avgBankLat 14454.69 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23904.93 # Average memory access latency -system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23830.08 # Average memory access latency +system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6442 # Number of row buffer hits during reads +system.physmem.readRowHits 6444 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19253444.94 # Average gap between requests +system.physmem.avgGap 19083904.82 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754611 # DTB read hits +system.cpu.dtb.read_hits 94754613 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754632 # DTB read accesses -system.cpu.dtb.write_hits 73521102 # DTB write hits +system.cpu.dtb.read_accesses 94754634 # DTB read accesses +system.cpu.dtb.write_hits 73521103 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521137 # DTB write accesses -system.cpu.dtb.data_hits 168275713 # DTB hits +system.cpu.dtb.write_accesses 73521138 # DTB write accesses +system.cpu.dtb.data_hits 168275716 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275769 # DTB accesses -system.cpu.itb.fetch_hits 49091192 # ITB hits -system.cpu.itb.fetch_misses 88817 # ITB misses +system.cpu.dtb.data_accesses 168275772 # DTB accesses +system.cpu.itb.fetch_hits 48611354 # ITB hits +system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49180009 # ITB accesses +system.cpu.itb.fetch_accesses 48655874 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282178594 # number of cpu cycles simulated +system.cpu.numCycles 279693814 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 53863325 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30909619 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 16029157 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 33388385 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15622160 # Number of BTB hits +system.cpu.branch_predictor.lookups 53489670 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30685393 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 15149659 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 32882351 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15212538 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 46.789205 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29654286 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24209039 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280812298 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 46.263535 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 440148157 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119908557 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722447 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631948 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 220105038 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100451904 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168699560 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14461353 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1567145 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 16028498 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 28559053 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.948370 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205751378 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2124332 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 219828429 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484563 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168485322 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 15149000 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 29438551 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.975851 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 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-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35249.941352 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42076.112864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.613913 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35919.490938 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35919.490938 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 764 # number of replacements +system.cpu.dcache.tagsinuse 3285.615449 # Cycle average of tags in use +system.cpu.dcache.total_refs 168254423 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 40523.704961 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3285.615449 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802152 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802152 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501238 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501238 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254423 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254423 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254423 # number of overall hits +system.cpu.dcache.overall_hits::total 168254423 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19491 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19491 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20795 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20795 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20795 # number of overall misses +system.cpu.dcache.overall_misses::total 20795 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64310000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64310000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 715525500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 715525500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 779835500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 779835500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 779835500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 779835500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49317.484663 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49317.484663 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36710.558719 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36710.558719 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37501.106035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37501.106035 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16708 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.229907 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16289 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16289 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16643 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16643 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16643 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16643 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 155739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 203182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49939.473684 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49939.473684 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48638.194878 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48638.194878 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 50694257d..8e356eaf5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index cf6e41473..c6043774f 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:15:17 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:29:31 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.066667 -Exiting @ tick 80362284000 because target called exit() +Exiting @ tick 77336466500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 698b9cfa0..d6188dabe 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080478 # Number of seconds simulated -sim_ticks 80478305500 # Number of ticks simulated -final_tick 80478305500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077336 # Number of seconds simulated +sim_ticks 77336466500 # Number of ticks simulated +final_tick 77336466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240864 # Simulator instruction rate (inst/s) -host_op_rate 240864 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51612452 # Simulator tick rate (ticks/s) -host_mem_usage 224036 # Number of bytes of host memory used -host_seconds 1559.28 # Real time elapsed on the host +host_inst_rate 195499 # Simulator instruction rate (inst/s) +host_op_rate 195499 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40256068 # Simulator tick rate (ticks/s) +host_mem_usage 221208 # Number of bytes of host memory used +host_seconds 1921.11 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 477632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222272 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3473 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7463 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2761887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3173029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5934916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2761887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2761887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2761887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3173029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5934916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7463 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255488 # Number of bytes read from this memory +system.physmem.bytes_read::total 476288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3992 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2855057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3303590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6158647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2855057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2855057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2855057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3303590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6158647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7442 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7463 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 477632 # Total number of bytes read from memory +system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 476288 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 477632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 480 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 530 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 388 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 386 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 448 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 456 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 407 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 545 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 424 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 503 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 80478237000 # Total gap between requests +system.physmem.totGap 77336398000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7463 # Categorize read packet sizes +system.physmem.readPktSize::6 7442 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 746 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 273 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 40041940 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 178323940 # Sum of mem lat for all requests -system.physmem.totBusLat 29852000 # Total cycles spent in databus access -system.physmem.totBankLat 108430000 # Total cycles spent in bank access -system.physmem.avgQLat 5365.39 # Average queueing delay per request -system.physmem.avgBankLat 14529.01 # Average bank access latency per request +system.physmem.totQLat 40921923 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 178783923 # Sum of mem lat for all requests +system.physmem.totBusLat 29768000 # Total cycles spent in databus access +system.physmem.totBankLat 108094000 # Total cycles spent in bank access +system.physmem.avgQLat 5498.78 # Average queueing delay per request +system.physmem.avgBankLat 14524.86 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23894.40 # Average memory access latency -system.physmem.avgRdBW 5.93 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24023.64 # Average memory access latency +system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 5.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6524 # Number of row buffer hits during reads +system.physmem.readRowHits 6502 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10783630.85 # Average gap between requests +system.physmem.avgGap 10391883.63 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103426473 # DTB read hits -system.cpu.dtb.read_misses 88806 # DTB read misses -system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 103515279 # DTB read accesses -system.cpu.dtb.write_hits 79003400 # DTB write hits -system.cpu.dtb.write_misses 1622 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79005022 # DTB write accesses -system.cpu.dtb.data_hits 182429873 # DTB hits -system.cpu.dtb.data_misses 90428 # DTB misses -system.cpu.dtb.data_acv 48605 # DTB access violations -system.cpu.dtb.data_accesses 182520301 # DTB accesses -system.cpu.itb.fetch_hits 52621913 # ITB hits -system.cpu.itb.fetch_misses 460 # ITB misses +system.cpu.dtb.read_hits 101791760 # DTB read hits +system.cpu.dtb.read_misses 77689 # DTB read misses +system.cpu.dtb.read_acv 48604 # DTB read access violations +system.cpu.dtb.read_accesses 101869449 # DTB read accesses +system.cpu.dtb.write_hits 78414713 # DTB write hits +system.cpu.dtb.write_misses 1485 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 78416198 # DTB write accesses +system.cpu.dtb.data_hits 180206473 # DTB hits +system.cpu.dtb.data_misses 79174 # DTB misses +system.cpu.dtb.data_acv 48607 # DTB access violations +system.cpu.dtb.data_accesses 180285647 # DTB accesses +system.cpu.itb.fetch_hits 50234226 # ITB hits +system.cpu.itb.fetch_misses 374 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52622373 # ITB accesses +system.cpu.itb.fetch_accesses 50234600 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,246 +218,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160956613 # number of cpu cycles simulated +system.cpu.numCycles 154672935 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52100857 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30315970 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1626186 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28771875 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24368935 # Number of BTB hits +system.cpu.BPredUnit.lookups 50254079 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 29238788 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1202354 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 26185724 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 23237791 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9361706 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1114 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53696929 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462928228 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52100857 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33730641 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81620286 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7858922 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19257347 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9632 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 52621913 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 634331 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160777203 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.879315 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.313319 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9009650 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1041 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 51121474 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448760218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50254079 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32247441 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78789768 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6120508 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19691338 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9175 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 50234226 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 409224 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154491833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.904750 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325280 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79156917 49.23% 49.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4375069 2.72% 51.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7280350 4.53% 56.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5649836 3.51% 60.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12467952 7.75% 67.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8098174 5.04% 72.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5694595 3.54% 76.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1921777 1.20% 77.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36132533 22.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75702065 49.00% 49.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4283300 2.77% 51.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6877325 4.45% 56.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5367764 3.47% 59.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11752749 7.61% 67.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7805511 5.05% 72.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5606089 3.63% 75.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1832349 1.19% 77.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35264681 22.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160777203 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323695 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.876106 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59247838 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14720272 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76811336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3809242 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6188515 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9757922 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4354 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 457314858 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12387 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6188515 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62549995 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4761260 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 404034 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77430709 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9442690 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451606730 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23776 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7810662 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 295220073 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593857298 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 314533396 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279323902 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154491833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324905 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.901349 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56470400 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15041439 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74166392 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3937938 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4875664 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9475904 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4278 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 444843868 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12237 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4875664 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59604786 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4871643 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 401502 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75064420 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9673818 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440376827 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19255 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7994088 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287328410 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 578957076 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 306311574 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 272645502 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35687744 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38419 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 331 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27285006 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 107056185 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81810329 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8900910 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6383401 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416688223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 322 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407927915 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1196295 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40854151 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20088069 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 107 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160777203 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.537225 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.006885 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27796081 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36810 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27798585 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104665260 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80564409 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8907082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6393839 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408148309 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 288 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401749536 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 973581 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32442077 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15221672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 73 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154491833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.600458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32206126 20.03% 20.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26582948 16.53% 36.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26044704 16.20% 52.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24850018 15.46% 68.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21542644 13.40% 81.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15495200 9.64% 91.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8651076 5.38% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4083423 2.54% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1321064 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28272588 18.30% 18.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25828142 16.72% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25544882 16.53% 51.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24283906 15.72% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21283015 13.78% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15483551 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8467826 5.48% 96.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4000243 2.59% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1327680 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160777203 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154491833 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35727 0.30% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 75761 0.64% 0.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 4382 0.04% 0.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3108 0.03% 1.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1825209 15.42% 16.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1783394 15.07% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5084367 42.96% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3023635 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 34079 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 57868 0.49% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5831 0.05% 0.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5354 0.05% 0.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1930027 16.34% 17.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1748928 14.81% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5061323 42.85% 74.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2967669 25.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 158069721 38.75% 38.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126542 0.52% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33490518 8.21% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7849895 1.92% 49.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2841429 0.70% 50.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16561983 4.06% 54.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1589872 0.39% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105338931 25.82% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80025443 19.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155748072 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126114 0.53% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32812204 8.17% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7499410 1.87% 49.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2793875 0.70% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556840 4.12% 54.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1578743 0.39% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103369723 25.73% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79230974 19.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407927915 # Type of FU issued -system.cpu.iq.rate 2.534397 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11835583 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029014 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 648317888 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 270248085 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237722545 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341347023 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187344847 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162957273 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245426205 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174303712 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14794032 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401749536 # Type of FU issued +system.cpu.iq.rate 2.597413 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11811079 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029399 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 634008068 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260192564 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234721556 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336767497 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180447135 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161345688 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241449037 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172077997 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15060402 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12301698 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 125436 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50278 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8289600 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9910773 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 111367 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 49045 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7043680 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260794 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2630 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2589 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6188515 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2498531 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 365597 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441640864 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 208656 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 107056185 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81810329 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 322 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 92 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50278 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1277121 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 568437 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1845558 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403336755 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103563942 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4591160 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4875664 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2512017 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 367237 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432932337 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125430 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104665260 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80564409 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 288 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 91 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 94 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 49045 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 948042 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 404840 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1352882 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398223090 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101918095 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3526446 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24952319 # number of nop insts executed -system.cpu.iew.exec_refs 182568992 # number of memory reference insts executed -system.cpu.iew.exec_branches 47207101 # Number of branches executed -system.cpu.iew.exec_stores 79005050 # Number of stores executed -system.cpu.iew.exec_rate 2.505873 # Inst execution rate -system.cpu.iew.wb_sent 401526892 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400679818 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195200441 # num instructions producing a value -system.cpu.iew.wb_consumers 273221552 # num instructions consuming a value +system.cpu.iew.exec_nop 24783740 # number of nop insts executed +system.cpu.iew.exec_refs 180334326 # number of memory reference insts executed +system.cpu.iew.exec_branches 46552042 # Number of branches executed +system.cpu.iew.exec_stores 78416231 # Number of stores executed +system.cpu.iew.exec_rate 2.574614 # Inst execution rate +system.cpu.iew.wb_sent 396695169 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396067244 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193570018 # num instructions producing a value +system.cpu.iew.wb_consumers 271138332 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.489365 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714440 # average fanout of values written-back +system.cpu.iew.wb_rate 2.560676 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713916 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43021782 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34296903 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1621908 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154588688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.578873 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965339 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1198153 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149616169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.664582 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.996061 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58995602 38.16% 38.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23401293 15.14% 53.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13308874 8.61% 61.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11694068 7.56% 69.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8446337 5.46% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5505575 3.56% 78.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5146283 3.33% 81.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3352831 2.17% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24737825 16.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55282421 36.95% 36.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22517619 15.05% 52.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13057157 8.73% 60.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11465050 7.66% 68.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8178831 5.47% 73.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5460295 3.65% 77.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5171821 3.46% 80.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3274025 2.19% 83.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25208950 16.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154588688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149616169 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,204 +468,340 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24737825 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25208950 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571534251 # The number of ROB reads -system.cpu.rob.rob_writes 889574996 # The number of ROB writes -system.cpu.timesIdled 3393 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 179410 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557365728 # The number of ROB reads +system.cpu.rob.rob_writes 870806965 # The number of ROB writes +system.cpu.timesIdled 3403 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 181102 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.428561 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.428561 # CPI: Total CPI of All Threads -system.cpu.ipc 2.333392 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.333392 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402843963 # number of integer regfile reads -system.cpu.int_regfile_writes 172601197 # number of integer regfile writes -system.cpu.fp_regfile_reads 158371131 # number of floating regfile reads -system.cpu.fp_regfile_writes 105217877 # number of floating regfile writes +system.cpu.cpi 0.411830 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.411830 # CPI: Total CPI of All Threads +system.cpu.ipc 2.428187 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.428187 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398054965 # number of integer regfile reads +system.cpu.int_regfile_writes 170113807 # number of integer regfile writes +system.cpu.fp_regfile_reads 156515246 # number of floating regfile reads +system.cpu.fp_regfile_writes 104037972 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2196 # number of replacements -system.cpu.icache.tagsinuse 1834.742216 # Cycle average of tags in use -system.cpu.icache.total_refs 52616364 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4124 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12758.575170 # Average number of references to valid blocks. +system.cpu.icache.replacements 2129 # number of replacements +system.cpu.icache.tagsinuse 1832.082194 # Cycle average of tags in use +system.cpu.icache.total_refs 50228789 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4056 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12383.823718 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1834.742216 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.895870 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.895870 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52616364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52616364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52616364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52616364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52616364 # number of overall hits -system.cpu.icache.overall_hits::total 52616364 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5549 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5549 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5549 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5549 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5549 # number of overall misses -system.cpu.icache.overall_misses::total 5549 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 228035499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 228035499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 228035499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 228035499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 228035499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 228035499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52621913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52621913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52621913 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52621913 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52621913 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52621913 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000105 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000105 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000105 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000105 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000105 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000105 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41094.881781 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41094.881781 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41094.881781 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41094.881781 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41094.881781 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41094.881781 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 278 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1832.082194 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894571 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894571 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50228789 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50228789 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50228789 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50228789 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50228789 # number of overall hits +system.cpu.icache.overall_hits::total 50228789 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5437 # number of overall misses +system.cpu.icache.overall_misses::total 5437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 226400000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 226400000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 226400000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 226400000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 226400000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 226400000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50234226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50234226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50234226 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50234226 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50234226 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50234226 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000108 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000108 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000108 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41640.610631 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41640.610631 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41640.610631 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41640.610631 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 238 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1425 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1425 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1425 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1425 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1425 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1425 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4124 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4124 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4124 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4124 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4124 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4124 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176594499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176594499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176594499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176594499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176594499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176594499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000078 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42821.168526 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42821.168526 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42821.168526 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42821.168526 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42821.168526 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42821.168526 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1381 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1381 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1381 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1381 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1381 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1381 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4056 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4056 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4056 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4056 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4056 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4056 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175832000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175832000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175832000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175832000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175832000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175832000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43351.084813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43351.084813 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43351.084813 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43351.084813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43351.084813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43351.084813 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 785 # number of replacements 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-system.cpu.dcache.writebacks::writebacks 663 # number of writebacks -system.cpu.dcache.writebacks::total 663 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 792 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16656 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16656 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17448 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17448 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17448 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17448 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses 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# number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 206315000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 206315000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 206315000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 657 # number of writebacks +system.cpu.dcache.writebacks::total 657 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 819 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 819 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16676 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16676 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17495 # number of demand (read+write) MSHR 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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 51550500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155023000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 155023000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 206573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 206573500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 206573500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -674,150 +810,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51669.028340 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51669.028340 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48566.155771 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48566.155771 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49298.685783 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49298.685783 # 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of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.091586 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.123080 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 781 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 663 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 663 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 65 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 65 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 195 # number of demand (read+write) hits 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-system.cpu.l2cache.demand_accesses::cpu.data 4185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8309 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4124 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8309 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.842144 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.868421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.847222 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979668 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.979668 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.842144 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.953405 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.898183 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.842144 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.953405 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.898183 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47780.593147 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56770.979021 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49561.648580 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48312.899106 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48312.899106 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47780.593147 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50131.704261 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49037.585421 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47780.593147 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50131.704261 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49037.585421 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3473 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4331 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3473 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7463 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3473 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7463 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 122186799 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38051999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 160238798 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112625004 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112625004 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 122186799 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 150677003 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 272863802 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 122186799 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150677003 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 272863802 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.847222 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979668 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979668 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953405 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.898183 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953405 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.898183 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35181.917363 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44349.649184 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36998.106211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35959.452107 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35959.452107 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35181.917363 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37763.659900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36562.213855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35181.917363 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37763.659900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36562.213855 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index ca4ea2a9a..f736a3c63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 2e2e5579e..4b90608f0 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 13:21:28 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 19:45:28 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -12,5 +12,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.070000 -Exiting @ tick 70907303500 because target called exit() +OO-style eon Time= 0.060000 +Exiting @ tick 68267465500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index d021c65df..e8af9a733 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071124 # Number of seconds simulated -sim_ticks 71123520500 # Number of ticks simulated -final_tick 71123520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068267 # Number of seconds simulated +sim_ticks 68267465500 # Number of ticks simulated +final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165652 # Simulator instruction rate (inst/s) -host_op_rate 211776 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43149002 # Simulator tick rate (ticks/s) -host_mem_usage 241844 # Number of bytes of host memory used -host_seconds 1648.32 # Real time elapsed on the host -sim_insts 273048466 # Number of instructions simulated -sim_ops 349076190 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272832 # Number of bytes read from this memory -system.physmem.bytes_read::total 467776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194944 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3046 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4263 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7309 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2740922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3836031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6576952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2740922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2740922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2740922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3836031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6576952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7309 # Total number of read requests seen +host_inst_rate 130031 # Simulator instruction rate (inst/s) +host_op_rate 166236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32510221 # Simulator tick rate (ticks/s) +host_mem_usage 238756 # Number of bytes of host memory used +host_seconds 2099.88 # Real time elapsed on the host +sim_insts 273048375 # Number of instructions simulated +sim_ops 349076099 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 273088 # Number of bytes read from this memory +system.physmem.bytes_read::total 467008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193920 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7297 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2840592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4000266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6840857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2840592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2840592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2840592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4000266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6840857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7297 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7309 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 467776 # Total number of bytes read from memory +system.physmem.cpureqs 7297 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 467008 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 467776 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 467008 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 346 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 514 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 578 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 477 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 480 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 484 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 581 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 359 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 71123348000 # Total gap between requests +system.physmem.totGap 68267282000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7309 # Categorize read packet sizes +system.physmem.readPktSize::6 7297 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 38077286 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 170549286 # Sum of mem lat for all requests -system.physmem.totBusLat 29236000 # Total cycles spent in databus access -system.physmem.totBankLat 103236000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.64 # Average queueing delay per request -system.physmem.avgBankLat 14124.50 # Average bank access latency per request +system.physmem.totQLat 36802775 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 167840775 # Sum of mem lat for all requests +system.physmem.totBusLat 29188000 # Total cycles spent in databus access +system.physmem.totBankLat 101850000 # Total cycles spent in bank access +system.physmem.avgQLat 5043.55 # Average queueing delay per request +system.physmem.avgBankLat 13957.79 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23334.15 # Average memory access latency -system.physmem.avgRdBW 6.58 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23001.34 # Average memory access latency +system.physmem.avgRdBW 6.84 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.58 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.84 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6380 # Number of row buffer hits during reads +system.physmem.readRowHits 6392 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9730927.35 # Average gap between requests +system.physmem.avgGap 9355527.20 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,108 +228,108 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 142247042 # number of cpu cycles simulated +system.cpu.numCycles 136534932 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 43100384 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21816758 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2115490 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28214597 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17877846 # Number of BTB hits +system.cpu.BPredUnit.lookups 41739250 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21065104 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1640413 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 26027262 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 16735646 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6960493 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7483 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 41104486 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 329097721 # Number of instructions fetch has processed -system.cpu.fetch.Branches 43100384 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24838339 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 73741038 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8424830 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20890852 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3376 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 39439386 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 697861 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 142038328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.976886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.453881 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6736138 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7270 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 38860071 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317518566 # Number of instructions fetch has processed +system.cpu.fetch.Branches 41739250 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23471784 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70794265 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6760095 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21559516 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37487912 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 519564 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136324280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.989165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456365 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68979513 48.56% 48.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7395782 5.21% 53.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5795573 4.08% 57.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6270161 4.41% 62.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4963047 3.49% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4315752 3.04% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3304919 2.33% 71.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4334607 3.05% 74.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36678974 25.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66156807 48.53% 48.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6761816 4.96% 53.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5641032 4.14% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6022575 4.42% 62.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4881557 3.58% 65.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4156543 3.05% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3204825 2.35% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4146681 3.04% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35352444 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 142038328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.302997 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.313565 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47965638 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16109831 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69363004 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2371211 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6228644 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7501471 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70557 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 414890822 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 218836 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6228644 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53736634 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1580220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 347679 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 65886950 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14258201 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 404388597 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 136 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1669522 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10203430 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 860 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 443737755 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2388674830 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1302452182 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1086222648 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584986 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 59152769 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14467 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 14465 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35681480 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105493757 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93214934 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4606734 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5678105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392069014 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25544 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378019437 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1377395 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42071369 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 110527513 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1062 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 142038328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.661390 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.043453 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 136324280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305704 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325548 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45389084 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16729555 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66615921 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2549925 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5039795 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7269016 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69099 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401164000 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 213330 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5039795 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50891753 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1911896 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 347462 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63595531 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14537843 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393365757 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1668272 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10291112 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1086 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 431881386 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2329985493 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1257436076 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072549417 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584833 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 47296553 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14334 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 14333 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36353497 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103432229 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91356063 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4280154 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5359345 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383896453 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25411 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373948163 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1224653 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34098402 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 84823076 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 961 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136324280 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.743078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29008018 20.42% 20.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20551186 14.47% 34.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20935508 14.74% 49.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18224796 12.83% 62.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24071271 16.95% 79.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15985787 11.25% 90.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9045864 6.37% 97.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3293540 2.32% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 922358 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24852306 18.23% 18.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19962410 14.64% 32.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20554570 15.08% 47.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18105177 13.28% 61.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23977307 17.59% 78.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15767707 11.57% 90.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8831817 6.48% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3361471 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 911515 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 142038328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136324280 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9132 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4698 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8956 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -348,349 +348,494 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 45614 0.25% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7807 0.04% 0.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 399 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 193826 1.08% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4889 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 240972 1.34% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9466915 52.66% 55.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8004617 44.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46185 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7671 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 470 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190051 1.07% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 6041 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241741 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9330966 52.43% 55.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7960919 44.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128267116 33.93% 33.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174674 0.58% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6840592 1.81% 36.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8692743 2.30% 38.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3457219 0.91% 39.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1621907 0.43% 39.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21346208 5.65% 45.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7171870 1.90% 47.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135741 1.89% 49.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102459140 27.10% 76.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88676941 23.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126153074 33.74% 33.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174128 0.58% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6786226 1.81% 36.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8470375 2.27% 38.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426412 0.92% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1600673 0.43% 39.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20911148 5.59% 45.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7171927 1.92% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134560 1.91% 49.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101505429 27.14% 76.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88438925 23.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378019437 # Type of FU issued -system.cpu.iq.rate 2.657485 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17978872 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047561 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 666289235 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 301587031 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252300909 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 251144234 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132592793 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118832927 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266512180 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129486129 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10875090 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373948163 # Type of FU issued +system.cpu.iq.rate 2.738846 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17797690 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047594 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653530496 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 287597541 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249877083 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249712453 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130436942 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118161488 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262975786 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128770067 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11107823 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10842660 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 119827 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14278 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10836994 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8781151 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 113920 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14326 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8978150 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19866 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1167 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 176383 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1158 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6228644 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 80063 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4890 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 392103714 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1113019 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105493757 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93214934 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14372 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 353 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14278 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1696490 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 500488 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2196978 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373371007 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101101213 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4648430 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5039795 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 281091 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41482 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 383923458 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 951525 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103432229 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91356063 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14236 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 345 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 384 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14326 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1283309 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 356464 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1639773 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370071311 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100289689 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3876852 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9156 # number of nop insts executed -system.cpu.iew.exec_refs 188456752 # number of memory reference insts executed -system.cpu.iew.exec_branches 38701393 # Number of branches executed -system.cpu.iew.exec_stores 87355539 # Number of stores executed -system.cpu.iew.exec_rate 2.624807 # Inst execution rate -system.cpu.iew.wb_sent 371934669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371133836 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184775670 # num instructions producing a value -system.cpu.iew.wb_consumers 367646771 # num instructions consuming a value +system.cpu.iew.exec_nop 1594 # number of nop insts executed +system.cpu.iew.exec_refs 187642898 # number of memory reference insts executed +system.cpu.iew.exec_branches 38279004 # Number of branches executed +system.cpu.iew.exec_stores 87353209 # Number of stores executed +system.cpu.iew.exec_rate 2.710451 # Inst execution rate +system.cpu.iew.wb_sent 368702519 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368038571 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182991065 # num instructions producing a value +system.cpu.iew.wb_consumers 363891400 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.609079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502590 # average fanout of values written-back +system.cpu.iew.wb_rate 2.695563 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502873 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43027028 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2045711 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135809685 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.570338 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.654112 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 34846819 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24450 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1571698 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131284486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.658933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.660928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38417531 28.29% 28.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29199317 21.50% 49.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13525216 9.96% 59.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11128430 8.19% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13789447 10.15% 78.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7275712 5.36% 83.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3957925 2.91% 86.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3970991 2.92% 89.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14545116 10.71% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34526115 26.30% 26.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28464962 21.68% 47.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13313072 10.14% 58.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11375196 8.66% 66.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13798040 10.51% 77.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7398451 5.64% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3831320 2.92% 85.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3930958 2.99% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14646372 11.16% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135809685 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049078 # Number of instructions committed -system.cpu.commit.committedOps 349076802 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 131284486 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273048987 # Number of instructions committed +system.cpu.commit.committedOps 349076711 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029037 # Number of memory references committed -system.cpu.commit.loads 94651097 # Number of loads committed +system.cpu.commit.refs 177028991 # Number of memory references committed +system.cpu.commit.loads 94651078 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 36549060 # Number of branches committed +system.cpu.commit.branches 36549040 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279594003 # Number of committed integer instructions. +system.cpu.commit.int_insts 279593931 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14545116 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14646372 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 513365876 # The number of ROB reads -system.cpu.rob.rob_writes 790440754 # The number of ROB writes -system.cpu.timesIdled 6359 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 208714 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048466 # Number of Instructions Simulated -system.cpu.committedOps 349076190 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048466 # Number of Instructions Simulated -system.cpu.cpi 0.520959 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520959 # CPI: Total CPI of All Threads -system.cpu.ipc 1.919537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.919537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1783321389 # number of integer regfile reads -system.cpu.int_regfile_writes 236147934 # number of integer regfile writes -system.cpu.fp_regfile_reads 189806588 # number of floating regfile reads -system.cpu.fp_regfile_writes 133619756 # number of floating regfile writes -system.cpu.misc_regfile_reads 991070858 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes -system.cpu.icache.replacements 14002 # number of replacements -system.cpu.icache.tagsinuse 1857.450296 # Cycle average of tags in use -system.cpu.icache.total_refs 39422164 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15897 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2479.849280 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 500559121 # The number of ROB reads +system.cpu.rob.rob_writes 772890927 # The number of ROB writes +system.cpu.timesIdled 6411 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 210652 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048375 # Number of Instructions Simulated +system.cpu.committedOps 349076099 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048375 # Number of Instructions Simulated +system.cpu.cpi 0.500039 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500039 # CPI: Total CPI of All Threads +system.cpu.ipc 1.999843 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.999843 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769305779 # number of integer regfile reads +system.cpu.int_regfile_writes 232713829 # number of integer regfile writes +system.cpu.fp_regfile_reads 188383123 # number of floating regfile reads +system.cpu.fp_regfile_writes 132609484 # number of floating regfile writes +system.cpu.misc_regfile_reads 973808735 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426415 # number of misc regfile writes +system.cpu.icache.replacements 13908 # number of replacements +system.cpu.icache.tagsinuse 1849.811927 # Cycle average of tags in use +system.cpu.icache.total_refs 37470862 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15795 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2372.324280 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1857.450296 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.906958 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.906958 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39422164 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39422164 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39422164 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39422164 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39422164 # number of overall hits -system.cpu.icache.overall_hits::total 39422164 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17219 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17219 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17219 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17219 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17219 # number of overall misses -system.cpu.icache.overall_misses::total 17219 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 362034000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 362034000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 362034000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 362034000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 362034000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 362034000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39439383 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39439383 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39439383 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39439383 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39439383 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39439383 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000437 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000437 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000437 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000437 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000437 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000437 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.262791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21025.262791 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.262791 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21025.262791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.262791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21025.262791 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 660 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1849.811927 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.903228 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.903228 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37470862 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37470862 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37470862 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37470862 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37470862 # number of overall hits +system.cpu.icache.overall_hits::total 37470862 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17049 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17049 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17049 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17049 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17049 # number of overall misses +system.cpu.icache.overall_misses::total 17049 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 356549497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 356549497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 356549497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 356549497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 356549497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 356549497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37487911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37487911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37487911 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37487911 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37487911 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37487911 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000455 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000455 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000455 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000455 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000455 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20913.220541 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20913.220541 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 585 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.789474 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1322 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1322 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1322 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1322 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1322 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1322 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15897 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15897 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15897 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15897 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15897 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15897 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 295359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 295359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 295359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 295359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 295359000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 295359000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall 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0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40455.183452 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40455.183452 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39020.440260 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39020.440260 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39250.936823 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39250.936823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39250.936823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39250.936823 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13009 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 844 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 400 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.522500 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 52.750000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks -system.cpu.dcache.writebacks::total 1035 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2253 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2253 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18405 # number of WriteReq MSHR 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demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -699,159 +844,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44031.803097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44031.803097 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46937.766714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46937.766714 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45800.541126 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45800.541126 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45800.541126 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45800.541126 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency 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latency -system.cpu.l2cache.overall_avg_miss_latency::total 48193.300720 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 50 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3046 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1467 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4513 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2796 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2796 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4263 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7309 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4263 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7309 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111924644 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54839196 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 166763840 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94353475 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94353475 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111924644 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149192671 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 261117315 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111924644 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149192671 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 261117315 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.811843 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254929 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993957 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993957 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922727 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356259 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922727 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356259 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36744.794485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37381.865031 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36951.881232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33745.878040 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33745.878040 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36744.794485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34997.107905 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35725.450130 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36744.794485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34997.107905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35725.450130 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 0ba1f17a2..219e926d0 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index b26c5402f..319c358f1 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:41:27 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:07:24 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 646278131000 because target called exit() +Exiting @ tick 626365181000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index ca0137184..cc561b02c 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.643360 # Number of seconds simulated -sim_ticks 643359514000 # Number of ticks simulated -final_tick 643359514000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.626365 # Number of seconds simulated +sim_ticks 626365181000 # Number of ticks simulated +final_tick 626365181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181804 # Simulator instruction rate (inst/s) -host_op_rate 181804 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64159253 # Simulator tick rate (ticks/s) -host_mem_usage 240484 # Number of bytes of host memory used -host_seconds 10027.54 # Real time elapsed on the host +host_inst_rate 141169 # Simulator instruction rate (inst/s) +host_op_rate 141169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48503245 # Simulator tick rate (ticks/s) +host_mem_usage 240100 # Number of bytes of host memory used +host_seconds 12913.88 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 179328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30296192 # Number of bytes read from this memory -system.physmem.bytes_read::total 30475520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 179328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 179328 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30294656 # Number of bytes read from this memory +system.physmem.bytes_read::total 30470720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473378 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476180 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473354 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476105 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 278737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47090610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47369347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 278737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 278737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6655862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6655862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6655862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 278737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47090610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54025209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476180 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 281088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48365805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48646893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 281088 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 281088 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6836446 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6836446 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6836446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 281088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48365805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55483340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476105 # Total number of read requests seen system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543088 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30475520 # Total number of bytes read from memory +system.physmem.cpureqs 543013 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30470720 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30475520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30470720 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 93 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29588 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29989 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 29577 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29984 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 29897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29812 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29833 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29824 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29806 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29835 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29819 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29663 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29641 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29707 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 29667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29798 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29791 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4187 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4171 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4154 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4170 # Tr system.physmem.perBankWrReqs::15 4213 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 643359452500 # Total gap between requests +system.physmem.totGap 626365119500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476180 # Categorize read packet sizes +system.physmem.readPktSize::6 476105 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 406668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 406602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1657778750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15956610750 # Sum of mem lat for all requests -system.physmem.totBusLat 1904408000 # Total cycles spent in databus access -system.physmem.totBankLat 12394424000 # Total cycles spent in bank access -system.physmem.avgQLat 3481.98 # Average queueing delay per request -system.physmem.avgBankLat 26033.13 # Average bank access latency per request +system.physmem.totQLat 2248288249 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 16547544249 # Sum of mem lat for all requests +system.physmem.totBusLat 1904048000 # Total cycles spent in databus access +system.physmem.totBankLat 12395208000 # Total cycles spent in bank access +system.physmem.avgQLat 4723.18 # Average queueing delay per request +system.physmem.avgBankLat 26039.70 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33515.11 # Average memory access latency -system.physmem.avgRdBW 47.37 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.37 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.66 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 34762.87 # Average memory access latency +system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.84 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.84 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.34 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.97 # Average write queue length over time -system.physmem.readRowHits 265466 # Number of row buffer hits during reads -system.physmem.writeRowHits 48780 # Number of row buffer hits during writes -system.physmem.readRowHitRate 55.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.91 # Row buffer hit rate for writes -system.physmem.avgGap 1184632.05 # Average gap between requests +system.physmem.busUtil 0.35 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.03 # Average read queue length over time +system.physmem.avgWrQLen 11.00 # Average write queue length over time +system.physmem.readRowHits 265467 # Number of row buffer hits during reads +system.physmem.writeRowHits 48790 # Number of row buffer hits during writes +system.physmem.readRowHitRate 55.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.92 # Row buffer hit rate for writes +system.physmem.avgGap 1153499.31 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 526069225 # DTB read hits -system.cpu.dtb.read_misses 579156 # DTB read misses +system.cpu.dtb.read_hits 522560373 # DTB read hits +system.cpu.dtb.read_misses 588728 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 526648381 # DTB read accesses -system.cpu.dtb.write_hits 297161949 # DTB write hits -system.cpu.dtb.write_misses 50214 # DTB write misses +system.cpu.dtb.read_accesses 523149101 # DTB read accesses +system.cpu.dtb.write_hits 283071161 # DTB write hits +system.cpu.dtb.write_misses 50270 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 297212163 # DTB write accesses -system.cpu.dtb.data_hits 823231174 # DTB hits -system.cpu.dtb.data_misses 629370 # DTB misses +system.cpu.dtb.write_accesses 283121431 # DTB write accesses +system.cpu.dtb.data_hits 805631534 # DTB hits +system.cpu.dtb.data_misses 638998 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 823860544 # DTB accesses -system.cpu.itb.fetch_hits 405407805 # ITB hits -system.cpu.itb.fetch_misses 819 # ITB misses +system.cpu.dtb.data_accesses 806270532 # DTB accesses +system.cpu.itb.fetch_hits 395323042 # ITB hits +system.cpu.itb.fetch_misses 713 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 405408624 # ITB accesses +system.cpu.itb.fetch_accesses 395323755 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1286719029 # number of cpu cycles simulated +system.cpu.numCycles 1252730363 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 402098178 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 264077360 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 27592144 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 331664988 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 265014495 # Number of BTB hits +system.cpu.BPredUnit.lookups 388924238 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 255857711 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 25855826 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 319270007 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 258448229 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 57783698 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7200 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 424132228 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3367367633 # Number of instructions fetch has processed -system.cpu.fetch.Branches 402098178 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 322798193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 646196241 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 166511643 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 68824339 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9321 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 70 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 405407805 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9489583 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1277592072 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.635714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.156498 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 57345473 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6929 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 410516643 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3276851782 # Number of instructions fetch has processed +system.cpu.fetch.Branches 388924238 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315793702 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630639053 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 158095234 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 69542401 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6974 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 395323042 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11287657 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1242455631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.637399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141502 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 631395831 49.42% 49.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 61908546 4.85% 54.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 44955490 3.52% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72442913 5.67% 63.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127234893 9.96% 73.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45699485 3.58% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41229418 3.23% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8398105 0.66% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 244327391 19.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 611816578 49.24% 49.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57562553 4.63% 53.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43380535 3.49% 57.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71885087 5.79% 63.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129158557 10.40% 73.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46353903 3.73% 77.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41221359 3.32% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7475471 0.60% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233601588 18.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1277592072 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.312499 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.617019 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 452657714 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55753482 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 621910588 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8852787 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 138417501 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 35688961 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12608 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3272292546 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46854 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 138417501 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 480561611 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 21495863 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27669 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 602513400 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 34576028 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3180651525 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 116 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 29849843 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2112719200 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3696606448 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3567977970 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 128628478 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1242455631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310461 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.615768 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438637304 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56111569 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 606899212 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9069214 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131738332 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31728331 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12429 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3195294876 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46495 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131738332 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467849375 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 21501203 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 26667 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 586406570 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 34933484 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3096787172 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15151 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28695106 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2055570524 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3581032022 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3460282692 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120749330 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 727750130 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4257 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 122 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112675652 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 746614838 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 365012896 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68733869 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9300063 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2678263841 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 113 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2207816608 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17947963 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 855152506 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 736519407 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 74 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1277592072 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.728108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.823912 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 670601454 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4229 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 95 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109203185 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 744330520 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351486216 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 69160897 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8862018 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2624452005 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 84 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2160789811 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17925786 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 801345385 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 726874664 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1242455631 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.739128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803652 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 463406335 36.27% 36.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 208221001 16.30% 52.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 253020667 19.80% 72.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119517466 9.35% 81.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 107963864 8.45% 90.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79412827 6.22% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 22155797 1.73% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18005418 1.41% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5888697 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 445618907 35.87% 35.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 197093468 15.86% 51.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251212495 20.22% 71.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120765174 9.72% 81.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104645405 8.42% 90.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79514591 6.40% 96.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24185782 1.95% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17651908 1.42% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1767901 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1277592072 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1242455631 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146338 3.02% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26001591 68.56% 71.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10776371 28.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146234 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25650345 69.73% 72.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9987945 27.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1263752223 57.24% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29225332 1.32% 58.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254699 0.37% 58.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204653 0.33% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 590734000 26.76% 86.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 308625853 13.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234634682 57.14% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851271 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589669482 27.29% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293155183 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2207816608 # Type of FU issued -system.cpu.iq.rate 1.715850 # Inst issue rate -system.cpu.iq.fu_busy_cnt 37924300 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017177 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5591649635 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3435076999 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2032506919 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 157447916 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 98414178 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 76358311 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2164690748 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 81047408 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 59332604 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2160789811 # Type of FU issued +system.cpu.iq.rate 1.724864 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36784524 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017024 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5467643878 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3337715121 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1990557348 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101685 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88155822 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73610149 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2120121697 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77449886 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62086371 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235544812 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11687 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 77448 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 154218000 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 233260494 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 21308 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76027 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140691320 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4399 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2001 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4419 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2184 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 138417501 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7967616 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 401073 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3039337687 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 731219 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 746614838 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 365012896 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 113 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 191088 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1450 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 77448 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 27584304 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 31589 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 27615893 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2113102879 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 526648496 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94713729 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131738332 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7963688 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 401158 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2987881141 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 737486 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 744330520 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351486216 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 84 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 191221 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1459 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76027 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25850018 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 29386 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25879404 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2066687986 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 523149239 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94101825 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 361073733 # number of nop insts executed -system.cpu.iew.exec_refs 823861177 # number of memory reference insts executed -system.cpu.iew.exec_branches 283370996 # Number of branches executed -system.cpu.iew.exec_stores 297212681 # Number of stores executed -system.cpu.iew.exec_rate 1.642241 # Inst execution rate -system.cpu.iew.wb_sent 2111610495 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2108865230 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1193923515 # num instructions producing a value -system.cpu.iew.wb_consumers 1771725000 # num instructions consuming a value +system.cpu.iew.exec_nop 363429052 # number of nop insts executed +system.cpu.iew.exec_refs 806271170 # number of memory reference insts executed +system.cpu.iew.exec_branches 277685226 # Number of branches executed +system.cpu.iew.exec_stores 283121931 # Number of stores executed +system.cpu.iew.exec_rate 1.649747 # Inst execution rate +system.cpu.iew.wb_sent 2066566988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2064167497 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1181646251 # num instructions producing a value +system.cpu.iew.wb_consumers 1754266128 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.638948 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673876 # average fanout of values written-back +system.cpu.iew.wb_rate 1.647735 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673584 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1013373341 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 961921272 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 27579934 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1139174571 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.763547 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.475615 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25843781 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1110717299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.808730 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509348 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 512941432 45.03% 45.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 233024401 20.46% 65.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 122205483 10.73% 76.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58495999 5.13% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 54572847 4.79% 86.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24070176 2.11% 88.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18202956 1.60% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 17085980 1.50% 91.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98575297 8.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 491335332 44.24% 44.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228930715 20.61% 64.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119800633 10.79% 75.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58838434 5.30% 80.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50772069 4.57% 85.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24138536 2.17% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19157540 1.72% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16738195 1.51% 90.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101005845 9.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1139174571 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1110717299 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,320 +475,192 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98575297 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101005845 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4057323809 # The number of ROB reads -system.cpu.rob.rob_writes 6183141843 # The number of ROB writes -system.cpu.timesIdled 212566 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9126957 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3974983920 # The number of ROB reads +system.cpu.rob.rob_writes 6073558017 # The number of ROB writes +system.cpu.timesIdled 212495 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10274732 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.705808 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.705808 # CPI: Total CPI of All Threads -system.cpu.ipc 1.416815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.416815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2692001611 # number of integer regfile reads -system.cpu.int_regfile_writes 1522401675 # number of integer regfile writes -system.cpu.fp_regfile_reads 82933521 # number of floating regfile reads -system.cpu.fp_regfile_writes 54035244 # number of floating regfile writes +system.cpu.cpi 0.687164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.687164 # CPI: Total CPI of All Threads +system.cpu.ipc 1.455256 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.455256 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2628560765 # number of integer regfile reads +system.cpu.int_regfile_writes 1497106363 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811457 # number of floating regfile reads +system.cpu.fp_regfile_writes 52660996 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8405 # number of replacements -system.cpu.icache.tagsinuse 1669.043453 # Cycle average of tags in use -system.cpu.icache.total_refs 405395000 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10125 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 40039.012346 # Average number of references to valid blocks. +system.cpu.icache.replacements 8336 # number of replacements +system.cpu.icache.tagsinuse 1656.236510 # Cycle average of tags in use +system.cpu.icache.total_refs 395310182 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10048 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39342.175756 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1669.043453 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.814963 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.814963 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 405395000 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 405395000 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 405395000 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 405395000 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 405395000 # number of overall hits -system.cpu.icache.overall_hits::total 405395000 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12805 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12805 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12805 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12805 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12805 # number of overall misses -system.cpu.icache.overall_misses::total 12805 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310013999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310013999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310013999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310013999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310013999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310013999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 405407805 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 405407805 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 405407805 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 405407805 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 405407805 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 405407805 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24210.386490 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24210.386490 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24210.386490 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24210.386490 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24210.386490 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24210.386490 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1240 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1656.236510 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.808709 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.808709 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 395310182 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 395310182 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 395310182 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 395310182 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 395310182 # number of overall hits +system.cpu.icache.overall_hits::total 395310182 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12860 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12860 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12860 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12860 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12860 # number of overall misses +system.cpu.icache.overall_misses::total 12860 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 302484999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 302484999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 302484999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 302484999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 302484999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 302484999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 395323042 # number of ReadReq accesses(hits+misses) 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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23521.384059 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23521.384059 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23521.384059 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23521.384059 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23521.384059 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23521.384059 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 562 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 72.941176 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.466667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2679 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2679 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2679 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2679 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2679 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2679 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10126 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10126 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10126 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10126 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10126 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 232973499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 232973499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 232973499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 232973499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 232973499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 232973499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2811 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2811 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2811 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2811 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2811 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2811 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10049 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10049 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10049 # number of demand (read+write) MSHR misses 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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23007.455955 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23007.455955 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23007.455955 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23007.455955 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23007.455955 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23007.455955 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22633.893820 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22633.893820 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22633.893820 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22633.893820 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22633.893820 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22633.893820 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1528133 # number of replacements -system.cpu.dcache.tagsinuse 4094.874938 # Cycle average of tags in use -system.cpu.dcache.total_refs 674537761 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1532229 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 440.232995 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 312771000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.874938 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999725 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999725 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 464804507 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 464804507 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733210 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733210 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 44 # number of LoadLockedReq hits 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(read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92855043859 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92855043859 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 466730361 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 466730361 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 45 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 45 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 677525257 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 677525257 # number of demand (read+write) accesses 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accesses -system.cpu.dcache.overall_miss_rate::total 0.004409 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30753.560758 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30753.560758 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31674.314118 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31674.314118 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31080.770085 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31080.770085 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.770085 # average overall miss latency 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+system.cpu.dcache.occ_percent::cpu.data 0.999727 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999727 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 458541726 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458541726 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209733214 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209733214 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 668274940 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 668274940 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 668274940 # number of overall hits +system.cpu.dcache.overall_hits::total 668274940 # number of overall hits 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WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 93404227357 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 93404227357 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 93404227357 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 93404227357 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 460467574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460467574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 671262470 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 671262470 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 671262470 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 671262470 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004182 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004182 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004451 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004451 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004451 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004451 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31031.868039 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31031.868039 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31687.045986 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31687.045986 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31264.699386 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31264.699386 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31264.699386 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31264.699386 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11600 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 365 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.780822 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 137 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 95985 # number of writebacks +system.cpu.dcache.writebacks::total 95985 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465605 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465605 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990044 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990044 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455649 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455649 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455649 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455649 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460243 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460243 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71638 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71638 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531881 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531881 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531881 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531881 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35985859000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35985859000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676864000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676864000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39662723000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39662723000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39662723000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39662723000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003171 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002282 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002282 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002282 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002282 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24643.746965 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24643.746965 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51325.609313 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51325.609313 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25891.517030 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25891.517030 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25891.517030 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25891.517030 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 39878e8d2..c3641e537 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 278fe40f3..220b82b27 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:46:31 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 20:00:53 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 653190727500 because target called exit() +Exiting @ tick 624867585500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index ac8776e10..65535d511 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.635788 # Number of seconds simulated -sim_ticks 635788224000 # Number of ticks simulated -final_tick 635788224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.624868 # Number of seconds simulated +sim_ticks 624867585500 # Number of ticks simulated +final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107590 # Simulator instruction rate (inst/s) -host_op_rate 146523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49411882 # Simulator tick rate (ticks/s) -host_mem_usage 254872 # Number of bytes of host memory used -host_seconds 12867.11 # Real time elapsed on the host -sim_insts 1384378595 # Number of instructions simulated -sim_ops 1885333347 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 160512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30246144 # Number of bytes read from this memory -system.physmem.bytes_read::total 30406656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 160512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 160512 # Number of instructions bytes read from this memory +host_inst_rate 92987 # Simulator instruction rate (inst/s) +host_op_rate 126636 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41971725 # Simulator tick rate (ticks/s) +host_mem_usage 253512 # Number of bytes of host memory used +host_seconds 14887.82 # Real time elapsed on the host +sim_insts 1384379060 # Number of instructions simulated +sim_ops 1885333812 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242752 # Number of bytes read from this memory +system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155584 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2508 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472596 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475104 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472543 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474974 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 252461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47572671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47825132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 252461 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 252461 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6653587 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6653587 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6653587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 252461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47572671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54478719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 475105 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 248987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48398657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48647644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6769869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6769869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6769869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48398657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55417514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474974 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545524 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30406656 # Total number of bytes read from memory +system.physmem.cpureqs 545402 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30398336 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30406656 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30398336 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 162 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4321 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29546 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29628 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29773 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29801 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29602 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29611 # Track reads on a per bank basis +system.physmem.servicedByWrQ 146 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4330 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29545 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29618 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29790 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29606 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29627 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29610 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4108 # Tr system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 635788203500 # Total gap between requests +system.physmem.totGap 624867513500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 475105 # Categorize read packet sizes +system.physmem.readPktSize::6 474974 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4321 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4330 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 407840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2296699471 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 17086173471 # Sum of mem lat for all requests -system.physmem.totBusLat 1899772000 # Total cycles spent in databus access -system.physmem.totBankLat 12889702000 # Total cycles spent in bank access -system.physmem.avgQLat 4835.74 # Average queueing delay per request -system.physmem.avgBankLat 27139.47 # Average bank access latency per request +system.physmem.totQLat 3316258619 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 18090208619 # Sum of mem lat for all requests +system.physmem.totBusLat 1899312000 # Total cycles spent in databus access +system.physmem.totBankLat 12874638000 # Total cycles spent in bank access +system.physmem.avgQLat 6984.13 # Average queueing delay per request +system.physmem.avgBankLat 27114.32 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35975.21 # Average memory access latency -system.physmem.avgRdBW 47.83 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.65 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.83 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.65 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38098.45 # Average memory access latency +system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.34 # Data bus utilization in percentage +system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 17.42 # Average write queue length over time -system.physmem.readRowHits 249227 # Number of row buffer hits during reads -system.physmem.writeRowHits 48069 # Number of row buffer hits during writes +system.physmem.avgWrQLen 17.43 # Average write queue length over time +system.physmem.readRowHits 249202 # Number of row buffer hits during reads +system.physmem.writeRowHits 48033 # Number of row buffer hits during writes system.physmem.readRowHitRate 52.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.72 # Row buffer hit rate for writes -system.physmem.avgGap 1174768.44 # Average gap between requests +system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes +system.physmem.avgGap 1154869.43 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,577 +235,450 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1271576449 # number of cpu cycles simulated +system.cpu.numCycles 1249735172 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 450228409 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 355532784 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 33221025 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 286250905 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 237054856 # Number of BTB hits +system.cpu.BPredUnit.lookups 439117025 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 350578524 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 30630316 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 248764319 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 227490785 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 53630453 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2814194 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 368782120 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2317566621 # Number of instructions fetch has processed -system.cpu.fetch.Branches 450228409 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 290685309 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 618187609 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 167802769 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 122950545 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2044 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 34033 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 346967374 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10833079 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1244485983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575716 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.174798 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 354123352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed +system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133000859 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 333825475 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10767149 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1215073364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 626344117 50.33% 50.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 45317842 3.64% 53.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101227769 8.13% 62.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 59470859 4.78% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 73017121 5.87% 72.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44727211 3.59% 76.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30024154 2.41% 78.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31448495 2.53% 81.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 232908415 18.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614410423 50.57% 50.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 72457573 5.96% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42599927 3.51% 75.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31039765 2.55% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31697654 2.61% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 229019054 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1244485983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.354071 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.822593 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 419135073 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95311788 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 577111124 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18421558 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134506440 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 50263790 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 26327 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3103411757 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 60284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134506440 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 455352486 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27182944 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 495803 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 558181591 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 68766719 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3020461835 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 80 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1786182 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58542729 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2987223490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14381793689 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13781741718 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 600051971 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993152898 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 994070592 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26249 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23484 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 177920569 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 971527729 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 505697139 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 29364054 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 38323451 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2844663565 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34202 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2471693501 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 7154025 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 946732451 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2394075214 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11217 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1244485983 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.986116 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887022 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1215073364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105461627 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44615078 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3041090435 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27022 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 127217578 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 540789818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71593101 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2966286071 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2940514356 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14121260893 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13550785312 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 947360714 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 972715984 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 490205592 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36288460 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40771047 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2804297042 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 31006 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2436370950 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13311855 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1215073364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 394145382 31.67% 31.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 193214413 15.53% 47.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204405304 16.42% 63.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171173190 13.75% 77.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 129740055 10.43% 87.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 97310600 7.82% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 36398713 2.92% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12543196 1.01% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5555130 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 379121475 31.20% 31.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132635579 10.92% 87.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 93723777 7.71% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37883178 3.12% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12361449 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3045427 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1244485983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1215073364 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 746380 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24393 0.03% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55867065 61.34% 62.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 34441237 37.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55143304 62.90% 63.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31782308 36.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1129092447 45.68% 45.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11228574 0.45% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5501982 0.22% 46.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23586280 0.95% 47.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 837187213 33.87% 81.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 456845236 18.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1107294192 45.45% 45.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11224034 0.46% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502357 0.23% 46.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23404551 0.96% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838357967 34.41% 81.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442336083 18.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2471693501 # Type of FU issued -system.cpu.iq.rate 1.943803 # Inst issue rate -system.cpu.iq.fu_busy_cnt 91079075 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036849 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6158633993 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3704145010 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2281572785 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 127472092 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 87353789 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 58523777 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2496546302 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 66226274 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 80772254 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2436370950 # Type of FU issued +system.cpu.iq.rate 1.949510 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6066277406 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82717236 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56437909 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2460715459 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63320089 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84361835 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 340138947 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 411099 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 228700241 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 341327109 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8250 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1428808 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 213208601 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 221 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134506440 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8643138 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 547079 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2844711818 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 10610498 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 971527729 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 505697139 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23185 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 540297 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2527 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 411099 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 34712988 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1840552 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 36553540 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2395281486 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 793221583 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 76412015 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 127217578 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1409393 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1558593 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2526 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1428808 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32521161 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1512713 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 34033874 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2362219907 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792646926 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 74151043 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14051 # number of nop insts executed -system.cpu.iew.exec_refs 1229345389 # number of memory reference insts executed -system.cpu.iew.exec_branches 327128098 # Number of branches executed -system.cpu.iew.exec_stores 436123806 # Number of stores executed -system.cpu.iew.exec_rate 1.883710 # Inst execution rate -system.cpu.iew.wb_sent 2368179118 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2340096562 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1354502475 # num instructions producing a value -system.cpu.iew.wb_consumers 2541864992 # num instructions consuming a value +system.cpu.iew.exec_nop 12429 # number of nop insts executed +system.cpu.iew.exec_refs 1216288233 # number of memory reference insts executed +system.cpu.iew.exec_branches 322226431 # Number of branches executed +system.cpu.iew.exec_stores 423641307 # Number of stores executed +system.cpu.iew.exec_rate 1.890176 # Inst execution rate +system.cpu.iew.wb_sent 2335115057 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2309436326 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347701281 # num instructions producing a value +system.cpu.iew.wb_consumers 2523709653 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.840311 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.532877 # average fanout of values written-back +system.cpu.iew.wb_rate 1.847941 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534016 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 959367728 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 22985 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 33197953 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1109979545 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.698540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.378671 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 918995782 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 23078 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 30617997 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1087855788 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.733083 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.398277 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 463287159 41.74% 41.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 297974077 26.85% 68.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 91457957 8.24% 76.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 72253905 6.51% 83.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 45208298 4.07% 87.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23225084 2.09% 89.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15854658 1.43% 90.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10141159 0.91% 91.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90577248 8.16% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 447553397 41.14% 41.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288592120 26.53% 67.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95115403 8.74% 76.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70228058 6.46% 82.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46464545 4.27% 87.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22184894 2.04% 89.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15849617 1.46% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10984656 1.01% 91.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90883098 8.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1109979545 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384389611 # Number of instructions committed -system.cpu.commit.committedOps 1885344363 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1087855788 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384390076 # Number of instructions committed +system.cpu.commit.committedOps 1885344828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385680 # Number of memory references committed -system.cpu.commit.loads 631388782 # Number of loads committed +system.cpu.commit.refs 908385866 # Number of memory references committed +system.cpu.commit.loads 631388875 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299635996 # Number of branches committed +system.cpu.commit.branches 299636089 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705271 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705643 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90577248 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90883098 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3864096043 # The number of ROB reads -system.cpu.rob.rob_writes 5823945497 # The number of ROB writes -system.cpu.timesIdled 351641 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27090466 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384378595 # Number of Instructions Simulated -system.cpu.committedOps 1885333347 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384378595 # Number of Instructions Simulated -system.cpu.cpi 0.918518 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.918518 # CPI: Total CPI of All Threads -system.cpu.ipc 1.088710 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.088710 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11907054979 # number of integer regfile reads -system.cpu.int_regfile_writes 2251695031 # number of integer regfile writes -system.cpu.fp_regfile_reads 70501707 # number of floating regfile reads -system.cpu.fp_regfile_writes 50326111 # number of floating regfile writes -system.cpu.misc_regfile_reads 3707678526 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776104 # number of misc regfile writes -system.cpu.icache.replacements 23916 # number of replacements -system.cpu.icache.tagsinuse 1661.487549 # Cycle average of tags in use -system.cpu.icache.total_refs 346930644 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 25614 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13544.571094 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3801294955 # The number of ROB reads +system.cpu.rob.rob_writes 5735909866 # The number of ROB writes +system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34661808 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384379060 # Number of Instructions Simulated +system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated +system.cpu.cpi 0.902741 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.902741 # CPI: Total CPI of All Threads +system.cpu.ipc 1.107738 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.107738 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11770471325 # number of integer regfile reads +system.cpu.int_regfile_writes 2224868034 # number of integer regfile writes +system.cpu.fp_regfile_reads 68796296 # number of floating regfile reads +system.cpu.fp_regfile_writes 49549961 # number of floating regfile writes +system.cpu.misc_regfile_reads 3658188004 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776290 # number of misc regfile writes +system.cpu.icache.replacements 22546 # number of replacements +system.cpu.icache.tagsinuse 1642.542137 # Cycle average of tags in use +system.cpu.icache.total_refs 333790581 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24232 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13774.784624 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1661.487549 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.811273 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.811273 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 346934721 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 346934721 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 346934721 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 346934721 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 346934721 # number of overall hits -system.cpu.icache.overall_hits::total 346934721 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 32652 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 32652 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 32652 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 32652 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 32652 # number of overall misses -system.cpu.icache.overall_misses::total 32652 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 492196499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 492196499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 492196499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 492196499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 492196499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 492196499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 346967373 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 346967373 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 346967373 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 346967373 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 346967373 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 346967373 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15074.007687 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15074.007687 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15074.007687 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15074.007687 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1459 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1642.542137 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.802023 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.802023 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 333794637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 333794637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 333794637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits +system.cpu.icache.overall_hits::total 333794637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 30836 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 30836 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 30836 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 30836 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 30836 # number of overall misses +system.cpu.icache.overall_misses::total 30836 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 469688998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 469688998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 469688998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 469688998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 469688998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 469688998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 333825473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 333825473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 333825473 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 333825473 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 333825473 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 333825473 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15231.839344 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15231.839344 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15231.839344 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15231.839344 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 35 # number of cycles access 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-system.cpu.icache.overall_mshr_hits::cpu.inst 2714 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2714 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29938 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 29938 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 29938 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 29938 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 29938 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 29938 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 396628999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 396628999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 396628999 # number of demand (read+write) MSHR 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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13248.346550 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13248.346550 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.580801 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.580801 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533079 # number of replacements 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0.003013 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000163 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000163 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002903 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002903 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002903 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002903 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34374.263463 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34374.263463 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47867.504803 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47867.504803 # average WriteReq miss latency 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(read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1294791 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1294791 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1294791 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464622 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464622 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76878 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76878 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541500 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541500 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541500 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541500 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36879858500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36879858500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3477356000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3477356000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40357214500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40357214500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40357214500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40357214500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002092 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002092 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001578 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001578 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001578 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001578 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25180.461921 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25180.461921 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45232.134031 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45232.134031 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26180.482971 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26180.482971 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26180.482971 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26180.482971 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 442324 # number of replacements -system.cpu.l2cache.tagsinuse 32688.980204 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1110893 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 475069 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.338382 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 442193 # number of replacements +system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 474940 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.336548 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1305.388172 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 55.371770 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31328.220262 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039837 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001690 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.956061 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997589 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 23103 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1058082 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1081185 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96247 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96247 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 1294.928331 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 48.758922 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31344.836948 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039518 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy 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latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.131845 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.396826 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.124981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.124981 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1532987 # number of replacements +system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use +system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits +system.cpu.dcache.overall_hits::total 969986101 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses +system.cpu.dcache.overall_misses::total 2787983 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369161000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 67369161000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954942470 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39954942470 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 107324103470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 107324103470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 107324103470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 107324103470 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38495.250319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38495.250319 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks +system.cpu.dcache.writebacks::total 96322 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884239500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884239500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index fc9577d62..00b189ec1 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index e501186a7..2318eb90a 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:54:39 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:19:26 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 47910283500 because target called exit() +Exiting @ tick 43266024500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index e532ddba3..130fea357 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043596 # Number of seconds simulated -sim_ticks 43595903500 # Number of ticks simulated -final_tick 43595903500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043266 # Number of seconds simulated +sim_ticks 43266024500 # Number of ticks simulated +final_tick 43266024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146921 # Simulator instruction rate (inst/s) -host_op_rate 146921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72505010 # Simulator tick rate (ticks/s) -host_mem_usage 252940 # Number of bytes of host memory used -host_seconds 601.28 # Real time elapsed on the host +host_inst_rate 113775 # Simulator instruction rate (inst/s) +host_op_rate 113775 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55722813 # Simulator tick rate (ticks/s) +host_mem_usage 252752 # Number of bytes of host memory used +host_seconds 776.45 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 454912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10138304 # Number of bytes read from this memory -system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 454912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 454912 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 454720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory +system.physmem.bytes_read::total 10593088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454720 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7108 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158411 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165517 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10434742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 232551758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242986500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10434742 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10434742 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 167350770 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 167350770 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 167350770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10434742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 232551758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 410337269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165519 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 10509863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 234326313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 244836176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10509863 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10509863 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 168626725 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 168626725 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 168626725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10509863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 234326313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 413462901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165517 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279516 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10593216 # Total number of bytes read from memory +system.physmem.cpureqs 279514 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10593088 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10593088 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10332 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10222 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10233 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 9969 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10217 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 10609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10334 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 10345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9920 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10624 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10242 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 6899 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 7374 # Tr system.physmem.perBankWrReqs::15 7193 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43595883500 # Total gap between requests +system.physmem.totGap 43266004500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165519 # Categorize read packet sizes +system.physmem.readPktSize::6 165517 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 71904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6270 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,13 +138,13 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4923 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4950 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see @@ -161,57 +161,57 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9323896604 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11720942604 # Sum of mem lat for all requests +system.physmem.totQLat 9309879146 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11706015146 # Sum of mem lat for all requests system.physmem.totBusLat 662068000 # Total cycles spent in databus access -system.physmem.totBankLat 1734978000 # Total cycles spent in bank access -system.physmem.avgQLat 56331.96 # Average queueing delay per request -system.physmem.avgBankLat 10482.17 # Average bank access latency per request +system.physmem.totBankLat 1734068000 # Total cycles spent in bank access +system.physmem.avgQLat 56247.27 # Average queueing delay per request +system.physmem.avgBankLat 10476.68 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70814.13 # Average memory access latency -system.physmem.avgRdBW 242.99 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 167.35 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 242.99 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 167.35 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 70723.94 # Average memory access latency +system.physmem.avgRdBW 244.84 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 168.63 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 244.84 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 168.63 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.56 # Data bus utilization in percentage +system.physmem.busUtil 2.58 # Data bus utilization in percentage system.physmem.avgRdQLen 0.27 # Average read queue length over time -system.physmem.avgWrQLen 10.36 # Average write queue length over time -system.physmem.readRowHits 151893 # Number of row buffer hits during reads -system.physmem.writeRowHits 41557 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.45 # Row buffer hit rate for writes -system.physmem.avgGap 155969.19 # Average gap between requests +system.physmem.avgWrQLen 10.35 # Average write queue length over time +system.physmem.readRowHits 151965 # Number of row buffer hits during reads +system.physmem.writeRowHits 41713 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.59 # Row buffer hit rate for writes +system.physmem.avgGap 154790.12 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277538 # DTB read hits +system.cpu.dtb.read_hits 20277550 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367686 # DTB read accesses -system.cpu.dtb.write_hits 14728672 # DTB write hits +system.cpu.dtb.read_accesses 20367698 # DTB read accesses +system.cpu.dtb.write_hits 14728696 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14735924 # DTB write accesses -system.cpu.dtb.data_hits 35006210 # DTB hits +system.cpu.dtb.write_accesses 14735948 # DTB write accesses +system.cpu.dtb.data_hits 35006246 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103610 # DTB accesses -system.cpu.itb.fetch_hits 12476759 # ITB hits -system.cpu.itb.fetch_misses 12943 # ITB misses +system.cpu.dtb.data_accesses 35103646 # DTB accesses +system.cpu.itb.fetch_hits 12367278 # ITB hits +system.cpu.itb.fetch_misses 11044 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12489702 # ITB accesses +system.cpu.itb.fetch_accesses 12378322 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87191808 # number of cpu cycles simulated +system.cpu.numCycles 86532050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18827150 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12439421 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5024981 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16201522 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5047120 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660945 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 18742312 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12317439 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4774431 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 15498318 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 4661486 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660962 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.152135 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8476186 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10350964 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74333119 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 30.077367 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8071751 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10670561 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74169472 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126652369 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65259 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126488722 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66053 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292889 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14121677 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064639 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4680318 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 234163 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4914481 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8857790 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.683882 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44776328 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293683 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14165611 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060577 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4447125 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216806 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4663931 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9108659 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.863863 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44777842 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77836216 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77186042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 230753 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16919077 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70272731 # Number of cycles cpu stages are processed. -system.cpu.activity 80.595566 # Percentage of cycles cpu is active +system.cpu.timesIdled 230961 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16958681 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69573369 # Number of cycles cpu stages are processed. +system.cpu.activity 80.401850 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -272,302 +272,194 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.986995 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.979527 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.986995 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013176 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.979527 # CPI: Total CPI of All Threads +system.cpu.ipc 1.020901 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.013176 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33768817 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53422991 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.270654 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44539685 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42652123 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.917581 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44072021 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43119787 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.453943 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65076368 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22115440 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.364126 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41085926 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46105882 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.878686 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85196 # number of replacements -system.cpu.icache.tagsinuse 1908.917223 # Cycle average of tags in use -system.cpu.icache.total_refs 12358549 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87242 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.658249 # Average number of references to valid blocks. +system.cpu.ipc_total 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-system.cpu.icache.overall_misses::cpu.inst 118203 # number of overall misses -system.cpu.icache.overall_misses::total 118203 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1846898500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1846898500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1846898500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1846898500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1846898500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1846898500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12476752 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12476752 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12476752 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12476752 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12476752 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12476752 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009474 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009474 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009474 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009474 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009474 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15624.802247 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15624.802247 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15624.802247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15624.802247 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1908.908494 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.932084 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.932084 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12250113 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250113 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250113 # number of demand (read+write) hits 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+system.cpu.icache.demand_miss_latency::total 1822166500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1822166500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1822166500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12367269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367269 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367269 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367269 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367269 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15553.334870 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15553.334870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15553.334870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15553.334870 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 309 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 12.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.263158 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 6.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30961 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30961 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30961 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30961 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30961 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30961 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87242 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87242 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87242 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87242 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87242 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87242 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1292347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1292347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1292347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1292347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1292347500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1292347500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006992 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006992 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006992 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14813.363976 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14813.363976 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30828 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30828 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30828 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30828 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30828 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86328 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 86328 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 86328 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 86328 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 86328 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 86328 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1279244500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1279244500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1279244500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1279244500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1279244500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1279244500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006980 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14818.419285 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14818.419285 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4078.664341 # Cycle average of tags in use -system.cpu.dcache.total_refs 33754987 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.184647 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 249990000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.664341 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995768 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995768 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180268 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180268 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574719 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574719 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754987 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754987 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754987 # number of overall hits -system.cpu.dcache.overall_hits::total 33754987 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96370 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96370 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038658 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038658 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135028 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135028 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135028 # number of overall misses -system.cpu.dcache.overall_misses::total 1135028 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3954988500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3954988500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 91520281000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 91520281000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95475269500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95475269500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95475269500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95475269500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071076 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071076 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032532 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032532 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032532 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032532 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.623327 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.623327 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88113.971105 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 88113.971105 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84117.105041 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84117.105041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84117.105041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84117.105041 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6175044 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 397 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116295 # 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-system.cpu.l2cache.overall_mshr_miss_rate::total 0.567645 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43706.399409 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43331.775254 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 43408.673386 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96667.511326 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96667.511326 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569427 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569427 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43308.036735 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43144.052142 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 43177.700572 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96624.975338 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96624.975338 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 200249 # number of replacements +system.cpu.dcache.tagsinuse 4078.683111 # Cycle average of tags in use +system.cpu.dcache.total_refs 33755002 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 204345 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 165.186337 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 248488000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4078.683111 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995772 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995772 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574731 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574731 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33755002 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33755002 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33755002 # number of overall hits +system.cpu.dcache.overall_hits::total 33755002 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038646 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135013 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135013 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135013 # number of overall misses +system.cpu.dcache.overall_misses::total 1135013 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3942448000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3942448000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 91414151500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 91414151500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95356599500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95356599500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95356599500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95356599500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032531 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032531 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032531 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032531 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40910.768209 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40910.768209 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88012.808503 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 88012.808503 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84013.662839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84013.662839 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6187652 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 65 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116324 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.193253 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 65 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks +system.cpu.dcache.writebacks::total 168350 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35602 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35602 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895066 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895066 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204345 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1934793000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1934793000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14541156500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14541156500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16475949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16475949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16475949500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16475949500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31840.582572 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31840.582572 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101275.640758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101275.640758 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 0698ab8df..06d858804 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 3d5324180..8fd1a4d9e 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:05:33 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:32:34 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 21619648000 because target called exit() +Exiting @ tick 24414646000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 04dfac9bb..c5e407e29 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024767 # Number of seconds simulated -sim_ticks 24766869000 # Number of ticks simulated -final_tick 24766869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024415 # Number of seconds simulated +sim_ticks 24414646000 # Number of ticks simulated +final_tick 24414646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162319 # Simulator instruction rate (inst/s) -host_op_rate 162319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50509376 # Simulator tick rate (ticks/s) -host_mem_usage 253968 # Number of bytes of host memory used -host_seconds 490.34 # Real time elapsed on the host +host_inst_rate 171645 # Simulator instruction rate (inst/s) +host_op_rate 171645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52651835 # Simulator tick rate (ticks/s) +host_mem_usage 254848 # Number of bytes of host memory used +host_seconds 463.70 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 491520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory -system.physmem.bytes_read::total 10646272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 491520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 491520 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 490368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153920 # Number of bytes read from this memory +system.physmem.bytes_read::total 10644288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490368 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7680 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158655 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166317 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19845867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 410013555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 429859422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19845867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19845867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 294625857 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 294625857 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 294625857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19845867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 410013555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 724485279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166348 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 20084993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 415894623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 435979616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20084993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20084993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 298876338 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 298876338 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 298876338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20084993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 415894623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 734855955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166317 # Total number of read requests seen system.physmem.writeReqs 114015 # Total number of write requests seen -system.physmem.cpureqs 280363 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10646272 # Total number of bytes read from memory +system.physmem.cpureqs 280332 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10644288 # Total number of bytes read from memory system.physmem.bytesWritten 7296960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10646272 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10644288 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10314 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10735 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10586 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10583 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10274 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 10277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10016 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10446 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10255 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis +system.physmem.perBankRdReqs::7 10017 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10445 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10374 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9953 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10252 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7409 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 6902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7249 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7298 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7207 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6885 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7299 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6884 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7381 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 7081 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 7120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7375 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6936 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7376 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7191 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24766835500 # Total gap between requests +system.physmem.totGap 24414612500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166348 # Categorize read packet sizes +system.physmem.readPktSize::6 166317 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,14 +138,14 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4936 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see @@ -161,57 +161,57 @@ system.physmem.wrQLenPdf::19 4957 # Wh system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9402171924 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11754135924 # Sum of mem lat for all requests -system.physmem.totBusLat 665384000 # Total cycles spent in databus access -system.physmem.totBankLat 1686580000 # Total cycles spent in bank access -system.physmem.avgQLat 56521.78 # Average queueing delay per request -system.physmem.avgBankLat 10138.99 # Average bank access latency per request +system.physmem.totQLat 9394568799 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11745778799 # Sum of mem lat for all requests +system.physmem.totBusLat 665260000 # Total cycles spent in databus access +system.physmem.totBankLat 1685950000 # Total cycles spent in bank access +system.physmem.avgQLat 56486.60 # Average queueing delay per request +system.physmem.avgBankLat 10137.09 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70660.77 # Average memory access latency -system.physmem.avgRdBW 429.86 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 294.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 429.86 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 294.63 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 70623.69 # Average memory access latency +system.physmem.avgRdBW 435.98 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 298.88 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 435.98 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 298.88 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 4.53 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.47 # Average read queue length over time -system.physmem.avgWrQLen 9.66 # Average write queue length over time -system.physmem.readRowHits 152267 # Number of row buffer hits during reads -system.physmem.writeRowHits 40679 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.68 # Row buffer hit rate for writes -system.physmem.avgGap 88338.46 # Average gap between requests +system.physmem.busUtil 4.59 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.48 # Average read queue length over time +system.physmem.avgWrQLen 10.01 # Average write queue length over time +system.physmem.readRowHits 152275 # Number of row buffer hits during reads +system.physmem.writeRowHits 40821 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 35.80 # Row buffer hit rate for writes +system.physmem.avgGap 87091.78 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22524754 # DTB read hits -system.cpu.dtb.read_misses 221109 # DTB read misses -system.cpu.dtb.read_acv 49 # DTB read access violations -system.cpu.dtb.read_accesses 22745863 # DTB read accesses -system.cpu.dtb.write_hits 15800982 # DTB write hits -system.cpu.dtb.write_misses 41722 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15842704 # DTB write accesses -system.cpu.dtb.data_hits 38325736 # DTB hits -system.cpu.dtb.data_misses 262831 # DTB misses -system.cpu.dtb.data_acv 50 # DTB access violations -system.cpu.dtb.data_accesses 38588567 # DTB accesses -system.cpu.itb.fetch_hits 14187534 # ITB hits -system.cpu.itb.fetch_misses 37797 # ITB misses +system.cpu.dtb.read_hits 22403664 # DTB read hits +system.cpu.dtb.read_misses 220373 # DTB read misses +system.cpu.dtb.read_acv 50 # DTB read access violations +system.cpu.dtb.read_accesses 22624037 # DTB read accesses +system.cpu.dtb.write_hits 15711393 # DTB write hits +system.cpu.dtb.write_misses 41143 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15752536 # DTB write accesses +system.cpu.dtb.data_hits 38115057 # DTB hits +system.cpu.dtb.data_misses 261516 # DTB misses +system.cpu.dtb.data_acv 54 # DTB access violations +system.cpu.dtb.data_accesses 38376573 # DTB accesses +system.cpu.itb.fetch_hits 13911095 # ITB hits +system.cpu.itb.fetch_misses 34570 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14225331 # ITB accesses +system.cpu.itb.fetch_accesses 13945665 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49533742 # number of cpu cycles simulated +system.cpu.numCycles 48829295 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16746521 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10800034 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477053 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12193904 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7496910 # Number of BTB hits +system.cpu.BPredUnit.lookups 16536427 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10675204 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 418905 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11705282 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7341882 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 2006546 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45028 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 16102899 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106919359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16746521 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9503456 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19851092 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2196928 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6491501 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314458 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14187534 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 227935 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44359313 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.410302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.133631 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1987114 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 42052 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15791672 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105370615 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16536427 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9328996 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19544366 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2001802 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6569447 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 313140 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13911095 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 206120 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43680847 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.412284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.135635 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24508221 55.25% 55.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1552927 3.50% 58.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1407762 3.17% 61.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1534147 3.46% 65.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4200830 9.47% 74.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1874236 4.23% 79.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 688640 1.55% 80.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1098273 2.48% 83.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7494277 16.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24136481 55.26% 55.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1528556 3.50% 58.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1370450 3.14% 61.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1506920 3.45% 65.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4142263 9.48% 74.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1846581 4.23% 79.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 675220 1.55% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1067886 2.44% 83.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7406490 16.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44359313 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.338083 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.158516 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17202144 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6044851 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18844952 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 783382 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1483984 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3808507 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109388 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 105012446 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304839 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1483984 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17687031 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3815602 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84566 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19093119 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2195011 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103566225 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 486 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2675 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2071816 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62457346 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124882897 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124424416 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 458481 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43680847 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.338658 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.157938 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16869436 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6110909 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18556945 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 793975 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1349582 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3748874 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107098 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103640564 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305578 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1349582 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17328003 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3849727 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84405 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18840913 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2228217 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102377631 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2729 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2099672 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61646345 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123373260 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122920505 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 452755 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9910465 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5561 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5559 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4548155 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23430190 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16410014 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1178549 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 390985 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91582200 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5227 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89129103 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 121099 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11405338 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5024468 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44359313 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.009253 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109781 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9099464 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5534 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4609870 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23237420 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16278692 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1191956 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 452268 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90762555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5288 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88451556 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 99102 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10723978 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4670719 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 705 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43680847 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.024951 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.111086 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15871640 35.78% 35.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6995929 15.77% 51.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5623158 12.68% 64.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4788485 10.79% 75.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4723434 10.65% 85.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2673880 6.03% 91.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1944632 4.38% 96.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1314765 2.96% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 423390 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15440168 35.35% 35.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6886071 15.76% 51.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5612203 12.85% 63.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4740584 10.85% 74.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4695591 10.75% 85.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2649897 6.07% 91.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1923598 4.40% 96.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1315990 3.01% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 416745 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44359313 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43680847 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 127127 6.74% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 794266 42.09% 48.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 965741 51.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126167 6.80% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 781555 42.12% 48.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 947649 51.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49762830 55.83% 55.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43850 0.05% 55.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121597 0.14% 56.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121881 0.14% 56.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 60 0.00% 56.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38947 0.04% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23025644 25.83% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16014206 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49366923 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43857 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121501 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121281 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 51 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22854121 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15904789 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89129103 # Type of FU issued -system.cpu.iq.rate 1.799361 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1887134 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021173 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224014583 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102585406 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87044839 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611169 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 425269 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 296604 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90710574 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305663 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1465776 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88451556 # Type of FU issued +system.cpu.iq.rate 1.811444 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1855371 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020976 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221933846 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101092156 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86564383 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 604586 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 417604 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294342 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90004545 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 302382 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1470214 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3153552 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5566 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18132 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1796637 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2960782 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4826 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18180 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1665315 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2518 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 82425 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2876 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 81924 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1483984 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2836184 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 76819 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101124099 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 260669 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23430190 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16410014 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5227 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60088 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 531 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18132 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 252052 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 171036 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 423088 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88146777 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22749364 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 982326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1349582 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2855245 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 77128 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100251958 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 208716 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23237420 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16278692 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5288 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60129 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 488 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18180 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 198098 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161281 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 359379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87608240 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22627118 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 843316 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9536672 # number of nop insts executed -system.cpu.iew.exec_refs 38592395 # number of memory reference insts executed -system.cpu.iew.exec_branches 15153499 # Number of branches executed -system.cpu.iew.exec_stores 15843031 # Number of stores executed -system.cpu.iew.exec_rate 1.779530 # Inst execution rate -system.cpu.iew.wb_sent 87753741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87341443 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33435183 # num instructions producing a value -system.cpu.iew.wb_consumers 43872218 # num instructions consuming a value +system.cpu.iew.exec_nop 9484115 # number of nop insts executed +system.cpu.iew.exec_refs 38379967 # number of memory reference insts executed +system.cpu.iew.exec_branches 15086881 # Number of branches executed +system.cpu.iew.exec_stores 15752849 # Number of stores executed +system.cpu.iew.exec_rate 1.794174 # Inst execution rate +system.cpu.iew.wb_sent 87251382 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86858725 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33364118 # num instructions producing a value +system.cpu.iew.wb_consumers 43780682 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.763272 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762104 # average fanout of values written-back +system.cpu.iew.wb_rate 1.778824 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762074 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9751269 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8914358 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 370067 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42875329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.060408 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.788298 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 313984 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42331265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.086889 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.804714 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19913451 46.45% 46.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7068985 16.49% 62.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3438952 8.02% 70.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2090019 4.87% 75.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2085052 4.86% 80.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1168150 2.72% 83.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1107868 2.58% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727256 1.70% 87.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275596 12.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19478152 46.01% 46.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7019307 16.58% 62.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3402930 8.04% 70.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2062880 4.87% 75.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2059752 4.87% 80.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1161194 2.74% 83.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1088223 2.57% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718067 1.70% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5340760 12.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42875329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42331265 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,304 +475,192 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275596 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5340760 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 134374332 # The number of ROB reads -system.cpu.rob.rob_writes 197671452 # The number of ROB writes -system.cpu.timesIdled 69954 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5174429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132928193 # The number of ROB reads +system.cpu.rob.rob_writes 195862433 # The number of ROB writes +system.cpu.timesIdled 69428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5148448 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.622348 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.622348 # CPI: Total CPI of All Threads -system.cpu.ipc 1.606819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.606819 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116696990 # number of integer regfile reads -system.cpu.int_regfile_writes 57893587 # number of integer regfile writes -system.cpu.fp_regfile_reads 251486 # number of floating regfile reads -system.cpu.fp_regfile_writes 240711 # number of floating regfile writes -system.cpu.misc_regfile_reads 38028 # number of misc regfile reads +system.cpu.cpi 0.613497 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.613497 # CPI: Total CPI of All Threads +system.cpu.ipc 1.630000 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.630000 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115949669 # number of integer regfile reads +system.cpu.int_regfile_writes 57525330 # number of integer regfile writes +system.cpu.fp_regfile_reads 249508 # number of floating regfile reads +system.cpu.fp_regfile_writes 240213 # number of floating regfile writes +system.cpu.misc_regfile_reads 38023 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 92300 # number of replacements -system.cpu.icache.tagsinuse 1931.186939 # Cycle average of tags in use -system.cpu.icache.total_refs 14080520 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 94348 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 149.240259 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20259707000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1931.186939 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942962 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942962 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14080520 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14080520 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14080520 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14080520 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14080520 # number of overall hits -system.cpu.icache.overall_hits::total 14080520 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 107014 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 107014 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 107014 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 107014 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 107014 # number of overall misses -system.cpu.icache.overall_misses::total 107014 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1801616999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1801616999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1801616999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1801616999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1801616999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1801616999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14187534 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14187534 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14187534 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14187534 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14187534 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14187534 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007543 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007543 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007543 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007543 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007543 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007543 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16835.339292 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16835.339292 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16835.339292 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16835.339292 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16835.339292 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16835.339292 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 434 # number of cycles access was blocked +system.cpu.icache.replacements 91621 # number of replacements +system.cpu.icache.tagsinuse 1930.572235 # Cycle average of tags in use +system.cpu.icache.total_refs 13805106 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93669 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.381802 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19945764000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1930.572235 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942662 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942662 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13805106 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13805106 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13805106 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13805106 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13805106 # number of overall hits +system.cpu.icache.overall_hits::total 13805106 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105989 # number of overall misses +system.cpu.icache.overall_misses::total 105989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1780097998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1780097998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1780097998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1780097998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1780097998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1780097998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13911095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13911095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13911095 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13911095 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13911095 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13911095 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007619 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007619 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007619 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007619 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007619 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007619 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16795.120229 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16795.120229 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16795.120229 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16795.120229 # average overall miss latency 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system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12665 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12665 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12665 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12665 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12665 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12665 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94349 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 94349 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 94349 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 94349 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 94349 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 94349 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1400064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1400064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1400064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1400064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1400064000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1400064000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006650 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006650 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006650 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14839.203383 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14839.203383 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14839.203383 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14839.203383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14839.203383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14839.203383 # average overall mshr miss latency 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were no-allocate -system.cpu.dcache.replacements 201586 # number of replacements -system.cpu.dcache.tagsinuse 4077.128651 # Cycle average of tags in use -system.cpu.dcache.total_refs 34331018 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205682 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.913089 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 177489000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4077.128651 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995393 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995393 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20756846 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20756846 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574115 # number of WriteReq hits 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-system.cpu.dcache.WriteReq_avg_miss_latency::total 89960.249290 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81073.396351 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81073.396351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81073.396351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81073.396351 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5474703 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 114 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112304 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.748958 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 114 # average number 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WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14654502991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16679620991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16679620991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16679620991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16679620991 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81094.218215 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81094.218215 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 132442 # number of replacements -system.cpu.l2cache.tagsinuse 30854.003971 # Cycle average of tags in use -system.cpu.l2cache.total_refs 160847 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 164507 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.977752 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 132407 # number of replacements +system.cpu.l2cache.tagsinuse 30853.775951 # Cycle average of tags in use +system.cpu.l2cache.total_refs 160055 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 164479 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.973103 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26667.895606 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2125.543689 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 2060.564676 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.813840 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.064866 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.062883 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941589 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 86668 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34393 # number of ReadReq hits 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ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35547 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130802 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130802 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7681 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158668 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166349 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7681 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158668 # number of overall misses -system.cpu.l2cache.overall_misses::total 166349 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 438125500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1616867500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2054993000 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35511874 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35511874 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35511874 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35511874 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012778 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012778 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071124 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071124 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036788 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036788 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036788 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036788 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46623.730083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46623.730083 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89897.727779 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89897.727779 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81052.032542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81052.032542 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5486905 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112436 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.800251 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168957 # number of writebacks +system.cpu.dcache.writebacks::total 168957 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204872 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204872 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895935 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895935 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100807 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100807 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100807 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100807 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62173 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62173 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143430 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143430 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205603 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205603 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205603 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205603 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2029919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2029919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14640535990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14640535990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16670455490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16670455490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16670455490 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16670455490 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005790 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005790 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32649.534364 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32649.534364 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102074.433452 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102074.433452 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index b2095b317..889e8b1f0 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 726190563..dc0676551 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:57:39 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 20:20:38 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24260940500 because target called exit() +Exiting @ tick 26292466000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index bbe40238a..69c62381b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026781 # Number of seconds simulated -sim_ticks 26780535000 # Number of ticks simulated -final_tick 26780535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026292 # Number of seconds simulated +sim_ticks 26292466000 # Number of ticks simulated +final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149394 # Simulator instruction rate (inst/s) -host_op_rate 211994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56410244 # Simulator tick rate (ticks/s) -host_mem_usage 261852 # Number of bytes of host memory used -host_seconds 474.75 # Real time elapsed on the host -sim_insts 70924159 # Number of instructions simulated -sim_ops 100643406 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 300160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7944448 # Number of bytes read from this memory -system.physmem.bytes_read::total 8244608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 300160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 300160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372672 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372672 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4690 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124132 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128822 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83948 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83948 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11208141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296650086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307858226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11208141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11208141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200618546 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200618546 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200618546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11208141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296650086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 508476772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128823 # Total number of read requests seen -system.physmem.writeReqs 83948 # Total number of write requests seen -system.physmem.cpureqs 213079 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8244608 # Total number of bytes read from memory -system.physmem.bytesWritten 5372672 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8244608 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372672 # bytesWritten derated as per pkt->getSize() +host_inst_rate 115195 # Simulator instruction rate (inst/s) +host_op_rate 163465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42703788 # Simulator tick rate (ticks/s) +host_mem_usage 260928 # Number of bytes of host memory used +host_seconds 615.69 # Real time elapsed on the host +sim_insts 70925094 # Number of instructions simulated +sim_ops 100644341 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83943 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11350476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302110574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 313461050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11350476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11350476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 204330472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 204330472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 204330472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11350476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302110574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 517791522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128777 # Total number of read requests seen +system.physmem.writeReqs 83943 # Total number of write requests seen +system.physmem.cpureqs 213018 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8241664 # Total number of bytes read from memory +system.physmem.bytesWritten 5372352 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372352 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 308 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8046 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 298 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8167 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8037 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7891 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 7896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7927 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8032 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7950 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7992 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8024 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8177 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8153 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8060 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8008 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7981 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5174 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 7983 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5171 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5234 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5166 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5164 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5232 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5126 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5372 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26780515500 # Total gap between requests +system.physmem.totGap 26292446500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128823 # Categorize read packet sizes +system.physmem.readPktSize::6 128777 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 83948 # categorize write packet sizes +system.physmem.writePktSize::6 83943 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,14 +102,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 308 # categorize neither packet sizes +system.physmem.neitherpktsize::6 298 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 71083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,11 +138,11 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -154,44 +154,44 @@ system.physmem.wrQLenPdf::12 3650 # Wh system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4847041699 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6735959699 # Sum of mem lat for all requests -system.physmem.totBusLat 515280000 # Total cycles spent in databus access -system.physmem.totBankLat 1373638000 # Total cycles spent in bank access -system.physmem.avgQLat 37626.47 # Average queueing delay per request -system.physmem.avgBankLat 10663.24 # Average bank access latency per request +system.physmem.totQLat 4868161034 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6756433034 # Sum of mem lat for all requests +system.physmem.totBusLat 515096000 # Total cycles spent in databus access +system.physmem.totBankLat 1373176000 # Total cycles spent in bank access +system.physmem.avgQLat 37803.91 # Average queueing delay per request +system.physmem.avgBankLat 10663.46 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52289.70 # Average memory access latency -system.physmem.avgRdBW 307.86 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 200.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 307.86 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 200.62 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52467.37 # Average memory access latency +system.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 204.33 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.18 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.25 # Average read queue length over time -system.physmem.avgWrQLen 9.64 # Average write queue length over time -system.physmem.readRowHits 118946 # Number of row buffer hits during reads -system.physmem.writeRowHits 27105 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.29 # Row buffer hit rate for writes -system.physmem.avgGap 125865.44 # Average gap between requests +system.physmem.busUtil 3.24 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.26 # Average read queue length over time +system.physmem.avgWrQLen 9.45 # Average write queue length over time +system.physmem.readRowHits 118938 # Number of row buffer hits during reads +system.physmem.writeRowHits 27082 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.26 # Row buffer hit rate for writes +system.physmem.avgGap 123601.20 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,581 +235,455 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53561071 # number of cpu cycles simulated +system.cpu.numCycles 52584933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16989438 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12991194 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 680202 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11755292 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8009849 # Number of BTB hits +system.cpu.BPredUnit.lookups 16605622 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12744819 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 601134 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10608037 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7769778 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1851785 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114363 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12914479 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87008149 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16989438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9861634 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21655288 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2666634 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10515039 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 571 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11971869 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 198806 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47045662 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.589318 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.332778 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12549160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10606958 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11672224 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 180779 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46048900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.587178 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25412140 54.02% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2169507 4.61% 58.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2024864 4.30% 62.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2094897 4.45% 67.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1497374 3.18% 70.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1417625 3.01% 73.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 986770 2.10% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1225872 2.61% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10216613 21.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24897026 54.07% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1463280 3.18% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1379331 3.00% 73.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 959670 2.08% 75.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1190775 2.59% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10011040 21.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47045662 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317198 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.624466 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15025286 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8880734 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19918391 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1367786 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1853465 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3434521 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108932 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119105730 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 372945 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1853465 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16780714 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2530019 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 932679 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19483180 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5465605 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116933277 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14375 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4623545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 215 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117254635 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 538431443 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 538426294 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5149 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18095515 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25625 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25611 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12984960 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29963650 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22702028 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3806099 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4346835 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113028204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41641 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108286515 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 316116 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12256138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28707838 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4549 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47045662 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.301732 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.993875 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 46048900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8956467 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19461806 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3326611 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104659 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116720432 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 360894 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 926852 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19086495 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114852318 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115176508 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529186359 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529181674 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 16015892 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 24809 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29582757 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22430841 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3912004 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4391398 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111440700 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41006 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107204361 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269260 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46048900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11469393 24.38% 24.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8159881 17.34% 41.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7486298 15.91% 57.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7193710 15.29% 72.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5478307 11.64% 84.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3936871 8.37% 92.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1856294 3.95% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881703 1.87% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 583205 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10795987 23.44% 23.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5412181 11.75% 84.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3900032 8.47% 92.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1833850 3.98% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 869462 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 573509 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47045662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46048900 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112009 4.47% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1372514 54.80% 59.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1019865 40.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1351687 54.87% 59.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1001007 40.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57275495 52.89% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91732 0.08% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 181 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29138143 26.91% 79.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21780957 20.11% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56616683 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91709 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 161 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28875176 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21620625 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108286515 # Type of FU issued -system.cpu.iq.rate 2.021739 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2504390 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023127 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 266438684 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125354112 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106381358 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110790645 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2168801 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107204361 # Type of FU issued +system.cpu.iq.rate 2.038690 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263189734 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 696 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109667441 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2181528 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2653236 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7465 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30261 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2142984 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2272156 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6578 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29396 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1871610 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 473 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 28 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 493 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1853465 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1042007 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 44975 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113079657 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 348290 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29963650 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22702028 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25073 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6129 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5511 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30261 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 453510 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 204690 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 658200 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107104018 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28789803 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1182497 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1617500 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 290951 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6480 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5483 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29396 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 390184 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 182395 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 572579 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106179962 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28578383 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1024399 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9812 # number of nop insts executed -system.cpu.iew.exec_refs 50259028 # number of memory reference insts executed -system.cpu.iew.exec_branches 14733119 # Number of branches executed -system.cpu.iew.exec_stores 21469225 # Number of stores executed -system.cpu.iew.exec_rate 1.999662 # Inst execution rate -system.cpu.iew.wb_sent 106622925 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106381514 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53628948 # num instructions producing a value -system.cpu.iew.wb_consumers 104196549 # num instructions consuming a value +system.cpu.iew.exec_nop 9804 # number of nop insts executed +system.cpu.iew.exec_refs 49916161 # number of memory reference insts executed +system.cpu.iew.exec_branches 14598129 # Number of branches executed +system.cpu.iew.exec_stores 21337778 # Number of stores executed +system.cpu.iew.exec_rate 2.019209 # Inst execution rate +system.cpu.iew.wb_sent 105751543 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105534073 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53248858 # num instructions producing a value +system.cpu.iew.wb_consumers 103476528 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.986172 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514690 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006926 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514598 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12431579 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 573556 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45192198 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.227131 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.747743 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44431401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15976760 35.35% 35.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11724717 25.94% 61.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3516948 7.78% 69.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2892652 6.40% 75.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1888504 4.18% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1974510 4.37% 84.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692586 1.53% 85.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 573861 1.27% 86.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5951660 13.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15343377 34.53% 34.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1877627 4.23% 79.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1953879 4.40% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 688656 1.55% 85.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 567495 1.28% 86.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6007585 13.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45192198 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929711 # Number of instructions committed -system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 44431401 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70930646 # Number of instructions committed +system.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869458 # Number of memory references committed -system.cpu.commit.loads 27310414 # Number of loads committed +system.cpu.commit.refs 47869832 # Number of memory references committed +system.cpu.commit.loads 27310601 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13744811 # Number of branches committed +system.cpu.commit.branches 13744998 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486751 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5951660 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 152295776 # The number of ROB reads -system.cpu.rob.rob_writes 228025366 # The number of ROB writes -system.cpu.timesIdled 74466 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6515409 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924159 # Number of Instructions Simulated -system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated -system.cpu.cpi 0.755188 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.755188 # CPI: Total CPI of All Threads -system.cpu.ipc 1.324174 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.324174 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 515451838 # number of integer regfile reads -system.cpu.int_regfile_writes 104231541 # number of integer regfile writes -system.cpu.fp_regfile_reads 698 # number of floating regfile reads -system.cpu.fp_regfile_writes 610 # number of floating regfile writes -system.cpu.misc_regfile_reads 145512549 # number of misc regfile reads -system.cpu.misc_regfile_writes 38452 # number of misc regfile writes -system.cpu.icache.replacements 31300 # number of replacements -system.cpu.icache.tagsinuse 1822.220766 # Cycle average of tags in use -system.cpu.icache.total_refs 11934433 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 33335 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 358.015089 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 149890854 # The number of ROB reads +system.cpu.rob.rob_writes 224611140 # The number of ROB writes +system.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6536033 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70925094 # Number of Instructions Simulated +system.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70925094 # Number of Instructions Simulated +system.cpu.cpi 0.741415 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.741415 # CPI: Total CPI of All Threads +system.cpu.ipc 1.348772 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.348772 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511431338 # number of integer regfile reads +system.cpu.int_regfile_writes 103318196 # number of integer regfile writes +system.cpu.fp_regfile_reads 686 # number of floating regfile reads +system.cpu.fp_regfile_writes 582 # number of floating regfile writes +system.cpu.misc_regfile_reads 143076838 # number of misc regfile reads +system.cpu.misc_regfile_writes 38826 # number of misc regfile writes +system.cpu.icache.replacements 30543 # number of replacements +system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use +system.cpu.icache.total_refs 11635566 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1822.220766 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.889756 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.889756 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11934443 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11934443 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11934443 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11934443 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11934443 # number of overall hits -system.cpu.icache.overall_hits::total 11934443 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 37425 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 37425 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 37425 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 37425 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 37425 # number of overall misses -system.cpu.icache.overall_misses::total 37425 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 718344999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 718344999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 718344999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 718344999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 718344999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 718344999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11971868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11971868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11971868 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11971868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11971868 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11971868 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003126 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003126 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003126 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003126 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003126 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003126 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19194.255150 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19194.255150 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19194.255150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19194.255150 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1820.333452 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11635567 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11635567 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits +system.cpu.icache.overall_hits::total 11635567 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 36657 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 36657 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 36657 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 36657 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 36657 # number of overall misses +system.cpu.icache.overall_misses::total 36657 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 709011999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 709011999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 709011999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 709011999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 709011999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 709011999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11672224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11672224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11672224 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11672224 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11672224 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11672224 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003141 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003141 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003141 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003141 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003141 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003141 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19341.790081 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19341.790081 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19341.790081 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19341.790081 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.157895 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33651 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 33651 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 33651 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 33651 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 33651 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 33651 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 589350499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 589350499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 589350499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 589350499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 589350499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 589350499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002811 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002811 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002811 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17513.610264 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17513.610264 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32884 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32884 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32884 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32884 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32884 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32884 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580604499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 580604499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580604499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 580604499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580604499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 580604499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002817 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002817 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.139734 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.139734 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158507 # number of replacements -system.cpu.dcache.tagsinuse 4072.917720 # Cycle average of tags in use -system.cpu.dcache.total_refs 44563863 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162603 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.065442 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 285154000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.917720 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994365 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994365 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26258448 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26258448 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18265067 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18265067 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20455 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20455 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44523515 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44523515 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44523515 # number of overall hits -system.cpu.dcache.overall_hits::total 44523515 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125393 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125393 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1584834 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1584834 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1710227 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1710227 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1710227 # number of overall misses -system.cpu.dcache.overall_misses::total 1710227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4597179000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4597179000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 120104513482 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 120104513482 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 949000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 949000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 124701692482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 124701692482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 124701692482 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 124701692482 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26383841 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26383841 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20499 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20499 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46233742 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46233742 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46233742 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46233742 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036991 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036991 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036991 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036991 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36662.166150 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36662.166150 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75783.655248 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75783.655248 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21568.181818 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21568.181818 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72915.286966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72915.286966 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2506 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 608 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.418803 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129149 # number of writebacks -system.cpu.dcache.writebacks::total 129149 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69778 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69778 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477521 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1477521 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1547299 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1547299 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1547299 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1547299 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55615 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55615 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107313 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107313 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162928 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162928 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162928 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162928 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2039094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2039094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257233993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257233993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10296327993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10296327993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10296327993 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10296327993 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002108 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002108 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003524 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003524 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003524 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003524 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36664.461027 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36664.461027 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76945.328087 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76945.328087 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63195.571007 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63195.571007 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63195.571007 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63195.571007 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 95689 # number of replacements -system.cpu.l2cache.tagsinuse 30139.737825 # Cycle average of tags in use -system.cpu.l2cache.total_refs 90978 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 126809 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.717441 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 95650 # number of replacements +system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use +system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.709468 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26886.974949 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1383.020531 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1869.742346 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.820525 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.042206 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.057060 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.919792 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 28461 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33637 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 62098 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129149 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129149 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 17 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4769 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4769 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 28461 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 38406 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 66867 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 28461 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 38406 # number of overall hits -system.cpu.l2cache.overall_hits::total 66867 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4707 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21944 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26651 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102253 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102253 # number of ReadExReq misses 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-system.cpu.l2cache.ReadReq_accesses::total 88749 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 129149 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 129149 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 325 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 325 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107022 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107022 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 33168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 162603 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 195771 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 33168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 162603 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 195771 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.141914 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.394811 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.300296 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947692 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947692 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955439 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955439 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141914 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.763805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.658443 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141914 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.763805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.658443 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57405.991077 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74807.441670 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71734.062512 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 147.727273 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 147.727273 # average UpgradeReq miss latency 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(read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks +system.cpu.dcache.writebacks::total 129052 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 38e3365ee..8009459e0 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 1e72565e9..43339a0ee 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:10:01 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:40:49 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 996061088500 because target called exit() +Exiting @ tick 985089830500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 9335161f5..7470c11aa 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.987579 # Number of seconds simulated -sim_ticks 987579062500 # Number of ticks simulated -final_tick 987579062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.985090 # Number of seconds simulated +sim_ticks 985089830500 # Number of ticks simulated +final_tick 985089830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79028 # Simulator instruction rate (inst/s) -host_op_rate 79028 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42888030 # Simulator tick rate (ticks/s) -host_mem_usage 458304 # Number of bytes of host memory used -host_seconds 23026.92 # Real time elapsed on the host +host_inst_rate 109003 # Simulator instruction rate (inst/s) +host_op_rate 109003 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59005665 # Simulator tick rate (ticks/s) +host_mem_usage 485696 # Number of bytes of host memory used +host_seconds 16694.83 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125364928 # Number of bytes read from this memory -system.physmem.bytes_read::total 125419904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125364992 # Number of bytes read from this memory +system.physmem.bytes_read::total 125419968 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958827 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959686 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1958828 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959687 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 126941662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 126997330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55667 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55667 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 65974991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 65974991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 65974991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 126941662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 192972321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959686 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 55808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 127262497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 127318306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 66141704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 66141704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 66141704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 127262497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193460010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959687 # Total number of read requests seen system.physmem.writeReqs 1018055 # Total number of write requests seen -system.physmem.cpureqs 2977741 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125419904 # Total number of bytes read from memory +system.physmem.cpureqs 2977742 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125419968 # Total number of bytes read from memory system.physmem.bytesWritten 65155520 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125419904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 125419968 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 577 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122432 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 122431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123239 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 122601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 122602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122222 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 122611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 122610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120102 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123178 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123177 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63438 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis @@ -69,7 +69,7 @@ system.physmem.perBankWrReqs::6 63395 # Tr system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63960 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 65307 # Tr system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 987579010500 # Total gap between requests +system.physmem.totGap 985089778500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959686 # Categorize read packet sizes +system.physmem.readPktSize::6 1959687 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1651837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1651728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 82029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32933 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,9 +138,9 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44249 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see @@ -161,9 +161,9 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 19599583947 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85189869947 # Sum of mem lat for all requests -system.physmem.totBusLat 7836436000 # Total cycles spent in databus access -system.physmem.totBankLat 57753850000 # Total cycles spent in bank access -system.physmem.avgQLat 10004.34 # Average queueing delay per request -system.physmem.avgBankLat 29479.65 # Average bank access latency per request +system.physmem.totQLat 19640844571 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85229742571 # Sum of mem lat for all requests +system.physmem.totBusLat 7836420000 # Total cycles spent in databus access +system.physmem.totBankLat 57752478000 # Total cycles spent in bank access +system.physmem.avgQLat 10025.42 # Average queueing delay per request +system.physmem.avgBankLat 29479.01 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43483.99 # Average memory access latency -system.physmem.avgRdBW 127.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 65.97 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 127.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 65.97 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43504.43 # Average memory access latency +system.physmem.avgRdBW 127.32 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 66.14 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 127.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 66.14 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 1.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.09 # Average read queue length over time system.physmem.avgWrQLen 10.28 # Average write queue length over time -system.physmem.readRowHits 834542 # Number of row buffer hits during reads -system.physmem.writeRowHits 194109 # Number of row buffer hits during writes +system.physmem.readRowHits 834572 # Number of row buffer hits during reads +system.physmem.writeRowHits 194113 # Number of row buffer hits during writes system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes -system.physmem.avgGap 331653.76 # Average gap between requests +system.physmem.avgGap 330817.71 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444784364 # DTB read hits +system.cpu.dtb.read_hits 444784566 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449681442 # DTB read accesses -system.cpu.dtb.write_hits 160833165 # DTB write hits +system.cpu.dtb.read_accesses 449681644 # DTB read accesses +system.cpu.dtb.write_hits 160833172 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534469 # DTB write accesses -system.cpu.dtb.data_hits 605617529 # DTB hits +system.cpu.dtb.write_accesses 162534476 # DTB write accesses +system.cpu.dtb.data_hits 605617738 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612215911 # DTB accesses -system.cpu.itb.fetch_hits 232120860 # ITB hits +system.cpu.dtb.data_accesses 612216120 # DTB accesses +system.cpu.itb.fetch_hits 231916745 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232120882 # ITB accesses +system.cpu.itb.fetch_accesses 231916767 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1975158126 # number of cpu cycles simulated +system.cpu.numCycles 1970179662 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328916009 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253846257 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140045817 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232481413 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138136467 # Number of BTB hits +system.cpu.branch_predictor.lookups 326556831 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 252596788 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 138232865 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 218937552 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 135479530 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.418284 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175138589 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153777420 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669811898 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 61.880444 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 172296521 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154260310 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667620352 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3046014515 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043822969 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 650984890 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617988746 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121313944 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12133415 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133447359 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81752917 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.010775 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139622793 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651716748 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617888959 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120522099 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11112308 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131634407 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83565858 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.168329 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139351244 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746581569 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1741570972 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7474420 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 398305853 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576852273 # Number of cycles cpu stages are processed. -system.cpu.activity 79.834230 # Percentage of cycles cpu is active +system.cpu.timesIdled 7474606 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 398498363 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571681299 # Number of cycles cpu stages are processed. +system.cpu.activity 79.773501 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -272,72 +272,72 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.085383 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.082647 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.085383 # CPI: Total CPI of All Threads -system.cpu.ipc 0.921334 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.082647 # CPI: Total CPI of All Threads +system.cpu.ipc 0.923662 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.921334 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 784384186 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190773940 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.287525 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1042820423 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932337703 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 47.203193 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1001198544 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973959582 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.310461 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1565492748 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409665378 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.740890 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 952315389 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022842737 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.785360 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.923662 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 783567133 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186612529 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.228646 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1036391021 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933788641 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 47.396116 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 997796043 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972383619 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.355073 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1560555740 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409623922 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.791196 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 948846788 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021332874 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.839581 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.497042 # Cycle average of tags in use -system.cpu.icache.total_refs 232119756 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 667.601881 # Cycle average of tags in use +system.cpu.icache.total_refs 231915637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270220.903376 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 269983.279395 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.497042 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325926 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325926 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232119756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232119756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232119756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232119756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232119756 # number of overall hits -system.cpu.icache.overall_hits::total 232119756 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1104 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1104 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1104 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1104 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1104 # number of overall misses -system.cpu.icache.overall_misses::total 1104 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58767000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58767000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58767000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58767000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58767000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58767000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232120860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232120860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232120860 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232120860 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232120860 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232120860 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 667.601881 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325977 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325977 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231915637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231915637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231915637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231915637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231915637 # number of overall hits +system.cpu.icache.overall_hits::total 231915637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses +system.cpu.icache.overall_misses::total 1108 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59929000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59929000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59929000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59929000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59929000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59929000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231916745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231916745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231916745 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231916745 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231916745 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231916745 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53230.978261 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53230.978261 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53230.978261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53230.978261 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54087.545126 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54087.545126 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency 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accesses -system.cpu.l2cache.demand_accesses::total 9112332 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111474 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112333 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111473 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112332 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111474 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112333 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses @@ -554,17 +446,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215059 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53701.979045 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64721.293112 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 64713.260466 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70143.270284 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70143.270284 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66878.120015 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66878.120015 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54074.505239 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64728.331374 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 64720.565160 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70184.095400 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70184.095400 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66898.787664 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66898.787664 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -576,27 +468,27 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks 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overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses @@ -608,17 +500,125 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41052.875437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51965.326261 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51957.371514 # average ReadReq mshr miss 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+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211991227000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211991227000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211991227000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211991227000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19940.512398 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19940.512398 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35981.075018 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35981.075018 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 2f4837fe9..fb395fc71 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 3e5b31249..78436c89b 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:10:10 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:41:35 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 621254733000 because target called exit() +Exiting @ tick 655919824500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 4dfb5e529..c867780d0 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.676099 # Number of seconds simulated -sim_ticks 676099363500 # Number of ticks simulated -final_tick 676099363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.655920 # Number of seconds simulated +sim_ticks 655919824500 # Number of ticks simulated +final_tick 655919824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178127 # Simulator instruction rate (inst/s) -host_op_rate 178127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69371375 # Simulator tick rate (ticks/s) -host_mem_usage 459324 # Number of bytes of host memory used -host_seconds 9746.09 # Real time elapsed on the host +host_inst_rate 137989 # Simulator instruction rate (inst/s) +host_op_rate 137989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52135439 # Simulator tick rate (ticks/s) +host_mem_usage 496344 # Number of bytes of host memory used +host_seconds 12581.07 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125805120 # Number of bytes read from this memory -system.physmem.bytes_read::total 125866688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265216 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965705 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966667 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019769 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019769 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 91064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 186074898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 186165961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96531989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96531989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96531989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 186074898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 282697950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966667 # Total number of read requests seen -system.physmem.writeReqs 1019769 # Total number of write requests seen -system.physmem.cpureqs 2986436 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125866688 # Total number of bytes read from memory -system.physmem.bytesWritten 65265216 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125866688 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65265216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 625 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125796416 # Number of bytes read from this memory +system.physmem.bytes_read::total 125857920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65262592 # Number of bytes written to this memory +system.physmem.bytes_written::total 65262592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965569 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966530 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019728 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019728 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 191786269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 191880037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 99497819 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 99497819 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 99497819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 191786269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 291377856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966530 # Total number of read requests seen +system.physmem.writeReqs 1019728 # Total number of write requests seen +system.physmem.cpureqs 2986258 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125857920 # Total number of bytes read from memory +system.physmem.bytesWritten 65262592 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125857920 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65262592 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 571 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 123034 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 123227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 121682 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123042 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122572 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 124906 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 123907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121965 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 123012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 120832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 122358 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 124956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123644 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63494 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63931 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63515 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 63255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62796 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63501 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63537 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 62612 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63480 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 64069 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 63419 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64815 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 123004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123537 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 123239 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 121669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 124908 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 123890 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122835 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 123027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 120849 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 122324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 124974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123664 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63268 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63478 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63945 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63503 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 63256 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63505 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63532 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 62611 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63461 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 64078 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 63409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64056 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64812 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 65441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64562 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64564 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 676099295000 # Total gap between requests +system.physmem.totGap 655919756000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966667 # Categorize read packet sizes +system.physmem.readPktSize::6 1966530 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1019769 # categorize write packet sizes +system.physmem.writePktSize::6 1019728 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,13 +105,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1634338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 235140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 26277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1634092 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 26268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44312 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 20663639504 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85829737504 # Sum of mem lat for all requests -system.physmem.totBusLat 7864168000 # Total cycles spent in databus access -system.physmem.totBankLat 57301930000 # Total cycles spent in bank access -system.physmem.avgQLat 10510.27 # Average queueing delay per request -system.physmem.avgBankLat 29145.83 # Average bank access latency per request +system.physmem.totQLat 20705208242 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85868216242 # Sum of mem lat for all requests +system.physmem.totBusLat 7863836000 # Total cycles spent in databus access +system.physmem.totBankLat 57299172000 # Total cycles spent in bank access +system.physmem.avgQLat 10531.86 # Average queueing delay per request +system.physmem.avgBankLat 29145.66 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43656.11 # Average memory access latency -system.physmem.avgRdBW 186.17 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 96.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 186.17 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 96.53 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43677.52 # Average memory access latency +system.physmem.avgRdBW 191.88 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 99.50 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 191.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 99.50 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.77 # Data bus utilization in percentage +system.physmem.busUtil 1.82 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 11.69 # Average write queue length over time -system.physmem.readRowHits 840809 # Number of row buffer hits during reads -system.physmem.writeRowHits 193935 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.55 # Average write queue length over time +system.physmem.readRowHits 840760 # Number of row buffer hits during reads +system.physmem.writeRowHits 193886 # Number of row buffer hits during writes system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 19.02 # Row buffer hit rate for writes -system.physmem.avgGap 226390.02 # Average gap between requests +system.physmem.writeRowHitRate 19.01 # Row buffer hit rate for writes +system.physmem.avgGap 219646.04 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 623300287 # DTB read hits -system.cpu.dtb.read_misses 11248161 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 634548448 # DTB read accesses -system.cpu.dtb.write_hits 212126260 # DTB write hits -system.cpu.dtb.write_misses 7156273 # DTB write misses +system.cpu.dtb.read_hits 613741491 # DTB read hits +system.cpu.dtb.read_misses 11247891 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 624989382 # DTB read accesses +system.cpu.dtb.write_hits 212247245 # DTB write hits +system.cpu.dtb.write_misses 7144332 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219282533 # DTB write accesses -system.cpu.dtb.data_hits 835426547 # DTB hits -system.cpu.dtb.data_misses 18404434 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 853830981 # DTB accesses -system.cpu.itb.fetch_hits 409165317 # ITB hits -system.cpu.itb.fetch_misses 53 # ITB misses +system.cpu.dtb.write_accesses 219391577 # DTB write accesses +system.cpu.dtb.data_hits 825988736 # DTB hits +system.cpu.dtb.data_misses 18392223 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 844380959 # DTB accesses +system.cpu.itb.fetch_hits 390708850 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 409165370 # ITB accesses +system.cpu.itb.fetch_accesses 390708888 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1352198728 # number of cpu cycles simulated +system.cpu.numCycles 1311839650 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 392126599 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 302845458 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19199722 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 274650283 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 270818962 # Number of BTB hits +system.cpu.BPredUnit.lookups 381024003 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 296029232 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16079219 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 261934224 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 259237388 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25776268 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6145 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421462775 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3238747115 # Number of instructions fetch has processed -system.cpu.fetch.Branches 392126599 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 296595230 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 591261083 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 148936596 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 163448952 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1316 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 409165317 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10196267 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1298229870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494741 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.143526 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 24703724 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3041 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 402148068 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3157560086 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381024003 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 283941112 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 573880213 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140086808 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 165153102 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390708850 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8061624 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1257505437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.510971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156516 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 706968787 54.46% 54.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44358932 3.42% 57.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22743833 1.75% 59.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 41944085 3.23% 62.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 132056857 10.17% 73.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 64435006 4.96% 77.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41239075 3.18% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30635006 2.36% 83.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 213848289 16.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 683625224 54.36% 54.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42619367 3.39% 57.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21744894 1.73% 59.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39684878 3.16% 62.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129121337 10.27% 72.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61516601 4.89% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38545793 3.07% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28125558 2.24% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212521785 16.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1298229870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289992 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.395171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 455239490 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 145264666 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 557656082 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18015537 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 122054095 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 61382914 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1012 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3154733525 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2110 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 122054095 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 478678718 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 92924622 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7988 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 549590922 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54973525 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3070816575 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 560752 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1743859 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 49056518 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2295520192 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3973370931 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3971968228 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1402703 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1257505437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.290450 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.406971 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433733980 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 146719588 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542274905 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18455051 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116321913 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58305735 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 954 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3085307728 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2035 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116321913 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456557347 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 93252503 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5104 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535232007 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56136563 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3003562340 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 560555 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1735251 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50037437 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2245657329 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3895152131 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3893909248 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1242883 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 919317229 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 211 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 118384405 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 691487195 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 258255800 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68719353 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37210437 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2756294295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 187 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2536632821 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3950694 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1007358741 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 432150244 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 158 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1298229870 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.953917 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.961710 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 869454366 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 190 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 189 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 120669951 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679225578 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255273844 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68130212 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37368209 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2722510883 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 144 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508555980 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3078936 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 977267031 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 413974741 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 115 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1257505437 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.994867 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.973352 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 442263739 34.07% 34.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 208903385 16.09% 50.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 191557841 14.76% 64.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 152463661 11.74% 76.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 137672348 10.60% 87.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81203098 6.25% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 63863451 4.92% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15081593 1.16% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5220754 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 417762073 33.22% 33.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201459942 16.02% 49.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185268981 14.73% 63.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153261704 12.19% 76.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133079768 10.58% 86.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81048988 6.45% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65262511 5.19% 98.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15257874 1.21% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5103596 0.41% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1298229870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1257505437 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2156518 11.37% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12254343 64.62% 76.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4551680 24.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2150864 11.67% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11870466 64.42% 76.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4405017 23.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1658475044 65.38% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 273 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 652209568 25.71% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 225947593 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643219876 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 253 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 26 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641326950 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224008572 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2536632821 # Type of FU issued -system.cpu.iq.rate 1.875932 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18962541 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007475 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6392425036 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3762406457 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2431792022 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1983711 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1351957 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 870252 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2554620629 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 974733 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62690136 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508555980 # Type of FU issued +system.cpu.iq.rate 1.912243 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18426347 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007345 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6294223850 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3698666551 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412312770 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1898830 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217307 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 851008 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526043830 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938497 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62613731 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 246891532 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263108 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 106999 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 97527298 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234629915 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 264851 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107543 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94545342 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 177 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1449625 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 100 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1452143 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 122054095 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 42236040 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1169448 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2901607263 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 18449890 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 691487195 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 258255800 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 187 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 295034 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19978 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 106999 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13433299 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8961049 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22394348 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2485079596 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 634549945 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 51553225 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116321913 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 41870148 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1143259 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2864507060 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8845706 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679225578 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255273844 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 144 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 295805 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17199 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107543 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10354551 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8556122 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18910673 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461271813 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 624989902 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47284167 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 145312781 # number of nop insts executed -system.cpu.iew.exec_refs 853832523 # number of memory reference insts executed -system.cpu.iew.exec_branches 304694140 # Number of branches executed -system.cpu.iew.exec_stores 219282578 # Number of stores executed -system.cpu.iew.exec_rate 1.837806 # Inst execution rate -system.cpu.iew.wb_sent 2461943508 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2432662274 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1394848463 # num instructions producing a value -system.cpu.iew.wb_consumers 1766930878 # num instructions consuming a value +system.cpu.iew.exec_nop 141996033 # number of nop insts executed +system.cpu.iew.exec_refs 844381512 # number of memory reference insts executed +system.cpu.iew.exec_branches 300766985 # Number of branches executed +system.cpu.iew.exec_stores 219391610 # Number of stores executed +system.cpu.iew.exec_rate 1.876199 # Inst execution rate +system.cpu.iew.wb_sent 2441119325 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413163778 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388569148 # num instructions producing a value +system.cpu.iew.wb_consumers 1764314853 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.799042 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789419 # average fanout of values written-back +system.cpu.iew.wb_rate 1.839526 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787030 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 860868467 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 823556826 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19198826 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1176175775 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.547201 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.484504 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16078403 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1141183524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.594643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.519930 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 658247718 55.97% 55.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175915600 14.96% 70.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90578875 7.70% 78.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53177308 4.52% 83.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35329719 3.00% 86.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23851430 2.03% 88.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 23326017 1.98% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23350140 1.99% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 92398968 7.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 628040121 55.03% 55.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174132211 15.26% 70.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86354537 7.57% 77.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53988637 4.73% 82.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34269513 3.00% 85.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24750272 2.17% 87.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22050678 1.93% 89.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22940990 2.01% 91.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94656565 8.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1176175775 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1141183524 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,317 +475,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 92398968 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94656565 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3678646200 # The number of ROB reads -system.cpu.rob.rob_writes 5483460601 # The number of ROB writes -system.cpu.timesIdled 829567 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53968858 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3604084711 # The number of ROB reads +system.cpu.rob.rob_writes 5403096067 # The number of ROB writes +system.cpu.timesIdled 804666 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 54334213 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.778897 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.778897 # CPI: Total CPI of All Threads -system.cpu.ipc 1.283867 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.283867 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3341460388 # number of integer regfile reads -system.cpu.int_regfile_writes 1950187380 # number of integer regfile writes -system.cpu.fp_regfile_reads 51936 # number of floating regfile reads -system.cpu.fp_regfile_writes 538 # number of floating regfile writes +system.cpu.cpi 0.755649 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.755649 # CPI: Total CPI of All Threads +system.cpu.ipc 1.323366 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.323366 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3316903206 # number of integer regfile reads +system.cpu.int_regfile_writes 1931453212 # number of integer regfile writes +system.cpu.fp_regfile_reads 30791 # number of floating regfile reads +system.cpu.fp_regfile_writes 509 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 771.801258 # Cycle average of tags in use -system.cpu.icache.total_refs 409163812 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 962 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 425326.207900 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 768.875728 # Cycle average of tags in use +system.cpu.icache.total_refs 390707378 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 406563.348595 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 771.801258 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.376856 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.376856 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 409163812 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 409163812 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 409163812 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 409163812 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 409163812 # number of overall hits -system.cpu.icache.overall_hits::total 409163812 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1504 # number of overall misses -system.cpu.icache.overall_misses::total 1504 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 80548999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 80548999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 80548999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 80548999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 80548999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 80548999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 409165316 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 409165316 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 409165316 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 409165316 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 409165316 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 409165316 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 768.875728 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.375428 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.375428 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390707378 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390707378 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390707378 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390707378 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390707378 # number of overall hits +system.cpu.icache.overall_hits::total 390707378 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1472 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1472 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1472 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1472 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1472 # number of overall misses +system.cpu.icache.overall_misses::total 1472 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 78332000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 78332000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 78332000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 78332000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 78332000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 78332000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 390708850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 390708850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 390708850 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 390708850 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 390708850 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 390708850 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53556.515293 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53556.515293 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53556.515293 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53556.515293 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1029 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53214.673913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53214.673913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53214.673913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53214.673913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53214.673913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53214.673913 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 147 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 542 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 542 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 542 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 542 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 542 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 542 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 962 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 962 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57069999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 57069999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57069999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 57069999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57069999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 57069999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 511 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 511 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 511 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 511 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 961 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 961 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 961 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56098500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 56098500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56098500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56098500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56098500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 56098500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59324.323285 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59324.323285 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58375.130073 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58375.130073 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58375.130073 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 58375.130073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58375.130073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 58375.130073 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9177397 # number of replacements -system.cpu.dcache.tagsinuse 4086.580271 # Cycle average of tags in use -system.cpu.dcache.total_refs 703801568 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9181493 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.654371 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5761373000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.580271 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997700 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997700 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 548148518 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 548148518 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155653046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155653046 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 703801564 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 703801564 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 703801564 # number of overall hits -system.cpu.dcache.overall_hits::total 703801564 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11295128 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11295128 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5075456 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5075456 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16370584 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16370584 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16370584 # number of overall misses -system.cpu.dcache.overall_misses::total 16370584 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 280321207500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 280321207500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 216815235389 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 216815235389 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 51500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 51500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 497136442889 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 497136442889 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 497136442889 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 497136442889 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 559443646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 559443646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 720172148 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 720172148 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 720172148 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 720172148 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020190 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020190 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031578 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031578 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022731 # miss 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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9176047 # number of replacements +system.cpu.dcache.tagsinuse 4087.418525 # Cycle average of tags in use +system.cpu.dcache.total_refs 694335392 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180143 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.634485 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5062814000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.418525 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997905 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997905 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538685115 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538685115 # number of ReadReq hits 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miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023008 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023008 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023008 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023008 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24839.581348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24839.581348 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42738.244280 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42738.244280 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30398.191337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30398.191337 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10428893 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5642690 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 733632 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.215428 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 86.632020 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3724933 # number of writebacks +system.cpu.dcache.writebacks::total 3724933 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3977017 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3977017 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3194676 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3194676 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7171693 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7171693 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7171693 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7171693 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883551 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883551 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 149546401000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 149546401000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65349746897 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 65349746897 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 46500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 46500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214896147897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 214896147897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214896147897 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214896147897 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20495.379418 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20495.379418 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34694.970774 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34694.970774 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 46500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 46500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 725d1f37b..34e401024 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 434faed57..e7a9dda21 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:45:19 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 20:33:15 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 479173106500 because target called exit() +Exiting @ tick 506342716000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 21ff71fb2..2a9784b55 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.515058 # Number of seconds simulated -sim_ticks 515058060000 # Number of ticks simulated -final_tick 515058060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.506343 # Number of seconds simulated +sim_ticks 506342716000 # Number of ticks simulated +final_tick 506342716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166099 # Simulator instruction rate (inst/s) -host_op_rate 185296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55388247 # Simulator tick rate (ticks/s) -host_mem_usage 494292 # Number of bytes of host memory used -host_seconds 9299.05 # Real time elapsed on the host -sim_insts 1544563078 # Number of instructions simulated -sim_ops 1723073890 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 144392128 # Number of bytes read from this memory -system.physmem.bytes_read::total 144440448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70617600 # Number of bytes written to this memory -system.physmem.bytes_written::total 70617600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2256127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2256882 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1103400 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1103400 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 280341459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 280435274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 137106096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 137106096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 137106096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 280341459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 417541370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2256882 # Total number of read requests seen -system.physmem.writeReqs 1103400 # Total number of write requests seen -system.physmem.cpureqs 3360282 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 144440448 # Total number of bytes read from memory -system.physmem.bytesWritten 70617600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 144440448 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70617600 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 637 # Number of read reqs serviced by write Q +host_inst_rate 134396 # Simulator instruction rate (inst/s) +host_op_rate 149928 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44057957 # Simulator tick rate (ticks/s) +host_mem_usage 522896 # Number of bytes of host memory used +host_seconds 11492.65 # Real time elapsed on the host +sim_insts 1544563043 # Number of instructions simulated +sim_ops 1723073855 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143751360 # Number of bytes read from this memory +system.physmem.bytes_read::total 143799104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70435456 # Number of bytes written to this memory +system.physmem.bytes_written::total 70435456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2246115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246861 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100554 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100554 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283901309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 283995601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 139106289 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 139106289 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 139106289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283901309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 423101890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246861 # Total number of read requests seen +system.physmem.writeReqs 1100554 # Total number of write requests seen +system.physmem.cpureqs 3347415 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143799104 # Total number of bytes read from memory +system.physmem.bytesWritten 70435456 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143799104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70435456 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 613 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 140407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 144367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 142491 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141453 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 138510 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 142120 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 141749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 141832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 140373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140948 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 141413 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 137790 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 141680 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 139536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 140645 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 70506 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69820 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 68968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 67927 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 68853 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68680 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 68439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 68530 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 68800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 68663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 67351 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70531 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69216 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69077 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 139880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 143856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141905 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 140877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 137960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141491 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 141233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 139496 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140890 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 137116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 141034 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 138952 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 139888 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69217 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 70379 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69592 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 68832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 67727 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 68713 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 68243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 68230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 68643 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 68550 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 67188 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70321 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69053 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68901 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 515058007000 # Total gap between requests +system.physmem.totGap 506342647500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2256882 # Categorize read packet sizes +system.physmem.readPktSize::6 2246861 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1103400 # categorize write packet sizes +system.physmem.writePktSize::6 1100554 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1580398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 450395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 158442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 66982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1577627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 446326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 156341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 65934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,60 +138,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 27231628654 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 103251704654 # Sum of mem lat for all requests -system.physmem.totBusLat 9024980000 # Total cycles spent in databus access -system.physmem.totBankLat 66995096000 # Total cycles spent in bank access -system.physmem.avgQLat 12069.45 # Average queueing delay per request -system.physmem.avgBankLat 29693.18 # Average bank access latency per request +system.physmem.totQLat 27053022176 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102785772176 # Sum of mem lat for all requests +system.physmem.totBusLat 8984992000 # Total cycles spent in databus access +system.physmem.totBankLat 66747758000 # Total cycles spent in bank access +system.physmem.avgQLat 12043.65 # Average queueing delay per request +system.physmem.avgBankLat 29715.22 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 45762.63 # Average memory access latency -system.physmem.avgRdBW 280.44 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 137.11 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 280.44 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 137.11 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 45758.87 # Average memory access latency +system.physmem.avgRdBW 284.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 139.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 284.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 139.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.61 # Data bus utilization in percentage +system.physmem.busUtil 2.64 # Data bus utilization in percentage system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 11.32 # Average write queue length over time -system.physmem.readRowHits 919391 # Number of row buffer hits during reads -system.physmem.writeRowHits 189315 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 17.16 # Row buffer hit rate for writes -system.physmem.avgGap 153278.21 # Average gap between requests +system.physmem.avgWrQLen 10.20 # Average write queue length over time +system.physmem.readRowHits 914443 # Number of row buffer hits during reads +system.physmem.writeRowHits 189193 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 17.19 # Row buffer hit rate for writes +system.physmem.avgGap 151263.78 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,569 +235,442 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1030116121 # number of cpu cycles simulated +system.cpu.numCycles 1012685433 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 307748972 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 253170818 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16168830 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 178836343 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 162524431 # Number of BTB hits +system.cpu.BPredUnit.lookups 301954621 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 248216809 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 15201913 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 174080905 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 160275912 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18394581 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 234 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 302711500 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2208582342 # Number of instructions fetch has processed -system.cpu.fetch.Branches 307748972 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 180919012 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 439713036 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 91477277 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 153604124 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 69 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 292882660 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6106896 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 969047070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.529561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.216174 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 17543051 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 217 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 296171329 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2177000343 # Number of instructions fetch has processed +system.cpu.fetch.Branches 301954621 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 177818963 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433079666 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 86445035 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 152984584 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 67 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 286733341 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5527590 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 951199831 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.533171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.216208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 529334144 54.62% 54.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25043926 2.58% 57.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39264186 4.05% 61.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48337631 4.99% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43062270 4.44% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 47882627 4.94% 75.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39313310 4.06% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19335068 2.00% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 177473908 18.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 518120232 54.47% 54.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25036737 2.63% 57.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39011944 4.10% 61.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48247673 5.07% 66.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 42552998 4.47% 70.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46316076 4.87% 75.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38402395 4.04% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18552878 1.95% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174958898 18.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 969047070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.298752 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.144013 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 334775915 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 131820236 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 409429631 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20003640 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 73017648 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46459880 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 721 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2395467722 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2521 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 73017648 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 358478616 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61310545 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17059 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 404218624 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72004578 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2331266224 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 128849 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5208113 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58805545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2308002536 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10761064902 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10761060796 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4106 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706320018 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 601682518 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1074 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1071 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160130696 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 634128265 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 221560674 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 87711423 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 69100091 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2223438682 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1093 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2032725138 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5162970 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 495697928 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1172411676 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 912 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 969047070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.097654 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906175 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 951199831 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.298172 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.149730 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 327457175 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 131287653 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403449648 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20041830 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 68963525 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46005772 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2358153457 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 68963525 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 350605393 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61238175 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13721 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 398828619 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71550398 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2297300888 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 126992 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5036459 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58395724 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2272291937 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10608987199 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10608983762 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3437 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 565971975 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 462 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158423553 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 623142693 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220479196 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86005454 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70775057 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2196663707 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 506 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2016028881 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3978647 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 469035072 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1108322137 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 332 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 951199831 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.119459 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906333 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 282916763 29.20% 29.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 152378116 15.72% 44.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 162831122 16.80% 61.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119917560 12.37% 74.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126106053 13.01% 87.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 74105592 7.65% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38169342 3.94% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10016302 1.03% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2606220 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 271401880 28.53% 28.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 150954811 15.87% 44.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160752249 16.90% 61.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119324059 12.54% 73.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124037458 13.04% 86.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73914082 7.77% 94.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38408733 4.04% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9827717 1.03% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2578842 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 969047070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 951199831 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 856823 3.47% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4485 0.02% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18914760 76.65% 80.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4900553 19.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 872713 3.66% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5800 0.02% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18252533 76.46% 80.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4741041 19.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1244244744 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 933049 0.05% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 593617066 29.20% 90.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193930151 9.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1235530867 61.29% 61.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 926678 0.05% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 25 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 11 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 586539458 29.09% 90.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193031781 9.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2032725138 # Type of FU issued -system.cpu.iq.rate 1.973297 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24676621 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012140 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5064336479 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2719325477 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1969225475 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 784 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 183 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2057401528 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63678179 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2016028881 # Type of FU issued +system.cpu.iq.rate 1.990775 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23872087 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011841 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5011107955 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2665888919 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1956633156 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 668 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 148 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2039900782 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 186 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64729425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 148201485 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 301622 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 191452 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46713618 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 137215920 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 273705 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192829 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45632147 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3827005 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3804190 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 73017648 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27244100 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1491546 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2223439933 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6134188 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 634128265 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 221560674 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1025 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 470403 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 191452 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8679785 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10261943 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18941728 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2001081478 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 578449212 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 31643660 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 68963525 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27139108 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1495868 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2196664320 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6096220 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 623142693 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220479196 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 440 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 474677 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 89373 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192829 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8139641 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9611816 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17751457 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986428018 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573006458 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29600863 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 158 # number of nop insts executed -system.cpu.iew.exec_refs 769422153 # number of memory reference insts executed -system.cpu.iew.exec_branches 239265351 # Number of branches executed -system.cpu.iew.exec_stores 190972941 # Number of stores executed -system.cpu.iew.exec_rate 1.942579 # Inst execution rate -system.cpu.iew.wb_sent 1978131551 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1969225658 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1302526017 # num instructions producing a value -system.cpu.iew.wb_consumers 2074719324 # num instructions consuming a value +system.cpu.iew.exec_nop 107 # number of nop insts executed +system.cpu.iew.exec_refs 763162577 # number of memory reference insts executed +system.cpu.iew.exec_branches 238305506 # Number of branches executed +system.cpu.iew.exec_stores 190156119 # Number of stores executed +system.cpu.iew.exec_rate 1.961545 # Inst execution rate +system.cpu.iew.wb_sent 1965069993 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1956633304 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295741844 # num instructions producing a value +system.cpu.iew.wb_consumers 2060291868 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.911654 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.627808 # average fanout of values written-back +system.cpu.iew.wb_rate 1.932123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628912 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 500462812 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 181 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16168149 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 896029423 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.923010 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.718948 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 473688675 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15201254 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 882236307 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.953075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.733441 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 406862083 45.41% 45.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193059933 21.55% 66.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73977423 8.26% 75.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35390708 3.95% 79.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18895903 2.11% 81.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30453376 3.40% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19841212 2.21% 86.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11401039 1.27% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106147746 11.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 395033936 44.78% 44.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192005187 21.76% 66.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72432268 8.21% 74.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35243986 3.99% 78.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18949129 2.15% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30789454 3.49% 84.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20064460 2.27% 86.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11401450 1.29% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106316437 12.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 896029423 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563096 # Number of instructions committed -system.cpu.commit.committedOps 1723073908 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 882236307 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563061 # Number of instructions committed +system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773836 # Number of memory references committed -system.cpu.commit.loads 485926780 # Number of loads committed +system.cpu.commit.refs 660773822 # Number of memory references committed +system.cpu.commit.loads 485926773 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462437 # Number of branches committed +system.cpu.commit.branches 213462430 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941885 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106147746 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106316437 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3013417798 # The number of ROB reads -system.cpu.rob.rob_writes 4520246386 # The number of ROB writes -system.cpu.timesIdled 1016810 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61069051 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563078 # Number of Instructions Simulated -system.cpu.committedOps 1723073890 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563078 # Number of Instructions Simulated -system.cpu.cpi 0.666930 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.666930 # CPI: Total CPI of All Threads -system.cpu.ipc 1.499407 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.499407 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10019536016 # number of integer regfile reads -system.cpu.int_regfile_writes 1949927429 # number of integer regfile writes -system.cpu.fp_regfile_reads 198 # number of floating regfile reads -system.cpu.fp_regfile_writes 204 # number of floating regfile writes -system.cpu.misc_regfile_reads 2950890294 # number of misc regfile reads -system.cpu.misc_regfile_writes 146 # number of misc regfile writes -system.cpu.icache.replacements 21 # number of replacements -system.cpu.icache.tagsinuse 635.874030 # Cycle average of tags in use -system.cpu.icache.total_refs 292881421 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 787 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 372149.200762 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2972681819 # The number of ROB reads +system.cpu.rob.rob_writes 4462636284 # The number of ROB writes +system.cpu.timesIdled 1007749 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 61485602 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563043 # Number of Instructions Simulated +system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated +system.cpu.cpi 0.655645 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.655645 # CPI: Total CPI of All Threads +system.cpu.ipc 1.525215 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.525215 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9949187154 # number of integer regfile reads +system.cpu.int_regfile_writes 1936551418 # number of integer regfile writes +system.cpu.fp_regfile_reads 155 # number of floating regfile reads +system.cpu.fp_regfile_writes 154 # number of floating regfile writes +system.cpu.misc_regfile_reads 2914618242 # number of misc regfile reads +system.cpu.misc_regfile_writes 132 # number of misc regfile writes +system.cpu.icache.replacements 22 # number of replacements +system.cpu.icache.tagsinuse 625.107966 # Cycle average of tags in use +system.cpu.icache.total_refs 286732187 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 775 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 369977.015484 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 635.874030 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.310485 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.310485 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 292881421 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 292881421 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 292881421 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 292881421 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 292881421 # number of overall hits -system.cpu.icache.overall_hits::total 292881421 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1239 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1239 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1239 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1239 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1239 # number of overall misses -system.cpu.icache.overall_misses::total 1239 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62929999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62929999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62929999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62929999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62929999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62929999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 292882660 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 292882660 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 292882660 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 292882660 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 292882660 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 292882660 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 625.107966 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.305228 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.305228 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 286732187 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 286732187 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 286732187 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 286732187 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 286732187 # number of overall hits +system.cpu.icache.overall_hits::total 286732187 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59543000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59543000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59543000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59543000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59543000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59543000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 286733341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 286733341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 286733341 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 286733341 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 286733341 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 286733341 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50790.959645 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50790.959645 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50790.959645 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50790.959645 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51597.053726 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51597.053726 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51597.053726 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51597.053726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51597.053726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51597.053726 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 452 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 452 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 452 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 452 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 452 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 787 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 787 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 787 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42672499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42672499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42672499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42672499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42672499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42672499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 379 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 379 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 379 # number of demand (read+write) MSHR hits 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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54221.726811 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53966.451613 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53966.451613 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9616996 # number of replacements -system.cpu.dcache.tagsinuse 4088.070177 # Cycle average of tags in use -system.cpu.dcache.total_refs 662383558 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9621092 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.847025 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3431633000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.070177 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998064 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998064 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 495328808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 495328808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167054576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167054576 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 102 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 102 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 72 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 72 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 662383384 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 662383384 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 662383384 # number of overall hits -system.cpu.dcache.overall_hits::total 662383384 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11493898 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11493898 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5531471 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5531471 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17025369 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17025369 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17025369 # number of overall misses -system.cpu.dcache.overall_misses::total 17025369 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 300469698500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 300469698500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 217116494201 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 217116494201 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 190500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 190500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 517586192701 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 517586192701 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 517586192701 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 517586192701 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 506822706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 506822706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 105 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 105 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 72 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 72 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 679408753 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 679408753 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 679408753 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 679408753 # number of overall (read+write) accesses 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+system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 488912900 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 488912900 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167053904 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167053904 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 87 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 87 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 655966804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 655966804 # number of demand (read+write) hits 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+system.cpu.dcache.overall_accesses::cpu.data 672978142 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 672978142 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022940 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022940 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032054 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032054 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025278 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025278 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025278 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025278 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26091.048022 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26091.048022 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39246.080030 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39246.080030 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30369.107646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30369.107646 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19754018 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 992148 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1171998 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.854993 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15.371892 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3781955 # number of writebacks +system.cpu.dcache.writebacks::total 3781955 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3770552 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3770552 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638638 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3638638 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7409190 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7409190 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7409190 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7409190 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708643 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708643 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893505 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893505 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170578712500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 170578712500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71843645589 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71843645589 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242422358089 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 242422358089 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242422358089 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 242422358089 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22128.241313 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22128.241313 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.147282 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.147282 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index db2911eab..402c5cbcd 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index b50317767..483ce54bf 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:35:16 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:10:16 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +21,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 42012413000 because target called exit() +122 123 124 Exiting @ tick 41615049000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index ba13ea976..7f70f56b6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041949 # Number of seconds simulated -sim_ticks 41948719000 # Number of ticks simulated -final_tick 41948719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041615 # Number of seconds simulated +sim_ticks 41615049000 # Number of ticks simulated +final_tick 41615049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82495 # Simulator instruction rate (inst/s) -host_op_rate 82495 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37654494 # Simulator tick rate (ticks/s) -host_mem_usage 221732 # Number of bytes of host memory used -host_seconds 1114.04 # Real time elapsed on the host +host_inst_rate 117678 # Simulator instruction rate (inst/s) +host_op_rate 117678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53286406 # Simulator tick rate (ticks/s) +host_mem_usage 217828 # Number of bytes of host memory used +host_seconds 780.97 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4262728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3271041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7533770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4262728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4262728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4262728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3271041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7533770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4296907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3297269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7594176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4296907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4296907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4296907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3297269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7594176 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41948681000 # Total gap between requests +system.physmem.totGap 41614997000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -99,8 +99,8 @@ system.physmem.neitherpktsize::6 0 # ca system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 3467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 421 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 18563928 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 107349928 # Sum of mem lat for all requests +system.physmem.totQLat 17845427 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 106827427 # Sum of mem lat for all requests system.physmem.totBusLat 19752000 # Total cycles spent in databus access -system.physmem.totBankLat 69034000 # Total cycles spent in bank access -system.physmem.avgQLat 3759.40 # Average queueing delay per request -system.physmem.avgBankLat 13980.15 # Average bank access latency per request +system.physmem.totBankLat 69230000 # Total cycles spent in bank access +system.physmem.avgQLat 3613.90 # Average queueing delay per request +system.physmem.avgBankLat 14019.85 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21739.56 # Average memory access latency -system.physmem.avgRdBW 7.53 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 21633.74 # Average memory access latency +system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 7.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4458 # Number of row buffer hits during reads +system.physmem.readRowHits 4457 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8495075.13 # Average gap between requests +system.physmem.avgGap 8427500.41 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996251 # DTB read hits +system.cpu.dtb.read_hits 19996253 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996261 # DTB read accesses +system.cpu.dtb.read_accesses 19996263 # DTB read accesses system.cpu.dtb.write_hits 6501863 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 6501886 # DTB write accesses -system.cpu.dtb.data_hits 26498114 # DTB hits +system.cpu.dtb.data_hits 26498116 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498147 # DTB accesses -system.cpu.itb.fetch_hits 10035746 # ITB hits +system.cpu.dtb.data_accesses 26498149 # DTB accesses +system.cpu.itb.fetch_hits 9956935 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10035795 # ITB accesses +system.cpu.itb.fetch_accesses 9956984 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83897439 # number of cpu cycles simulated +system.cpu.numCycles 83230099 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13564910 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9782241 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4497823 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7992573 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3850501 # Number of BTB hits +system.cpu.branch_predictor.lookups 13412629 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9650146 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4269214 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7424481 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3768497 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.175988 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5999726 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7565184 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73745307 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 126 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 50.757716 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73570547 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136320779 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206802 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136146019 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058690 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38528710 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26769089 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3520477 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 976488 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4496965 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5743737 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.912663 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57470360 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38521872 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26722393 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57404029 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83635742 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970257 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10897 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7614848 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76282591 # Number of cycles cpu stages are processed. -system.cpu.activity 90.923623 # Percentage of cycles cpu is active +system.cpu.timesIdled 10685 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7622365 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607734 # Number of cycles cpu stages are processed. +system.cpu.activity 90.841817 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -265,72 +265,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.912891 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.905629 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.912891 # CPI: Total CPI of All Threads -system.cpu.ipc 1.095421 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.905629 # CPI: Total CPI of All Threads +system.cpu.ipc 1.104205 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.095421 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27675918 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221521 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 67.012202 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34449958 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49447481 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.938010 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33919397 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49978042 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.570402 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65867839 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029600 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.490048 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29953374 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53944065 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.297630 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 8127 # number of replacements -system.cpu.icache.tagsinuse 1492.667941 # Cycle average of tags in use -system.cpu.icache.total_refs 10023995 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1001.198062 # Average number of references to valid blocks. +system.cpu.ipc_total 1.104205 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27549736 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680363 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.899311 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33978401 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251698 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.175345 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33378776 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851323 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.895787 # Percentage of cycles stage was utilized (processing insts). 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26488629 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11915.712551 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 1441.892023 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352024 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352024 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493006 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493006 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488629 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488629 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488629 # number of overall hits +system.cpu.dcache.overall_hits::total 26488629 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8097 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8097 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8672 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8672 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8672 # number of overall misses +system.cpu.dcache.overall_misses::total 8672 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28721000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28721000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 329862500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 329862500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 358583500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 358583500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 358583500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 358583500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49949.565217 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49949.565217 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40738.853897 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40738.853897 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41349.573339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41349.573339 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11994 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 830 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.450602 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6349 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6349 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6449 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22990000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22990000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81618000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 81618000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 104608000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 104608000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 104608000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 104608000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48400 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48400 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46692.219680 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46692.219680 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 064828e12..231709206 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index bbfeb5540..4f948ec38 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:49:45 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:23:29 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +21,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23661066000 because target called exit() +122 123 124 Exiting @ tick 23378067000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index ef2eb2fe7..91f902e42 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023714 # Number of seconds simulated -sim_ticks 23713623000 # Number of ticks simulated -final_tick 23713623000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023378 # Number of seconds simulated +sim_ticks 23378067000 # Number of ticks simulated +final_tick 23378067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202255 # Simulator instruction rate (inst/s) -host_op_rate 202255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56975613 # Simulator tick rate (ticks/s) -host_mem_usage 222752 # Number of bytes of host memory used -host_seconds 416.21 # Real time elapsed on the host +host_inst_rate 166789 # Simulator instruction rate (inst/s) +host_op_rate 166789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46320112 # Simulator tick rate (ticks/s) +host_mem_usage 219224 # Number of bytes of host memory used +host_seconds 504.71 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 196928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 335488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196928 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5242 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8304425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5843055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14147480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8304425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8304425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8304425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5843055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14147480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5242 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::total 334592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8388033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5924185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14312218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8388033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8388033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8388033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5924185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14312218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5228 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5242 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 335488 # Total number of bytes read from memory +system.physmem.cpureqs 5228 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 334592 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 335488 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 334592 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 367 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 254 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 253 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 316 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 255 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 373 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 320 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 275 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 288 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 326 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 380 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 382 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 352 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23713517000 # Total gap between requests +system.physmem.totGap 23377961000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5242 # Categorize read packet sizes +system.physmem.readPktSize::6 5228 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 365 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 21552231 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 116524231 # Sum of mem lat for all requests -system.physmem.totBusLat 20968000 # Total cycles spent in databus access -system.physmem.totBankLat 74004000 # Total cycles spent in bank access -system.physmem.avgQLat 4111.45 # Average queueing delay per request -system.physmem.avgBankLat 14117.51 # Average bank access latency per request +system.physmem.totQLat 21787213 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 116311213 # Sum of mem lat for all requests +system.physmem.totBusLat 20912000 # Total cycles spent in databus access +system.physmem.totBankLat 73612000 # Total cycles spent in bank access +system.physmem.avgQLat 4167.41 # Average queueing delay per request +system.physmem.avgBankLat 14080.34 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22228.96 # Average memory access latency -system.physmem.avgRdBW 14.15 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22247.75 # Average memory access latency +system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.15 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4692 # Number of row buffer hits during reads +system.physmem.readRowHits 4677 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4523753.72 # Average gap between requests +system.physmem.avgGap 4471683.44 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23220961 # DTB read hits -system.cpu.dtb.read_misses 199829 # DTB read misses +system.cpu.dtb.read_hits 23102664 # DTB read hits +system.cpu.dtb.read_misses 192481 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23420790 # DTB read accesses -system.cpu.dtb.write_hits 7077526 # DTB write hits -system.cpu.dtb.write_misses 1364 # DTB write misses -system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 7078890 # DTB write accesses -system.cpu.dtb.data_hits 30298487 # DTB hits -system.cpu.dtb.data_misses 201193 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 30499680 # DTB accesses -system.cpu.itb.fetch_hits 14949647 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses +system.cpu.dtb.read_accesses 23295145 # DTB read accesses +system.cpu.dtb.write_hits 7068005 # DTB write hits +system.cpu.dtb.write_misses 1092 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7069097 # DTB write accesses +system.cpu.dtb.data_hits 30170669 # DTB hits +system.cpu.dtb.data_misses 193573 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 30364242 # DTB accesses +system.cpu.itb.fetch_hits 14708082 # ITB hits +system.cpu.itb.fetch_misses 96 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14949752 # ITB accesses +system.cpu.itb.fetch_accesses 14708178 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,246 +218,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47427247 # number of cpu cycles simulated +system.cpu.numCycles 46756135 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15025642 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10894363 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 964786 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8694430 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7072700 # Number of BTB hits +system.cpu.BPredUnit.lookups 14833517 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10762267 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 917019 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8075874 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6944735 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1485982 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3318 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15702309 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128217574 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15025642 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8558682 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22383156 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4634796 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5563262 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2124 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14949647 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 339712 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47286808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.711487 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.371391 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1466052 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3147 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15430530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126815242 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14833517 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8410787 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22106787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4454905 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5569972 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2009 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14708082 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 322729 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46612836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.720608 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376239 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24903652 52.67% 52.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2390695 5.06% 57.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1208579 2.56% 60.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1776118 3.76% 64.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2803213 5.93% 69.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1173314 2.48% 72.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1230561 2.60% 75.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 786829 1.66% 76.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11013847 23.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24506049 52.57% 52.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2362426 5.07% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191299 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1739407 3.73% 63.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2752944 5.91% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1147923 2.46% 72.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1216668 2.61% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 768362 1.65% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10927758 23.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47286808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316815 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.703458 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17546675 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4261865 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20763738 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090514 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3624016 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2545492 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12249 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125138336 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32050 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3624016 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18714540 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 973231 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20663986 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3302745 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122153228 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 68 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 400521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2428440 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89689212 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158636809 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148888433 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9748376 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46612836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317253 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.712270 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17256308 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4263506 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20503237 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1097959 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3491826 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2511850 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12028 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123858190 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32546 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3491826 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18399179 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 964925 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7287 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20435541 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3314078 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121046582 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 48 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 399182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2434828 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 88894409 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157311905 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 147648223 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9663682 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21261851 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 999 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1008 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8748966 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25553670 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8298282 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2624329 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 917691 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106148372 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2425 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96973982 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186832 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21507239 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16151719 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2036 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47286808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.050762 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875057 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20467048 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 739 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 732 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8795383 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25343096 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8237940 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2594464 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 920924 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105370947 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1446 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96530679 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178191 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20721356 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15565520 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1057 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46612836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.070903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875751 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12523872 26.48% 26.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9450826 19.99% 46.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8468072 17.91% 64.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6321623 13.37% 77.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4941695 10.45% 88.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2845109 6.02% 94.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1728871 3.66% 97.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 797328 1.69% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209412 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12074665 25.90% 25.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9351108 20.06% 45.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8402793 18.03% 63.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6288710 13.49% 77.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4905546 10.52% 88.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2859533 6.13% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1729691 3.71% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 796460 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 204330 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47286808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46612836 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 189731 12.08% 12.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 196 0.01% 12.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7230 0.46% 12.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5874 0.37% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843349 53.68% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445490 28.35% 94.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79325 5.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 190047 12.12% 12.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 203 0.01% 12.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7055 0.45% 12.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5882 0.38% 12.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842974 53.75% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 444058 28.31% 95.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78249 4.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58981330 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480636 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58717725 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479593 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802326 2.89% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115452 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386635 2.46% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311394 0.32% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759833 0.78% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23966232 24.71% 92.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7169818 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2796739 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115257 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386885 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311006 0.32% 67.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760000 0.79% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23812199 24.67% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7150949 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96973982 # Type of FU issued -system.cpu.iq.rate 2.044689 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1571195 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016202 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227861218 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118862045 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87356059 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15131581 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8830751 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7068549 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90549768 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7995402 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518620 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96530679 # Type of FU issued +system.cpu.iq.rate 2.064556 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016248 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226318050 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117401953 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87051166 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15102803 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8726703 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7059295 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90117667 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7981473 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1519109 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5557472 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19450 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34891 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1797179 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5346898 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18469 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35032 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1736837 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10488 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1489 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10557 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3624016 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 135468 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17609 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116444859 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 396288 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25553670 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8298282 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2425 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3185 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 28 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34891 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 568741 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508698 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1077439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95679677 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23421457 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1294305 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3491826 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 132020 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18316 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115597875 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 364987 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25343096 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8237940 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1446 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3142 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35032 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 529110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 494336 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1023446 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95309066 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23295605 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1221613 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10294062 # number of nop insts executed -system.cpu.iew.exec_refs 30500537 # number of memory reference insts executed -system.cpu.iew.exec_branches 12076025 # Number of branches executed -system.cpu.iew.exec_stores 7079080 # Number of stores executed -system.cpu.iew.exec_rate 2.017399 # Inst execution rate -system.cpu.iew.wb_sent 94965900 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94424608 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64613443 # num instructions producing a value -system.cpu.iew.wb_consumers 89987902 # num instructions consuming a value +system.cpu.iew.exec_nop 10225482 # number of nop insts executed +system.cpu.iew.exec_refs 30364899 # number of memory reference insts executed +system.cpu.iew.exec_branches 12021435 # Number of branches executed +system.cpu.iew.exec_stores 7069294 # Number of stores executed +system.cpu.iew.exec_rate 2.038429 # Inst execution rate +system.cpu.iew.wb_sent 94627849 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94110461 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64468484 # num instructions producing a value +system.cpu.iew.wb_consumers 89853069 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.990936 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.718024 # average fanout of values written-back +system.cpu.iew.wb_rate 2.012794 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717488 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24543105 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23695922 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 952948 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43662792 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.104837 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.733240 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 905358 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43121010 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.131283 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.747044 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17112386 39.19% 39.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9977533 22.85% 62.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4511330 10.33% 72.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2294197 5.25% 77.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1617378 3.70% 81.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1129034 2.59% 83.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 721116 1.65% 85.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 819651 1.88% 87.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5480167 12.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16684738 38.69% 38.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9903892 22.97% 61.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4485087 10.40% 72.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2259914 5.24% 77.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1605498 3.72% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1123100 2.60% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 719913 1.67% 85.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818667 1.90% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5520201 12.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43662792 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43121010 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,372 +467,372 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5480167 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5520201 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154627745 # The number of ROB reads -system.cpu.rob.rob_writes 236540658 # The number of ROB writes -system.cpu.timesIdled 5097 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 140439 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153198746 # The number of ROB reads +system.cpu.rob.rob_writes 234713539 # The number of ROB writes +system.cpu.timesIdled 5103 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 143299 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.563405 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.563405 # CPI: Total CPI of All Threads -system.cpu.ipc 1.774923 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.774923 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129451321 # number of integer regfile reads -system.cpu.int_regfile_writes 70766811 # number of integer regfile writes -system.cpu.fp_regfile_reads 6191777 # number of floating regfile reads -system.cpu.fp_regfile_writes 6050030 # number of floating regfile writes -system.cpu.misc_regfile_reads 714415 # number of misc regfile reads +system.cpu.cpi 0.555432 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.555432 # CPI: Total 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(read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 320401000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 320401000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14949646 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14949646 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14949646 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14949646 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14949646 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14949646 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000999 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000999 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 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LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004255 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51372.798434 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51372.798434 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48121.751298 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48121.751298 # average WriteReq mshr miss latency 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-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.697198 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2024.332365 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 377.238893 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061778 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011512 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073830 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 9069 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 9123 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108 # number of 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misses -system.cpu.l2cache.ReadExReq_misses::total 1707 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3077 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5242 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3077 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses -system.cpu.l2cache.overall_misses::total 5242 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 139425500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25252500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 164678000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81258000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 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accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1733 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1733 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 14391 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 14391 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.253334 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.279270 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984997 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.984997 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.253334 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.364255 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.253334 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.364255 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45312.154696 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55136.462882 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 46585.007072 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47602.811951 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47602.811951 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45312.154696 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49196.535797 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46916.444105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45312.154696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49196.535797 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46916.444105 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3077 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3535 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1707 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3077 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5242 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3077 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5242 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 100633163 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19510628 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120143791 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60209566 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60209566 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100633163 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79720194 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 180353357 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100633163 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79720194 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 180353357 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279270 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984997 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984997 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.364255 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.364255 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32704.960351 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42599.624454 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33986.928147 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35272.153486 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35272.153486 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32704.960351 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36822.260508 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34405.447730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32704.960351 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36822.260508 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34405.447730 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 6abd7ca4a..27e85dd46 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index b01ca9643..df8c6714b 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 13:57:03 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 20:48:26 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 76020082000 because target called exit() +122 123 124 Exiting @ tick 74245032000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 3d59bfc93..341764510 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.075963 # Number of seconds simulated -sim_ticks 75962996000 # Number of ticks simulated -final_tick 75962996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074245 # Number of seconds simulated +sim_ticks 74245032000 # Number of ticks simulated +final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82470 # Simulator instruction rate (inst/s) -host_op_rate 90296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36352186 # Simulator tick rate (ticks/s) -host_mem_usage 236740 # Number of bytes of host memory used -host_seconds 2089.64 # Real time elapsed on the host -sim_insts 172333241 # Number of instructions simulated -sim_ops 188686723 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory -system.physmem.bytes_read::total 244928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3827 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1747377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1476930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3224307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1747377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1747377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1747377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1476930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3224307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3828 # Total number of read requests seen +host_inst_rate 109443 # Simulator instruction rate (inst/s) +host_op_rate 119829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47150577 # Simulator tick rate (ticks/s) +host_mem_usage 234068 # Number of bytes of host memory used +host_seconds 1574.64 # Real time elapsed on the host +sim_insts 172333441 # Number of instructions simulated +sim_ops 188686923 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory +system.physmem.bytes_read::total 242688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2047 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3792 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1764536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1504208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3268744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1764536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1764536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1764536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1504208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3268744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3793 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 244928 # Total number of bytes read from memory +system.physmem.cpureqs 3795 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 242688 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 244928 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 242688 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 194 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 284 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 263 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 182 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 238 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 242 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 259 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 179 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 237 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 75962976500 # Total gap between requests +system.physmem.totGap 74245012500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3828 # Categorize read packet sizes +system.physmem.readPktSize::6 3793 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,15 +95,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 1 # categorize neither packet sizes +system.physmem.neitherpktsize::6 2 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2791 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 15909310 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 90413310 # Sum of mem lat for all requests -system.physmem.totBusLat 15312000 # Total cycles spent in databus access -system.physmem.totBankLat 59192000 # Total cycles spent in bank access -system.physmem.avgQLat 4156.04 # Average queueing delay per request -system.physmem.avgBankLat 15462.90 # Average bank access latency per request +system.physmem.totQLat 12366785 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests +system.physmem.totBusLat 15172000 # Total cycles spent in databus access +system.physmem.totBankLat 58828000 # Total cycles spent in bank access +system.physmem.avgQLat 3260.42 # Average queueing delay per request +system.physmem.avgBankLat 15509.62 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23618.94 # Average memory access latency -system.physmem.avgRdBW 3.22 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22770.05 # Average memory access latency +system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.22 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3324 # Number of row buffer hits during reads +system.physmem.readRowHits 3295 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads +system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19844037.75 # Average gap between requests +system.physmem.avgGap 19574218.96 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,647 +228,645 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 151925993 # number of cpu cycles simulated +system.cpu.numCycles 148490065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96812188 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76032236 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6553809 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46446152 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44209779 # Number of BTB hits +system.cpu.BPredUnit.lookups 94824011 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 74811084 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6283419 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 44691419 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 43068728 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4476893 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 89558 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40612935 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 388214882 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96812188 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48686672 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82228989 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28431080 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7111966 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9226 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37654254 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1887415 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 151824267 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.799061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69765849 45.95% 45.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5500538 3.62% 49.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10700560 7.05% 56.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10437997 6.88% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8786758 5.79% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6834684 4.50% 73.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6296298 4.15% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8361211 5.51% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25140372 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8658719 5.84% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6556174 4.42% 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6250200 4.21% 77.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8011886 5.40% 83.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151824267 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.637233 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.555289 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46639472 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5819765 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76543741 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1113557 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21707732 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14816289 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162918 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401266810 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 729123 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21707732 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52145776 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 716376 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 699385 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72090483 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4464515 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 378976726 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 316631 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3575950 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 15 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 642441440 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1614452334 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1596874036 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17578298 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092491 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 344348949 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33473 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33471 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12628265 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43987484 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16888261 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5791013 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3746055 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334831031 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55567 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 252811108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 890392 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 144974552 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 373956822 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4307 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151824267 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.665156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759693 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14343881 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164426 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392938907 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 736414 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20843724 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43027461 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16443523 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5668310 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3691413 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329308816 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 54643 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249531465 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 795533 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58367016 38.44% 38.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23007793 15.15% 53.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25146514 16.56% 70.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20482198 13.49% 83.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12879503 8.48% 92.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6581643 4.34% 96.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4062886 2.68% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1113562 0.73% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 183152 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12554169 8.46% 92.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6514357 4.39% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4035019 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1109043 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151824267 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 966665 37.55% 37.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5596 0.22% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 27 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1198357 46.55% 84.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 403391 15.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1162967 46.43% 85.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 373557 14.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197328873 78.05% 78.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995382 0.39% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33194 0.01% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 163810 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255234 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76440 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467356 0.18% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206283 0.08% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71857 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39021114 15.43% 94.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14191245 5.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194943196 78.12% 78.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 980225 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33090 0.01% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164479 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254525 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76418 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465710 0.19% 78.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206458 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38372441 15.38% 94.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13962748 5.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 252811108 # Type of FU issued -system.cpu.iq.rate 1.664041 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2574130 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010182 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 657138452 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 477635375 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240576408 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3772553 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2244745 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1851453 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253490963 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1894275 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2028433 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249531465 # Type of FU issued +system.cpu.iq.rate 1.680459 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2189794 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1841578 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250160112 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1876275 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2013222 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14131956 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16953 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19730 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4237583 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13171893 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18785 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3792805 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 84 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 96 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21707732 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16237 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 835 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334904365 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 834808 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43987484 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16888261 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33011 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19730 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4101344 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3925912 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8027256 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 245818022 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37400003 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6993086 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20843724 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 209 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18785 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3890771 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3762289 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7653060 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 243027736 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36864796 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6503729 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17767 # number of nop insts executed -system.cpu.iew.exec_refs 51208402 # number of memory reference insts executed -system.cpu.iew.exec_branches 54033495 # Number of branches executed -system.cpu.iew.exec_stores 13808399 # Number of stores executed -system.cpu.iew.exec_rate 1.618012 # Inst execution rate -system.cpu.iew.wb_sent 243559168 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242427861 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150062323 # num instructions producing a value -system.cpu.iew.wb_consumers 269174598 # num instructions consuming a value +system.cpu.iew.exec_nop 16968 # number of nop insts executed +system.cpu.iew.exec_refs 50523279 # number of memory reference insts executed +system.cpu.iew.exec_branches 53444477 # Number of branches executed +system.cpu.iew.exec_stores 13658483 # Number of stores executed +system.cpu.iew.exec_rate 1.636660 # Inst execution rate +system.cpu.iew.wb_sent 240848315 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239789364 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148488630 # num instructions producing a value +system.cpu.iew.wb_consumers 267300896 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.595697 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557491 # average fanout of values written-back +system.cpu.iew.wb_rate 1.614851 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555511 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 146203238 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51260 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6400494 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130116536 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.450247 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.162155 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 140679091 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51300 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6130085 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127544650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.479492 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.184685 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59888298 46.03% 46.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32076129 24.65% 70.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13982572 10.75% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7654340 5.88% 87.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4412681 3.39% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1335897 1.03% 91.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1741211 1.34% 93.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1283921 0.99% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7741487 5.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57798190 45.32% 45.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31737959 24.88% 70.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13785979 10.81% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7635406 5.99% 87.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4383857 3.44% 90.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1319533 1.03% 91.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1705049 1.34% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1307627 1.03% 93.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7871050 6.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130116536 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347629 # Number of instructions committed -system.cpu.commit.committedOps 188701111 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 127544650 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347829 # Number of instructions committed +system.cpu.commit.committedOps 188701311 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506206 # Number of memory references committed -system.cpu.commit.loads 29855528 # Number of loads committed +system.cpu.commit.refs 42506286 # Number of memory references committed +system.cpu.commit.loads 29855568 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40306355 # Number of branches committed +system.cpu.commit.branches 40306395 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130393 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130553 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7741487 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7871050 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457274197 # The number of ROB reads -system.cpu.rob.rob_writes 691635591 # The number of ROB writes -system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 101726 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333241 # Number of Instructions Simulated -system.cpu.committedOps 188686723 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333241 # Number of Instructions Simulated -system.cpu.cpi 0.881583 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.881583 # CPI: Total CPI of All Threads -system.cpu.ipc 1.134324 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.134324 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091906245 # number of integer regfile reads -system.cpu.int_regfile_writes 388600616 # number of integer regfile writes -system.cpu.fp_regfile_reads 2911397 # number of floating regfile reads -system.cpu.fp_regfile_writes 2511024 # number of floating regfile writes -system.cpu.misc_regfile_reads 474438629 # number of misc regfile reads -system.cpu.misc_regfile_writes 832124 # number of misc regfile writes -system.cpu.icache.replacements 2644 # number of replacements -system.cpu.icache.tagsinuse 1367.286315 # Cycle average of tags in use -system.cpu.icache.total_refs 37648759 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4386 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8583.848381 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 449048801 # The number of ROB reads +system.cpu.rob.rob_writes 679713725 # The number of ROB writes +system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333441 # Number of Instructions Simulated +system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated +system.cpu.cpi 0.861644 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861644 # CPI: Total CPI of All Threads +system.cpu.ipc 1.160572 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160572 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079711901 # number of integer regfile reads +system.cpu.int_regfile_writes 384939818 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes +system.cpu.misc_regfile_reads 464692735 # number of misc regfile reads +system.cpu.misc_regfile_writes 832204 # number of misc regfile writes +system.cpu.icache.replacements 2508 # number of replacements +system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use +system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1367.286315 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.667620 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.667620 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37648759 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37648759 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37648759 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37648759 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37648759 # number of overall hits -system.cpu.icache.overall_hits::total 37648759 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5495 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5495 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5495 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5495 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5495 # number of overall misses -system.cpu.icache.overall_misses::total 5495 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 164010000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 164010000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 164010000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 164010000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 164010000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 164010000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37654254 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37654254 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37654254 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37654254 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37654254 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37654254 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29847.133758 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29847.133758 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29847.133758 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29847.133758 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 669 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36854521 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36854521 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits +system.cpu.icache.overall_hits::total 36854521 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses +system.cpu.icache.overall_misses::total 5339 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36859860 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36859860 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36859860 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29710.900730 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29710.900730 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29710.900730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29710.900730 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.166667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35.529412 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1106 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1106 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1106 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1106 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1106 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1106 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4389 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4389 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4389 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4389 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4389 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4389 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 126227500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 126227500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 126227500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 126227500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 126227500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 126227500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28759.968102 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28759.968102 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28759.968102 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28759.968102 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28759.968102 # average overall mshr miss latency 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34894208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30262 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 30262 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28451 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28451 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47258495 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47258495 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47258495 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47258495 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000057 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000057 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000205 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000205 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000205 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000205 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45479.462475 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45479.462475 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38644.436869 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38644.436869 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40033.704082 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40033.704082 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 45 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.363636 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6641 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6641 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7838 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7838 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7838 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7838 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1089 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1089 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38083000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38083000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 48635999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 48635999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86718999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 86718999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86718999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 86718999 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49139.354839 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49139.354839 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44661.156107 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44661.156107 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46523.068133 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46523.068133 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46523.068133 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46523.068133 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1988.724621 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2398 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2755 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.870417 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3.999610 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1449.117125 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 535.607885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.044224 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016345 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.060691 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits -system.cpu.l2cache.overall_hits::total 2405 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2079 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2764 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2079 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1765 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3844 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2079 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1765 # number of overall misses -system.cpu.l2cache.overall_misses::total 3844 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98742500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 36322000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 135064500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 47502500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 47502500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 98742500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 83824500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 182567000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 98742500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 83824500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 182567000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4387 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5160 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 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ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991736 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.991736 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.473900 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.947905 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.615138 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.473900 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.947905 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.615138 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47495.189995 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53024.817518 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48865.593343 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43983.796296 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43983.796296 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 47494.016649 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 47494.016649 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3828 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3828 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 72306456 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27405972 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 99712428 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33965187 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33965187 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72306456 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61371159 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 133677615 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72306456 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61371159 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 133677615 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532558 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.612578 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.612578 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34846.484819 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40722.098068 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36285.454148 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31449.247222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31449.247222 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index c4bf026a2..153c74c08 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,17 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -430,17 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -462,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -470,30 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -503,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -521,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 37b3dd11b..b5276d904 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:29:07 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 17:50:59 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +22,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 84416735500 because target called exit() +122 123 124 Exiting @ tick 82887492500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index e84462d08..664d70a56 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084675 # Number of seconds simulated -sim_ticks 84674525000 # Number of ticks simulated -final_tick 84674525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.082887 # Number of seconds simulated +sim_ticks 82887492500 # Number of ticks simulated +final_tick 82887492500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95140 # Simulator instruction rate (inst/s) -host_op_rate 159463 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60996786 # Simulator tick rate (ticks/s) -host_mem_usage 238356 # Number of bytes of host memory used -host_seconds 1388.18 # Real time elapsed on the host +host_inst_rate 73575 # Simulator instruction rate (inst/s) +host_op_rate 123318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46175257 # Simulator tick rate (ticks/s) +host_mem_usage 235032 # Number of bytes of host memory used +host_seconds 1795.06 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362960 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124736 # Number of bytes read from this memory -system.physmem.bytes_read::total 344640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219904 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3436 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1949 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5385 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2597050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1473123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4070173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2597050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2597050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2597050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1473123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4070173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5387 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 218112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124480 # Number of bytes read from this memory +system.physmem.bytes_read::total 342592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218112 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1945 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5353 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2631422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1501795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4133217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2631422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2631422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2631422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1501795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4133217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5355 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5559 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 344640 # Total number of bytes read from memory +system.physmem.cpureqs 5520 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 342592 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 344640 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 342592 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 172 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 307 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 316 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 330 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 309 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 435 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 355 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 165 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 321 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 434 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 352 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 293 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 84674494000 # Total gap between requests +system.physmem.totGap 82887463000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5387 # Categorize read packet sizes +system.physmem.readPktSize::6 5355 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,16 +95,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 172 # categorize neither packet sizes +system.physmem.neitherpktsize::6 165 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,266 +164,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 14711866 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 121393866 # Sum of mem lat for all requests -system.physmem.totBusLat 21548000 # Total cycles spent in databus access -system.physmem.totBankLat 85134000 # Total cycles spent in bank access -system.physmem.avgQLat 2730.99 # Average queueing delay per request -system.physmem.avgBankLat 15803.60 # Average bank access latency per request +system.physmem.totQLat 16692334 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 122490334 # Sum of mem lat for all requests +system.physmem.totBusLat 21420000 # Total cycles spent in databus access +system.physmem.totBankLat 84378000 # Total cycles spent in bank access +system.physmem.avgQLat 3117.15 # Average queueing delay per request +system.physmem.avgBankLat 15756.86 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22534.60 # Average memory access latency -system.physmem.avgRdBW 4.07 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22874.01 # Average memory access latency +system.physmem.avgRdBW 4.13 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.07 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.13 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4765 # Number of row buffer hits during reads +system.physmem.readRowHits 4747 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.45 # Row buffer hit rate for reads +system.physmem.readRowHitRate 88.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15718302.21 # Average gap between requests +system.physmem.avgGap 15478517.83 # Average gap between requests system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 169349051 # number of cpu cycles simulated +system.cpu.numCycles 165774986 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20696936 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20696936 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2256292 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15133236 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13734962 # Number of BTB hits +system.cpu.BPredUnit.lookups 19962549 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 19962549 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2008101 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13827383 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13115978 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27265023 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227328092 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20696936 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13734962 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59711428 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19294366 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 65485440 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1823 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 77 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25705537 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 473097 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169231475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.210885 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333405 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25874933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219082558 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19962549 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13115978 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 57603231 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17636080 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 66812180 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 382 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1920 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 86 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24490621 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 428850 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 165653450 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.184047 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324284 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 111185486 65.70% 65.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3235568 1.91% 67.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2477028 1.46% 69.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3104255 1.83% 70.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3512943 2.08% 72.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3722385 2.20% 75.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4581451 2.71% 77.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2802404 1.66% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34609955 20.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 109646244 66.19% 66.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3069160 1.85% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2390407 1.44% 69.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2911043 1.76% 71.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3444057 2.08% 73.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3578858 2.16% 75.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4315336 2.61% 78.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2737464 1.65% 79.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33560881 20.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169231475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122215 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.342364 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40175646 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55730709 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46717910 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9839836 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16767374 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365014393 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16767374 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47729605 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14672331 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23050 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48352284 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41686831 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355859336 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17343697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22236120 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 410085130 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 987094969 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 977133981 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9960988 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 165653450 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.120420 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.321566 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38806807 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56798437 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44693921 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9993567 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15360718 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 353645742 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 15360718 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 46261084 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 15045259 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23094 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46566997 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42396298 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 345315167 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 90 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18136112 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22140506 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 107 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 398865932 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 960470736 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 950586912 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9883824 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 150656527 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1756 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1746 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90004350 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89661097 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32850020 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59013027 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19193820 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 342911318 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4601 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 271901324 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 302838 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 121030414 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 246288577 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169231475 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.606683 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.513723 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 139437329 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1690 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1680 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90473578 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 86725107 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31801013 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58042243 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18917665 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 333696674 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3504 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 267486026 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 249957 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111886449 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 230098096 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2258 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 165653450 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.614733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.503292 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 47472289 28.05% 28.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47010231 27.78% 55.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33048937 19.53% 75.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20116720 11.89% 87.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13476087 7.96% 95.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4976431 2.94% 98.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2409834 1.42% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 570016 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 150930 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 45188105 27.28% 27.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46827780 28.27% 55.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32851570 19.83% 75.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19799355 11.95% 87.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13199962 7.97% 95.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4781234 2.89% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2328741 1.41% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 535047 0.32% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 141656 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169231475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 165653450 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133953 5.05% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2250624 84.89% 89.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 266784 10.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130850 4.93% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2255745 85.02% 89.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 266492 10.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212972 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177077896 65.13% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1583975 0.58% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68517375 25.20% 91.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23509106 8.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212176 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174220200 65.13% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1600871 0.60% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67180560 25.12% 91.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23272219 8.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 271901324 # Type of FU issued -system.cpu.iq.rate 1.605567 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2651361 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009751 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 710689981 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 459620232 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 264156330 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5298341 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4622160 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2541189 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 270684077 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2655636 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19034495 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 267486026 # Type of FU issued +system.cpu.iq.rate 1.613549 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2653087 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009919 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 698167044 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 441210039 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260260402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5361502 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4667533 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2580716 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266230560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2696377 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18979902 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33011511 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33645 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 301635 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12334304 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30075521 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29325 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 296266 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11285297 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49870 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 57 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49068 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16767374 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 579251 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 261764 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 342915919 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 264352 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89661097 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32850020 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1726 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 174105 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29972 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 301635 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1337300 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1023491 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2360791 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 268724619 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67385634 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3176705 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15360718 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 583386 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 263755 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 333700178 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 187889 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 86725107 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31801013 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1675 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 149208 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 31553 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 296266 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1173784 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 915890 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2089674 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264607897 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66196383 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2878129 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90490308 # number of memory reference insts executed -system.cpu.iew.exec_branches 14777839 # Number of branches executed -system.cpu.iew.exec_stores 23104674 # Number of stores executed -system.cpu.iew.exec_rate 1.586809 # Inst execution rate -system.cpu.iew.wb_sent 267641874 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266697519 # cumulative count of insts written-back -system.cpu.iew.wb_producers 215269478 # num instructions producing a value -system.cpu.iew.wb_consumers 378445061 # num instructions consuming a value +system.cpu.iew.exec_refs 89076319 # number of memory reference insts executed +system.cpu.iew.exec_branches 14601653 # Number of branches executed +system.cpu.iew.exec_stores 22879936 # Number of stores executed +system.cpu.iew.exec_rate 1.596187 # Inst execution rate +system.cpu.iew.wb_sent 263672307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 262841118 # cumulative count of insts written-back +system.cpu.iew.wb_producers 212055070 # num instructions producing a value +system.cpu.iew.wb_consumers 375144375 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.574839 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.568826 # average fanout of values written-back +system.cpu.iew.wb_rate 1.585529 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.565263 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 121635359 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 112374263 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2256476 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 152464101 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.451902 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.927405 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2008288 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150292732 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.472879 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.939566 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52775060 34.61% 34.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57579919 37.77% 72.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14057130 9.22% 81.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11929298 7.82% 89.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4294184 2.82% 92.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2937870 1.93% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1056484 0.69% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 997351 0.65% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6836805 4.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50934932 33.89% 33.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57339097 38.15% 72.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13849183 9.21% 81.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12078421 8.04% 89.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4153000 2.76% 92.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2960899 1.97% 94.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1067284 0.71% 94.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1009293 0.67% 95.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6900623 4.59% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 152464101 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 150292732 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -434,366 +434,366 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6836805 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6900623 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 488625615 # The number of ROB reads -system.cpu.rob.rob_writes 702805180 # The number of ROB writes -system.cpu.timesIdled 3014 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 117576 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 477129332 # The number of ROB reads +system.cpu.rob.rob_writes 682869787 # The number of ROB writes +system.cpu.timesIdled 2894 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 121536 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.282256 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.282256 # CPI: Total CPI of All Threads -system.cpu.ipc 0.779876 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.779876 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 567778401 # number of integer regfile reads -system.cpu.int_regfile_writes 302773713 # number of integer regfile writes -system.cpu.fp_regfile_reads 3495333 # number of floating regfile reads -system.cpu.fp_regfile_writes 2213146 # number of floating regfile writes -system.cpu.misc_regfile_reads 139456752 # number of misc regfile reads +system.cpu.cpi 1.255194 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.255194 # CPI: Total CPI of All Threads +system.cpu.ipc 0.796690 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.796690 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 562502955 # number of integer regfile reads +system.cpu.int_regfile_writes 298724994 # number of integer regfile writes +system.cpu.fp_regfile_reads 3533274 # number of floating regfile reads +system.cpu.fp_regfile_writes 2240391 # number of floating regfile writes +system.cpu.misc_regfile_reads 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68697960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68697960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68697960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68697960 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 67574425 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67574425 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67574425 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67574425 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46282.129743 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46282.129743 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44225.806452 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44225.806452 # average WriteReq miss latency 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WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000085 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52918.414918 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52918.414918 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42211.072664 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42211.072664 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44334.720296 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44334.720296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44334.720296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44334.720296 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52984.560570 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52984.560570 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42564.161850 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42564.161850 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44603.672710 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44603.672710 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44603.672710 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44603.672710 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2574.474688 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3918 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3834 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.021909 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.998861 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2280.064423 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 292.411404 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000061 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069582 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.008924 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.078567 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3883 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3915 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3883 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 40 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3923 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3883 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 40 # number of overall hits -system.cpu.l2cache.overall_hits::total 3923 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3436 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 396 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3832 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 172 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 172 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1555 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1555 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3436 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1951 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5387 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3436 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1951 # number of overall misses -system.cpu.l2cache.overall_misses::total 5387 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158572500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21872000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 180444500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67710500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 67710500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 158572500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 89582500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 248155000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 158572500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 89582500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 248155000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7319 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 428 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7747 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 172 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 172 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7319 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1991 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9310 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7319 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1991 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9310 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.469463 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.925234 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.494643 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994882 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.469463 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.979910 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.578625 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.469463 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.979910 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.578625 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46150.320140 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55232.323232 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 47088.856994 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43543.729904 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43543.729904 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46150.320140 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 45916.196822 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46065.528123 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46150.320140 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 45916.196822 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46065.528123 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3436 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 396 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3832 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 172 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 172 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3436 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5387 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3436 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5387 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115214557 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16918595 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132133152 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1720172 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1720172 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 47963988 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 47963988 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115214557 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64882583 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 180097140 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115214557 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64882583 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 180097140 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.925234 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.494643 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979910 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.578625 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979910 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.578625 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33531.594005 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42723.724747 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34481.511482 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30845.008360 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30845.008360 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33531.594005 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33256.065095 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33431.806200 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33531.594005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33256.065095 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33431.806200 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index f7aca5bc7..ab195624f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -62,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -92,22 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,22 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -148,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -155,24 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -182,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -200,7 +204,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -222,15 +226,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index da760535c..05dfd62f0 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 16:51:51 -gem5 started Aug 13 2012 17:17:12 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:20:12 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21979500 because target called exit() +Exiting @ tick 18737000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 823f9b4c3..6769b3cad 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18769500 # Number of ticks simulated -final_tick 18769500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18737000 # Number of ticks simulated +final_tick 18737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10228 # Simulator instruction rate (inst/s) -host_op_rate 10227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30039955 # Simulator tick rate (ticks/s) -host_mem_usage 216300 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host +host_inst_rate 37767 # Simulator instruction rate (inst/s) +host_op_rate 37763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 110721753 # Simulator tick rate (ticks/s) +host_mem_usage 213516 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1022936146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 572844242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1595780388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1022936146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1022936146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1022936146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 572844242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1595780388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1024710466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 573837861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1598548327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1024710466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1024710466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1024710466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 573837861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1598548327 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18755000 # Total gap between requests +system.physmem.totGap 18722500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -165,26 +165,26 @@ system.physmem.wrQLenPdf::30 0 # Wh system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 1862969 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11662969 # Sum of mem lat for all requests +system.physmem.totMemAccLat 11648969 # Sum of mem lat for all requests system.physmem.totBusLat 1876000 # Total cycles spent in databus access -system.physmem.totBankLat 7924000 # Total cycles spent in bank access +system.physmem.totBankLat 7910000 # Total cycles spent in bank access system.physmem.avgQLat 3972.22 # Average queueing delay per request -system.physmem.avgBankLat 16895.52 # Average bank access latency per request +system.physmem.avgBankLat 16865.67 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24867.74 # Average memory access latency -system.physmem.avgRdBW 1595.78 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24837.89 # Average memory access latency +system.physmem.avgRdBW 1598.55 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1595.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1598.55 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.97 # Data bus utilization in percentage +system.physmem.busUtil 9.99 # Data bus utilization in percentage system.physmem.avgRdQLen 0.62 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 401 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 39989.34 # Average gap between requests +system.physmem.avgGap 39920.04 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -201,10 +201,10 @@ system.cpu.dtb.data_hits 2048 # DT system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 909 # ITB hits +system.cpu.itb.fetch_hits 915 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 926 # ITB accesses +system.cpu.itb.fetch_accesses 932 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 37540 # number of cpu cycles simulated +system.cpu.numCycles 37475 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1605 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1125 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 713 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1185 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits +system.cpu.branch_predictor.lookups 1632 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1160 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 706 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1266 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 352 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 26.497890 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1141 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5235 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 27.804107 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5202 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9802 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9769 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2929 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2181 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 368 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 652 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 399 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.036156 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4462 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 2948 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2152 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 645 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 406 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.370124 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 4448 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11564 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11520 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 496 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30143 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7397 # Number of cycles cpu stages are processed. -system.cpu.activity 19.704315 # Percentage of cycles cpu is active +system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30101 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7374 # Number of cycles cpu stages are processed. +system.cpu.activity 19.677118 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -265,72 +265,72 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 5.874804 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 5.864632 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 5.874804 # CPI: Total CPI of All Threads -system.cpu.ipc 0.170218 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 5.864632 # CPI: Total CPI of All Threads +system.cpu.ipc 0.170514 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.170218 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32631 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4909 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.076718 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33667 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3873 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 10.316995 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33372 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4168 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 11.102824 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 36235 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.170514 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32551 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 13.139426 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33582 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 10.388259 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33313 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4162 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 11.106071 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 36170 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.476292 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33023 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4517 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 12.032499 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.482322 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 32961 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4514 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 12.045364 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.255742 # Cycle average of tags in use -system.cpu.icache.total_refs 556 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 143.133594 # Cycle average of tags in use +system.cpu.icache.total_refs 561 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.847176 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.863787 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.255742 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069949 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069949 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 556 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 556 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 556 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 556 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 556 # number of overall hits -system.cpu.icache.overall_hits::total 556 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 353 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 353 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 353 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 353 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 353 # number of overall misses -system.cpu.icache.overall_misses::total 353 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17380500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17380500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17380500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17380500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17380500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17380500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 909 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 909 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 909 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 909 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.388339 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.388339 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.388339 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.388339 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.388339 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.388339 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49236.543909 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49236.543909 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49236.543909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49236.543909 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 143.133594 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069889 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069889 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 561 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 561 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 561 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 561 # number of overall hits +system.cpu.icache.overall_hits::total 561 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 354 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 354 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 354 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 354 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 354 # number of overall misses +system.cpu.icache.overall_misses::total 354 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17402500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17402500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17402500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17402500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17402500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17402500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 915 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 915 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386885 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.386885 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.386885 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.386885 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.386885 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.386885 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49159.604520 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49159.604520 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49159.604520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49159.604520 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -339,154 +339,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 48 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 51 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 51 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 51 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 52 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 52 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 52 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14765000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14765000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14765000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14765000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14765000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14765000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332233 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.332233 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.332233 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48890.728477 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48890.728477 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14751500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14751500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48846.026490 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48846.026490 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 104.285094 # Cycle average of tags in use -system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 104.285094 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025460 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025460 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 515 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5354500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14914000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14914000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20268500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20268500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20268500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20268500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55201.030928 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55201.030928 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42611.428571 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42611.428571 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45343.400447 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45343.400447 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 279 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 279 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8753000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8753000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53463.157895 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53463.157895 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50328.767123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50328.767123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 200.317780 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 200.167240 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 143.356757 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.961023 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004375 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006113 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 143.234891 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.932349 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006109 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -504,17 +398,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14446500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19424000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3596500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14446500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8574000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23020500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14446500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8574000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23020500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14433000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4976500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19409500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3596000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14433000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8572500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23005500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14433000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8572500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23005500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -537,17 +431,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47995.016611 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52394.736842 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49050.505051 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49267.123288 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49084.221748 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49084.221748 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47950.166113 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52384.210526 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49013.888889 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49260.273973 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49260.273973 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49052.238806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49052.238806 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -567,17 +461,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10662000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10648000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14454120 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14440120 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10662000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10648000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17128216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10662000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17114216 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10648000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17128216 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17114216 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -589,17 +483,123 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35421.926910 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35375.415282 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36500.303030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36464.949495 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 104.225653 # Cycle average of tags in use +system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 104.225653 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025446 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025446 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 515 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1601 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1601 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1601 # number of overall hits +system.cpu.dcache.overall_hits::total 1601 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 350 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 350 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 447 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses +system.cpu.dcache.overall_misses::total 447 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5353500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5353500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14913500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14913500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20267000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20267000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20267000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20267000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55190.721649 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55190.721649 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42610 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42610 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45340.044743 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45340.044743 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 279 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 279 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3673500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3673500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8751500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8751500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53452.631579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53452.631579 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50321.917808 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50321.917808 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 6c764cc38..8465ac1d0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -448,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -455,24 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +504,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -522,15 +526,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index a77141c3d..9cdc62046 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 16:51:51 -gem5 started Aug 13 2012 17:17:12 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:20:12 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12735500 because target called exit() +Exiting @ tick 15802500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index fb45a6f1f..56f807ea0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 15653000 # Number of ticks simulated -final_tick 15653000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15802500 # Number of ticks simulated +final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 11804 # Simulator instruction rate (inst/s) -host_op_rate 11803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28994780 # Simulator tick rate (ticks/s) -host_mem_usage 217308 # Number of bytes of host memory used -host_seconds 0.54 # Real time elapsed on the host +host_inst_rate 38730 # Simulator instruction rate (inst/s) +host_op_rate 38726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96032767 # Simulator tick rate (ticks/s) +host_mem_usage 214332 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1279754680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 711429119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1991183799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1279754680 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1279754680 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1279754680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 711429119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1991183799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1267647524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 704698624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1972346148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1267647524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1267647524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1267647524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 704698624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1972346148 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 487 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady @@ -41,12 +41,12 @@ system.physmem.perBankRdReqs::1 18 # Tr system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 73 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15508000 # Total gap between requests +system.physmem.totGap 15655000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -99,9 +99,9 @@ system.physmem.neitherpktsize::6 0 # ca system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2668987 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12414987 # Sum of mem lat for all requests +system.physmem.totQLat 3073487 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12819487 # Sum of mem lat for all requests system.physmem.totBusLat 1948000 # Total cycles spent in databus access system.physmem.totBankLat 7798000 # Total cycles spent in bank access -system.physmem.avgQLat 5480.47 # Average queueing delay per request +system.physmem.avgQLat 6311.06 # Average queueing delay per request system.physmem.avgBankLat 16012.32 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25492.79 # Average memory access latency -system.physmem.avgRdBW 1991.18 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26323.38 # Average memory access latency +system.physmem.avgRdBW 1972.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1991.18 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1972.35 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.44 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.busUtil 12.33 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.81 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 417 # Number of row buffer hits during reads +system.physmem.readRowHits 416 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 31843.94 # Average gap between requests +system.physmem.avgGap 32145.79 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2048 # DTB read hits -system.cpu.dtb.read_misses 58 # DTB read misses +system.cpu.dtb.read_hits 2068 # DTB read hits +system.cpu.dtb.read_misses 50 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2106 # DTB read accesses -system.cpu.dtb.write_hits 1074 # DTB write hits -system.cpu.dtb.write_misses 32 # DTB write misses +system.cpu.dtb.read_accesses 2118 # DTB read accesses +system.cpu.dtb.write_hits 1071 # DTB write hits +system.cpu.dtb.write_misses 29 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1106 # DTB write accesses -system.cpu.dtb.data_hits 3122 # DTB hits -system.cpu.dtb.data_misses 90 # DTB misses +system.cpu.dtb.write_accesses 1100 # DTB write accesses +system.cpu.dtb.data_hits 3139 # DTB hits +system.cpu.dtb.data_misses 79 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3212 # DTB accesses -system.cpu.itb.fetch_hits 2395 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 3218 # DTB accesses +system.cpu.itb.fetch_hits 2370 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2433 # ITB accesses +system.cpu.itb.fetch_accesses 2409 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,243 +218,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 31307 # number of cpu cycles simulated +system.cpu.numCycles 31606 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2894 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1701 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 520 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2227 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 814 # Number of BTB hits +system.cpu.BPredUnit.lookups 2927 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1718 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 517 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2238 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 757 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 422 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 72 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8391 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16487 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1236 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2984 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1891 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 950 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 757 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2395 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 373 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.145010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.528367 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 420 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1177 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2985 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1897 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1074 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 762 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2370 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 362 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.161487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.555904 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11415 79.28% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 325 2.26% 81.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 232 1.61% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 251 1.74% 84.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 272 1.89% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 212 1.47% 88.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 276 1.92% 90.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 187 1.30% 91.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1229 8.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11431 79.29% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 317 2.20% 81.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 233 1.62% 83.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 212 1.47% 84.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 264 1.83% 86.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 229 1.59% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 265 1.84% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 186 1.29% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1279 8.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.092439 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.526623 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9352 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 969 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 14416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.092609 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.529773 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9179 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1146 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2779 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1211 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch +system.cpu.decode.UnblockCycles 90 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1222 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 249 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15295 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1211 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 276 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 373 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2656 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 325 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14562 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 299 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18155 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18138 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 15526 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1222 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9389 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 326 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2653 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 349 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14793 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 317 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 11113 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18446 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18429 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 714 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2751 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1359 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 6543 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 811 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2756 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12925 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10660 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6224 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3683 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.740329 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.373860 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10819 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6341 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.750486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.391653 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9938 69.02% 69.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1614 11.21% 80.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1141 7.92% 88.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 759 5.27% 93.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 488 3.39% 96.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 274 1.90% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 143 0.99% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.20% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9926 68.85% 68.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1619 11.23% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1135 7.87% 87.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 768 5.33% 93.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 481 3.34% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 285 1.98% 98.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 151 1.05% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 37 0.26% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14399 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14416 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 7.89% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 66 57.89% 65.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 34.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 14 11.97% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 64 54.70% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7159 67.16% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2350 22.05% 89.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1146 10.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7317 67.63% 67.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2355 21.77% 89.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1142 10.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10660 # Type of FU issued -system.cpu.iq.rate 0.340499 # Inst issue rate -system.cpu.iq.fu_busy_cnt 114 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010694 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35869 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19185 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9545 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10819 # Type of FU issued +system.cpu.iq.rate 0.342308 # Inst issue rate +system.cpu.iq.fu_busy_cnt 117 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010814 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19446 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9723 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10761 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10923 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1568 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1573 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 494 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 92 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 90 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1211 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13042 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2751 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1359 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1222 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 52 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13186 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 157 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2756 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1363 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 376 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 520 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10013 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2117 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 647 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 522 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10167 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88 # number of nop insts executed -system.cpu.iew.exec_refs 3225 # number of memory reference insts executed -system.cpu.iew.exec_branches 1609 # Number of branches executed -system.cpu.iew.exec_stores 1108 # Number of stores executed -system.cpu.iew.exec_rate 0.319833 # Inst execution rate -system.cpu.iew.wb_sent 9713 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9555 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5016 # num instructions producing a value -system.cpu.iew.wb_consumers 6802 # num instructions consuming a value +system.cpu.iew.exec_nop 87 # number of nop insts executed +system.cpu.iew.exec_refs 3231 # number of memory reference insts executed +system.cpu.iew.exec_branches 1614 # Number of branches executed +system.cpu.iew.exec_stores 1102 # Number of stores executed +system.cpu.iew.exec_rate 0.321679 # Inst execution rate +system.cpu.iew.wb_sent 9882 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9733 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5145 # num instructions producing a value +system.cpu.iew.wb_consumers 6933 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.305203 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737430 # average fanout of values written-back +system.cpu.iew.wb_rate 0.307948 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742103 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6652 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6795 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 438 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13188 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.484456 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.302208 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 435 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.484235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.303292 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10412 78.95% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1478 11.21% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 518 3.93% 94.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 238 1.80% 95.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 160 1.21% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 94 0.71% 97.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 109 0.83% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.27% 98.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 144 1.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10420 78.98% 78.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1475 11.18% 90.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 517 3.92% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 247 1.87% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 154 1.17% 97.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 92 0.70% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.80% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 146 1.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13194 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -465,70 +466,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 144 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 146 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25734 # The number of ROB reads -system.cpu.rob.rob_writes 27303 # The number of ROB writes -system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25881 # The number of ROB reads +system.cpu.rob.rob_writes 27599 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17190 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 4.913214 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.913214 # CPI: Total CPI of All Threads -system.cpu.ipc 0.203533 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.203533 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12695 # number of integer regfile reads -system.cpu.int_regfile_writes 7186 # number of integer regfile writes +system.cpu.cpi 4.960138 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.960138 # CPI: Total CPI of All Threads +system.cpu.ipc 0.201607 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.201607 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12907 # number of integer regfile reads +system.cpu.int_regfile_writes 7365 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.377030 # Cycle average of tags in use -system.cpu.icache.total_refs 1916 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 160.479269 # Cycle average of tags in use +system.cpu.icache.total_refs 1894 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.101911 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 6.031847 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.377030 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078309 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078309 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1916 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1916 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1916 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1916 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1916 # number of overall hits -system.cpu.icache.overall_hits::total 1916 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses -system.cpu.icache.overall_misses::total 479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21334000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21334000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21334000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21334000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21334000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21334000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2395 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2395 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2395 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2395 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2395 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2395 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.200000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.200000 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.200000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.200000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44538.622129 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44538.622129 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44538.622129 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44538.622129 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 160.479269 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078359 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078359 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1894 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1894 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1894 # number of demand (read+write) hits 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blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,154 +538,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 165 # number of overall MSHR hits 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overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15306500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15306500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15306500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15306500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15306500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15306500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131106 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131106 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131106 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48746.815287 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48746.815287 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15404000 # number of ReadReq MSHR miss cycles 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accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.132489 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49057.324841 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49057.324841 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.831538 # Cycle average of tags in use -system.cpu.dcache.total_refs 2240 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.873563 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.831538 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026326 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026326 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1734 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1734 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2240 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2240 # number of demand (read+write) hits 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of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15746484 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24054984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24054984 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24054984 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24054984 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084477 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.084477 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.188112 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.188112 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.188112 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.188112 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51928.125000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51928.125000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43862.072423 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43862.072423 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46348.716763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46348.716763 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 810 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.928571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 345 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 345 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6029500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6029500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3803500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3803500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9833000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9833000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9833000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9833000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59698.019802 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59698.019802 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52102.739726 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52102.739726 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 220.955415 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.902491 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 160.525117 # Average occupied blocks per requestor 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of demand (read+write) hits @@ -702,17 +597,17 @@ system.cpu.l2cache.demand_misses::total 487 # nu system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 487 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14981000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5921000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20902000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3727500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3727500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14981000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9648500 # number of demand (read+write) miss cycles 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11136994 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4966088 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16103082 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2842064 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2842064 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11136994 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7808152 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18945146 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11136994 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7808152 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18945146 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses @@ -787,17 +682,123 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35279.533546 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46322.613861 # average ReadReq mshr miss latency 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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35581.450479 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49169.188119 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38896.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38932.383562 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38932.383562 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 107.834334 # Cycle average of tags in use +system.cpu.dcache.total_refs 2264 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.011494 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 107.834334 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026327 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026327 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2264 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2264 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2264 # number of overall hits +system.cpu.dcache.overall_hits::total 2264 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) 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+system.cpu.dcache.ReadReq_accesses::cpu.data 1927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2792 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2792 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2792 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2792 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087701 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087701 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.189112 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.189112 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.189112 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.189112 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53642.011834 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53642.011834 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44115.554318 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44115.554318 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47164.742424 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47164.742424 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 801 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807692 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6319000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6319000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3813500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3813500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10132500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10132500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10132500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10132500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052413 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052413 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062321 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062321 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62564.356436 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62564.356436 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52239.726027 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52239.726027 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 35d1c924c..4d782f4dd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -448,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -455,24 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +504,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -522,15 +526,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 07442c5d8..8f40149c5 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:08:29 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:20:24 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7252000 because target called exit() +Exiting @ tick 9059000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 9eea9fb92..f9cbb8511 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9061000 # Number of ticks simulated -final_tick 9061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 9059000 # Number of ticks simulated +final_tick 9059000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62320 # Simulator instruction rate (inst/s) -host_op_rate 62299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 236406021 # Simulator tick rate (ticks/s) -host_mem_usage 216020 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 28083 # Simulator instruction rate (inst/s) +host_op_rate 28078 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 106544733 # Simulator tick rate (ticks/s) +host_mem_usage 213348 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1320825516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 600375235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1921200750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1320825516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1320825516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1320825516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 600375235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1921200750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1321117121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 600507782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1921624903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1321117121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1321117121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1321117121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 600507782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1921624903 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady @@ -36,7 +36,7 @@ system.physmem.bytesConsumedRd 17408 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis @@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 27 # Tr system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 8992500 # Total gap between requests +system.physmem.totGap 8990500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -100,8 +100,8 @@ system.physmem.neitherpktsize::7 0 # ca system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 149 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1105772 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6813772 # Sum of mem lat for all requests +system.physmem.totQLat 1180771 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6930771 # Sum of mem lat for all requests system.physmem.totBusLat 1088000 # Total cycles spent in databus access -system.physmem.totBankLat 4620000 # Total cycles spent in bank access -system.physmem.avgQLat 4065.34 # Average queueing delay per request -system.physmem.avgBankLat 16985.29 # Average bank access latency per request +system.physmem.totBankLat 4662000 # Total cycles spent in bank access +system.physmem.avgQLat 4341.07 # Average queueing delay per request +system.physmem.avgBankLat 17139.71 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25050.63 # Average memory access latency -system.physmem.avgRdBW 1921.20 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25480.78 # Average memory access latency +system.physmem.avgRdBW 1921.62 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1921.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1921.62 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 12.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.75 # Average read queue length over time +system.physmem.avgRdQLen 0.77 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 228 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33060.66 # Average gap between requests +system.physmem.avgGap 33053.31 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 743 # DTB read hits -system.cpu.dtb.read_misses 38 # DTB read misses +system.cpu.dtb.read_hits 717 # DTB read hits +system.cpu.dtb.read_misses 25 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 781 # DTB read accesses -system.cpu.dtb.write_hits 387 # DTB write hits -system.cpu.dtb.write_misses 24 # DTB write misses +system.cpu.dtb.read_accesses 742 # DTB read accesses +system.cpu.dtb.write_hits 359 # DTB write hits +system.cpu.dtb.write_misses 19 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 411 # DTB write accesses -system.cpu.dtb.data_hits 1130 # DTB hits -system.cpu.dtb.data_misses 62 # DTB misses +system.cpu.dtb.write_accesses 378 # DTB write accesses +system.cpu.dtb.data_hits 1076 # DTB hits +system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1192 # DTB accesses -system.cpu.itb.fetch_hits 1097 # ITB hits +system.cpu.dtb.data_accesses 1120 # DTB accesses +system.cpu.itb.fetch_hits 1063 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1127 # ITB accesses +system.cpu.itb.fetch_accesses 1093 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,245 +218,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 18123 # number of cpu cycles simulated +system.cpu.numCycles 18119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1200 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 612 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 260 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 849 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 266 # Number of BTB hits +system.cpu.BPredUnit.lookups 1180 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 594 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 261 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 806 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 235 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 229 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 227 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4258 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7288 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1200 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 495 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1268 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 917 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 438 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4211 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7069 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1180 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 462 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1219 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 881 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 344 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 961 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 959 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1097 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.961604 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.365122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1063 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 190 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.961769 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.375037 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6311 83.27% 83.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.70% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 134 1.77% 85.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 102 1.35% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 181 2.39% 89.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 82 1.08% 90.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 68 0.90% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.86% 92.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 583 7.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6131 83.41% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57 0.78% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 120 1.63% 85.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.29% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 168 2.29% 89.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 73 0.99% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 67 0.91% 91.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.87% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 575 7.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.066214 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.402141 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5340 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 471 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1207 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 547 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 173 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6471 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 7350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065125 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.390143 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5296 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 369 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1168 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 510 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 170 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6269 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 547 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5441 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 165 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 510 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5398 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 91 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 250 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1119 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 57 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 6174 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4474 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6979 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6967 # Number of integer rename lookups +system.cpu.rename.RunCycles 1075 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 26 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5981 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4351 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6729 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6717 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2706 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2583 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1006 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 508 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5283 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 979 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 463 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5055 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4254 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2663 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1563 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4086 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2501 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1445 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7579 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.561288 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.273203 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.555918 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.264810 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5858 77.29% 77.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 621 8.19% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 415 5.48% 90.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 261 3.44% 94.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 216 2.85% 97.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 132 1.74% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 51 0.67% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10 0.13% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5719 77.81% 77.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 555 7.55% 85.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 404 5.50% 90.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 261 3.55% 94.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 214 2.91% 97.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 126 1.71% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 50 0.68% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14 0.19% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7579 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7350 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.13% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 46.81% 48.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 24 51.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2999 70.50% 70.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 829 19.49% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 425 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2910 71.22% 71.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 789 19.31% 90.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 386 9.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4254 # Type of FU issued -system.cpu.iq.rate 0.234729 # Inst issue rate -system.cpu.iq.fu_busy_cnt 47 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011048 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 16186 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7949 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3830 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4086 # Type of FU issued +system.cpu.iq.rate 0.225509 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010768 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15607 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7560 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3685 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4294 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4123 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 591 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 564 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 214 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 169 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 547 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5652 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1006 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 508 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 510 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 82 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5405 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 979 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 463 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 155 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 217 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 4043 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 782 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 211 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 218 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3887 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 743 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 199 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363 # number of nop insts executed -system.cpu.iew.exec_refs 1193 # number of memory reference insts executed -system.cpu.iew.exec_branches 672 # Number of branches executed -system.cpu.iew.exec_stores 411 # Number of stores executed -system.cpu.iew.exec_rate 0.223087 # Inst execution rate -system.cpu.iew.wb_sent 3934 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3836 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1789 # num instructions producing a value -system.cpu.iew.wb_consumers 2358 # num instructions consuming a value +system.cpu.iew.exec_nop 344 # number of nop insts executed +system.cpu.iew.exec_refs 1121 # number of memory reference insts executed +system.cpu.iew.exec_branches 656 # Number of branches executed +system.cpu.iew.exec_stores 378 # Number of stores executed +system.cpu.iew.exec_rate 0.214526 # Inst execution rate +system.cpu.iew.wb_sent 3770 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3691 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1735 # num instructions producing a value +system.cpu.iew.wb_consumers 2218 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.211665 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.758694 # average fanout of values written-back +system.cpu.iew.wb_rate 0.203709 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.782236 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 3067 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2808 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 182 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7032 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.366325 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.202351 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 183 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.234221 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6145 87.39% 87.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 219 3.11% 90.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 312 4.44% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 120 1.71% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 65 0.92% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 56 0.80% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.47% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 21 0.30% 99.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 61 0.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5975 87.35% 87.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 201 2.94% 90.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 309 4.52% 94.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 115 1.68% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 68 0.99% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 49 0.72% 98.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.48% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23 0.34% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7032 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -467,69 +467,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12367 # The number of ROB reads -system.cpu.rob.rob_writes 11843 # The number of ROB writes +system.cpu.rob.rob_reads 11910 # The number of ROB reads +system.cpu.rob.rob_writes 11291 # The number of ROB writes system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 10769 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 7.592375 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.592375 # CPI: Total CPI of All Threads -system.cpu.ipc 0.131711 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.131711 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4904 # number of integer regfile reads -system.cpu.int_regfile_writes 2974 # number of integer regfile writes +system.cpu.cpi 7.590700 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.590700 # CPI: Total CPI of All Threads +system.cpu.ipc 0.131740 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.131740 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4685 # number of integer regfile reads +system.cpu.int_regfile_writes 2864 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 92.415859 # Cycle average of tags in use -system.cpu.icache.total_refs 849 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 92.986102 # Cycle average of tags in use +system.cpu.icache.total_refs 813 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.540107 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.347594 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 92.415859 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045125 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045125 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 849 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 849 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 849 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 849 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 849 # number of overall hits -system.cpu.icache.overall_hits::total 849 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses -system.cpu.icache.overall_misses::total 248 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11771499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11771499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11771499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11771499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11771499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11771499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1097 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1097 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1097 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1097 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.226071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.226071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.226071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.226071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.226071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.226071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47465.721774 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47465.721774 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47465.721774 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47465.721774 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47465.721774 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47465.721774 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 92.986102 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045403 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045403 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 813 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 813 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 813 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 813 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 813 # number of overall hits +system.cpu.icache.overall_hits::total 813 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11955999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11955999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11955999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11955999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11955999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11955999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1063 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1063 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1063 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1063 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235183 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.235183 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.235183 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.235183 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.235183 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.235183 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47823.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47823.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47823.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47823.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -538,154 +538,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 34 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9118999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9118999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9118999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9118999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9118999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9118999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170465 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.170465 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.170465 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48764.700535 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48764.700535 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48764.700535 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48764.700535 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48764.700535 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48764.700535 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9236999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9236999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175917 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.175917 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.175917 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49395.716578 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49395.716578 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.370052 # Cycle average of tags in use -system.cpu.dcache.total_refs 789 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.282353 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.370052 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011077 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011077 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 576 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 576 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 789 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 789 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 789 # number of overall hits -system.cpu.dcache.overall_hits::total 789 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 204 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 204 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 204 # number of overall misses -system.cpu.dcache.overall_misses::total 204 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5446500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5446500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4115000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9561500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9561500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9561500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9561500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 699 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 699 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 993 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 993 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 993 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 993 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.175966 # 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average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46870.098039 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46870.098039 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46870.098039 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46870.098039 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # 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number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -760,17 +654,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6582780 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2536058 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9118838 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6701279 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2512062 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9213341 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35202.032086 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41574.721311 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36769.508065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35835.716578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41181.344262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37150.568548 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42792.666667 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42792.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41918.611765 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5152500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4115500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9268000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9268000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9268000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9268000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 966 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 966 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 966 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 966 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.165179 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.165179 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.198758 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.198758 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.198758 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.198758 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46418.918919 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46418.918919 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50808.641975 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 50808.641975 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48270.833333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48270.833333 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 107 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 107 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 107 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3326500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3326500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1349500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1349500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4676000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4676000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4676000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4676000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090774 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090774 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087992 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087992 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54532.786885 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54532.786885 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56229.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56229.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 6e3934424..6a6ed7d49 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -128,7 +128,7 @@ icache_port=system.cpu.icache.cpu_side type=O3Checker children=dtb itb tracer checker=Null -clock=1 +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -161,7 +161,7 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] @@ -174,7 +174,7 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[4] @@ -187,18 +187,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -217,7 +217,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -490,18 +490,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -523,7 +523,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -531,24 +531,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -558,10 +558,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port @@ -598,15 +598,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 425371c96..edb619587 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:20:03 +gem5 compiled Nov 1 2012 15:18:10 +gem5 started Nov 1 2012 22:40:56 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10738000 because target called exit() +Exiting @ tick 13371000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ccb8279d9..0b4c661be 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,47 +1,47 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13414500 # Number of ticks simulated -final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13371000 # Number of ticks simulated +final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59216 # Simulator instruction rate (inst/s) -host_op_rate 73866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172781643 # Simulator tick rate (ticks/s) -host_mem_usage 231444 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 32660 # Simulator instruction rate (inst/s) +host_op_rate 40743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 94998008 # Simulator tick rate (ticks/s) +host_mem_usage 228356 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401 # Total number of read requests seen +system.physmem.num_reads::total 394 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 25600 # Total number of bytes read from memory +system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25216 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis @@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 28 # Tr system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13356500 # Total gap between requests +system.physmem.totGap 13312500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 401 # Categorize read packet sizes +system.physmem.readPktSize::6 394 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2497399 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests -system.physmem.totBusLat 1604000 # Total cycles spent in databus access -system.physmem.totBankLat 6636000 # Total cycles spent in bank access -system.physmem.avgQLat 6227.93 # Average queueing delay per request -system.physmem.avgBankLat 16548.63 # Average bank access latency per request +system.physmem.totQLat 2460894 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests +system.physmem.totBusLat 1576000 # Total cycles spent in databus access +system.physmem.totBankLat 6524000 # Total cycles spent in bank access +system.physmem.avgQLat 6245.92 # Average queueing delay per request +system.physmem.avgBankLat 16558.38 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26776.56 # Average memory access latency -system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26804.30 # Average memory access latency +system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.93 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.80 # Average read queue length over time +system.physmem.busUtil 11.79 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 326 # Number of row buffer hits during reads +system.physmem.readRowHits 319 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33307.98 # Average gap between requests +system.physmem.avgGap 33788.07 # Average gap between requests system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -273,245 +273,244 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 26830 # number of cpu cycles simulated +system.cpu.numCycles 26743 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2508 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect +system.cpu.BPredUnit.lookups 2505 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits +system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2440 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2245 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2446 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2247 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8896 # Type of FU issued -system.cpu.iq.rate 0.331569 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8988 # Type of FU issued +system.cpu.iq.rate 0.336088 # Inst issue rate +system.cpu.iq.fu_busy_cnt 228 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3284 # number of memory reference insts executed -system.cpu.iew.exec_branches 1437 # Number of branches executed -system.cpu.iew.exec_stores 1174 # Number of stores executed -system.cpu.iew.exec_rate 0.316996 # Inst execution rate -system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8071 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3897 # num instructions producing a value -system.cpu.iew.wb_consumers 7827 # num instructions consuming a value +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3300 # number of memory reference insts executed +system.cpu.iew.exec_branches 1446 # Number of branches executed +system.cpu.iew.exec_stores 1164 # Number of stores executed +system.cpu.iew.exec_rate 0.320233 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8109 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3899 # num instructions producing a value +system.cpu.iew.wb_consumers 7837 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back +system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -522,69 +521,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23385 # The number of ROB reads -system.cpu.rob.rob_writes 23680 # The number of ROB writes -system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22988 # The number of ROB reads +system.cpu.rob.rob_writes 23599 # The number of ROB writes +system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39120 # number of integer regfile reads -system.cpu.int_regfile_writes 7969 # number of integer regfile writes +system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39369 # number of integer regfile reads +system.cpu.int_regfile_writes 8027 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15172 # number of misc regfile reads +system.cpu.misc_regfile_reads 15007 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use -system.cpu.icache.total_refs 1570 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use +system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1570 # number of overall hits -system.cpu.icache.overall_hits::total 1570 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses -system.cpu.icache.overall_misses::total 373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1943 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1943 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1943 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1943 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191971 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.191971 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.191971 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.191971 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.191971 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.191971 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47356.568365 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47356.568365 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47356.568365 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47356.568365 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits +system.cpu.icache.overall_hits::total 1601 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses +system.cpu.icache.overall_misses::total 359 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -593,236 +592,236 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 60 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 75 # number 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(read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14464500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14464500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14464500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153371 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153371 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.153371 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48538.590604 # average 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(read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.306986 # Cycle average of tags in use -system.cpu.dcache.total_refs 2349 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.979592 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use +system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.306986 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021071 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021071 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1728 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1728 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor 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overall hits -system.cpu.dcache.overall_hits::total 2324 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 201 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 201 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits +system.cpu.dcache.overall_hits::total 2371 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 518 # number of overall misses -system.cpu.dcache.overall_misses::total 518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8747500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8747500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15091000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15091000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses +system.cpu.dcache.overall_misses::total 498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23838500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23838500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23838500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23838500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1929 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1929 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2842 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2842 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2842 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2842 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.104199 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.104199 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182266 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182266 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182266 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182266 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43519.900498 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43519.900498 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47605.678233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47605.678233 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46020.270270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46020.270270 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 95 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 370 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 370 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 370 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 370 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 351 # number 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-system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index f5b7d940d..c182ad17a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index dc9a7546c..116fbeb57 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:19:07 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 18:52:17 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10738000 because target called exit() +Exiting @ tick 13371000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 62de1d1aa..76131bc35 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,47 +1,47 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13414500 # Number of ticks simulated -final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13371000 # Number of ticks simulated +final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64991 # Simulator instruction rate (inst/s) -host_op_rate 81070 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189628588 # Simulator tick rate (ticks/s) -host_mem_usage 230428 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 37264 # Simulator instruction rate (inst/s) +host_op_rate 46486 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108387516 # Simulator tick rate (ticks/s) +host_mem_usage 228452 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401 # Total number of read requests seen +system.physmem.num_reads::total 394 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 25600 # Total number of bytes read from memory +system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25216 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis @@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 28 # Tr system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13356500 # Total gap between requests +system.physmem.totGap 13312500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 401 # Categorize read packet sizes +system.physmem.readPktSize::6 394 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2497399 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests -system.physmem.totBusLat 1604000 # Total cycles spent in databus access -system.physmem.totBankLat 6636000 # Total cycles spent in bank access -system.physmem.avgQLat 6227.93 # Average queueing delay per request -system.physmem.avgBankLat 16548.63 # Average bank access latency per request +system.physmem.totQLat 2460894 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests +system.physmem.totBusLat 1576000 # Total cycles spent in databus access +system.physmem.totBankLat 6524000 # Total cycles spent in bank access +system.physmem.avgQLat 6245.92 # Average queueing delay per request +system.physmem.avgBankLat 16558.38 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26776.56 # Average memory access latency -system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26804.30 # Average memory access latency +system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.93 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.80 # Average read queue length over time +system.physmem.busUtil 11.79 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 326 # Number of row buffer hits during reads +system.physmem.readRowHits 319 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33307.98 # Average gap between requests +system.physmem.avgGap 33788.07 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,245 +228,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 26830 # number of cpu cycles simulated +system.cpu.numCycles 26743 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2508 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect +system.cpu.BPredUnit.lookups 2505 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits +system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2440 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2245 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2446 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2247 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8896 # Type of FU issued -system.cpu.iq.rate 0.331569 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8988 # Type of FU issued +system.cpu.iq.rate 0.336088 # Inst issue rate +system.cpu.iq.fu_busy_cnt 228 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3284 # number of memory reference insts executed -system.cpu.iew.exec_branches 1437 # Number of branches executed -system.cpu.iew.exec_stores 1174 # Number of stores executed -system.cpu.iew.exec_rate 0.316996 # Inst execution rate -system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8071 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3897 # num instructions producing a value -system.cpu.iew.wb_consumers 7827 # num instructions consuming a value +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3300 # number of memory reference insts executed +system.cpu.iew.exec_branches 1446 # Number of branches executed +system.cpu.iew.exec_stores 1164 # Number of stores executed +system.cpu.iew.exec_rate 0.320233 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8109 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3899 # num instructions producing a value +system.cpu.iew.wb_consumers 7837 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back +system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -477,69 +476,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23385 # The number of ROB reads -system.cpu.rob.rob_writes 23680 # The number of ROB writes -system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22988 # The number of ROB reads +system.cpu.rob.rob_writes 23599 # The number of ROB writes +system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39120 # number of integer regfile reads -system.cpu.int_regfile_writes 7969 # number of integer regfile writes +system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39369 # number of integer regfile reads +system.cpu.int_regfile_writes 8027 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15172 # number of misc regfile reads +system.cpu.misc_regfile_reads 15007 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use -system.cpu.icache.total_refs 1570 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use +system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1570 # number of overall hits -system.cpu.icache.overall_hits::total 1570 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses -system.cpu.icache.overall_misses::total 373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1943 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1943 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1943 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1943 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191971 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.191971 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.191971 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.191971 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.191971 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.191971 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47356.568365 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47356.568365 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47356.568365 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47356.568365 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits +system.cpu.icache.overall_hits::total 1601 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses +system.cpu.icache.overall_misses::total 359 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1960 # number 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of tags in use -system.cpu.dcache.total_refs 2349 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.979592 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use +system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.306986 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021071 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021071 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1728 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1728 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2324 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2324 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2324 # number of overall hits -system.cpu.dcache.overall_hits::total 2324 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 201 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 201 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits +system.cpu.dcache.overall_hits::total 2371 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 518 # number of overall misses -system.cpu.dcache.overall_misses::total 518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8747500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8747500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15091000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15091000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses +system.cpu.dcache.overall_misses::total 498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23838500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23838500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23838500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23838500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1929 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1929 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2842 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2842 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2842 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2842 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.104199 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.104199 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182266 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182266 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182266 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182266 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43519.900498 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43519.900498 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47605.678233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47605.678233 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46020.270270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46020.270270 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 95 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 370 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 370 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 370 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 370 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4906000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4906000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2418500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2418500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7324500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7324500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7324500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7324500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.052076 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.052076 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46283.018868 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46283.018868 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57583.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57583.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 186.094427 # Cycle average of tags in use -system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.048248 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.046179 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004274 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001405 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits -system.cpu.l2cache.overall_hits::total 41 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 405 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13965500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4578500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2375500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2375500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13965500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6954000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20919500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13965500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6954000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20919500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 404 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 446 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 446 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932886 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.801887 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.898515 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932886 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.858108 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908072 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932886 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.858108 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908072 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50235.611511 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53864.705882 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51085.399449 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56559.523810 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56559.523810 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51653.086420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51653.086420 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10474409 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3438066 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13912475 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1855540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1855540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10474409 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5293606 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 1ce31c334..bda1e98df 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -64,7 +64,7 @@ icache_port=system.membus.slave[1] type=DummyChecker children=dtb itb tracer checker=Null -clock=1 +clock=500 cpu_id=-1 defer_registration=false do_checkpoint_insts=true @@ -94,7 +94,7 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system @@ -106,7 +106,7 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system @@ -121,7 +121,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -137,7 +137,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -177,7 +177,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index 21ae26652..57c2a5d84 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:19:07 +gem5 compiled Nov 1 2012 15:18:10 +gem5 started Nov 1 2012 22:41:17 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 592f491b0..147a664f0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92985 # Simulator instruction rate (inst/s) -host_op_rate 115998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58104040 # Simulator tick rate (ticks/s) -host_mem_usage 217212 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 135088 # Simulator instruction rate (inst/s) +host_op_rate 168502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84394877 # Simulator tick rate (ticks/s) +host_mem_usage 218472 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index a81f3fb10..df7d00601 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -62,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -92,22 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,22 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -148,6 +149,11 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=MipsInterrupts +[system.cpu.isa] +type=MipsISA +num_threads=1 +num_vpes=1 + [system.cpu.itb] type=MipsTLB size=64 @@ -155,24 +161,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -182,10 +188,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -200,7 +206,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -222,15 +228,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 893f17599..75053b5ab 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:00:38 -gem5 started Aug 13 2012 18:11:29 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:08:52 +gem5 started Oct 30 2012 13:57:29 +gem5 executing on u200540-lin command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 20518000 because target called exit() +Exiting @ tick 18578000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 02dd2c613..5bb87ba63 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18578000 # Number of ticks simulated final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97793 # Simulator instruction rate (inst/s) -host_op_rate 97754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 312246493 # Simulator tick rate (ticks/s) -host_mem_usage 216964 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 59954 # Simulator instruction rate (inst/s) +host_op_rate 59945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191522194 # Simulator tick rate (ticks/s) +host_mem_usage 214528 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2353954 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12657954 # Sum of mem lat for all requests +system.physmem.totQLat 2354454 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12658454 # Sum of mem lat for all requests system.physmem.totBusLat 1820000 # Total cycles spent in databus access system.physmem.totBankLat 8484000 # Total cycles spent in bank access -system.physmem.avgQLat 5173.53 # Average queueing delay per request +system.physmem.avgQLat 5174.62 # Average queueing delay per request system.physmem.avgBankLat 18646.15 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27819.68 # Average memory access latency +system.physmem.avgMemAccLat 27820.78 # Average memory access latency system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s @@ -207,34 +207,34 @@ system.cpu.workload.num_syscalls 8 # Nu system.cpu.numCycles 37157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1146 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 844 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 861 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 300 # Number of BTB hits +system.cpu.branch_predictor.lookups 1154 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 858 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 603 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 877 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 336 # Number of BTB hits system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.BTBHitPct 38.312429 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1290 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2235 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 596 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 319 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 65.136612 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3144 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 1292 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2229 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 274 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 594 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 321 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 64.918033 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3135 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9465 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9462 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed @@ -257,66 +257,66 @@ system.cpu.cpi_total 6.390953 # CP system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33517 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.796270 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34336 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2821 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.592109 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34391 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.444089 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 33508 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3649 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 9.820491 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34341 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2816 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.578653 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34392 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.441397 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 34254 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2903 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.812794 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 34255 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.810103 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 149.857420 # Cycle average of tags in use -system.cpu.icache.total_refs 410 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 149.849185 # Cycle average of tags in use +system.cpu.icache.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.857420 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073173 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073173 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 410 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 410 # number of overall hits -system.cpu.icache.overall_hits::total 410 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 149.849185 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073169 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073169 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits +system.cpu.icache.overall_hits::total 428 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses system.cpu.icache.overall_misses::total 346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18065500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18065500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18065500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18065500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18065500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18065500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 756 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 756 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 756 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 756 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 756 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 756 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.457672 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.457672 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.457672 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.457672 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.457672 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.457672 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52212.427746 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52212.427746 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52212.427746 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52212.427746 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18063500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18063500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18063500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18063500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18063500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18063500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 774 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 774 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 774 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.447028 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.447028 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.447028 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.447028 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.447028 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.447028 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52206.647399 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52206.647399 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52206.647399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52206.647399 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -337,140 +337,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16466000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16466000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16466000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16466000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16466000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16466000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.421958 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.421958 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.421958 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51617.554859 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51617.554859 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16468000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16468000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.412145 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.412145 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.412145 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51623.824451 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51623.824451 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.860913 # Cycle average of tags in use -system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.860913 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021939 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021939 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1644 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1644 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1644 # number of overall hits -system.cpu.dcache.overall_hits::total 1644 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 93 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 351 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 351 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 444 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses -system.cpu.dcache.overall_misses::total 444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5589000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14658500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14658500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20247500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20247500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20247500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20247500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.379459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.379459 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60096.774194 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60096.774194 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41762.108262 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41762.108262 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45602.477477 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45602.477477 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7773500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7773500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59252.873563 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59252.873563 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 207.494837 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 207.484772 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 151.607312 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.887525 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004627 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 151.598539 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.886233 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004626 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits @@ -490,17 +384,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16120500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5061500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21182000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16122500 # number of ReadReq miss cycles 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# number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7626500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23749000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16122500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7626500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23749000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -523,17 +417,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50853.312303 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58178.160920 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52430.693069 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50859.621451 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58183.908046 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52436.881188 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52190.109890 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52190.109890 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52195.604396 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52195.604396 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -553,17 +447,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12117017 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982094 # number of ReadReq MSHR miss cycles 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12117017 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5911666 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18028683 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12118017 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5912166 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18030183 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12118017 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5912166 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18030183 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -575,17 +469,123 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38224.028391 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45771.195402 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39849.284653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38227.182965 # average ReadReq mshr miss latency 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Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 89.859083 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021938 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021938 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1644 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1644 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1644 # number of overall hits +system.cpu.dcache.overall_hits::total 1644 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 93 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 351 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 351 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 444 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses +system.cpu.dcache.overall_misses::total 444 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5589500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14659500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14659500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20249000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20249000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20249000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20249000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses 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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60102.150538 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60102.150538 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41764.957265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41764.957265 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45605.855856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45605.855856 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7774000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7774000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7774000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7774000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59258.620690 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59258.620690 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 453ce4d95..6eeed9c1d 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -448,6 +449,11 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=MipsInterrupts +[system.cpu.isa] +type=MipsISA +num_threads=1 +num_vpes=1 + [system.cpu.itb] type=MipsTLB size=64 @@ -455,24 +461,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +488,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +506,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -522,15 +528,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 56b18a79d..5f05c3882 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:00:38 -gem5 started Aug 13 2012 18:11:40 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:08:52 +gem5 started Oct 30 2012 13:57:41 +gem5 executing on u200540-lin command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12925500 because target called exit() +Exiting @ tick 16532500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 7222464d9..d0a749f15 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16437500 # Number of ticks simulated -final_tick 16437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16532500 # Number of ticks simulated +final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79981 # Simulator instruction rate (inst/s) -host_op_rate 79951 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 254800448 # Simulator tick rate (ticks/s) -host_mem_usage 217976 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 48770 # Simulator instruction rate (inst/s) +host_op_rate 48763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 156337427 # Simulator tick rate (ticks/s) +host_mem_usage 215260 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 30720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21696 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 480 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1319908745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 548988593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1868897338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1319908745 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1319908745 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1319908745 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 548988593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1868897338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 480 # Total number of read requests seen +system.physmem.num_reads::total 476 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1296839558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 545833963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1842673522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1296839558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1296839558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1296839558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 545833963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1842673522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30720 # Total number of bytes read from memory +system.physmem.cpureqs 476 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30464 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30720 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30464 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -41,7 +41,7 @@ system.physmem.perBankRdReqs::1 30 # Tr system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis @@ -49,9 +49,9 @@ system.physmem.perBankRdReqs::9 18 # Tr system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16357500 # Total gap between requests +system.physmem.totGap 16452500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 480 # Categorize read packet sizes +system.physmem.readPktSize::6 476 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2266480 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12950480 # Sum of mem lat for all requests -system.physmem.totBusLat 1920000 # Total cycles spent in databus access -system.physmem.totBankLat 8764000 # Total cycles spent in bank access -system.physmem.avgQLat 4721.83 # Average queueing delay per request -system.physmem.avgBankLat 18258.33 # Average bank access latency per request +system.physmem.totQLat 2527972 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13083972 # Sum of mem lat for all requests +system.physmem.totBusLat 1904000 # Total cycles spent in databus access +system.physmem.totBankLat 8652000 # Total cycles spent in bank access +system.physmem.avgQLat 5310.87 # Average queueing delay per request +system.physmem.avgBankLat 18176.47 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26980.17 # Average memory access latency -system.physmem.avgRdBW 1868.90 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27487.34 # Average memory access latency +system.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1868.90 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.68 # Data bus utilization in percentage +system.physmem.busUtil 11.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 378 # Number of row buffer hits during reads +system.physmem.readRowHits 376 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.75 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34078.12 # Average gap between requests +system.physmem.avgGap 34564.08 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -204,243 +204,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 32876 # number of cpu cycles simulated +system.cpu.numCycles 33066 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2145 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1420 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 444 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1692 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 498 # Number of BTB hits +system.cpu.BPredUnit.lookups 2120 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1453 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1651 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 517 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 258 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8858 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13016 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2145 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 768 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3241 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 897 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8641 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2015 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14043 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.926867 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.227706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10802 76.92% 76.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1358 9.67% 86.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 113 0.80% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 147 1.05% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.17% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 111 0.79% 91.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 157 1.12% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 126 0.90% 93.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 924 6.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10748 77.06% 77.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1351 9.69% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 103 0.74% 87.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 137 0.98% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 291 2.09% 90.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 93 0.67% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 169 1.21% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 155 1.11% 93.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 900 6.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14043 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065245 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.395912 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8962 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1117 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3062 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 858 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction +system.cpu.fetch.rateDist::total 13947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064114 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.390008 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8777 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1236 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3037 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 851 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 137 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 12081 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 858 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9149 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking +system.cpu.decode.SquashedInsts 166 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 851 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8957 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 360 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 762 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2921 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11564 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 95 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7026 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13727 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13723 # Number of integer rename lookups +system.cpu.rename.RunCycles 2904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 113 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11654 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 97 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7041 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13857 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13853 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3628 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3643 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 17 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 273 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1184 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 265 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1198 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9022 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9172 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8202 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3390 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1898 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8209 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3542 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2140 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14043 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.584063 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.245002 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.588585 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.249847 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10483 74.65% 74.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1421 10.12% 84.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 877 6.25% 91.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 557 3.97% 94.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 353 2.51% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 225 1.60% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 84 0.60% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10394 74.52% 74.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1403 10.06% 84.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 889 6.37% 90.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 554 3.97% 94.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 357 2.56% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 219 1.57% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 88 0.63% 99.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14043 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13947 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 1.96% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 97 63.40% 65.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 53 34.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.73% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 100 62.11% 65.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 55 34.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4842 59.03% 59.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2249 27.42% 86.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1102 13.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4835 58.90% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 58.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2260 27.53% 86.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1105 13.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8202 # Type of FU issued -system.cpu.iq.rate 0.249483 # Inst issue rate -system.cpu.iq.fu_busy_cnt 153 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018654 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30641 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12433 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7364 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8209 # Type of FU issued +system.cpu.iq.rate 0.248261 # Inst issue rate +system.cpu.iq.fu_busy_cnt 161 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019613 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30577 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12735 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7402 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8353 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8368 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1275 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1313 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 273 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 858 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 190 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10500 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1184 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 851 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 242 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10697 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1198 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 363 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 471 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7830 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2115 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 372 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 330 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 433 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7849 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2119 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 360 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1465 # number of nop insts executed -system.cpu.iew.exec_refs 3191 # number of memory reference insts executed -system.cpu.iew.exec_branches 1342 # Number of branches executed -system.cpu.iew.exec_stores 1076 # Number of stores executed -system.cpu.iew.exec_rate 0.238168 # Inst execution rate -system.cpu.iew.wb_sent 7455 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7366 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2870 # num instructions producing a value -system.cpu.iew.wb_consumers 4099 # num instructions consuming a value +system.cpu.iew.exec_nop 1512 # number of nop insts executed +system.cpu.iew.exec_refs 3196 # number of memory reference insts executed +system.cpu.iew.exec_branches 1341 # Number of branches executed +system.cpu.iew.exec_stores 1077 # Number of stores executed +system.cpu.iew.exec_rate 0.237374 # Inst execution rate +system.cpu.iew.wb_sent 7488 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7404 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2925 # num instructions producing a value +system.cpu.iew.wb_consumers 4228 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.224054 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.700171 # average fanout of values written-back +system.cpu.iew.wb_rate 0.223916 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691816 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4679 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4876 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 399 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13185 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.440880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.228954 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 377 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13096 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.443876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.229358 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10802 81.93% 81.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 977 7.41% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 629 4.77% 94.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 318 2.41% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 150 1.14% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 86 0.65% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 74 0.56% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.32% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10722 81.87% 81.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 944 7.21% 89.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 654 4.99% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 320 2.44% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 142 1.08% 97.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 103 0.79% 98.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.50% 98.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.31% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13185 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13096 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -451,286 +452,180 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23557 # The number of ROB reads -system.cpu.rob.rob_writes 21850 # The number of ROB writes +system.cpu.rob.rob_reads 23666 # The number of ROB reads +system.cpu.rob.rob_writes 22238 # The number of ROB writes system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18833 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19119 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 6.376261 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.376261 # CPI: Total CPI of All Threads -system.cpu.ipc 0.156832 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.156832 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10643 # number of integer regfile reads -system.cpu.int_regfile_writes 5150 # number of integer regfile writes +system.cpu.cpi 6.413111 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.413111 # CPI: Total CPI of All Threads +system.cpu.ipc 0.155931 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.155931 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10670 # number of integer regfile reads +system.cpu.int_regfile_writes 5185 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 154 # number of misc regfile reads +system.cpu.misc_regfile_reads 147 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 164.359097 # Cycle average of tags in use -system.cpu.icache.total_refs 1560 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.561404 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 163.149412 # Cycle average of tags in use +system.cpu.icache.total_refs 1502 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 164.359097 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080253 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080253 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1560 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1560 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1560 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1560 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1560 # number of overall hits -system.cpu.icache.overall_hits::total 1560 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses -system.cpu.icache.overall_misses::total 455 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21541500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21541500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21541500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21541500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21541500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21541500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2015 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2015 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2015 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2015 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2015 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2015 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.225806 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.225806 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.225806 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.225806 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.225806 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.225806 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47343.956044 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47343.956044 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47343.956044 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47343.956044 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 163.149412 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079663 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079663 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits +system.cpu.icache.overall_hits::total 1502 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses +system.cpu.icache.overall_misses::total 446 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21402000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21402000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21402000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21402000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21402000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21402000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47986.547085 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47986.547085 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47986.547085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47986.547085 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17063000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17063000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17063000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17063000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17063000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17063000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.169727 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.169727 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.169727 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49891.812865 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49891.812865 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49891.812865 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49891.812865 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49891.812865 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49891.812865 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16954500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16954500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173511 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.173511 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.173511 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50161.242604 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50161.242604 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 91.458224 # Cycle average of tags in use -system.cpu.dcache.total_refs 2418 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.148936 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993737 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36641.722714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46867.511111 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38786.993007 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36904.611940 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48228.588889 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39302.630588 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 92.011405 # Cycle average of tags in use +system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 17.163121 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 92.011405 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022464 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022464 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1848 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1848 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2420 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2420 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2420 # number of overall hits +system.cpu.dcache.overall_hits::total 2420 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 151 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 504 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 504 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 504 # number of overall misses +system.cpu.dcache.overall_misses::total 504 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8901000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8901000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15603499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15603499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24504499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24504499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24504499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24504499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2924 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2924 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2924 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2924 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075538 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075538 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.172367 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172367 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172367 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172367 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58947.019868 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58947.019868 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44202.546742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44202.546742 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48620.037698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48620.037698 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 363 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 363 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 363 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8296999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8296999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8296999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8296999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61588.888889 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61588.888889 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 7e4ac0c88..71523c506 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -79,6 +79,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -130,18 +131,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -424,18 +425,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -449,6 +450,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=PowerInterrupts +[system.cpu.isa] +type=PowerISA + [system.cpu.itb] type=PowerTLB size=64 @@ -456,24 +460,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -483,10 +487,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -501,7 +505,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/power/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -523,15 +527,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 4f1d93bdf..71a23fbd5 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:02:09 -gem5 started Aug 13 2012 18:12:24 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:09:52 +gem5 started Oct 30 2012 13:58:22 +gem5 executing on u200540-lin command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11763500 because target called exit() +Exiting @ tick 14065500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 5e0f9ad46..b47dafade 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14081500 # Number of ticks simulated -final_tick 14081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 14065500 # Number of ticks simulated +final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87308 # Simulator instruction rate (inst/s) -host_op_rate 87279 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 212126284 # Simulator tick rate (ticks/s) -host_mem_usage 214180 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 60799 # Simulator instruction rate (inst/s) +host_op_rate 60790 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 147601989 # Simulator tick rate (ticks/s) +host_mem_usage 210652 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory -system.physmem.bytes_read::total 28992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory -system.physmem.num_reads::total 453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1595284593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 463586976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2058871569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1595284593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1595284593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1595284593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 463586976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2058871569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 453 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory +system.physmem.bytes_read::total 28544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory +system.physmem.num_reads::total 446 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1569798443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459564182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2029362625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1569798443 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1569798443 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1569798443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459564182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2029362625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 446 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 453 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28992 # Total number of bytes read from memory +system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28544 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28992 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -40,16 +40,16 @@ system.physmem.perBankRdReqs::0 64 # Tr system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 49 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 42 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13946000 # Total gap between requests +system.physmem.totGap 13957000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 453 # Categorize read packet sizes +system.physmem.readPktSize::6 446 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1940453 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11214453 # Sum of mem lat for all requests -system.physmem.totBusLat 1812000 # Total cycles spent in databus access -system.physmem.totBankLat 7462000 # Total cycles spent in bank access -system.physmem.avgQLat 4283.56 # Average queueing delay per request -system.physmem.avgBankLat 16472.41 # Average bank access latency per request +system.physmem.totQLat 1923444 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11085444 # Sum of mem lat for all requests +system.physmem.totBusLat 1784000 # Total cycles spent in databus access +system.physmem.totBankLat 7378000 # Total cycles spent in bank access +system.physmem.avgQLat 4312.65 # Average queueing delay per request +system.physmem.avgBankLat 16542.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24755.97 # Average memory access latency -system.physmem.avgRdBW 2058.87 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24855.26 # Average memory access latency +system.physmem.avgRdBW 2029.36 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2058.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2029.36 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.87 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.80 # Average read queue length over time +system.physmem.busUtil 12.68 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 376 # Number of row buffer hits during reads +system.physmem.readRowHits 369 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.00 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 30785.87 # Average gap between requests +system.physmem.avgGap 31293.72 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -204,244 +204,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 28164 # number of cpu cycles simulated +system.cpu.numCycles 28132 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2468 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2024 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2049 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 624 # Number of BTB hits +system.cpu.BPredUnit.lookups 2247 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1810 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1863 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 602 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 159 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7429 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2468 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 783 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2394 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1429 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 964 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1877 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 322 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.222760 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.655950 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 198 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7397 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2267 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1136 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1812 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 306 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11663 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.133328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.550093 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9372 79.65% 79.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 173 1.47% 81.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 165 1.40% 82.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.21% 83.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 200 1.70% 85.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 147 1.25% 86.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 252 2.14% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 109 0.93% 89.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1206 10.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9396 80.56% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 175 1.50% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.51% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.22% 84.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.95% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 132 1.13% 87.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.20% 90.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 109 0.93% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1049 8.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.087630 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.510829 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7522 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1142 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2216 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 806 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 353 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12752 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 806 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7732 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 454 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 444 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2079 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 251 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12099 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 210 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10388 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19762 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19707 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 11663 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.079873 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.469856 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7468 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1305 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2099 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 156 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11753 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7658 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 585 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 451 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1983 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 277 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11310 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 233 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18197 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18142 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5390 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2089 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1942 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9281 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4902 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4209 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11766 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.788798 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.528040 # Number of insts issued each cycle +system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1829 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8959 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4243 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11663 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.768156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.499073 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8334 70.83% 70.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1092 9.28% 80.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.71% 86.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 514 4.37% 91.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 473 4.02% 95.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 331 2.81% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 146 1.24% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 50 0.42% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 37 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8296 71.13% 71.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1090 9.35% 80.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 795 6.82% 87.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 496 4.25% 91.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 4.00% 95.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 308 2.64% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 133 1.14% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 43 0.37% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11766 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11663 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 2.26% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 77 43.50% 45.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 96 54.24% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.60% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 71 40.80% 45.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 95 54.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5705 61.47% 61.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1860 20.04% 81.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1714 18.47% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5501 61.40% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1805 20.15% 81.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1651 18.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9281 # Type of FU issued -system.cpu.iq.rate 0.329534 # Inst issue rate -system.cpu.iq.fu_busy_cnt 177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019071 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30620 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15880 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8398 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8959 # Type of FU issued +system.cpu.iq.rate 0.318463 # Inst issue rate +system.cpu.iq.fu_busy_cnt 174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019422 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29881 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14574 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8164 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9424 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9099 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1128 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 896 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 783 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 806 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 266 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11006 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2089 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1942 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 383 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8796 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 485 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 370 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10360 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1829 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 264 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 330 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8539 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1683 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 420 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3302 # number of memory reference insts executed -system.cpu.iew.exec_branches 1388 # Number of branches executed -system.cpu.iew.exec_stores 1577 # Number of stores executed -system.cpu.iew.exec_rate 0.312314 # Inst execution rate -system.cpu.iew.wb_sent 8586 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8425 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4372 # num instructions producing a value -system.cpu.iew.wb_consumers 7073 # num instructions consuming a value +system.cpu.iew.exec_refs 3224 # number of memory reference insts executed +system.cpu.iew.exec_branches 1354 # Number of branches executed +system.cpu.iew.exec_stores 1541 # Number of stores executed +system.cpu.iew.exec_rate 0.303533 # Inst execution rate +system.cpu.iew.wb_sent 8307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8191 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4222 # num instructions producing a value +system.cpu.iew.wb_consumers 6683 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.299141 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618125 # average fanout of values written-back +system.cpu.iew.wb_rate 0.291163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631752 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5223 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.528467 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.329717 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.528757 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.330367 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8573 78.22% 78.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1014 9.25% 87.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 623 5.68% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 252 2.30% 95.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.61% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 110 1.00% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 64 0.58% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.38% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 105 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8576 78.29% 78.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1000 9.13% 87.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 620 5.66% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 265 2.42% 95.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 172 1.57% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 106 0.97% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 68 0.62% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.41% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10954 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -452,285 +451,182 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21870 # The number of ROB reads -system.cpu.rob.rob_writes 22837 # The number of ROB writes -system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16398 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21218 # The number of ROB reads +system.cpu.rob.rob_writes 21442 # The number of ROB writes +system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16469 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 4.862569 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.862569 # CPI: Total CPI of All Threads -system.cpu.ipc 0.205653 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.205653 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13961 # number of integer regfile reads -system.cpu.int_regfile_writes 7286 # number of integer regfile writes +system.cpu.cpi 4.857044 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.857044 # CPI: Total CPI of All Threads +system.cpu.ipc 0.205887 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.205887 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13537 # number of integer regfile reads +system.cpu.int_regfile_writes 7068 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 171.601938 # Cycle average of tags in use -system.cpu.icache.total_refs 1437 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.036517 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 168.326699 # Cycle average of tags in use +system.cpu.icache.total_refs 1375 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3.917379 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 171.601938 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.083790 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.083790 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1437 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1437 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1437 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1437 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1437 # number of overall hits -system.cpu.icache.overall_hits::total 1437 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 440 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 440 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 440 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 440 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 440 # number of overall misses -system.cpu.icache.overall_misses::total 440 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20404500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20404500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20404500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20404500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20404500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20404500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1877 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1877 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1877 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1877 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234417 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.234417 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234417 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.234417 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234417 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.234417 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46373.863636 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46373.863636 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46373.863636 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46373.863636 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46373.863636 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46373.863636 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 338 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 168.326699 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.082191 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.082191 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1375 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1375 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1375 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1375 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1375 # number of overall hits +system.cpu.icache.overall_hits::total 1375 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses +system.cpu.icache.overall_misses::total 437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20187000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20187000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20187000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20187000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20187000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20187000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1812 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1812 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1812 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1812 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241170 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.241170 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.241170 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.241170 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.241170 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.241170 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46194.508009 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46194.508009 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46194.508009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46194.508009 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17051500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17051500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17051500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17051500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17051500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17051500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.189664 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.189664 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.189664 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47897.471910 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47897.471910 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47897.471910 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47897.471910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47897.471910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47897.471910 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16769000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16769000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193709 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.193709 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.193709 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47774.928775 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47774.928775 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.108123 # Cycle average of tags in use -system.cpu.dcache.total_refs 2206 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.627451 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.108123 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015407 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015407 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1490 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1490 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 716 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 716 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2206 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2206 # number of overall hits -system.cpu.dcache.overall_hits::total 2206 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 330 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 330 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 427 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 427 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 427 # number of overall misses -system.cpu.dcache.overall_misses::total 427 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4870000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4870000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14038497 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14038497 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18908497 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18908497 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18908497 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18908497 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1587 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1587 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2633 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2633 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2633 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2633 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061122 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061122 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315488 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.315488 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162172 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162172 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.162172 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.162172 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.185567 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.185567 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42540.900000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42540.900000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 44282.194379 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 44282.194379 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 44282.194379 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 44282.194379 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 416 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42491.890909 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35929.965517 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46586.042553 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46586.042553 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34901.743590 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44378.411765 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37035.562914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34901.743590 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44378.411765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37035.562914 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34884.101449 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42862 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35963.817043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46522.212766 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46522.212766 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 63.407702 # Cycle average of tags in use +system.cpu.dcache.total_refs 2190 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 21.470588 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 63.407702 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015480 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015480 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2190 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2190 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2190 # number of overall hits +system.cpu.dcache.overall_hits::total 2190 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses +system.cpu.dcache.overall_misses::total 435 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5221500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5221500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14127997 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14127997 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19349497 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19349497 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19349497 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19349497 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2625 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2625 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2625 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2625 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065864 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065864 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.165714 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165714 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165714 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165714 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.730769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.730769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42682.770393 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42682.770393 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44481.602299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44481.602299 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 414 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2814999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2814999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5860999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5860999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5860999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5860999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55381.818182 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55381.818182 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59893.595745 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59893.595745 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index 2fea3a81f..505121624 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -92,22 +92,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,22 +123,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -155,24 +155,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -182,10 +182,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -200,7 +200,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -222,15 +222,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index c486c847c..ff91b8c31 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:12:48 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:52 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 18878500 because target called exit() +Hello World!Exiting @ tick 16286500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 0f666ffe1..f975c5003 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16282500 # Number of ticks simulated -final_tick 16282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16286500 # Number of ticks simulated +final_tick 16286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46082 # Simulator instruction rate (inst/s) -host_op_rate 46072 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140796560 # Simulator tick rate (ticks/s) -host_mem_usage 222960 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 32524 # Simulator instruction rate (inst/s) +host_op_rate 32520 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 99417983 # Simulator tick rate (ticks/s) +host_mem_usage 221588 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1135943498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 526700445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1662643943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1135943498 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1135943498 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1135943498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 526700445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1662643943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1135664507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 526571086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1662235594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1135664507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1135664507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1135664507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 526571086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1662235594 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16231000 # Total gap between requests +system.physmem.totGap 16235000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,17 +164,17 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2301921 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11301921 # Sum of mem lat for all requests +system.physmem.totQLat 2302422 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11302422 # Sum of mem lat for all requests system.physmem.totBusLat 1692000 # Total cycles spent in databus access system.physmem.totBankLat 7308000 # Total cycles spent in bank access -system.physmem.avgQLat 5441.89 # Average queueing delay per request +system.physmem.avgQLat 5443.08 # Average queueing delay per request system.physmem.avgBankLat 17276.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26718.49 # Average memory access latency -system.physmem.avgRdBW 1662.64 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26719.67 # Average memory access latency +system.physmem.avgRdBW 1662.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1662.64 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1662.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 10.39 # Data bus utilization in percentage @@ -184,44 +184,44 @@ system.physmem.readRowHits 336 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 38371.16 # Average gap between requests +system.physmem.avgGap 38380.61 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 32566 # number of cpu cycles simulated +system.cpu.numCycles 32574 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1630 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1034 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 436 # Number of BTB hits +system.cpu.branch_predictor.lookups 1636 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1090 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 897 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1343 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 584 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 37.424893 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 503 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5631 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 43.484736 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9619 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9600 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1675 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 1483 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 838 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 277 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 75.156951 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3966 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 1718 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 1472 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 376 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 458 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 834 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 281 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 74.798206 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3957 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9640 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9655 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26364 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6202 # Number of cycles cpu stages are processed. -system.cpu.activity 19.044402 # Percentage of cycles cpu is active +system.cpu.idleCycles 26327 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6247 # Number of cycles cpu stages are processed. +system.cpu.activity 19.177872 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -233,72 +233,72 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.113385 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.114886 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.113385 # CPI: Total CPI of All Threads -system.cpu.ipc 0.163576 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.114886 # CPI: Total CPI of All Threads +system.cpu.ipc 0.163535 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.163576 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 28007 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4559 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.999263 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.163535 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27935 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 14.241420 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3189 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.792422 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 29532 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.316465 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 31591 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.814576 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 29541 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.311107 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 31599 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.993920 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29408 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3158 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.697230 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.993185 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29417 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 9.691779 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.411463 # Cycle average of tags in use -system.cpu.icache.total_refs 814 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 143.423519 # Cycle average of tags in use +system.cpu.icache.total_refs 896 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.797251 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.411463 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070025 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070025 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 814 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 814 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 814 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 814 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 814 # number of overall hits -system.cpu.icache.overall_hits::total 814 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18418500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18418500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18418500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18418500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18418500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18418500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.308998 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.308998 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.308998 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.308998 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.308998 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.308998 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50600.274725 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50600.274725 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50600.274725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50600.274725 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 143.423519 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070031 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070031 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits +system.cpu.icache.overall_hits::total 896 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses +system.cpu.icache.overall_misses::total 362 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18347500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18347500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18347500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18347500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18347500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18347500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50683.701657 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50683.701657 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50683.701657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50683.701657 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,12 +307,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses @@ -325,12 +325,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000 system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency @@ -339,14 +339,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.214129 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.214129 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020804 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020804 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -363,14 +363,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3347500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19185000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19185000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22532500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22532500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22532500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22532500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -387,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54877.049180 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54877.049180 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46452.784504 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46452.784504 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47536.919831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47536.919831 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked @@ -421,12 +421,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 135 system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4153500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4153500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7092500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7092500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7092500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7092500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -437,22 +437,22 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 169.991473 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 170.006396 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.874602 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 27.116871 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004360 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.886606 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 27.119790 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000828 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005188 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits @@ -478,14 +478,14 @@ system.cpu.l2cache.overall_misses::total 423 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2872500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 17748000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4070000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4070000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4069000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4069000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 14875500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6942500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21818000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6941500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21817000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 14875500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6942500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21818000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6941500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21817000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -511,14 +511,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.992958 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51472.318339 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54198.113208 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 51894.736842 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50246.913580 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50246.913580 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50234.567901 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50234.567901 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51579.196217 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51576.832151 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51579.196217 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51576.832151 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11235436 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11236437 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13443008 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066568 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066568 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11235436 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5274140 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16509576 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11235436 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5274140 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16509576 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13444009 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066068 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066068 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11236437 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5273640 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16510077 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11236437 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5273640 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16510077 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38876.941176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38880.404844 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39307.040936 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37858.864198 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37858.864198 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.967836 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37852.691358 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37852.691358 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index a6a41648e..5620e85e4 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -82,7 +82,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -106,7 +106,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 3e672ef03..3359de27e 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:12:59 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:46:02 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 9a9c3bf56..a4c6ca2b7 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126208 # Simulator instruction rate (inst/s) -host_op_rate 126157 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63788253 # Simulator tick rate (ticks/s) -host_mem_usage 221040 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 63026 # Simulator instruction rate (inst/s) +host_op_rate 63015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31868954 # Simulator tick rate (ticks/s) +host_mem_usage 212680 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index 61c642df2..ab18e451d 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -106,7 +106,7 @@ version=0 [system.dir_cntrl0.directory] type=RubyDirectoryMemory map_levels=4 -numa_high_bit=6 +numa_high_bit=5 size=134217728 use_map=false version=0 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr index e45cd058f..5da3f0737 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr @@ -1,2 +1,6 @@ +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index d65bb97a2..18fb5a397 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 9 2012 13:47:14 -gem5 started Sep 9 2012 13:47:33 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:52 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 59ceed6d6..0ee67c488 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu sim_ticks 107952 # Number of ticks simulated final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 10153 # Simulator instruction rate (inst/s) -host_op_rate 10153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 205737 # Simulator tick rate (ticks/s) -host_mem_usage 240612 # Number of bytes of host memory used -host_seconds 0.52 # Real time elapsed on the host +host_inst_rate 33106 # Simulator instruction rate (inst/s) +host_op_rate 33103 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 670773 # Simulator tick rate (ticks/s) +host_mem_usage 232832 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 135ea172c..bf88dfd5e 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -61,22 +61,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -92,22 +92,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -124,24 +124,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -151,10 +151,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -169,7 +169,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -193,7 +193,7 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index 2fc16fb0f..ff092cd6d 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:07 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:46:02 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 29527000 because target called exit() +Hello World!Exiting @ tick 27800000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 37ab13bca..df9fd5f9b 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 251441 # Simulator instruction rate (inst/s) -host_op_rate 251244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1310200039 # Simulator tick rate (ticks/s) -host_mem_usage 220428 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 85623 # Simulator instruction rate (inst/s) +host_op_rate 85602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 446634768 # Simulator tick rate (ticks/s) +host_mem_usage 221096 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 98b722b0c..85178b3d5 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -431,18 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -455,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -464,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -472,31 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -506,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -524,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/x86/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -546,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 1bec04837..c8ef0214a 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,13 +1,11 @@ -Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 21:50:34 -gem5 started Sep 10 2012 21:50:39 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 16:15:47 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 12607000 because target called exit() +Exiting @ tick 15014000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 272509d41..e6a1ad3f3 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,53 +1,53 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15249000 # Number of ticks simulated -final_tick 15249000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15014000 # Number of ticks simulated +final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41998 # Simulator instruction rate (inst/s) -host_op_rate 76065 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119014725 # Simulator tick rate (ticks/s) -host_mem_usage 225728 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 32657 # Simulator instruction rate (inst/s) +host_op_rate 59148 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91121721 # Simulator tick rate (ticks/s) +host_mem_usage 223384 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory -system.physmem.bytes_read::total 28800 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1280083940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 608564496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1888648436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1280083940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1280083940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1280083940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 608564496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1888648436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory +system.physmem.bytes_read::total 28736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1291594512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 622352471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1913946983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1291594512 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1291594512 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1291594512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 622352471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1913946983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28800 # Total number of bytes read from memory +system.physmem.cpureqs 450 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28736 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28800 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 41 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 39 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15226500 # Total gap between requests +system.physmem.totGap 14992500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 451 # Categorize read packet sizes +system.physmem.readPktSize::6 450 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -99,8 +99,8 @@ system.physmem.neitherpktsize::6 0 # ca system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -164,265 +164,265 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1663951 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11993951 # Sum of mem lat for all requests -system.physmem.totBusLat 1804000 # Total cycles spent in databus access -system.physmem.totBankLat 8526000 # Total cycles spent in bank access -system.physmem.avgQLat 3689.47 # Average queueing delay per request -system.physmem.avgBankLat 18904.66 # Average bank access latency per request +system.physmem.totQLat 1656450 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12024450 # Sum of mem lat for all requests +system.physmem.totBusLat 1800000 # Total cycles spent in databus access +system.physmem.totBankLat 8568000 # Total cycles spent in bank access +system.physmem.avgQLat 3681.00 # Average queueing delay per request +system.physmem.avgBankLat 19040.00 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26594.13 # Average memory access latency -system.physmem.avgRdBW 1888.65 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26721.00 # Average memory access latency +system.physmem.avgRdBW 1913.95 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1888.65 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1913.95 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.busUtil 11.96 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.80 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 354 # Number of row buffer hits during reads +system.physmem.readRowHits 352 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.49 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33761.64 # Average gap between requests +system.physmem.avgGap 33316.67 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 30499 # number of cpu cycles simulated +system.cpu.numCycles 30029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3124 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3124 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 575 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2554 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits +system.cpu.BPredUnit.lookups 3018 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3018 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 546 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2500 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 796 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 9097 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15002 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3124 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4073 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2573 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3671 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1972 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 19065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.398846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.899430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8962 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.378572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.879282 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 15096 79.18% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 179 0.94% 80.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 149 0.78% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 207 1.09% 81.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 179 0.94% 82.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 177 0.93% 83.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 231 1.21% 85.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 192 1.01% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2655 13.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 175 0.94% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 261 1.40% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 19065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.102430 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.491885 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9663 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3644 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3665 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1953 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25430 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1953 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 10013 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2382 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 508 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3439 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 770 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 23869 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 648 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 26126 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57405 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 57389 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3547 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24449 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3325 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22967 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25104 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55188 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 55172 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 15066 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14044 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 31 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2094 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1772 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21302 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1755 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 20454 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17998 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10762 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14777 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17349 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9974 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13873 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 19065 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.944034 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.806602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.933595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.794406 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13533 70.98% 70.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1394 7.31% 78.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1058 5.55% 83.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 719 3.77% 87.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 757 3.97% 91.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 676 3.55% 95.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 613 3.22% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 275 1.44% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 40 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1386 7.46% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1042 5.61% 84.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 19065 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 18583 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 132 74.58% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 23 12.99% 87.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 12.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 138 77.53% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14399 80.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2084 11.58% 91.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1511 8.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13962 80.48% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1900 10.95% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1482 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17998 # Type of FU issued -system.cpu.iq.rate 0.590118 # Inst issue rate -system.cpu.iq.fu_busy_cnt 177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009834 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 55439 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32107 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16514 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17349 # Type of FU issued +system.cpu.iq.rate 0.577742 # Inst issue rate +system.cpu.iq.fu_busy_cnt 178 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010260 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53664 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30472 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16003 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18167 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17518 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 180 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1953 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1731 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 30 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21339 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2405 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1772 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20491 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1755 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 717 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17023 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1944 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 975 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16425 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3334 # number of memory reference insts executed -system.cpu.iew.exec_branches 1674 # Number of branches executed -system.cpu.iew.exec_stores 1390 # Number of stores executed -system.cpu.iew.exec_rate 0.558149 # Inst execution rate -system.cpu.iew.wb_sent 16747 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16518 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10593 # num instructions producing a value -system.cpu.iew.wb_consumers 16382 # num instructions consuming a value +system.cpu.iew.exec_refs 3140 # number of memory reference insts executed +system.cpu.iew.exec_branches 1630 # Number of branches executed +system.cpu.iew.exec_stores 1363 # Number of stores executed +system.cpu.iew.exec_rate 0.546971 # Inst execution rate +system.cpu.iew.wb_sent 16197 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16007 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10178 # num instructions producing a value +system.cpu.iew.wb_consumers 15727 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.541592 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.646624 # average fanout of values written-back +system.cpu.iew.wb_rate 0.533051 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.647167 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11593 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10745 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 604 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 17112 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.569483 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.430880 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.581687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.458321 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13541 79.13% 79.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1338 7.82% 86.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 619 3.62% 90.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 703 4.11% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 373 2.18% 96.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 140 0.82% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 0.71% 98.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 74 0.43% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 203 1.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13226 78.95% 78.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1316 7.86% 86.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 596 3.56% 90.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 120 0.72% 98.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 75 0.45% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 17112 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -433,283 +433,179 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9650 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 203 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 38247 # The number of ROB reads -system.cpu.rob.rob_writes 44659 # The number of ROB writes -system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11434 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 37022 # The number of ROB reads +system.cpu.rob.rob_writes 42839 # The number of ROB writes +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 5.668959 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.668959 # CPI: Total CPI of All Threads -system.cpu.ipc 0.176399 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.176399 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 29908 # number of integer regfile reads -system.cpu.int_regfile_writes 17845 # number of integer regfile writes +system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads +system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28874 # number of integer regfile reads +system.cpu.int_regfile_writes 17232 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7467 # number of misc regfile reads +system.cpu.misc_regfile_reads 7155 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.993781 # Cycle average of tags in use -system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 306 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.117647 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use +system.cpu.icache.total_refs 1482 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.993781 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071286 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071286 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits -system.cpu.icache.overall_hits::total 1566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 406 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 406 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 406 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 406 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 406 # number of overall misses -system.cpu.icache.overall_misses::total 406 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19356000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19356000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19356000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19356000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19356000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19356000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1972 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1972 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1972 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1972 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1972 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205882 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.205882 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.205882 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.205882 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.205882 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.205882 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47674.876847 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47674.876847 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47674.876847 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47674.876847 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47674.876847 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47674.876847 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 302 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 144.838361 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1482 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1482 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits +system.cpu.icache.overall_hits::total 1482 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses +system.cpu.icache.overall_misses::total 398 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19300000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19300000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19300000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19300000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19300000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19300000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1880 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1880 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1880 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1880 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1880 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1880 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.211702 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.211702 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.211702 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.211702 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.211702 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.211702 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48492.462312 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48492.462312 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48492.462312 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48492.462312 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 100 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 100 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 100 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 100 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 306 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 306 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 306 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 306 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 306 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 306 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15469000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15469000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15469000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15469000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15469000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15469000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155172 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.155172 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.155172 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50552.287582 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50552.287582 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50552.287582 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50552.287582 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50552.287582 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50552.287582 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15461500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15461500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161702 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.161702 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.161702 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.489938 # Cycle average of tags in use -system.cpu.dcache.total_refs 2406 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.825175 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.489938 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020383 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020383 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1548 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1548 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2406 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2406 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2406 # number of overall hits -system.cpu.dcache.overall_hits::total 2406 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses -system.cpu.dcache.overall_misses::total 208 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6548500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6548500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4231000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4231000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10779500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10779500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10779500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10779500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1680 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1680 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078571 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078571 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.079572 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.079572 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.079572 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.079572 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49609.848485 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49609.848485 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55671.052632 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55671.052632 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51824.519231 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51824.519231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51824.519231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51824.519231 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 108 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # 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mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997783 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37108.045902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41686.771429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37962.741333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40008.026316 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40008.026316 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37108.045902 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40812.904110 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38307.401330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37108.045902 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40812.904110 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38307.401330 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.033003 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38183.219251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use +system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits +system.cpu.dcache.overall_hits::total 2284 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses +system.cpu.dcache.overall_misses::total 202 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081186 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081186 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045747 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045747 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 358d71402..431cc37fd 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -129,18 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +423,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -455,24 +455,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +482,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -519,7 +519,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -541,15 +541,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index b2c42f9a9..d895f3126 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 16:51:51 -gem5 started Aug 13 2012 17:17:24 -gem5 executing on zizzer +gem5 compiled Nov 1 2012 14:46:44 +gem5 started Nov 1 2012 15:18:34 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -11,4 +11,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 14993500 because target called exit() +Exiting @ tick 19857000 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 6142b96e8..b523abef7 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20334000 # Number of ticks simulated -final_tick 20334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19857000 # Number of ticks simulated +final_tick 19857000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80964 # Simulator instruction rate (inst/s) -host_op_rate 80958 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 129154883 # Simulator tick rate (ticks/s) -host_mem_usage 217900 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 50642 # Simulator instruction rate (inst/s) +host_op_rate 50640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78893380 # Simulator tick rate (ticks/s) +host_mem_usage 214784 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 39872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22784 # Number of bytes read from this memory -system.physmem.bytes_read::total 62656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39872 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 356 # Number of read requests responded to by this memory -system.physmem.num_reads::total 979 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1960853743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1120487853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3081341595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1960853743 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1960853743 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1960853743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1120487853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3081341595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 979 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory +system.physmem.bytes_read::total 62208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39808 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory +system.physmem.num_reads::total 972 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2004733847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1128065670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3132799517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2004733847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2004733847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2004733847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1128065670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3132799517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 972 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 979 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 62656 # Total number of bytes read from memory +system.physmem.cpureqs 972 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 62208 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62656 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 62208 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 123 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 81 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 70 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 122 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 76 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 74 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 99 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 76 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 75 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 71 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 74 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 76 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20181000 # Total gap between requests +system.physmem.totGap 19816500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 979 # Categorize read packet sizes +system.physmem.readPktSize::6 972 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 215 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 11431477 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 34163477 # Sum of mem lat for all requests -system.physmem.totBusLat 3916000 # Total cycles spent in databus access -system.physmem.totBankLat 18816000 # Total cycles spent in bank access -system.physmem.avgQLat 11676.69 # Average queueing delay per request -system.physmem.avgBankLat 19219.61 # Average bank access latency per request +system.physmem.totQLat 11651972 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 34145972 # Sum of mem lat for all requests +system.physmem.totBusLat 3888000 # Total cycles spent in databus access +system.physmem.totBankLat 18606000 # Total cycles spent in bank access +system.physmem.avgQLat 11987.63 # Average queueing delay per request +system.physmem.avgBankLat 19141.98 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34896.30 # Average memory access latency -system.physmem.avgRdBW 3081.34 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 35129.60 # Average memory access latency +system.physmem.avgRdBW 3132.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3081.34 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3132.80 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 19.26 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.68 # Average read queue length over time +system.physmem.busUtil 19.58 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.72 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 740 # Number of row buffer hits during reads +system.physmem.readRowHits 733 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.59 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 20613.89 # Average gap between requests +system.physmem.avgGap 20387.35 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4607 # DTB read hits -system.cpu.dtb.read_misses 109 # DTB read misses +system.cpu.dtb.read_hits 4359 # DTB read hits +system.cpu.dtb.read_misses 96 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4716 # DTB read accesses -system.cpu.dtb.write_hits 2105 # DTB write hits -system.cpu.dtb.write_misses 77 # DTB write misses +system.cpu.dtb.read_accesses 4455 # DTB read accesses +system.cpu.dtb.write_hits 2014 # DTB write hits +system.cpu.dtb.write_misses 72 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2182 # DTB write accesses -system.cpu.dtb.data_hits 6712 # DTB hits -system.cpu.dtb.data_misses 186 # DTB misses +system.cpu.dtb.write_accesses 2086 # DTB write accesses +system.cpu.dtb.data_hits 6373 # DTB hits +system.cpu.dtb.data_misses 168 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6898 # DTB accesses -system.cpu.itb.fetch_hits 5687 # ITB hits -system.cpu.itb.fetch_misses 59 # ITB misses +system.cpu.dtb.data_accesses 6541 # DTB accesses +system.cpu.itb.fetch_hits 5250 # ITB hits +system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5746 # ITB accesses +system.cpu.itb.fetch_accesses 5307 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,358 +219,358 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 40669 # number of cpu cycles simulated +system.cpu.numCycles 39715 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6981 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3954 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1690 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5146 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 870 # Number of BTB hits +system.cpu.BPredUnit.lookups 6348 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3569 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1446 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4530 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 874 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 937 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1717 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 38666 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6981 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1807 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6508 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2004 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 376 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5687 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 915 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 27168 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.423218 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.808405 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 898 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 184 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1539 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 35371 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6348 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1772 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5994 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1779 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5250 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 858 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 26295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.345161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.748208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20660 76.05% 76.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 537 1.98% 78.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 399 1.47% 79.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 504 1.86% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 464 1.71% 83.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 436 1.60% 84.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 485 1.79% 86.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 591 2.18% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3092 11.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20301 77.20% 77.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 545 2.07% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 388 1.48% 80.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 414 1.57% 82.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 431 1.64% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 401 1.53% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 440 1.67% 87.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 561 2.13% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2814 10.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 27168 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.171654 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.950749 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38149 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6961 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5575 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 517 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2929 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 646 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 395 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 33907 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 727 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2929 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38897 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 984 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5237 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2250 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 31157 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2290 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 23416 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 38564 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 38530 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 26295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.159839 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.890621 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37128 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7028 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5161 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 465 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2623 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 533 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 326 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 31237 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 663 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2623 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37789 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3807 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1133 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4855 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2198 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 28851 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 2210 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21669 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 35547 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 35513 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 53 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6217 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3020 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1445 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 12529 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 51 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6010 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2907 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2972 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1380 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 10 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 2775 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1297 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 27184 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 71 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 22298 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 13301 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8222 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 27168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.820745 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.402255 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 25429 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 70 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21088 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11668 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7282 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 26295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.801978 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.371425 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17752 65.34% 65.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3320 12.22% 77.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2545 9.37% 86.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1596 5.87% 92.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1085 3.99% 96.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 559 2.06% 98.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 231 0.85% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 61 0.22% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 19 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17201 65.42% 65.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3228 12.28% 77.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2604 9.90% 87.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1566 5.96% 93.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 907 3.45% 97.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 493 1.87% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 226 0.86% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.21% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 27168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 26295 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13 6.70% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 118 60.82% 67.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63 32.47% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 5.67% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 117 60.31% 65.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 66 34.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7510 66.63% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2596 23.03% 89.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1160 10.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6973 65.93% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2492 23.56% 89.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1106 10.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11271 # Type of FU issued +system.cpu.iq.FU_type_0::total 10576 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7311 66.30% 66.32% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.33% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.35% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2558 23.20% 89.54% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1153 10.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7011 66.70% 66.71% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.72% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.74% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2403 22.86% 89.60% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1093 10.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11027 # Type of FU issued +system.cpu.iq.FU_type_1::total 10512 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14821 66.47% 66.49% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 66.49% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 66.49% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.51% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type::MemRead 5154 23.11% 89.63% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2313 10.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 13984 66.31% 66.33% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 66.34% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 66.34% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.36% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4895 23.21% 89.57% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2199 10.43% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 22298 # Type of FU issued -system.cpu.iq.rate 0.548280 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 100 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 94 # FU busy when requested +system.cpu.iq.FU_type::total 21088 # Type of FU issued +system.cpu.iq.rate 0.530983 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 100 # FU busy when requested system.cpu.iq.fu_busy_cnt::total 194 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004485 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004216 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008700 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 72061 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 40564 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19339 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate::0 0.004458 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004742 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.009200 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 68733 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 37173 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 18381 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22466 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21256 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1837 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 580 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1724 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 295 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 77 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 355 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1789 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 515 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1592 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 432 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 256 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 238 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2929 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 685 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 27441 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 749 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5992 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2825 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 71 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 275 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1233 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1508 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20701 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2373 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2359 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4732 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1597 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2623 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 887 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25678 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 656 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5682 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2660 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 70 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 31 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 235 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1060 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1295 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 19629 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2279 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2190 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4469 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1459 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 114 # number of nop insts executed -system.cpu.iew.exec_nop::1 72 # number of nop insts executed -system.cpu.iew.exec_nop::total 186 # number of nop insts executed -system.cpu.iew.exec_refs::0 3487 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3445 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6932 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1642 # Number of branches executed -system.cpu.iew.exec_branches::1 1642 # Number of branches executed -system.cpu.iew.exec_branches::total 3284 # Number of branches executed -system.cpu.iew.exec_stores::0 1114 # Number of stores executed -system.cpu.iew.exec_stores::1 1086 # Number of stores executed -system.cpu.iew.exec_stores::total 2200 # Number of stores executed -system.cpu.iew.exec_rate 0.509012 # Inst execution rate -system.cpu.iew.wb_sent::0 9936 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9721 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19657 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9778 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9581 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19359 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5047 # num instructions producing a value -system.cpu.iew.wb_producers::1 4925 # num instructions producing a value -system.cpu.iew.wb_producers::total 9972 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6570 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6411 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12981 # num instructions consuming a value +system.cpu.iew.exec_nop::0 110 # number of nop insts executed +system.cpu.iew.exec_nop::1 69 # number of nop insts executed +system.cpu.iew.exec_nop::total 179 # number of nop insts executed +system.cpu.iew.exec_refs::0 3341 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3226 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6567 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1545 # Number of branches executed +system.cpu.iew.exec_branches::1 1563 # Number of branches executed +system.cpu.iew.exec_branches::total 3108 # Number of branches executed +system.cpu.iew.exec_stores::0 1062 # Number of stores executed +system.cpu.iew.exec_stores::1 1036 # Number of stores executed +system.cpu.iew.exec_stores::total 2098 # Number of stores executed +system.cpu.iew.exec_rate 0.494247 # Inst execution rate +system.cpu.iew.wb_sent::0 9363 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9308 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 18671 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9223 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9178 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18401 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4724 # num instructions producing a value +system.cpu.iew.wb_producers::1 4736 # num instructions producing a value +system.cpu.iew.wb_producers::total 9460 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6156 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6184 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12340 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.240429 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.235585 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.476014 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.768189 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.768211 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.768200 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.232230 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.231097 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.463326 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.767381 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.765847 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.766613 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 14694 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12926 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1316 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 27077 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.471950 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.251708 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1134 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 26218 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487413 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.275738 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21479 79.33% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2818 10.41% 89.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1191 4.40% 94.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 503 1.86% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 353 1.30% 97.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 251 0.93% 98.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 184 0.68% 98.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 85 0.31% 99.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 213 0.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20568 78.45% 78.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2989 11.40% 89.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1062 4.05% 93.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 514 1.96% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 342 1.30% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 238 0.91% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 201 0.77% 98.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.27% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 232 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 27077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 26218 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6390 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -601,83 +601,83 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 129384 # The number of ROB reads -system.cpu.rob.rob_writes 57896 # The number of ROB writes -system.cpu.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13501 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 123093 # The number of ROB reads +system.cpu.rob.rob_writes 54044 # The number of ROB writes +system.cpu.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13420 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6373 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 6.382454 # CPI: Cycles Per Instruction -system.cpu.cpi::1 6.381453 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.190977 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.156680 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.156704 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.313384 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 26029 # number of integer regfile reads -system.cpu.int_regfile_writes 14619 # number of integer regfile writes +system.cpu.cpi::0 6.232737 # CPI: Cycles Per Instruction +system.cpu.cpi::1 6.231759 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.116124 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.160443 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.160468 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.320911 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 24691 # number of integer regfile reads +system.cpu.int_regfile_writes 13868 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.icache.replacements::0 6 # number of replacements +system.cpu.icache.replacements::0 7 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 309.378150 # Cycle average of tags in use -system.cpu.icache.total_refs 4652 # Total number of references to valid blocks. +system.cpu.icache.replacements::total 7 # number of replacements +system.cpu.icache.tagsinuse 306.891389 # Cycle average of tags in use +system.cpu.icache.total_refs 4214 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.443200 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 6.742400 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 309.378150 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.151064 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.151064 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4652 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4652 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4652 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4652 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4652 # number of overall hits -system.cpu.icache.overall_hits::total 4652 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 306.891389 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.149849 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.149849 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4214 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4214 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4214 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4214 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4214 # number of overall hits +system.cpu.icache.overall_hits::total 4214 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1030 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1030 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1030 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1030 # number of overall misses system.cpu.icache.overall_misses::total 1030 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56036996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56036996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56036996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56036996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56036996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56036996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5682 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5682 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5682 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5682 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5682 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5682 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.181274 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.181274 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.181274 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.181274 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.181274 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.181274 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54404.850485 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54404.850485 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54404.850485 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54404.850485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54404.850485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54404.850485 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2136 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56718997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56718997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56718997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56718997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56718997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56718997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5244 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5244 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5244 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5244 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5244 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5244 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196415 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.196415 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.196415 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.196415 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.196415 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.196415 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.987379 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55066.987379 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55066.987379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55066.987379 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2360 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.142857 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -693,207 +693,207 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 625 system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 625 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37870497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37870497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37870497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37870497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37870497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37870497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109996 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.109996 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.109996 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60592.795200 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60592.795200 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60592.795200 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60592.795200 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60592.795200 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60592.795200 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38021997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38021997 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38021997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38021997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38021997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38021997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119184 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.119184 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.119184 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60835.195200 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60835.195200 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60835.195200 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60835.195200 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60835.195200 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60835.195200 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 213.566251 # Cycle average of tags in use -system.cpu.dcache.total_refs 4636 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 356 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.022472 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 210.613846 # Cycle average of tags in use +system.cpu.dcache.total_refs 4387 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 349 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.570201 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 213.566251 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.052140 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.052140 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3620 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3620 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1016 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1016 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4636 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4636 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4636 # number of overall hits -system.cpu.dcache.overall_hits::total 4636 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 336 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 336 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 714 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 714 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1050 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1050 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1050 # number of overall misses -system.cpu.dcache.overall_misses::total 1050 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20070500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20070500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32974457 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32974457 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 53044957 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53044957 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 53044957 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53044957 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 210.613846 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.051419 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.051419 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3369 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3369 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4387 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4387 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4387 # number of overall hits +system.cpu.dcache.overall_hits::total 4387 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1035 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1035 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1035 # number of overall misses +system.cpu.dcache.overall_misses::total 1035 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19559500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19559500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33573958 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33573958 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53133458 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53133458 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53133458 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53133458 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3692 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3692 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5686 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5686 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5686 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5686 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084934 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.084934 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184664 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184664 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184664 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184664 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59733.630952 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59733.630952 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46182.712885 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46182.712885 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50519.006667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50519.006667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50519.006667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50519.006667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2851 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5422 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5422 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5422 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5422 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087486 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087486 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.190889 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.190889 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.190889 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.190889 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60555.727554 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60555.727554 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47154.435393 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47154.435393 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51336.674396 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51336.674396 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3056 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 107 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.644860 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.669903 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 568 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 568 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 694 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 694 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 694 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 694 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 356 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 979 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29496155 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11535670 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41031825 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6881648 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6881648 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29496155 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18417318 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 47913473 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29496155 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18417318 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 47913473 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 622 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 972 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 622 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 972 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29639174 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11445162 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41084336 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6748648 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6748648 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29639174 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18193810 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 47832984 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29639174 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18193810 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 47832984 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995200 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996381 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995200 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997961 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996923 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995200 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997961 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47345.353130 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54931.761905 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49257.893157 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 47134.575342 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 47134.575342 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47345.353130 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51734.039326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48941.239019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47345.353130 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51734.039326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48941.239019 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996923 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47651.405145 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56103.735294 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49738.905569 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46223.616438 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46223.616438 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47651.405145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51982.314286 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49210.888889 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47651.405145 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51982.314286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49210.888889 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini index ddb8a4949..b0053eeff 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -92,22 +92,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,22 +123,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -155,24 +155,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -182,10 +182,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -200,7 +200,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -222,15 +222,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index e5fdf01a9..3730e9192 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:17 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:40 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 25614500 because target called exit() +Exiting @ tick 22838500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 165716ee5..87550aab2 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22522500 # Number of ticks simulated -final_tick 22522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 22838500 # Number of ticks simulated +final_tick 22838500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65265 # Simulator instruction rate (inst/s) -host_op_rate 65259 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96930117 # Simulator tick rate (ticks/s) -host_mem_usage 222888 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 15645 # Simulator instruction rate (inst/s) +host_op_rate 15645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23565036 # Simulator tick rate (ticks/s) +host_mem_usage 221420 # Number of bytes of host memory used +host_seconds 0.97 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 846797647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 392141192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1238938839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 846797647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 846797647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 846797647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 392141192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1238938839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 835081113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 386715415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1221796528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 835081113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 835081113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 835081113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 386715415 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1221796528 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 22489000 # Total gap between requests +system.physmem.totGap 22805000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,64 +164,64 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1783436 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10779436 # Sum of mem lat for all requests +system.physmem.totQLat 2327934 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11337934 # Sum of mem lat for all requests system.physmem.totBusLat 1744000 # Total cycles spent in databus access -system.physmem.totBankLat 7252000 # Total cycles spent in bank access -system.physmem.avgQLat 4090.45 # Average queueing delay per request -system.physmem.avgBankLat 16633.03 # Average bank access latency per request +system.physmem.totBankLat 7266000 # Total cycles spent in bank access +system.physmem.avgQLat 5339.30 # Average queueing delay per request +system.physmem.avgBankLat 16665.14 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24723.48 # Average memory access latency -system.physmem.avgRdBW 1238.94 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26004.44 # Average memory access latency +system.physmem.avgRdBW 1221.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1238.94 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1221.80 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.74 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.48 # Average read queue length over time +system.physmem.busUtil 7.64 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.50 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 359 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 51580.28 # Average gap between requests +system.physmem.avgGap 52305.05 # Average gap between requests system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 45046 # number of cpu cycles simulated +system.cpu.numCycles 45678 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 5017 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 3408 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 3514 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 2140 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 5149 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 3529 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 2365 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 4104 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2723 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 173 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 60.899260 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 2316 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2701 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 14466 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 66.349903 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 2896 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 25565 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 25496 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 4899 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3932 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 1367 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 948 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 2315 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 1043 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 68.939845 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 11058 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 5052 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3844 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 1540 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 762 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 2302 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 1056 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 68.552710 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 11045 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21840 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21901 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 501 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27681 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17365 # Number of cycles cpu stages are processed. -system.cpu.activity 38.549483 # Percentage of cycles cpu is active +system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28111 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17567 # Number of cycles cpu stages are processed. +system.cpu.activity 38.458339 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -233,72 +233,72 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 2.970980 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.012663 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 2.970980 # CPI: Total CPI of All Threads -system.cpu.ipc 0.336589 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.012663 # CPI: Total CPI of All Threads +system.cpu.ipc 0.331932 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.336589 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 31894 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 13152 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 29.196821 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 35835 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9211 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 20.447987 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36237 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8809 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 19.555565 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 42168 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.331932 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32253 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 13425 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 29.390516 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36325 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 20.475940 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 36875 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 19.271860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 42800 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 6.389025 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 35732 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9314 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 20.676642 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 6.300626 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36370 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9308 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 20.377425 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 171.605866 # Cycle average of tags in use -system.cpu.icache.total_refs 2584 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 172.580385 # Cycle average of tags in use +system.cpu.icache.total_refs 2999 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.642140 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10.030100 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 171.605866 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.083792 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.083792 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 2584 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2584 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2584 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2584 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2584 # number of overall hits -system.cpu.icache.overall_hits::total 2584 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 372 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 372 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 372 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 372 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 372 # number of overall misses -system.cpu.icache.overall_misses::total 372 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18064500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18064500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18064500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18064500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18064500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18064500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.125846 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.125846 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.125846 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.125846 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.125846 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.125846 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48560.483871 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48560.483871 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48560.483871 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48560.483871 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48560.483871 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48560.483871 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.580385 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084268 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084268 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2999 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2999 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2999 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2999 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2999 # number of overall hits +system.cpu.icache.overall_hits::total 2999 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 381 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 381 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 381 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses +system.cpu.icache.overall_misses::total 381 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18870500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18870500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18870500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18870500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18870500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18870500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3380 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3380 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3380 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3380 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3380 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3380 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112722 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.112722 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.112722 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.112722 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.112722 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.112722 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49528.871391 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49528.871391 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49528.871391 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49528.871391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49528.871391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49528.871391 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,46 +307,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14600500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14600500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14600500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14600500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14600500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14600500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101827 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.101827 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.101827 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48506.644518 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48506.644518 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48506.644518 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48506.644518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48506.644518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48506.644518 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15159500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15159500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15159500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15159500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15159500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15159500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.089053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.089053 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.089053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.089053 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.089053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.089053 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50363.787375 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50363.787375 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50363.787375 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50363.787375 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50363.787375 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50363.787375 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.150895 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 99.521292 # Cycle average of tags in use system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 99.150895 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024207 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024207 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 99.521292 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024297 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024297 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -365,14 +365,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3300500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19262500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19262500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22563000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22563000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22563000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22563000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3301000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3301000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19263500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19263500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22564500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22564500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22564500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22564500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -391,14 +391,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56905.172414 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56905.172414 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45645.734597 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45645.734597 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47006.250000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47006.250000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47006.250000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47006.250000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56913.793103 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56913.793103 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45648.104265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45648.104265 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47009.375000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47009.375000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 680 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked @@ -423,14 +423,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4513000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4513000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7413000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7413000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7413000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7413000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7414500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7414500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7414500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7414500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -439,26 +439,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54716.981132 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54716.981132 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53094.117647 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53094.117647 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54726.415094 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54726.415094 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53105.882353 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53105.882353 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 202.986818 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 204.089765 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 170.969481 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.017336 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005218 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000977 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006195 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.939057 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.150708 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005247 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000981 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006228 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -476,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14317500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2845500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17163000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4425000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4425000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14317500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7270500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21588000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14317500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7270500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21588000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14876500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2846000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17722500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4426000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4426000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14876500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7272000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22148500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14876500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7272000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22148500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -509,17 +509,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47884.615385 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53688.679245 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48758.522727 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52058.823529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52058.823529 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49400.457666 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49400.457666 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49754.180602 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53698.113208 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50348.011364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52070.588235 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52070.588235 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49754.180602 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50683.066362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49754.180602 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50683.066362 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -539,17 +539,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547482 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11107481 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12729050 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13289049 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547482 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11107481 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16111114 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547482 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16671113 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11107481 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16111114 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16671113 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -561,17 +561,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35275.859532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37148.765886 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36162.073864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37752.980114 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37148.765886 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37148.765886 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38149 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index d68715156..9a57b4e8b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -129,18 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +423,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -455,24 +455,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +482,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -522,15 +522,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index d7d566072..9433cbefd 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:20 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:40 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 20275500 because target called exit() +Exiting @ tick 23190500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 39a395968..e7a1232b3 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,50 +1,50 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23428500 # Number of ticks simulated -final_tick 23428500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 23190500 # Number of ticks simulated +final_tick 23190500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53742 # Simulator instruction rate (inst/s) -host_op_rate 53738 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87205048 # Simulator tick rate (ticks/s) -host_mem_usage 223912 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 24201 # Simulator instruction rate (inst/s) +host_op_rate 24200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38875523 # Simulator tick rate (ticks/s) +host_mem_usage 222232 # Number of bytes of host memory used +host_seconds 0.60 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory -system.physmem.bytes_read::total 30848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory +system.physmem.bytes_read::total 30912 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory -system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 917856457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 398830484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1316686941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 917856457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 917856457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 917856457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 398830484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1316686941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 482 # Total number of read requests seen +system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory +system.physmem.num_reads::total 483 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 927276255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 405683362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1332959617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 927276255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 927276255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 927276255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 405683362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1332959617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 483 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30848 # Total number of bytes read from memory +system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30912 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23376000 # Total gap between requests +system.physmem.totGap 23130500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 482 # Categorize read packet sizes +system.physmem.readPktSize::6 483 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,262 +164,262 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2488982 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12396982 # Sum of mem lat for all requests -system.physmem.totBusLat 1928000 # Total cycles spent in databus access -system.physmem.totBankLat 7980000 # Total cycles spent in bank access -system.physmem.avgQLat 5163.86 # Average queueing delay per request -system.physmem.avgBankLat 16556.02 # Average bank access latency per request +system.physmem.totQLat 2984483 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12938483 # Sum of mem lat for all requests +system.physmem.totBusLat 1932000 # Total cycles spent in databus access +system.physmem.totBankLat 8022000 # Total cycles spent in bank access +system.physmem.avgQLat 6179.05 # Average queueing delay per request +system.physmem.avgBankLat 16608.70 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25719.88 # Average memory access latency -system.physmem.avgRdBW 1316.69 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26787.75 # Average memory access latency +system.physmem.avgRdBW 1332.96 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1316.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1332.96 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 8.23 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.53 # Average read queue length over time +system.physmem.busUtil 8.33 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.56 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 393 # Number of row buffer hits during reads +system.physmem.readRowHits 394 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48497.93 # Average gap between requests +system.physmem.avgGap 47889.23 # Average gap between requests system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 46858 # number of cpu cycles simulated +system.cpu.numCycles 46382 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6941 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4630 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5115 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2636 # Number of BTB hits +system.cpu.BPredUnit.lookups 6758 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4516 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1074 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4657 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2448 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12393 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 32407 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6941 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3078 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9616 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3187 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8221 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31427 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6758 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3075 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8320 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 943 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5564 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 468 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33142 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.977823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.154937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5337 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 32520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.966390 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.158060 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23526 70.99% 70.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4767 14.38% 85.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 497 1.50% 86.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 473 1.43% 88.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 713 2.15% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 723 2.18% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 250 0.75% 93.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 284 0.86% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1909 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23340 71.77% 71.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4525 13.91% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 464 1.43% 87.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 371 1.14% 88.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1896 5.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33142 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.148128 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.691600 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13096 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9104 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8780 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1965 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30240 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1965 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 355 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8257 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8329 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 447 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27456 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 134 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24477 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 50943 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 50943 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 32520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.145703 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.677569 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8404 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29366 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13469 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8329 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8008 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 128 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24166 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49969 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 49969 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10658 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 696 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 697 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2830 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3653 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 691 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2732 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2330 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23144 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 660 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21674 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6018 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 185 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.653974 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.274325 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 22740 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21250 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 137 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8195 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5897 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 32520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.653444 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.275128 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23639 71.33% 71.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3658 11.04% 82.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2441 7.37% 89.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1702 5.14% 94.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 894 2.70% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 488 1.47% 99.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 244 0.74% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 60 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 16 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23284 71.60% 71.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3476 10.69% 82.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 913 2.81% 97.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 49 28.16% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.94% 43.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 99 56.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27 17.65% 47.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16000 73.82% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3426 15.81% 89.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2248 10.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15763 74.18% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3339 15.71% 89.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2148 10.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21674 # Type of FU issued -system.cpu.iq.rate 0.462546 # Inst issue rate -system.cpu.iq.fu_busy_cnt 174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008028 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76777 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32254 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19887 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21250 # Type of FU issued +system.cpu.iq.rate 0.458152 # Inst issue rate +system.cpu.iq.fu_busy_cnt 153 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007200 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75310 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31611 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19572 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21848 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21403 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1965 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 238 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24981 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 536 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3653 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 660 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24529 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 387 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2330 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 295 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 957 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20477 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3262 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1197 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20156 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3213 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1094 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1177 # number of nop insts executed -system.cpu.iew.exec_refs 5386 # number of memory reference insts executed -system.cpu.iew.exec_branches 4289 # Number of branches executed -system.cpu.iew.exec_stores 2124 # Number of stores executed -system.cpu.iew.exec_rate 0.437001 # Inst execution rate -system.cpu.iew.wb_sent 20145 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19887 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9217 # num instructions producing a value -system.cpu.iew.wb_consumers 11299 # num instructions consuming a value +system.cpu.iew.exec_nop 1139 # number of nop insts executed +system.cpu.iew.exec_refs 5233 # number of memory reference insts executed +system.cpu.iew.exec_branches 4247 # Number of branches executed +system.cpu.iew.exec_stores 2020 # Number of stores executed +system.cpu.iew.exec_rate 0.434565 # Inst execution rate +system.cpu.iew.wb_sent 19807 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19572 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9210 # num instructions producing a value +system.cpu.iew.wb_consumers 11373 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.424410 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.815736 # average fanout of values written-back +system.cpu.iew.wb_rate 0.421974 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9729 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9292 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31194 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.486055 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.173479 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 30632 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.494973 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.191764 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23830 76.39% 76.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4047 12.97% 89.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1444 4.63% 94.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 788 2.53% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 343 1.10% 97.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 244 0.78% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 322 1.03% 99.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 69 0.22% 99.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 107 0.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23334 76.18% 76.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1377 4.50% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 324 1.06% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 65 0.21% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30632 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -430,68 +430,68 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 55155 # The number of ROB reads -system.cpu.rob.rob_writes 51753 # The number of ROB writes -system.cpu.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13716 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54149 # The number of ROB reads +system.cpu.rob.rob_writes 50819 # The number of ROB writes +system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13862 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.245913 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.245913 # CPI: Total CPI of All Threads -system.cpu.ipc 0.308080 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.308080 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32584 # number of integer regfile reads -system.cpu.int_regfile_writes 18115 # number of integer regfile writes -system.cpu.misc_regfile_reads 7035 # number of misc regfile reads +system.cpu.cpi 3.212940 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.212940 # CPI: Total CPI of All Threads +system.cpu.ipc 0.311241 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.311241 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32188 # number of integer regfile reads +system.cpu.int_regfile_writes 17920 # number of integer regfile writes +system.cpu.misc_regfile_reads 6865 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 194.443697 # Cycle average of tags in use -system.cpu.icache.total_refs 5086 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 191.561206 # Cycle average of tags in use +system.cpu.icache.total_refs 4845 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15.047337 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 14.334320 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 194.443697 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.094943 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.094943 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5086 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5086 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5086 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5086 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5086 # number of overall hits -system.cpu.icache.overall_hits::total 5086 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses -system.cpu.icache.overall_misses::total 478 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21903000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21903000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21903000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21903000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21903000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21903000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5564 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5564 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5564 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5564 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5564 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5564 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085909 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085909 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085909 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085909 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085909 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085909 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45822.175732 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45822.175732 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45822.175732 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45822.175732 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45822.175732 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45822.175732 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 191.561206 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.093536 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.093536 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4845 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4845 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4845 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4845 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4845 # number of overall hits +system.cpu.icache.overall_hits::total 4845 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 492 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 492 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 492 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 492 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 492 # number of overall misses +system.cpu.icache.overall_misses::total 492 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23061000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23061000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23061000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23061000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23061000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23061000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5337 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5337 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5337 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5337 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5337 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5337 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092187 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092187 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092187 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092187 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092187 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092187 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46871.951220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46871.951220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46871.951220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46871.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46871.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46871.951220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,103 +500,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 140 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 140 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 140 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 140 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 140 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 140 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 154 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 154 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 154 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 154 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16530500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16530500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16530500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16530500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16530500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16530500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060748 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060748 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060748 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.060748 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060748 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.060748 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48906.804734 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48906.804734 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48906.804734 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48906.804734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48906.804734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48906.804734 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17056000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17056000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17056000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17056000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17056000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17056000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063331 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063331 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063331 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.063331 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063331 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.063331 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50461.538462 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50461.538462 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50461.538462 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50461.538462 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50461.538462 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50461.538462 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 100.624732 # Cycle average of tags in use -system.cpu.dcache.total_refs 4052 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.944828 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 99.978765 # Cycle average of tags in use +system.cpu.dcache.total_refs 4011 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 27.285714 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 100.624732 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024567 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024567 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3013 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3013 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 99.978765 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024409 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024409 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2972 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2972 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4046 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4046 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4046 # number of overall hits -system.cpu.dcache.overall_hits::total 4046 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 129 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 129 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4005 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4005 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4005 # number of overall hits +system.cpu.dcache.overall_hits::total 4005 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 130 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 130 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 538 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 538 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 538 # number of overall misses -system.cpu.dcache.overall_misses::total 538 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6836500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6836500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19507474 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19507474 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26343974 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26343974 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26343974 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26343974 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3142 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3142 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses +system.cpu.dcache.overall_misses::total 539 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6945000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6945000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19513974 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19513974 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26458974 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26458974 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26458974 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26458974 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3102 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3102 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4584 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4584 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4584 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4584 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041057 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.041057 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4544 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4544 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4544 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4544 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041908 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.041908 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117365 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117365 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117365 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117365 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52996.124031 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52996.124031 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47695.535452 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47695.535452 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48966.494424 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48966.494424 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48966.494424 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48966.494424 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 427 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.118618 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118618 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118618 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118618 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53423.076923 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53423.076923 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47711.427873 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47711.427873 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49089.005566 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49089.005566 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49089.005566 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49089.005566 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.724138 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -608,50 +608,50 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 392 system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56667.808219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56667.808219 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032350 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032350 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032350 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032350 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59953.125000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59953.125000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54307.228916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54307.228916 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55755.102041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51540.372671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49696.428571 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55755.102041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51540.372671 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -722,49 +722,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18850140 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12468016 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6382124 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18850140 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35546.178571 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47223.174603 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37389.914787 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40892.313253 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40892.313253 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35546.178571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43624.123288 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37993.024896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35546.178571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43624.123288 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37993.024896 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37107.190476 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38620.195000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40988.698795 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40988.698795 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37107.190476 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43415.809524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39027.204969 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37107.190476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43415.809524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39027.204969 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 8143784d6..eec9abdb9 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -82,7 +82,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -106,7 +106,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index ffad57b6b..a099312ec 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:25 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:46:06 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index feda286ec..fb1046e47 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1344667 # Simulator instruction rate (inst/s) -host_op_rate 1342613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 673049198 # Simulator tick rate (ticks/s) -host_mem_usage 220960 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 19584 # Simulator instruction rate (inst/s) +host_op_rate 19584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9831731 # Simulator tick rate (ticks/s) +host_mem_usage 212388 # Number of bytes of host memory used +host_seconds 0.77 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index cd98523de..0cf9ff042 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -61,22 +61,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -92,22 +92,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -124,24 +124,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -151,10 +151,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -169,7 +169,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -193,7 +193,7 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index cacf98182..8494e13f4 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:28 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:40 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 43106000 because target called exit() +Exiting @ tick 41368000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index af9b5d77e..54610aef7 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 41368000 # Number of ticks simulated final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 652409 # Simulator instruction rate (inst/s) -host_op_rate 651936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1777530278 # Simulator tick rate (ticks/s) -host_mem_usage 220352 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 17560 # Simulator instruction rate (inst/s) +host_op_rate 17560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47909450 # Simulator tick rate (ticks/s) +host_mem_usage 220988 # Number of bytes of host memory used +host_seconds 0.86 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 07b9bbe53..1c2308afb 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -129,10 +129,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -140,7 +140,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -423,10 +423,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -434,7 +434,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -463,7 +463,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -575,10 +575,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -586,7 +586,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -869,10 +869,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -880,7 +880,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -1002,10 +1002,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -1013,7 +1013,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -1296,10 +1296,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -1307,7 +1307,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -1429,10 +1429,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -1440,7 +1440,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -1723,10 +1723,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -1734,7 +1734,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -1760,22 +1760,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -1793,22 +1793,35 @@ master=system.physmem.port slave=system.l2c.mem_side system.system_port [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 63ee30b34..b5c2c149d 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:31 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:40 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -15,54 +15,54 @@ Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 Iteration 1 completed -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 Iteration 4 completed -[Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 Iteration 5 completed +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 6, Thread 3] Got lock [Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 Iteration 6 completed [Iteration 7, Thread 2] Got lock [Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1 Iteration 7 completed -[Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 Iteration 8 completed [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 @@ -71,12 +71,12 @@ Iteration 8 completed [Iteration 9, Thread 2] Got lock [Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 10, Thread 3] Got lock [Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 113910500 because target called exit() +Exiting @ tick 104830500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index c68736462..13ed71f23 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,86 +1,86 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000109 # Number of seconds simulated -sim_ticks 108678000 # Number of ticks simulated -final_tick 108678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000105 # Number of seconds simulated +sim_ticks 104830500 # Number of ticks simulated +final_tick 104830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97735 # Simulator instruction rate (inst/s) -host_op_rate 97735 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9914053 # Simulator tick rate (ticks/s) -host_mem_usage 237564 # Number of bytes of host memory used -host_seconds 10.96 # Real time elapsed on the host -sim_insts 1071369 # Number of instructions simulated -sim_ops 1071369 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory +host_inst_rate 100032 # Simulator instruction rate (inst/s) +host_op_rate 100032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10132772 # Simulator tick rate (ticks/s) +host_mem_usage 236868 # Number of bytes of host memory used +host_seconds 10.35 # Real time elapsed on the host +sim_insts 1034897 # Number of instructions simulated +sim_ops 1034897 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5184 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28416 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 86 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 81 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 668 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 212002429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 98934467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50645025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11777913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 3533374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7655643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1177791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7655643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 393382285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 212002429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50645025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 3533374 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1177791 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267358619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 212002429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 98934467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50645025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11777913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 3533374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7655643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1177791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7655643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 393382285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 669 # Total number of read requests seen +system.physmem.num_reads::total 658 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 217341327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 102565570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49451257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 12210187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1831528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7936621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2442037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7936621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 401715150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 217341327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49451257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1831528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2442037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 271066150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 217341327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 102565570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49451257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 12210187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1831528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7936621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2442037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7936621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401715150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 659 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 993 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 42752 # Total number of bytes read from memory +system.physmem.cpureqs 980 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 42112 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 42752 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 42112 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 72 # Reqs where no action is needed system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 71 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 36 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 29 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 56 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 61 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 53 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 71 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 60 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 5 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 79 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 78 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 44 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -100,14 +100,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 108650000 # Total gap between requests +system.physmem.totGap 104802500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 669 # Categorize read packet sizes +system.physmem.readPktSize::6 659 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,12 +125,12 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 76 # categorize neither packet sizes +system.physmem.neitherpktsize::6 72 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -194,335 +194,335 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3390669 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 18414669 # Sum of mem lat for all requests -system.physmem.totBusLat 2676000 # Total cycles spent in databus access -system.physmem.totBankLat 12348000 # Total cycles spent in bank access -system.physmem.avgQLat 5068.26 # Average queueing delay per request -system.physmem.avgBankLat 18457.40 # Average bank access latency per request +system.physmem.totQLat 2987155 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 17761155 # Sum of mem lat for all requests +system.physmem.totBusLat 2636000 # Total cycles spent in databus access +system.physmem.totBankLat 12138000 # Total cycles spent in bank access +system.physmem.avgQLat 4532.86 # Average queueing delay per request +system.physmem.avgBankLat 18418.82 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27525.66 # Average memory access latency -system.physmem.avgRdBW 393.38 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26951.68 # Average memory access latency +system.physmem.avgRdBW 401.72 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 393.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 401.72 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.46 # Data bus utilization in percentage +system.physmem.busUtil 2.51 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 513 # Number of row buffer hits during reads +system.physmem.readRowHits 506 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 162406.58 # Average gap between requests +system.physmem.avgGap 159032.63 # Average gap between requests system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 217357 # number of cpu cycles simulated +system.cpu0.numCycles 209662 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 85486 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 83146 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1297 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 83094 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 80730 # Number of BTB hits +system.cpu0.BPredUnit.lookups 82004 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 79765 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1218 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 79291 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 77227 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 510 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 516 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17254 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 507547 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 85486 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81240 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 166653 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3954 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12694 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 16907 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 159637 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3804 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 12545 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1571 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6105 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 500 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 200686 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.529060 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.210670 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1361 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5871 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 192893 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.523176 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215866 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34033 16.96% 16.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 82572 41.14% 58.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 593 0.30% 58.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 970 0.48% 58.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 529 0.26% 59.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 78464 39.10% 98.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 697 0.35% 98.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 363 0.18% 98.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2465 1.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33256 17.24% 17.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79042 40.98% 58.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 584 0.30% 58.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 987 0.51% 59.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 454 0.24% 59.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 75108 38.94% 98.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 578 0.30% 98.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364 0.19% 98.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2520 1.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 200686 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.393298 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.335085 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18097 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14161 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 165636 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 283 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2509 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 504485 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2509 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18775 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 695 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12879 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 165279 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 549 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 501228 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 342771 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 999720 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 999720 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 329211 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13560 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 922 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 944 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3899 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 160553 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 81037 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 78269 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 78067 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 419118 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 416267 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 155 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11107 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10171 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 200686 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.074220 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.084012 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 192893 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391125 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.321370 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17503 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14000 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 158668 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 284 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2438 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 483730 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2438 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18159 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 648 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12765 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 158332 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 551 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 480873 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 329027 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 958899 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 958899 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 315995 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13032 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 877 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 903 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3587 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 153720 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 77689 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 74928 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 74758 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 402151 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 399521 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10786 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9496 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 192893 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.071205 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.088777 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33200 16.54% 16.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5091 2.54% 19.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 80178 39.95% 59.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 79595 39.66% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1563 0.78% 99.47% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 681 0.34% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 279 0.14% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 88 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 11 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 32269 16.73% 16.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4844 2.51% 19.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 76822 39.83% 59.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76327 39.57% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1582 0.82% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 687 0.36% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 263 0.14% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 200686 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 192893 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 45 20.36% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 20.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 64 28.96% 49.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 25.45% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 53 23.66% 49.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 114 50.89% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 175769 42.23% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 160047 38.45% 80.67% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 80451 19.33% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 169105 42.33% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 153283 38.37% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77133 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 416267 # Type of FU issued -system.cpu0.iq.rate 1.915130 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000531 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1033596 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 431231 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 414361 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 399521 # Type of FU issued +system.cpu0.iq.rate 1.905548 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 992323 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 413903 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 397700 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 416488 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 399745 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 77814 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 74515 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2358 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1433 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2133 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1389 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2509 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 439 # Number of cycles IEW is blocking +system.cpu0.iew.iewSquashCycles 2438 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 389 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 498940 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 337 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 160553 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 81037 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 840 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewDispatchedInsts 478542 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 300 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 153720 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 77689 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 377 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1128 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 415155 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 159727 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1112 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 327 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1115 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 398429 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 152970 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1092 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 78871 # number of nop insts executed -system.cpu0.iew.exec_refs 240043 # number of memory reference insts executed -system.cpu0.iew.exec_branches 82509 # Number of branches executed -system.cpu0.iew.exec_stores 80316 # Number of stores executed -system.cpu0.iew.exec_rate 1.910014 # Inst execution rate -system.cpu0.iew.wb_sent 414703 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 414361 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 245547 # num instructions producing a value -system.cpu0.iew.wb_consumers 248019 # num instructions consuming a value +system.cpu0.iew.exec_nop 75469 # number of nop insts executed +system.cpu0.iew.exec_refs 229968 # number of memory reference insts executed +system.cpu0.iew.exec_branches 79152 # Number of branches executed +system.cpu0.iew.exec_stores 76998 # Number of stores executed +system.cpu0.iew.exec_rate 1.900340 # Inst execution rate +system.cpu0.iew.wb_sent 398024 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 397700 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 235727 # num instructions producing a value +system.cpu0.iew.wb_consumers 238246 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.906361 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.990033 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.896863 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989427 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12749 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1297 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 198194 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.452991 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.132633 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 190472 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.448360 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.135276 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33728 17.02% 17.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 82160 41.45% 58.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2430 1.23% 59.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 731 0.37% 60.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 570 0.29% 60.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 77594 39.15% 99.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 452 0.23% 99.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 290 0.15% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32802 17.22% 17.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 78740 41.34% 58.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2340 1.23% 59.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 545 0.29% 60.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 74330 39.02% 99.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 456 0.24% 99.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 317 0.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 198194 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 486168 # Number of instructions committed -system.cpu0.commit.committedOps 486168 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 190472 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 466344 # Number of instructions committed +system.cpu0.commit.committedOps 466344 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 237799 # Number of memory references committed -system.cpu0.commit.loads 158195 # Number of loads committed +system.cpu0.commit.refs 227887 # Number of memory references committed +system.cpu0.commit.loads 151587 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 81491 # Number of branches committed +system.cpu0.commit.branches 78187 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 327542 # Number of committed integer instructions. +system.cpu0.commit.int_insts 314326 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 290 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 317 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 695660 # The number of ROB reads -system.cpu0.rob.rob_writes 1000360 # The number of ROB writes -system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 16671 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 407861 # Number of Instructions Simulated -system.cpu0.committedOps 407861 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 407861 # Number of Instructions Simulated -system.cpu0.cpi 0.532919 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.532919 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.876457 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.876457 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 742624 # number of integer regfile reads -system.cpu0.int_regfile_writes 334702 # number of integer regfile writes +system.cpu0.rob.rob_reads 667502 # The number of ROB reads +system.cpu0.rob.rob_writes 959472 # The number of ROB writes +system.cpu0.timesIdled 316 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 16769 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 391341 # Number of Instructions Simulated +system.cpu0.committedOps 391341 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 391341 # Number of Instructions Simulated +system.cpu0.cpi 0.535753 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.535753 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.866533 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.866533 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 712669 # number of integer regfile reads +system.cpu0.int_regfile_writes 321346 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 241901 # number of misc regfile reads +system.cpu0.misc_regfile_reads 231752 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 305 # number of replacements -system.cpu0.icache.tagsinuse 247.227558 # Cycle average of tags in use -system.cpu0.icache.total_refs 5357 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 596 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.988255 # Average number of references to valid blocks. +system.cpu0.icache.replacements 297 # number of replacements +system.cpu0.icache.tagsinuse 245.466325 # Cycle average of tags in use +system.cpu0.icache.total_refs 5129 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.737649 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 247.227558 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.482866 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.482866 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5357 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5357 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5357 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5357 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5357 # number of overall hits -system.cpu0.icache.overall_hits::total 5357 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 748 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 748 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 748 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 748 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 748 # number of overall misses -system.cpu0.icache.overall_misses::total 748 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25787000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 25787000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 25787000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 25787000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 25787000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 25787000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6105 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6105 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6105 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6105 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6105 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6105 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122523 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.122523 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122523 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.122523 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122523 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.122523 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34474.598930 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 34474.598930 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34474.598930 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 34474.598930 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34474.598930 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 34474.598930 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 245.466325 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.479426 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.479426 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5129 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5129 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5129 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5129 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5129 # number of overall hits +system.cpu0.icache.overall_hits::total 5129 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 742 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 742 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 742 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 742 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 742 # number of overall misses +system.cpu0.icache.overall_misses::total 742 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25612000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 25612000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 25612000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 25612000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 25612000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 25612000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5871 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5871 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5871 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5871 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5871 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5871 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126384 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.126384 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126384 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126384 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34517.520216 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 34517.520216 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 34517.520216 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 34517.520216 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,106 +531,106 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 151 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 151 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 151 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 151 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 151 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 151 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 597 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 597 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 597 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 597 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 597 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 597 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20662500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 20662500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20662500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 20662500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20662500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 20662500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097789 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097789 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097789 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.097789 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097789 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.097789 # 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of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 20478500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20478500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 20478500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100153 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.100153 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.100153 # mshr miss rate for overall accesses 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of tags in use +system.cpu0.dcache.total_refs 153554 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 942.988235 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 903.258824 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 144.093465 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.281433 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.281433 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 81376 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 81376 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79021 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 79021 # number of WriteReq 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160397 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 473 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 473 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 541 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 541 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 153631 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153631 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153631 # number of overall hits +system.cpu0.dcache.overall_hits::total 153631 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 471 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 471 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 550 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 550 # number of WriteReq misses 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SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34063498 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34063498 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34063498 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34063498 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 81849 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 81849 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 79562 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 79562 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1021 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1021 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1021 # number of overall misses +system.cpu0.dcache.overall_misses::total 1021 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11085500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11085500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22991498 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 22991498 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 390000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 34076998 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34076998 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34076998 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34076998 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78394 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78394 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76258 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76258 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 161411 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 161411 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161411 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 161411 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005779 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005779 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006800 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006800 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 154652 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 154652 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154652 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154652 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006008 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006008 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007212 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007212 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006282 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006282 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006282 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006282 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23517.970402 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23517.970402 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42402.029575 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42402.029575 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18850 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 18850 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33593.193294 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33593.193294 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33593.193294 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33593.193294 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006602 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006602 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006602 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006602 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41802.723636 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41802.723636 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19500 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19500 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33376.099902 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33376.099902 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked @@ -641,364 +641,363 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 282 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 282 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 652 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 652 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 652 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 652 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 191 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 384 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 384 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 661 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 661 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 661 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 661 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 194 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 194 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 166 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 166 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses 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miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10440500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002334 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002334 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002149 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002149 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4894000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5605500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5605500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 350000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 350000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10499500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10499500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002475 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002475 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002177 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002177 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002243 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002243 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002243 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002243 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25429.319372 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25429.319372 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32652.046784 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32652.046784 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16850 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16850 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28841.160221 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28841.160221 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28841.160221 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28841.160221 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002328 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002328 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33768.072289 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33768.072289 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17500 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17500 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 181799 # number of cpu cycles simulated +system.cpu1.numCycles 174084 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 59567 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 56529 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1500 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 52860 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 52019 # Number of BTB hits +system.cpu1.BPredUnit.lookups 52904 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 50238 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1268 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 46828 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 46138 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 823 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 659 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 25837 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 338154 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 59567 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 52842 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 115388 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4298 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 25769 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 297398 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52904 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46797 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 103835 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3694 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 29305 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6220 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1046 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 17180 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 322 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 176992 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.910561 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.213171 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 6116 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 727 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 18660 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 169680 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.752699 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.165176 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 61604 34.81% 34.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 57789 32.65% 67.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4656 2.63% 70.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3206 1.81% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 672 0.38% 72.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 43499 24.58% 96.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1205 0.68% 97.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 866 0.49% 98.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3495 1.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 65845 38.81% 38.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52566 30.98% 69.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5632 3.32% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3204 1.89% 74.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 655 0.39% 75.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 36566 21.55% 96.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1212 0.71% 97.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 766 0.45% 98.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3234 1.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 176992 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.327653 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.860043 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 29997 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 23620 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 110723 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3705 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2727 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 334194 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2727 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 30767 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 10715 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12086 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 107285 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7192 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 331783 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 53 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 234003 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 646246 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 646246 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 218850 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15153 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1340 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9848 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 96301 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 46898 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 45474 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 41683 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 277198 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 277583 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 147 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12330 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11288 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 176992 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.568336 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.306945 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 169680 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.303899 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.708359 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 31981 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 26240 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 98388 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4607 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2348 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 293925 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2348 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 32683 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 13600 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11858 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 94082 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 8993 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 291891 # Number of instructions processed by rename +system.cpu1.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 205019 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 562522 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 562522 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 192184 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12835 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1091 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1214 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 11554 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 83196 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 39822 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 39557 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 34785 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 242788 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5818 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 244431 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 88 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10770 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 573 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 169680 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.440541 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.314007 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 58949 33.31% 33.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 18466 10.43% 43.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 46965 26.54% 70.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 47589 26.89% 97.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3312 1.87% 99.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1274 0.72% 99.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 318 0.18% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 58 0.03% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 63213 37.25% 37.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 21011 12.38% 49.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 39930 23.53% 73.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 40650 23.96% 97.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3306 1.95% 99.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1205 0.71% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 253 0.15% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 176992 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 169680 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 20 6.43% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 81 26.05% 32.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 67.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17 5.76% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 68 23.05% 28.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 132190 47.62% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 99212 35.74% 83.36% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 46181 16.64% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 118248 48.38% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 87044 35.61% 83.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 39139 16.01% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 277583 # Type of FU issued -system.cpu1.iq.rate 1.526868 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 311 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001120 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 732616 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 294445 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 275571 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 244431 # Type of FU issued +system.cpu1.iq.rate 1.404098 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 658925 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 259421 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 242675 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 277894 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 244726 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 41481 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 34549 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1604 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2395 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2727 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 837 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 328541 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 96301 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 46898 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 60 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 954 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 289058 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 83196 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 39822 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 70 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 494 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1175 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 276246 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 95320 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1337 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 930 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 243269 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 82226 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1162 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 46466 # number of nop insts executed -system.cpu1.iew.exec_refs 141403 # number of memory reference insts executed -system.cpu1.iew.exec_branches 55896 # Number of branches executed -system.cpu1.iew.exec_stores 46083 # Number of stores executed -system.cpu1.iew.exec_rate 1.519513 # Inst execution rate -system.cpu1.iew.wb_sent 275857 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 275571 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 158251 # num instructions producing a value -system.cpu1.iew.wb_consumers 163120 # num instructions consuming a value +system.cpu1.iew.exec_nop 40452 # number of nop insts executed +system.cpu1.iew.exec_refs 121286 # number of memory reference insts executed +system.cpu1.iew.exec_branches 49717 # Number of branches executed +system.cpu1.iew.exec_stores 39060 # Number of stores executed +system.cpu1.iew.exec_rate 1.397423 # Inst execution rate +system.cpu1.iew.wb_sent 242942 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 242675 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 138073 # num instructions producing a value +system.cpu1.iew.wb_consumers 142763 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.515800 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.970151 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.394011 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.967148 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14237 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4286 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1500 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 168046 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.870327 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.085151 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12362 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5245 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1268 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 161217 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.716302 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.045846 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 57008 33.92% 33.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 53849 32.04% 65.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6186 3.68% 69.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5193 3.09% 72.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1537 0.91% 73.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 41906 24.94% 98.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 558 0.33% 98.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 997 0.59% 99.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 812 0.48% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 62248 38.61% 38.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 47764 29.63% 68.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6052 3.75% 71.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.97% 76.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 35062 21.75% 98.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 510 0.32% 98.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1010 0.63% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 821 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 168046 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 314301 # Number of instructions committed -system.cpu1.commit.committedOps 314301 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161217 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 276697 # Number of instructions committed +system.cpu1.commit.committedOps 276697 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 138950 # Number of memory references committed -system.cpu1.commit.loads 93656 # Number of loads committed -system.cpu1.commit.membars 3574 # Number of memory barriers committed -system.cpu1.commit.branches 54833 # Number of branches committed +system.cpu1.commit.refs 119191 # Number of memory references committed +system.cpu1.commit.loads 80801 # Number of loads committed +system.cpu1.commit.membars 4532 # Number of memory barriers committed +system.cpu1.commit.branches 48885 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 215906 # Number of committed integer instructions. +system.cpu1.commit.int_insts 190199 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 821 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 495185 # The number of ROB reads -system.cpu1.rob.rob_writes 659817 # The number of ROB writes -system.cpu1.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4807 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35556 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 265102 # Number of Instructions Simulated -system.cpu1.committedOps 265102 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 265102 # Number of Instructions Simulated -system.cpu1.cpi 0.685770 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.685770 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.458215 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.458215 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 483798 # number of integer regfile reads -system.cpu1.int_regfile_writes 224930 # number of integer regfile writes +system.cpu1.rob.rob_reads 448868 # The number of ROB reads +system.cpu1.rob.rob_writes 580470 # The number of ROB writes +system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 4404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 232489 # Number of Instructions Simulated +system.cpu1.committedOps 232489 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 232489 # Number of Instructions Simulated +system.cpu1.cpi 0.748784 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.748784 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.335499 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.335499 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 422509 # number of integer regfile reads +system.cpu1.int_regfile_writes 197149 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 143054 # number of misc regfile reads +system.cpu1.misc_regfile_reads 122869 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 321 # number of replacements -system.cpu1.icache.tagsinuse 91.372145 # Cycle average of tags in use -system.cpu1.icache.total_refs 16670 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 38.233945 # Average number of references to valid blocks. +system.cpu1.icache.replacements 317 # number of replacements +system.cpu1.icache.tagsinuse 85.783317 # Cycle average of tags in use +system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 42.771765 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 91.372145 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.178461 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.178461 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 16670 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16670 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16670 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16670 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16670 # number of overall hits -system.cpu1.icache.overall_hits::total 16670 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 510 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 510 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 510 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 510 # number of overall misses -system.cpu1.icache.overall_misses::total 510 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10781500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10781500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10781500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10781500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10781500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10781500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 17180 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 17180 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 17180 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 17180 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 17180 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 17180 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029686 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029686 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029686 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029686 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029686 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029686 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21140.196078 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21140.196078 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21140.196078 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21140.196078 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21140.196078 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21140.196078 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 85.783317 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.167546 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.167546 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 18178 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 18178 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 18178 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 18178 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 18178 # number of overall hits +system.cpu1.icache.overall_hits::total 18178 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses +system.cpu1.icache.overall_misses::total 482 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9898500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9898500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9898500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9898500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9898500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9898500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 18660 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 18660 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 18660 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 18660 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 18660 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 18660 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025831 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.025831 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025831 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.025831 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025831 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.025831 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20536.307054 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20536.307054 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20536.307054 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20536.307054 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1007,106 +1006,106 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 74 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 74 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 74 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8808000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8808000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8808000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8808000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8808000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8808000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.025378 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.025378 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.025378 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.025378 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.025378 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.025378 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20201.834862 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20201.834862 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20201.834862 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 20201.834862 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20201.834862 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 20201.834862 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 57 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 57 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 57 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 57 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8055000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8055000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8055000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8055000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8055000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8055000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022776 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022776 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022776 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18952.941176 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.445610 # Cycle average of tags in use -system.cpu1.dcache.total_refs 51579 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1778.586207 # Average number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.224773 # Cycle average of tags in use +system.cpu1.dcache.total_refs 44406 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 1585.928571 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage 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98490 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 415 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 415 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 145 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 145 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 560 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 560 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 560 # number of overall misses -system.cpu1.dcache.overall_misses::total 560 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6026000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6026000 # number of ReadReq miss cycles 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WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 45228 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 99050 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 99050 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 99050 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 99050 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007711 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.007711 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003206 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003206 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.818182 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005654 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005654 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005654 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005654 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14520.481928 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14520.481928 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21772.413793 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21772.413793 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 10287.037037 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 10287.037037 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16398.214286 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16398.214286 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16398.214286 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16398.214286 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 27.224773 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.053173 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.053173 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 47254 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 47254 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 38186 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 38186 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 85440 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 85440 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 85440 # number of overall hits +system.cpu1.dcache.overall_hits::total 85440 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 407 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 407 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 53 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 544 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 544 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 544 # number of overall misses +system.cpu1.dcache.overall_misses::total 544 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6159500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6159500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2649500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2649500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 528500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 528500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8809000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8809000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8809000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8809000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 47661 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 47661 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 38323 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 38323 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 85984 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 85984 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 85984 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 85984 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008539 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008539 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003575 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003575 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.791045 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.791045 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006327 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006327 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006327 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006327 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15133.906634 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15133.906634 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19339.416058 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19339.416058 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9971.698113 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9971.698113 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16193.014706 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16193.014706 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1115,364 +1114,364 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 257 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 37 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 37 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 294 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 294 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 294 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 294 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1540500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1540500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1377000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1377000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 447500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 447500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2917500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2917500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2917500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2917500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002936 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002936 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002388 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002388 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.818182 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.818182 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002686 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002686 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002686 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002686 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9750 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9750 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12750 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12750 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8287.037037 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8287.037037 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10968.045113 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10968.045113 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10968.045113 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10968.045113 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 252 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 284 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 284 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 284 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 284 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 53 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1383500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1383500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 422500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 422500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2913500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2913500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2913500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2913500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003252 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003252 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002740 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002740 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.791045 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.791045 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003024 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003024 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9870.967742 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9870.967742 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13176.190476 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13176.190476 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7971.698113 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7971.698113 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 181474 # number of cpu cycles simulated +system.cpu2.numCycles 173759 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 55930 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 52799 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1548 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 49143 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 48122 # Number of BTB hits +system.cpu2.BPredUnit.lookups 43658 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 40905 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1282 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 37514 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 36718 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 28647 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 313051 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 55930 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 48979 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 109339 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4440 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 31939 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 33388 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 235313 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 43658 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 37372 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 88227 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3786 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 41179 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6238 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 20302 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 180005 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.739124 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.167787 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6107 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 690 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 25041 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 172022 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.367924 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.005612 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 70666 39.26% 39.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 55453 30.81% 70.06% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6160 3.42% 73.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3207 1.78% 75.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 684 0.38% 75.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 38160 21.20% 96.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1206 0.67% 97.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 867 0.48% 98.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3602 2.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 83795 48.71% 48.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 46271 26.90% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8744 5.08% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3171 1.84% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 732 0.43% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 24119 14.02% 96.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1119 0.65% 97.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 764 0.44% 98.08% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3307 1.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 180005 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.308198 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.725046 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 34354 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 28279 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 103112 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5207 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2815 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 308841 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2815 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 35130 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 15148 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12314 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 98150 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 10210 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 306064 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 214486 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 588858 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 588858 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 198873 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15613 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1249 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1373 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 13264 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 87101 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 41559 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 41593 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 36327 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 253620 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6426 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 255375 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 12537 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11608 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 180005 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.418711 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.312032 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 172022 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.251256 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.354249 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 40935 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 35177 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 79843 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 7534 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2426 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 231751 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2426 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 41648 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 22387 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11999 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 72579 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14876 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 229374 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 158064 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 425055 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 425055 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 145196 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12868 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1106 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 17601 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 61347 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 27349 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 30218 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 22307 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 186544 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8963 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 190992 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 11074 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10969 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 172022 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.110277 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.273783 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 68069 37.82% 37.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23048 12.80% 50.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 41620 23.12% 73.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 42277 23.49% 97.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3294 1.83% 99.06% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1277 0.71% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 306 0.17% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 81441 47.34% 47.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 30126 17.51% 64.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 27409 15.93% 80.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 28202 16.39% 97.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3303 1.92% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1178 0.68% 99.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 180005 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172022 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 123049 48.18% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.18% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 91506 35.83% 84.02% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 40820 15.98% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 96218 50.38% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 68109 35.66% 86.04% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 26665 13.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 255375 # Type of FU issued -system.cpu2.iq.rate 1.407226 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 299 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001171 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 691125 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 272626 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 253322 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 190992 # Type of FU issued +system.cpu2.iq.rate 1.099178 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 287 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001503 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 554402 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 206628 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 189208 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 255674 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 191279 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 36105 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 22028 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2679 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1636 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2518 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1460 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2815 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 752 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 302670 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 87101 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 41559 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 904 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 226591 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 61347 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 27349 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1066 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1214 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1723 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 254008 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 86102 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1367 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1394 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 189816 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 60231 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 42624 # number of nop insts executed -system.cpu2.iew.exec_refs 126828 # number of memory reference insts executed -system.cpu2.iew.exec_branches 52054 # Number of branches executed -system.cpu2.iew.exec_stores 40726 # Number of stores executed -system.cpu2.iew.exec_rate 1.399694 # Inst execution rate -system.cpu2.iew.wb_sent 253605 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 253322 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 143679 # num instructions producing a value -system.cpu2.iew.wb_consumers 148564 # num instructions consuming a value +system.cpu2.iew.exec_nop 31084 # number of nop insts executed +system.cpu2.iew.exec_refs 86812 # number of memory reference insts executed +system.cpu2.iew.exec_branches 40244 # Number of branches executed +system.cpu2.iew.exec_stores 26581 # Number of stores executed +system.cpu2.iew.exec_rate 1.092410 # Inst execution rate +system.cpu2.iew.wb_sent 189478 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 189208 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 103581 # num instructions producing a value +system.cpu2.iew.wb_consumers 108246 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.395913 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.967119 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.088911 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.956904 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14523 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5804 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1548 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 170953 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.685416 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.035354 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12701 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 8313 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1282 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 163490 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.308153 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.875243 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 67602 39.54% 39.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 50009 29.25% 68.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6225 3.64% 72.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6684 3.91% 76.35% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1541 0.90% 77.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 36526 21.37% 98.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 553 0.32% 98.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1000 0.58% 99.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 83402 51.01% 51.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 38322 23.44% 74.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6091 3.73% 78.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 9201 5.63% 83.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1555 0.95% 84.76% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 22612 13.83% 98.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 481 0.29% 98.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1011 0.62% 99.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 815 0.50% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 170953 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 288127 # Number of instructions committed -system.cpu2.commit.committedOps 288127 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 163490 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 213870 # Number of instructions committed +system.cpu2.commit.committedOps 213870 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 124345 # Number of memory references committed -system.cpu2.commit.loads 84422 # Number of loads committed -system.cpu2.commit.membars 5089 # Number of memory barriers committed -system.cpu2.commit.branches 50979 # Number of branches committed +system.cpu2.commit.refs 84718 # Number of memory references committed +system.cpu2.commit.loads 58829 # Number of loads committed +system.cpu2.commit.membars 7592 # Number of memory barriers committed +system.cpu2.commit.branches 39438 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 197443 # Number of committed integer instructions. +system.cpu2.commit.int_insts 146274 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 813 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 472203 # The number of ROB reads -system.cpu2.rob.rob_writes 608127 # The number of ROB writes -system.cpu2.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1469 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35881 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 241270 # Number of Instructions Simulated -system.cpu2.committedOps 241270 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 241270 # Number of Instructions Simulated -system.cpu2.cpi 0.752161 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.752161 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.329502 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.329502 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 440107 # number of integer regfile reads -system.cpu2.int_regfile_writes 204983 # number of integer regfile writes +system.cpu2.rob.rob_reads 388659 # The number of ROB reads +system.cpu2.rob.rob_writes 455572 # The number of ROB writes +system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1737 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35901 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 176057 # Number of Instructions Simulated +system.cpu2.committedOps 176057 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 176057 # Number of Instructions Simulated +system.cpu2.cpi 0.986947 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.986947 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.013225 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.013225 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 319017 # number of integer regfile reads +system.cpu2.int_regfile_writes 150022 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 128465 # number of misc regfile reads +system.cpu2.misc_regfile_reads 88362 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 323 # number of replacements -system.cpu2.icache.tagsinuse 83.164978 # Cycle average of tags in use -system.cpu2.icache.total_refs 19795 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 45.194064 # Average number of references to valid blocks. +system.cpu2.icache.replacements 319 # number of replacements +system.cpu2.icache.tagsinuse 80.119670 # Cycle average of tags in use +system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 57.263403 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 83.164978 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.162432 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.162432 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 19795 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19795 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19795 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19795 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19795 # number of overall hits -system.cpu2.icache.overall_hits::total 19795 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 507 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 507 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 507 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 507 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 507 # number of overall misses -system.cpu2.icache.overall_misses::total 507 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6587500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6587500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6587500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6587500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6587500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6587500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 20302 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 20302 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 20302 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 20302 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 20302 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 20302 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024973 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024973 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024973 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024973 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024973 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024973 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 12993.096647 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 12993.096647 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 12993.096647 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 12993.096647 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 12993.096647 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 12993.096647 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 80.119670 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.156484 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.156484 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 24566 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 24566 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 24566 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 24566 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 24566 # number of overall hits +system.cpu2.icache.overall_hits::total 24566 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 475 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 475 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 475 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 475 # number of overall misses +system.cpu2.icache.overall_misses::total 475 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6356500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6356500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6356500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6356500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6356500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6356500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 25041 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 25041 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 25041 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 25041 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 25041 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 25041 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.018969 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.018969 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018969 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.018969 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018969 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.018969 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13382.105263 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13382.105263 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13382.105263 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13382.105263 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1481,106 +1480,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 69 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 69 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 69 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5265000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5265000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5265000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5265000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5265000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5265000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021574 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021574 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021574 # mshr miss rate for demand accesses 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of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 46 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 429 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 429 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 429 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 429 # number of overall MSHR misses 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0.010397 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010397 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005152 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.005152 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.786667 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.786667 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008281 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.008281 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008281 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.008281 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12935.768262 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 12935.768262 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17620.300752 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 17620.300752 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9576.271186 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9576.271186 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14111.320755 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14111.320755 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1589,364 +1588,364 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 266 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 301 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 301 # number of overall MSHR hits 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-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9237.827715 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 227 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 32 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 259 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 259 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 259 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 259 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1409000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1409000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1142500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1142500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 447000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 447000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2551500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2551500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2551500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2551500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004452 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004452 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003913 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003913 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.786667 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.786667 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004234 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004234 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8288.235294 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8288.235294 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11311.881188 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11311.881188 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7576.271186 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7576.271186 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 181164 # number of cpu cycles simulated +system.cpu3.numCycles 173449 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 41552 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 38392 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1515 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 34829 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 33780 # Number of BTB hits +system.cpu3.BPredUnit.lookups 53688 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 50962 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1276 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 47521 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 46771 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 860 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 661 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 36927 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 218203 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 41552 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 34640 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 84802 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4380 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 47727 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 301358 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 53688 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 47432 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 105431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3739 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 29902 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6229 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 974 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 28719 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 179453 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.215934 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 1.926514 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6125 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 19205 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 172027 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.751806 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.162661 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 94651 52.74% 52.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 45326 25.26% 78.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10365 5.78% 83.78% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3238 1.80% 85.58% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 710 0.40% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 19490 10.86% 96.84% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1177 0.66% 97.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 887 0.49% 97.99% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3609 2.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 66596 38.71% 38.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 53420 31.05% 69.77% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 5840 3.39% 73.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3208 1.86% 75.03% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 724 0.42% 75.45% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 37059 21.54% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1114 0.65% 97.64% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 769 0.45% 98.08% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3297 1.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 179453 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.229361 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.204450 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 46454 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 40187 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 74815 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 8979 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2789 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 213927 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2789 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 47212 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 26606 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12751 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 66126 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 17740 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 211407 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 144414 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 382760 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 382760 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 129180 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15234 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1257 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1396 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 20650 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 54196 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 23010 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 27226 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 17768 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 169289 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 10641 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 175038 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12721 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11252 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 865 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 179453 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.975397 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.233089 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 172027 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.309532 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.737444 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 32330 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 26595 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 99738 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4852 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2387 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 297869 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2387 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 33042 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 14161 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11648 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 95158 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 9506 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 295495 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 42 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 206972 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 568769 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 568769 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 194051 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1213 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 12164 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 84321 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 40263 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 40233 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 35230 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 245462 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6061 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 247263 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10948 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10583 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 569 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 172027 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.437350 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.311410 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 92486 51.54% 51.54% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 34868 19.43% 70.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 23272 12.97% 83.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 23945 13.34% 97.28% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3213 1.79% 99.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1245 0.69% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 315 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 63993 37.20% 37.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 21775 12.66% 49.86% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 40281 23.42% 73.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 41063 23.87% 97.14% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3352 1.95% 99.09% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1207 0.70% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 253 0.15% 99.94% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 179453 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 172027 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 20 6.92% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 59 20.42% 27.34% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 72.66% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 90201 51.53% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.53% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 62467 35.69% 87.22% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 22370 12.78% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 119304 48.25% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 88373 35.74% 83.99% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 39586 16.01% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 175038 # Type of FU issued -system.cpu3.iq.rate 0.966185 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001651 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 529859 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 192688 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 173081 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 247263 # Type of FU issued +system.cpu3.iq.rate 1.425566 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 287 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001161 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 666924 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 262516 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 245480 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 175327 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 247550 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 17671 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 34961 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1490 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2463 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2789 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 857 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 208183 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 54196 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 23010 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1178 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 786 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 292666 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 339 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 84321 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 40263 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 501 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1172 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1673 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 173760 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 53123 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1278 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 246084 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 83306 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1179 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 28253 # number of nop insts executed -system.cpu3.iew.exec_refs 75420 # number of memory reference insts executed -system.cpu3.iew.exec_branches 37599 # Number of branches executed -system.cpu3.iew.exec_stores 22297 # Number of stores executed -system.cpu3.iew.exec_rate 0.959131 # Inst execution rate -system.cpu3.iew.wb_sent 173368 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 173081 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 92251 # num instructions producing a value -system.cpu3.iew.wb_consumers 97140 # num instructions consuming a value +system.cpu3.iew.exec_nop 41143 # number of nop insts executed +system.cpu3.iew.exec_refs 122808 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50377 # Number of branches executed +system.cpu3.iew.exec_stores 39502 # Number of stores executed +system.cpu3.iew.exec_rate 1.418769 # Inst execution rate +system.cpu3.iew.wb_sent 245746 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 245480 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 139608 # num instructions producing a value +system.cpu3.iew.wb_consumers 144273 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.955383 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.949671 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.415286 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.967665 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14656 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 9776 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1515 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 170436 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.135365 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.770418 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12526 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5492 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1276 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 163516 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.713105 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.043722 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 95921 56.28% 56.28% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 35624 20.90% 77.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6200 3.64% 80.82% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 10664 6.26% 87.08% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1534 0.90% 87.98% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 18221 10.69% 98.67% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 461 0.27% 98.94% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1004 0.59% 99.53% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 807 0.47% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 63247 38.68% 38.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 48404 29.60% 68.28% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6092 3.73% 72.01% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6399 3.91% 75.92% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1556 0.95% 76.87% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 35437 21.67% 98.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 553 0.34% 98.88% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1016 0.62% 99.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 170436 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 193507 # Number of instructions committed -system.cpu3.commit.committedOps 193507 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 163516 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 280120 # Number of instructions committed +system.cpu3.commit.committedOps 280120 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 73074 # Number of memory references committed -system.cpu3.commit.loads 51554 # Number of loads committed -system.cpu3.commit.membars 9056 # Number of memory barriers committed -system.cpu3.commit.branches 36531 # Number of branches committed +system.cpu3.commit.refs 120652 # Number of memory references committed +system.cpu3.commit.loads 81858 # Number of loads committed +system.cpu3.commit.membars 4779 # Number of memory barriers committed +system.cpu3.commit.branches 49540 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 131724 # Number of committed integer instructions. +system.cpu3.commit.int_insts 192312 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 807 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 377205 # The number of ROB reads -system.cpu3.rob.rob_writes 419128 # The number of ROB writes -system.cpu3.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1711 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 36191 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 157136 # Number of Instructions Simulated -system.cpu3.committedOps 157136 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 157136 # Number of Instructions Simulated -system.cpu3.cpi 1.152912 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.152912 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.867369 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.867369 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 286066 # number of integer regfile reads -system.cpu3.int_regfile_writes 135262 # number of integer regfile writes +system.cpu3.rob.rob_reads 454763 # The number of ROB reads +system.cpu3.rob.rob_writes 587684 # The number of ROB writes +system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1422 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 36211 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 235010 # Number of Instructions Simulated +system.cpu3.committedOps 235010 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 235010 # Number of Instructions Simulated +system.cpu3.cpi 0.738049 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.738049 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.354923 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.354923 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 427031 # number of integer regfile reads +system.cpu3.int_regfile_writes 198982 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 77098 # number of misc regfile reads +system.cpu3.misc_regfile_reads 124365 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 322 # number of replacements -system.cpu3.icache.tagsinuse 86.042865 # Cycle average of tags in use -system.cpu3.icache.total_refs 28227 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 64.740826 # Average number of references to valid blocks. +system.cpu3.icache.replacements 318 # number of replacements +system.cpu3.icache.tagsinuse 83.493816 # Cycle average of tags in use +system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 428 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 43.764019 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 86.042865 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.168052 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.168052 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 28227 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 28227 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 28227 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 28227 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 28227 # number of overall hits -system.cpu3.icache.overall_hits::total 28227 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 492 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 492 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 492 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 492 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 492 # number of overall misses -system.cpu3.icache.overall_misses::total 492 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6235000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6235000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6235000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6235000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6235000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6235000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 28719 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 28719 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 28719 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 28719 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 28719 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 28719 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.017132 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.017132 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.017132 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.017132 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.017132 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.017132 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12672.764228 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 12672.764228 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12672.764228 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 12672.764228 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12672.764228 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 12672.764228 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 83.493816 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.163074 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 18731 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 18731 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 18731 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 18731 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 18731 # number of overall hits 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overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6191000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 19205 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 19205 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 19205 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 19205 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 19205 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 19205 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024681 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.024681 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024681 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.024681 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024681 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.024681 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13061.181435 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13061.181435 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13061.181435 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13061.181435 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1955,106 +1954,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 56 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 56 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 56 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 56 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 436 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 436 # 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# average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11403.669725 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11403.669725 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 428 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 428 # number of demand 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number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7674500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7674500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7674500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 48327 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 48327 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 38727 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 38727 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 87054 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 87054 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 87054 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 87054 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008815 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.008815 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003667 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003667 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835821 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006525 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006525 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12539.906103 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12539.906103 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16426.056338 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 16426.056338 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9910.714286 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9910.714286 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 13511.443662 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 13511.443662 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2063,288 +2062,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 204 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 204 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 238 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 238 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 238 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 238 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 165 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1399500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1399500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1252500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1252500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 509500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 509500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2652000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2652000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2652000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2652000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004657 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004657 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004896 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004896 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.770270 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.770270 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004747 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004747 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004747 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004747 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8481.818182 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8481.818182 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 11928.571429 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 11928.571429 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 8938.596491 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 8938.596491 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9822.222222 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9822.222222 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9822.222222 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9822.222222 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 273 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 273 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 306 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 306 # number of 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+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1265000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1265000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1159500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1159500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 443000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 443000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2424500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2424500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2424500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2424500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003166 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002815 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002815 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835821 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003010 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003010 # mshr miss rate for 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-system.l2c.occ_blocks::cpu0.inst 293.557210 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.439095 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 69.391444 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.684600 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 3.455152 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.725294 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 0.907046 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.768385 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.828895 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 289.891501 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.268437 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 63.508816 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.639642 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2.310248 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.728233 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.354110 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.766714 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004479 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000907 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001059 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000053 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000904 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000969 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000035 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000036 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006634 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 236 # number of ReadReq hits +system.l2c.occ_percent::total 0.006490 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42656.432432 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42455.023256 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.311437 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42575.351351 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41858.571429 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 33501.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 34334 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 38316.561338 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10211.105263 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10056.444444 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10027.263158 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10225.550000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10132.315789 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40862.851064 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56501.076923 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45834.750000 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 37657.734848 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.578947 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10084.166667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10200.600000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10025.950000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.888889 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40740.531915 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55347.153846 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45751.500000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42584.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 43027.916031 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36411.567867 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41652.880952 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42455.023256 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51376.200000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 33501.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46616.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28002 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42818.007634 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41548.726190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50626.150000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46540 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39239.113602 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36411.567867 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41652.880952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42455.023256 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51376.200000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 33501.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46616.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36462.350140 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41548.726190 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37359.580247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50626.150000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 34334 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46540 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45376.750000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39239.113602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index 980beb479..6cfde7057 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -65,10 +65,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -76,11 +76,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -96,10 +96,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -107,11 +107,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -136,7 +136,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -184,10 +184,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -195,11 +195,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -215,10 +215,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -226,11 +226,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -284,10 +284,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -295,11 +295,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -315,10 +315,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -326,11 +326,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -384,10 +384,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -395,11 +395,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -415,10 +415,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -426,11 +426,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -452,22 +452,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -487,7 +487,7 @@ slave=system.l2c.mem_side system.system_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -500,7 +500,7 @@ port=system.membus.master[0] [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 77c22c008..c63257902 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:36 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:52 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 686f019bc..bb7e4e4f9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163854 # Simulator instruction rate (inst/s) -host_op_rate 163852 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21217098 # Simulator tick rate (ticks/s) -host_mem_usage 1151472 # Number of bytes of host memory used -host_seconds 4.13 # Real time elapsed on the host +host_inst_rate 174734 # Simulator instruction rate (inst/s) +host_op_rate 174733 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22625965 # Simulator tick rate (ticks/s) +host_mem_usage 1150028 # Number of bytes of host memory used +host_seconds 3.88 # Real time elapsed on the host sim_insts 677327 # Number of instructions simulated sim_ops 677327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index c224b90ec..244af9704 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -61,10 +61,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -72,11 +72,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -92,10 +92,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -103,11 +103,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -132,7 +132,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -176,10 +176,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -187,11 +187,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -207,10 +207,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -218,11 +218,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -272,10 +272,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -283,11 +283,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -303,10 +303,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -314,11 +314,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -368,10 +368,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -379,11 +379,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -399,10 +399,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -410,11 +410,11 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system -tgts_per_mshr=8 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -436,22 +436,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -471,7 +471,7 @@ slave=system.l2c.mem_side system.system_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -484,7 +484,7 @@ port=system.membus.master[0] [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index d61ea072e..3b151bc02 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,82 +1,82 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:39 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:46:01 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 Iteration 1 completed -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 Iteration 2 completed +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 Iteration 4 completed +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 Iteration 5 completed -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 Iteration 6 completed +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 Iteration 9 completed -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 10, Thread 3] Got lock [Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 268898000 because target called exit() +Exiting @ tick 261623500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index df50fe29d..6b9b27a43 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000262 # Nu sim_ticks 261623500 # Number of ticks simulated final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 776063 # Simulator instruction rate (inst/s) -host_op_rate 776047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 307506962 # Simulator tick rate (ticks/s) -host_mem_usage 231300 # Number of bytes of host memory used -host_seconds 0.85 # Real time elapsed on the host +host_inst_rate 114971 # Simulator instruction rate (inst/s) +host_op_rate 114971 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45557694 # Simulator tick rate (ticks/s) +host_mem_usage 232524 # Number of bytes of host memory used +host_seconds 5.74 # Real time elapsed on the host sim_insts 660239 # Number of instructions simulated sim_ops 660239 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory |