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authorGabe Black <gblack@eecs.umich.edu>2007-12-01 23:00:58 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-12-01 23:00:58 -0800
commit4e3ff42762f8fd08e130b10e59525139f12c932d (patch)
tree19ca18a54c0bcbd0faed82d8db91fbb728637ceb
parentbfc62d1a7035dfdbad405c0ddbd897ea1174360d (diff)
downloadgem5-4e3ff42762f8fd08e130b10e59525139f12c932d.tar.xz
X86: Implement wrbase and wrlimit for loading pseudo descriptors.
--HG-- extra : convert_revision : fe03c4aed95ef12773e80cdb3d9cff68a2b20f02
-rw-r--r--src/arch/x86/isa/microops/regop.isa16
-rw-r--r--src/arch/x86/isa/operands.isa3
2 files changed, 19 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 4ac3a9d98..67e6fa1e9 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -936,4 +936,20 @@ let {{
ControlDest = newVal;
}
'''
+
+ class Wrbase(RegOp):
+ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+ super(Wrbase, self).__init__(dest, \
+ src1, "NUM_INTREGS", flags, dataSize)
+ code = '''
+ SegBaseDest = psrc1;
+ '''
+
+ class Wrlimit(RegOp):
+ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+ super(Wrlimit, self).__init__(dest, \
+ src1, "NUM_INTREGS", flags, dataSize)
+ code = '''
+ SegLimitDest = psrc1;
+ '''
}};
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 7a2631a9c..fff60ce60 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -127,5 +127,8 @@ def operands {{
'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73),
'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74),
'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
+ 'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 75),
+ 'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 76),
+
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}};