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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 23:26:36 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 23:26:36 -0400 |
| commit | 540d939fada9df6519e5ae0c34c1781b058235ce (patch) | |
| tree | 2e7a6e669e29b23e2a24f7c42b4814f8d605a9ef | |
| parent | 97449ef3dad10f4846b5328c983cc8fe523b81f5 (diff) | |
| download | gem5-540d939fada9df6519e5ae0c34c1781b058235ce.tar.xz | |
inorder: gem5.opt compile
variable name typo.
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index f6f027850..73dd9c527 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -433,7 +433,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size, if (inst->fault != NoFault) { DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating " - "addr:%08p for [sn:%i].\n", tid, tlb_fault->name(), + "addr:%08p for [sn:%i].\n", tid, inst->fault->name(), cache_req->memReq->getVaddr(), inst->seqNum); tlbBlocked[tid] = true; |