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authorNilay Vaish <nilay@cs.wisc.edu>2011-11-04 11:26:12 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2011-11-04 11:26:12 -0500
commit5ff6e05ffdf926523969de471044c9de8b00d593 (patch)
tree12d7d0c23dab7e93ff6dc89c05267e2eeb74d2b8
parent582ea4d5431f9fa9edbeb16835b04171647ea18b (diff)
downloadgem5-5ff6e05ffdf926523969de471044c9de8b00d593.tar.xz
MESI Protocol: Add functions for profiling misses
-rw-r--r--src/mem/protocol/MESI_CMP_directory-L1cache.sm15
-rw-r--r--src/mem/protocol/MESI_CMP_directory-L2cache.sm18
2 files changed, 32 insertions, 1 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
index b2ba0872e..f0be1fd34 100644
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
@@ -679,6 +679,17 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
mandatoryQueue_in.recycle();
}
+ action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
+ peek(mandatoryQueue_in, RubyRequest) {
+ L1IcacheMemory.profileMiss(in_msg);
+ }
+ }
+
+ action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
+ peek(mandatoryQueue_in, RubyRequest) {
+ L1DcacheMemory.profileMiss(in_msg);
+ }
+ }
//*****************************************************
// TRANSITIONS
@@ -698,6 +709,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
oo_allocateL1DCacheBlock;
i_allocateTBE;
a_issueGETS;
+ uu_profileDataMiss;
k_popMandatoryQueue;
}
@@ -705,6 +717,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
pp_allocateL1ICacheBlock;
i_allocateTBE;
ai_issueGETINSTR;
+ uu_profileInstMiss;
k_popMandatoryQueue;
}
@@ -712,6 +725,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
oo_allocateL1DCacheBlock;
i_allocateTBE;
b_issueGETX;
+ uu_profileDataMiss;
k_popMandatoryQueue;
}
@@ -729,6 +743,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
transition(S, Store, SM) {
i_allocateTBE;
c_issueUPGRADE;
+ uu_profileDataMiss;
k_popMandatoryQueue;
}
diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
index a8fcb07d1..2d8ae4ca8 100644
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
@@ -716,9 +716,25 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
}
}
+ GenericRequestType convertToGenericType(CoherenceRequestType type) {
+ if(type == CoherenceRequestType:GETS) {
+ return GenericRequestType:GETS;
+ } else if(type == CoherenceRequestType:GETX) {
+ return GenericRequestType:GETX;
+ } else if(type == CoherenceRequestType:GET_INSTR) {
+ return GenericRequestType:GET_INSTR;
+ } else if(type == CoherenceRequestType:UPGRADE) {
+ return GenericRequestType:UPGRADE;
+ } else {
+ DPRINTF(RubySlicc, "%s\n", type);
+ error("Invalid CoherenceRequestType\n");
+ }
+ }
+
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- //profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, L1CacheMachIDToProcessorNum(in_msg.Requestor));
+ L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type),
+ in_msg.AccessMode, in_msg.Prefetch);
}
}