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| author | Ali Saidi <saidi@eecs.umich.edu> | 2004-01-27 18:14:04 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-01-27 18:14:04 -0500 |
| commit | 6f3c09a12c7120b518e1c41d995094538b120ba0 (patch) | |
| tree | 9b59fa5c5c4699bf3346369414a7cd4ef508b91f | |
| parent | b7f44f6e0676a933c5aa4d892d789c46daeaaa27 (diff) | |
| download | gem5-6f3c09a12c7120b518e1c41d995094538b120ba0.tar.xz | |
uart works in linux
dev/tsunami_uart.cc:
added code make it work with linux's uart code.
--HG--
extra : convert_revision : 893a3439dac16cfe68dbd50daa475be04d9ee3de
| -rw-r--r-- | dev/tsunami_uart.cc | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/dev/tsunami_uart.cc b/dev/tsunami_uart.cc index 88f6a6f8a..373f3eb0d 100644 --- a/dev/tsunami_uart.cc +++ b/dev/tsunami_uart.cc @@ -42,6 +42,7 @@ Fault TsunamiUart::read(MemReqPtr req, uint8_t *data) { Addr daddr = req->paddr & addr_mask; + DPRINTF(TsunamiUart, " read register %#x\n", daddr); switch (req->size) { case sizeof(uint64_t): @@ -85,7 +86,7 @@ TsunamiUart::read(MemReqPtr req, uint8_t *data) return No_Fault; } } else { - int reg = (1 << 2); + int reg = (1 << 2) | (1 << 5) | (1 << 6); if (status & CONS_INT_RX) reg |= (1 << 0); *data = reg; @@ -105,6 +106,9 @@ TsunamiUart::read(MemReqPtr req, uint8_t *data) next_char = -1; // cons.next(); return No_Fault; + case 0x9: // Interrupt Enable Register + *data = 0; + return No_Fault; } panic("%s: read daddr=%#x type=read *data=%#x\n", name(), daddr, *data); @@ -116,6 +120,8 @@ Fault TsunamiUart::write(MemReqPtr req, const uint8_t *data) { Addr daddr = req->paddr & addr_mask; + + DPRINTF(TsunamiUart, " write register %#x value %#x\n", daddr, *(uint8_t*)data); switch (daddr) { case 0xb: status_store = *data; @@ -148,10 +154,10 @@ TsunamiUart::write(MemReqPtr req, const uint8_t *data) cons->out(*(uint64_t *)data); return No_Fault; case 0x9: // DLM - DPRINTF(TsunamiUart, "writing to DLM/IER %#x\n", *(uint64_t*)data); + DPRINTF(TsunamiUart, "writing to DLM/IER %#x\n", *(uint8_t*)data); return No_Fault; case 0xc: // MCR - DPRINTF(TsunamiUart, "writing to MCR %#x\n", *(uint64_t*)data); + DPRINTF(TsunamiUart, "writing to MCR %#x\n", *(uint8_t*)data); return No_Fault; } |