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authorGabe Black <gblack@eecs.umich.edu>2007-12-01 23:06:03 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-12-01 23:06:03 -0800
commit988c6f227afbd2048df2eeae55aed29a1addcab7 (patch)
tree191324aa2a2ab1855a4f731a39889bc9f9929ad7
parentfe833dd2c33818a1f92f87ea26b17e6b85d3976e (diff)
downloadgem5-988c6f227afbd2048df2eeae55aed29a1addcab7.tar.xz
X86: Implement mov from control register.
--HG-- extra : convert_revision : c8280f0686a3ae6d5c405327540ad15a3a5531f9
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/move.py4
-rw-r--r--src/arch/x86/isa/microops/regop.isa12
3 files changed, 17 insertions, 1 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 717a8f26f..b50c42cd9 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -216,7 +216,7 @@
0x04: decode LEGACY_DECODEVAL {
// no prefix
0x0: decode OPCODE_OP_BOTTOM3 {
- 0x0: mov_Rd_Cd();
+ 0x0: Inst::MOV(Rd,Cd);
0x1: mov_Rd_Dd();
0x2: Inst::MOV(Cd,Rd);
0x3: mov_Dd_Rd();
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
index aaddcf962..069d1010e 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -193,6 +193,10 @@ def macroop MOV_C_R {
wrcr reg, regm
};
+def macroop MOV_R_C {
+ rdcr reg, regm
+};
+
def macroop MOV_R_S {
rdsel reg, regm
};
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index de9f76e73..e761f0034 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -885,6 +885,18 @@ let {{
class Zext(RegOp):
code = 'DestReg = bits(psrc1, op2, 0);'
+ class Rdcr(RegOp):
+ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+ super(Rdcr, self).__init__(dest, \
+ src1, "NUM_INTREGS", flags, dataSize)
+ code = '''
+ if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
+ fault = new InvalidOpcode();
+ } else {
+ DestReg = ControlSrc1;
+ }
+ '''
+
class Wrcr(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Wrcr, self).__init__(dest, \