Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.

author: Ali Saidi <saidi@eecs.umich.edu> 2008-10-20 19:00:07 -0400
committer: Ali Saidi <saidi@eecs.umich.edu> 2008-10-20 19:00:07 -0400
commit: aac93b7d0ce5e8e0241c7299b49cc59a9d095f3e (patch)
tree: bbfdf01ccc199204dd2a385f1b4fab0b44c16a32
parent: b760b99f4d9f5469d88c67ae8a06e5f9543a43e7 (diff)
download: gem5-aac93b7d0ce5e8e0241c7299b49cc59a9d095f3e.tar.xz
14 files changed, 4695 insertions, 1 deletions
diff --git a/tests/SConscript b/tests/SConscript
index 984eaa97c..762262dfa 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -216,7 +216,8 @@ if env['FULL_SYSTEM']:
                         'tsunami-simple-timing',
                         'tsunami-simple-atomic-dual',
                         'tsunami-simple-timing-dual',
-                        'twosys-tsunami-simple-atomic']
+                        'twosys-tsunami-simple-atomic',
+                        'tsunami-o3', 'tsunami-o3-dual']
     if env['TARGET_ISA'] == 'sparc':
         configs += ['t1000-simple-atomic',
                     't1000-simple-timing']
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
new file mode 100644
index 000000000..5dbfa5a8b
--- /dev/null
+++ b/tests/configs/tsunami-o3-dual.py
@@ -0,0 +1,99 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.AddToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
+#cpu
+cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeLinuxAlphaSystem('timing')
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
+for c in cpus:
+    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                                L1(size = '32kB', assoc = 4))
+    # connect cpu level-1 caches to shared level-2 cache
+    c.connectMemPorts(system.toL2Bus)
+    c.clock = '2GHz'
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
new file mode 100644
index 000000000..ee60ea8ae
--- /dev/null
+++ b/tests/configs/tsunami-o3.py
@@ -0,0 +1,98 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.AddToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+    latency = '1ns'
+    block_size = 64
+    mshrs = 4
+    tgts_per_mshr = 8
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+    block_size = 64
+    latency = '10ns'
+    mshrs = 92
+    tgts_per_mshr = 16
+    write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
+#cpu
+cpu = DerivO3CPU(cpu_id=0)
+#the system
+system = FSConfig.makeLinuxAlphaSystem('timing')
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+                            L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectMemPorts(system.toL2Bus)
+cpu.clock = '2GHz'
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
new file mode 100644
index 000000000..dca62b55f
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -0,0 +1,1363 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=LinuxAlphaSystem
+children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+boot_cpu_frequency=500
+boot_osflags=root=/dev/hda1 console=ttyS0
+console=/dist/m5/system/binaries/console
+init_param=0
+kernel=/dist/m5/system/binaries/vmlinux
+mem_mode=timing
+pal=/dist/m5/system/binaries/ts_osfpal
+physmem=system.physmem
+readfile=tests/halt.sh
+symbolfile=
+system_rev=1024
+system_type=34
+
+[system.bridge]
+type=Bridge
+delay=50000
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:8589934591
+nack_delay=4000
+req_size_a=16
+req_size_b=16
+resp_size_a=16
+resp_size_b=16
+write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
+
+[system.cpu0]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu0.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu0.interrupts
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu0.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu0.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=4
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu0.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu0.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7
+
+[system.cpu0.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu0.fuPool.FUList0.opList
+
+[system.cpu0.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu0.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
+
+[system.cpu0.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu0.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu0.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
+
+[system.cpu0.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu0.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu0.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu0.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
+
+[system.cpu0.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu0.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu0.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu0.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu0.fuPool.FUList4.opList
+
+[system.cpu0.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu0.fuPool.FUList5]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu0.fuPool.FUList5.opList
+
+[system.cpu0.fuPool.FUList5.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu0.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
+
+[system.cpu0.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu0.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu0.fuPool.FUList7]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu0.fuPool.FUList7.opList
+
+[system.cpu0.fuPool.FUList7.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu0.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=4
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu0.interrupts]
+type=AlphaInterrupts
+
+[system.cpu0.itb]
+type=AlphaITB
+size=48
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=1
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu1.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu1.interrupts
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu1.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu1.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=4
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.dcache_port
+mem_side=system.toL2Bus.port[4]
+
+[system.cpu1.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu1.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7
+
+[system.cpu1.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu1.fuPool.FUList0.opList
+
+[system.cpu1.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu1.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
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+
+[system.cpu1.fuPool.FUList2.opList0]
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+
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+
+[system.cpu1.fuPool.FUList4.opList]
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+
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+
+[system.cpu1.fuPool.FUList7.opList]
+type=OpDesc
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+
+[system.cpu1.icache]
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+cpu_side=system.cpu1.icache_port
+mem_side=system.toL2Bus.port[3]
+
+[system.cpu1.interrupts]
+type=AlphaInterrupts
+
+[system.cpu1.itb]
+type=AlphaITB
+size=48
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.disk0]
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+
+[system.disk0.image]
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+table_size=65536
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.disk2]
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+driveID=master
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+
+[system.disk2.image]
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+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
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+default=system.tsunami.pciconfig.pio
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+
+[system.iocache]
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+prioritizeRequests=false
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+size=1024
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+cpu_side=system.iobus.port[28]
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+
+[system.l2c]
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+split=false
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+tgts_per_mshr=16
+trace_addr=0
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+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[3]
+
+[system.membus]
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+default=system.membus.responder.pio
+port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
+
+[system.membus.responder]
+type=IsaFake
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+platform=system.tsunami
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+ret_data32=4294967295
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+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.default
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
+[system.simple_disk]
+type=SimpleDisk
+children=disk
+disk=system.simple_disk.disk
+system=system
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
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+default=system.toL2Bus.responder.pio
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
+
+[system.toL2Bus.responder]
+type=IsaFake
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+pio_size=8
+platform=system.tsunami
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+system=system
+update_data=false
+warn_access=
+pio=system.toL2Bus.default
+
+[system.tsunami]
+type=Tsunami
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+intrctrl=system.intrctrl
+system=system
+
+[system.tsunami.backdoor]
+type=AlphaBackdoor
+cpu=system.cpu0
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[25]
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+pio_addr=8803072344064
+pio_latency=1000
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+pio=system.iobus.port[1]
+
+[system.tsunami.ethernet]
+type=NSGigE
+BAR0=1
+BAR0Size=256
+BAR1=0
+BAR1Size=4096
+BAR2=0
+BAR2Size=0
+BAR3=0
+BAR3Size=0
+BAR4=0
+BAR4Size=0
+BAR5=0
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=34
+ExpansionROM=0
+HeaderType=0
+InterruptLine=30
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=52
+MinimumGrant=176
+ProgIF=0
+Revision=0
+Status=656
+SubClassCode=0
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=4107
+clock=0
+config_latency=20000
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
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+hardware_address=00:90:00:00:00:01
+intr_delay=10000000
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+rss=false
+rx_delay=1000000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=1000000
+tx_fifo_size=524288
+tx_thread=false
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
+pio=system.iobus.port[27]
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+pio_addr=8796093677568
+pio_latency=1000
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+platform=system.tsunami
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+ret_data16=65535
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+ret_data8=255
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+pio=system.iobus.port[9]
+
+[system.tsunami.fake_ata0]
+type=IsaFake
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+pio=system.iobus.port[20]
+
+[system.tsunami.fake_ata1]
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+pio=system.iobus.port[21]
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
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+pio=system.iobus.port[10]
+
+[system.tsunami.fake_pnp_read0]
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+pio=system.iobus.port[12]
+
+[system.tsunami.fake_pnp_read1]
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+pio=system.iobus.port[13]
+
+[system.tsunami.fake_pnp_read2]
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+pio=system.iobus.port[14]
+
+[system.tsunami.fake_pnp_read3]
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+pio=system.iobus.port[15]
+
+[system.tsunami.fake_pnp_read4]
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+pio=system.iobus.port[16]
+
+[system.tsunami.fake_pnp_read5]
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+warn_access=
+pio=system.iobus.port[17]
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
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+pio=system.iobus.port[18]
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
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+warn_access=
+pio=system.iobus.port[19]
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
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+pio=system.iobus.port[11]
+
+[system.tsunami.fake_ppc]
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+pio=system.iobus.port[8]
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
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+warn_access=
+pio=system.iobus.port[3]
+
+[system.tsunami.fake_uart1]
+type=IsaFake
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+warn_access=
+pio=system.iobus.port[4]
+
+[system.tsunami.fake_uart2]
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+warn_access=
+pio=system.iobus.port[5]
+
+[system.tsunami.fake_uart3]
+type=IsaFake
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+warn_access=
+pio=system.iobus.port[6]
+
+[system.tsunami.fake_uart4]
+type=IsaFake
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+system=system
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+warn_access=
+pio=system.iobus.port[7]
+
+[system.tsunami.fb]
+type=BadDevice
+devicename=FrameBuffer
+pio_addr=8804615848912
+pio_latency=1000
+platform=system.tsunami
+system=system
+pio=system.iobus.port[22]
+
+[system.tsunami.ide]
+type=IdeController
+BAR0=1
+BAR0Size=8
+BAR1=1
+BAR1Size=4
+BAR2=1
+BAR2Size=8
+BAR3=1
+BAR3Size=4
+BAR4=1
+BAR4Size=16
+BAR5=1
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+disks=system.disk0 system.disk2
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+system=system
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
+pio=system.iobus.port[26]
+
+[system.tsunami.io]
+type=TsunamiIO
+frequency=976562500
+pio_addr=8804615847936
+pio_latency=1000
+platform=system.tsunami
+system=system
+time=Thu Jan  1 00:00:00 2009
+tsunami=system.tsunami
+year_is_bcd=false
+pio=system.iobus.port[23]
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+pio_addr=8802535473152
+pio_latency=1000
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+pio=system.iobus.port[2]
+
+[system.tsunami.pciconfig]
+type=PciConfigAll
+bus=0
+pio_latency=1
+platform=system.tsunami
+size=16777216
+system=system
+pio=system.iobus.default
+
+[system.tsunami.uart]
+type=Uart8250
+pio_addr=8804615848952
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[24]
+
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt
new file mode 100644
index 000000000..39d149122
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt
@@ -0,0 +1,1123 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits                      4974822                       # Number of BTB hits
+global.BPredUnit.BTBHits                      2263931                       # Number of BTB hits
+global.BPredUnit.BTBLookups                   9262166                       # Number of BTB lookups
+global.BPredUnit.BTBLookups                   5044198                       # Number of BTB lookups
+global.BPredUnit.RASInCorrect                   24314                       # Number of incorrect RAS predictions.
+global.BPredUnit.RASInCorrect                   16401                       # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect                 550360                       # Number of conditional branches incorrect
+global.BPredUnit.condIncorrect                 327538                       # Number of conditional branches incorrect
+global.BPredUnit.condPredicted                8474519                       # Number of conditional branches predicted
+global.BPredUnit.condPredicted                4548926                       # Number of conditional branches predicted
+global.BPredUnit.lookups                     10092697                       # Number of BP lookups
+global.BPredUnit.lookups                      5530798                       # Number of BP lookups
+global.BPredUnit.usedRAS                       690318                       # Number of times the RAS was used to get a target.
+global.BPredUnit.usedRAS                       415111                       # Number of times the RAS was used to get a target.
+host_inst_rate                                 132625                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 292844                       # Number of bytes of host memory used
+host_seconds                                   423.41                       # Real time elapsed on the host
+host_tick_rate                             4505618304                       # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads            2050196                       # Number of conflicting loads.
+memdepunit.memDep.conflictingLoads             902547                       # Number of conflicting loads.
+memdepunit.memDep.conflictingStores           1831551                       # Number of conflicting stores.
+memdepunit.memDep.conflictingStores            816276                       # Number of conflicting stores.
+memdepunit.memDep.insertedLoads               7552776                       # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads               4240735                       # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores              4835977                       # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores              2555030                       # Number of stores inserted to the mem dependence unit.
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                    56154063                       # Number of instructions simulated
+sim_seconds                                  1.907705                       # Number of seconds simulated
+sim_ticks                                1907705350500                       # Number of ticks simulated
+system.cpu0.commit.COM:branches               5979955                       # Number of branches committed
+system.cpu0.commit.COM:bw_lim_events           670629                       # number cycles where commit BW limit reached
+system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
+system.cpu0.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle.samples     69429521                      
+system.cpu0.commit.COM:committed_per_cycle.min_value            0                      
+                               0     52132882   7508.75%           
+                               1      7659816   1103.25%           
+                               2      4444319    640.12%           
+                               3      2023012    291.38%           
+                               4      1474688    212.40%           
+                               5       453462     65.31%           
+                               6       276660     39.85%           
+                               7       294053     42.35%           
+                               8       670629     96.59%           
+system.cpu0.commit.COM:committed_per_cycle.max_value            8                      
+system.cpu0.commit.COM:committed_per_cycle.end_dist
+
+system.cpu0.commit.COM:count                 39866915                       # Number of instructions committed
+system.cpu0.commit.COM:loads                  6404567                       # Number of loads committed
+system.cpu0.commit.COM:membars                 151031                       # Number of memory barriers committed
+system.cpu0.commit.COM:refs                  10831807                       # Number of memory references committed
+system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
+system.cpu0.commit.branchMispredicts           524319                       # The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts      39866915                       # The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls         458411                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts        6215021                       # The number of squashed insts skipped by commit
+system.cpu0.committedInsts                   37661300                       # Number of Instructions Simulated
+system.cpu0.committedInsts_total             37661300                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.679168                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.679168                       # CPI: Total CPI of All Threads
+system.cpu0.dcache.LoadLockedReq_accesses       147705                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15410.210138                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.163354                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits          135237                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency    192134500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate     0.084411                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses         12468                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_hits         3212                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    109898000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate     0.062665                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_misses         9256                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses           6414335                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 28975.310559                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.266435                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_hits               5467655                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency   27430347000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate         0.147588                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses              946680                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits           250995                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency  19978171500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate     0.108458                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses         695685                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    639869500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses       156562                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency 54665.657574                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51665.657574                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits           140541                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency    875798500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate     0.102330                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses          16021                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency    827735500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate     0.102330                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses        16021                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses          4258124                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609779                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53932.670870                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_hits              2612795                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency  80386842240                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate        0.386398                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses            1645329                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits         1362201                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency  15269849238                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate     0.066491                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses        283128                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1050385997                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.avg_blocked_cycles_no_mshrs  9304.837348                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles_no_targets        16250                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_refs                  9.224078                       # Average number of references to valid blocks.
+system.cpu0.dcache.blocked_no_mshrs            116353                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_no_targets               2                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_mshrs   1082645740                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_targets        32500                       # number of cycles access was blocked
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.demand_accesses           10672459                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 41595.993394                       # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.985488                       # average overall mshr miss latency
+system.cpu0.dcache.demand_hits                8080450                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency   107817189240                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate          0.242869                       # miss rate for demand accesses
+system.cpu0.dcache.demand_misses              2592009                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits           1613196                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency  35248020738                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate     0.091714                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses          978813                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_accesses          10672459                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 41595.993394                       # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.985488                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_hits               8080450                       # number of overall hits
+system.cpu0.dcache.overall_miss_latency  107817189240                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate         0.242869                       # miss rate for overall accesses
+system.cpu0.dcache.overall_misses             2592009                       # number of overall misses
+system.cpu0.dcache.overall_mshr_hits          1613196                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency  35248020738                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate     0.091714                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses         978813                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency   1690255497                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu0.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu0.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu0.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.dcache.replacements                922698                       # number of replacements
+system.cpu0.dcache.sampled_refs                923094                       # Sample count of references to valid blocks.
+system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.tagsinuse               442.177178                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                 8514691                       # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle              21439000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks                  297324                       # number of writebacks
+system.cpu0.decode.DECODE:BlockedCycles      33637373                       # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:BranchMispred         26509                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DECODE:BranchResolved       401334                       # Number of times decode resolved a branch
+system.cpu0.decode.DECODE:DecodedInsts       50924220                       # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles         25725806                       # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles           9142179                       # Number of cycles decode is running
+system.cpu0.decode.DECODE:SquashCycles        1093475                       # Number of cycles decode is squashing
+system.cpu0.decode.DECODE:SquashedInsts         84178                       # Number of squashed instructions handled by decode
+system.cpu0.decode.DECODE:UnblockCycles        924162                       # Number of cycles decode is unblocking
+system.cpu0.dtb.accesses                       812630                       # DTB accesses
+system.cpu0.dtb.acv                               800                       # DTB access violations
+system.cpu0.dtb.hits                         11624529                       # DTB hits
+system.cpu0.dtb.misses                          28502                       # DTB misses
+system.cpu0.dtb.read_accesses                  605275                       # DTB read accesses
+system.cpu0.dtb.read_acv                          596                       # DTB read access violations
+system.cpu0.dtb.read_hits                     7062851                       # DTB read hits
+system.cpu0.dtb.read_misses                     24043                       # DTB read misses
+system.cpu0.dtb.write_accesses                 207355                       # DTB write accesses
+system.cpu0.dtb.write_acv                         204                       # DTB write access violations
+system.cpu0.dtb.write_hits                    4561678                       # DTB write hits
+system.cpu0.dtb.write_misses                     4459                       # DTB write misses
+system.cpu0.fetch.Branches                   10092697                       # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines                  6456334                       # Number of cache lines fetched
+system.cpu0.fetch.Cycles                     16708506                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes               292498                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts                      51999783                       # Number of instructions fetch has processed
+system.cpu0.fetch.MiscStallCycles                 404                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.SquashCycles                 660089                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.branchRate                 0.100026                       # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles           6456334                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.predictedBranches           5665140                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.rate                       0.515355                       # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist.start_dist                          # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist.samples           70522996                      
+system.cpu0.fetch.rateDist.min_value                0                      
+                               0     60301622   8550.63%           
+                               1       760699    107.87%           
+                               2      1434176    203.36%           
+                               3       635243     90.08%           
+                               4      2330465    330.45%           
+                               5       474381     67.27%           
+                               6       552250     78.31%           
+                               7       815542    115.64%           
+                               8      3218618    456.39%           
+system.cpu0.fetch.rateDist.max_value                8                      
+system.cpu0.fetch.rateDist.end_dist
+
+system.cpu0.icache.ReadReq_accesses           6456334                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 15194.690740                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.489789                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits               5806036                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency    9881076999                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate         0.100722                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses              650298                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_hits            29862                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_miss_latency   7526812999                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate     0.096097                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses         620436                       # number of ReadReq MSHR misses
+system.cpu0.icache.avg_blocked_cycles_no_mshrs 11557.114286                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_refs                  9.359502                       # Average number of references to valid blocks.
+system.cpu0.icache.blocked_no_mshrs                35                       # number of cycles access was blocked
+system.cpu0.icache.blocked_no_targets               0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_mshrs       404499                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.demand_accesses            6456334                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 15194.690740                       # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 12131.489789                       # average overall mshr miss latency
+system.cpu0.icache.demand_hits                5806036                       # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency     9881076999                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate          0.100722                       # miss rate for demand accesses
+system.cpu0.icache.demand_misses               650298                       # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits             29862                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency   7526812999                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate     0.096097                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses          620436                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.overall_accesses           6456334                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 15194.690740                       # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 12131.489789                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_hits               5806036                       # number of overall hits
+system.cpu0.icache.overall_miss_latency    9881076999                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate         0.100722                       # miss rate for overall accesses
+system.cpu0.icache.overall_misses              650298                       # number of overall misses
+system.cpu0.icache.overall_mshr_hits            29862                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency   7526812999                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate     0.096097                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses         620436                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu0.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu0.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu0.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.icache.replacements                619824                       # number of replacements
+system.cpu0.icache.sampled_refs                620336                       # Sample count of references to valid blocks.
+system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.tagsinuse               509.829045                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                 5806036                       # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           25308080000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks                       0                       # number of writebacks
+system.cpu0.idleCycles                       30377938                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.iew.EXEC:branches                 6436145                       # Number of branches executed
+system.cpu0.iew.EXEC:nop                      2512619                       # number of nop insts executed
+system.cpu0.iew.EXEC:rate                    0.402630                       # Inst execution rate
+system.cpu0.iew.EXEC:refs                    11739664                       # number of memory reference insts executed
+system.cpu0.iew.EXEC:stores                   4575851                       # Number of stores executed
+system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
+system.cpu0.iew.WB:consumers                 24160254                       # num instructions consuming a value
+system.cpu0.iew.WB:count                     40224289                       # cumulative count of insts written-back
+system.cpu0.iew.WB:fanout                    0.779043                       # average fanout of values written-back
+system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.iew.WB:producers                 18821888                       # num instructions producing a value
+system.cpu0.iew.WB:rate                      0.398651                       # insts written-back per cycle
+system.cpu0.iew.WB:sent                      40292052                       # cumulative count of insts sent to commit
+system.cpu0.iew.branchMispredicts              568729                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewBlockCycles                7177517                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewDispLoadInsts              7552776                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispNonSpecInsts           1229726                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispSquashedInsts           771663                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispStoreInsts             4835977                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispatchedInsts           46188038                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewExecLoadInsts              7163813                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           359179                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecutedInsts             40625745                       # Number of executed instructions
+system.cpu0.iew.iewIQFullEvents                 33838                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu0.iew.iewLSQFullEvents                 4189                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles               1093475                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewUnblockCycles               453457                       # Number of cycles IEW is unblocking
+system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu0.iew.lsq.thread.0.cacheBlocked       242605                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread.0.forwLoads         357762                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread.0.ignoredResponses         8885                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu0.iew.lsq.thread.0.memOrderViolation        33999                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread.0.rescheduledLoads        12233                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread.0.squashedLoads      1148209                       # Number of loads squashed
+system.cpu0.iew.lsq.thread.0.squashedStores       408737                       # Number of stores squashed
+system.cpu0.iew.memOrderViolationEvents         33999                       # Number of memory order violations
+system.cpu0.iew.predictedNotTakenIncorrect       255829                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect        312900                       # Number of branches that were predicted taken incorrectly
+system.cpu0.ipc                              0.373250                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.373250                       # IPC: Total IPC of All Threads
+system.cpu0.iq.ISSUE:FU_type_0               40984924                       # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0.start_dist
+                      No_OpClass         3324      0.01%            # Type of FU issued
+                          IntAlu     28266314     68.97%            # Type of FU issued
+                         IntMult        42210      0.10%            # Type of FU issued
+                          IntDiv            0      0.00%            # Type of FU issued
+                        FloatAdd        12073      0.03%            # Type of FU issued
+                        FloatCmp            0      0.00%            # Type of FU issued
+                        FloatCvt            0      0.00%            # Type of FU issued
+                       FloatMult            0      0.00%            # Type of FU issued
+                        FloatDiv         1656      0.00%            # Type of FU issued
+                       FloatSqrt            0      0.00%            # Type of FU issued
+                         MemRead      7397265     18.05%            # Type of FU issued
+                        MemWrite      4611960     11.25%            # Type of FU issued
+                       IprAccess       650122      1.59%            # Type of FU issued
+                    InstPrefetch            0      0.00%            # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0.end_dist
+system.cpu0.iq.ISSUE:fu_busy_cnt               290360                       # FU busy when requested
+system.cpu0.iq.ISSUE:fu_busy_rate            0.007085                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.ISSUE:fu_full.start_dist
+                      No_OpClass            0      0.00%            # attempts to use FU when none available
+                          IntAlu        33477     11.53%            # attempts to use FU when none available
+                         IntMult            0      0.00%            # attempts to use FU when none available
+                          IntDiv            0      0.00%            # attempts to use FU when none available
+                        FloatAdd            0      0.00%            # attempts to use FU when none available
+                        FloatCmp            0      0.00%            # attempts to use FU when none available
+                        FloatCvt            0      0.00%            # attempts to use FU when none available
+                       FloatMult            0      0.00%            # attempts to use FU when none available
+                        FloatDiv            0      0.00%            # attempts to use FU when none available
+                       FloatSqrt            0      0.00%            # attempts to use FU when none available
+                         MemRead       185557     63.91%            # attempts to use FU when none available
+                        MemWrite        71326     24.56%            # attempts to use FU when none available
+                       IprAccess            0      0.00%            # attempts to use FU when none available
+                    InstPrefetch            0      0.00%            # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full.end_dist
+system.cpu0.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle.samples     70522996                      
+system.cpu0.iq.ISSUE:issued_per_cycle.min_value            0                      
+                               0     49763845   7056.40%           
+                               1     10504305   1489.49%           
+                               2      4625788    655.93%           
+                               3      2839071    402.57%           
+                               4      1729907    245.30%           
+                               5       663571     94.09%           
+                               6       315326     44.71%           
+                               7        67073      9.51%           
+                               8        14110      2.00%           
+system.cpu0.iq.ISSUE:issued_per_cycle.max_value            8                      
+system.cpu0.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu0.iq.ISSUE:rate                    0.406190                       # Inst issue rate
+system.cpu0.iq.iqInstsAdded                  42277563                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsIssued                 40984924                       # Number of instructions issued
+system.cpu0.iq.iqNonSpecInstsAdded            1397856                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqSquashedInstsExamined        5734915                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsIssued            23390                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedNonSpecRemoved        939445                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.iqSquashedOperandsExamined      3057501                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.itb.accesses                       875611                       # ITB accesses
+system.cpu0.itb.acv                               895                       # ITB acv
+system.cpu0.itb.hits                           845707                       # ITB hits
+system.cpu0.itb.misses                          29904                       # ITB misses
+system.cpu0.kern.callpal                       129595                       # number of callpals executed
+system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
+system.cpu0.kern.callpal_wripir                    96      0.07%      0.07% # number of callpals executed
+system.cpu0.kern.callpal_wrmces                     1      0.00%      0.08% # number of callpals executed
+system.cpu0.kern.callpal_wrfen                      1      0.00%      0.08% # number of callpals executed
+system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.08% # number of callpals executed
+system.cpu0.kern.callpal_swpctx                  2410      1.86%      1.94% # number of callpals executed
+system.cpu0.kern.callpal_tbi                       51      0.04%      1.98% # number of callpals executed
+system.cpu0.kern.callpal_wrent                      7      0.01%      1.98% # number of callpals executed
+system.cpu0.kern.callpal_swpipl                116022     89.53%     91.51% # number of callpals executed
+system.cpu0.kern.callpal_rdps                    6357      4.91%     96.41% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp                      1      0.00%     96.41% # number of callpals executed
+system.cpu0.kern.callpal_wrusp                      3      0.00%     96.42% # number of callpals executed
+system.cpu0.kern.callpal_rdusp                      9      0.01%     96.42% # number of callpals executed
+system.cpu0.kern.callpal_whami                      2      0.00%     96.43% # number of callpals executed
+system.cpu0.kern.callpal_rti                     4116      3.18%     99.60% # number of callpals executed
+system.cpu0.kern.callpal_callsys                  381      0.29%     99.90% # number of callpals executed
+system.cpu0.kern.callpal_imb                      136      0.10%    100.00% # number of callpals executed
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.hwrei                    144434                       # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce                    4855                       # number of quiesce instructions executed
+system.cpu0.kern.ipl_count                     122325                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0                    47769     39.05%     39.05% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21                     239      0.20%     39.25% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22                    1931      1.58%     40.82% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30                      17      0.01%     40.84% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31                   72369     59.16%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good                       96409                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0                     47119     48.87%     48.87% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_21                      239      0.25%     49.12% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_22                     1931      2.00%     51.12% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30                       17      0.02%     51.14% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31                    47103     48.86%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks               1907288705500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0             1871607297000     98.13%     98.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21               101503500      0.01%     98.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22               397999500      0.02%     98.16% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30                 9331000      0.00%     98.16% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31             35172574500      1.84%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used_0                  0.986393                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_31                 0.650873                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel                1284                      
+system.cpu0.kern.mode_good_user                  1284                      
+system.cpu0.kern.mode_good_idle                     0                      
+system.cpu0.kern.mode_switch_kernel              5894                       # number of protection mode switches
+system.cpu0.kern.mode_switch_user                1284                       # number of protection mode switches
+system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
+system.cpu0.kern.mode_switch_good        <err: div-0>                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel     0.217849                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks_kernel       1905144241000     99.89%     99.89% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user           2121161500      0.11%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    2411                       # number of times the context was actually changed
+system.cpu0.kern.syscall                          222                       # number of syscalls executed
+system.cpu0.kern.syscall_2                          8      3.60%      3.60% # number of syscalls executed
+system.cpu0.kern.syscall_3                         19      8.56%     12.16% # number of syscalls executed
+system.cpu0.kern.syscall_4                          4      1.80%     13.96% # number of syscalls executed
+system.cpu0.kern.syscall_6                         32     14.41%     28.38% # number of syscalls executed
+system.cpu0.kern.syscall_12                         1      0.45%     28.83% # number of syscalls executed
+system.cpu0.kern.syscall_17                         9      4.05%     32.88% # number of syscalls executed
+system.cpu0.kern.syscall_19                        10      4.50%     37.39% # number of syscalls executed
+system.cpu0.kern.syscall_20                         6      2.70%     40.09% # number of syscalls executed
+system.cpu0.kern.syscall_23                         1      0.45%     40.54% # number of syscalls executed
+system.cpu0.kern.syscall_24                         3      1.35%     41.89% # number of syscalls executed
+system.cpu0.kern.syscall_33                         7      3.15%     45.05% # number of syscalls executed
+system.cpu0.kern.syscall_41                         2      0.90%     45.95% # number of syscalls executed
+system.cpu0.kern.syscall_45                        36     16.22%     62.16% # number of syscalls executed
+system.cpu0.kern.syscall_47                         3      1.35%     63.51% # number of syscalls executed
+system.cpu0.kern.syscall_48                        10      4.50%     68.02% # number of syscalls executed
+system.cpu0.kern.syscall_54                        10      4.50%     72.52% # number of syscalls executed
+system.cpu0.kern.syscall_58                         1      0.45%     72.97% # number of syscalls executed
+system.cpu0.kern.syscall_59                         6      2.70%     75.68% # number of syscalls executed
+system.cpu0.kern.syscall_71                        23     10.36%     86.04% # number of syscalls executed
+system.cpu0.kern.syscall_73                         3      1.35%     87.39% # number of syscalls executed
+system.cpu0.kern.syscall_74                         6      2.70%     90.09% # number of syscalls executed
+system.cpu0.kern.syscall_87                         1      0.45%     90.54% # number of syscalls executed
+system.cpu0.kern.syscall_90                         3      1.35%     91.89% # number of syscalls executed
+system.cpu0.kern.syscall_92                         9      4.05%     95.95% # number of syscalls executed
+system.cpu0.kern.syscall_97                         2      0.90%     96.85% # number of syscalls executed
+system.cpu0.kern.syscall_98                         2      0.90%     97.75% # number of syscalls executed
+system.cpu0.kern.syscall_132                        1      0.45%     98.20% # number of syscalls executed
+system.cpu0.kern.syscall_144                        2      0.90%     99.10% # number of syscalls executed
+system.cpu0.kern.syscall_147                        2      0.90%    100.00% # number of syscalls executed
+system.cpu0.numCycles                       100900934                       # number of cpu cycles simulated
+system.cpu0.rename.RENAME:BlockCycles        10626974                       # Number of cycles rename is blocking
+system.cpu0.rename.RENAME:CommittedMaps      27338376                       # Number of HB maps that are committed
+system.cpu0.rename.RENAME:IQFullEvents         742955                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.RENAME:IdleCycles         26930007                       # Number of cycles rename is idle
+system.cpu0.rename.RENAME:LSQFullEvents       1646671                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RENAME:ROBFullEvents         16625                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.RENAME:RenameLookups      58873396                       # Number of register rename lookups that rename has made
+system.cpu0.rename.RENAME:RenamedInsts       48153710                       # Number of instructions processed by rename
+system.cpu0.rename.RENAME:RenamedOperands     32532330                       # Number of destination operands rename has renamed
+system.cpu0.rename.RENAME:RunCycles           9103233                       # Number of cycles rename is running
+system.cpu0.rename.RENAME:SquashCycles        1093475                       # Number of cycles rename is squashing
+system.cpu0.rename.RENAME:UnblockCycles       3612957                       # Number of cycles rename is unblocking
+system.cpu0.rename.RENAME:UndoneMaps          5193954                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:serializeStallCycles     19156348                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializingInsts      1163476                       # count of serializing insts renamed
+system.cpu0.rename.RENAME:skidInsts           8536447                       # count of insts added to the skid buffer
+system.cpu0.rename.RENAME:tempSerializingInsts       181426                       # count of temporary serializing insts renamed
+system.cpu0.timesIdled                         904874                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.commit.COM:branches               2941268                       # Number of branches committed
+system.cpu1.commit.COM:bw_lim_events           404281                       # number cycles where commit BW limit reached
+system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
+system.cpu1.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle.samples     37417437                      
+system.cpu1.commit.COM:committed_per_cycle.min_value            0                      
+                               0     29372798   7850.03%           
+                               1      3570649    954.27%           
+                               2      1730450    462.47%           
+                               3      1048421    280.20%           
+                               4       705992    188.68%           
+                               5       261184     69.80%           
+                               6       182468     48.77%           
+                               7       141194     37.73%           
+                               8       404281    108.05%           
+system.cpu1.commit.COM:committed_per_cycle.max_value            8                      
+system.cpu1.commit.COM:committed_per_cycle.end_dist
+
+system.cpu1.commit.COM:count                 19624114                       # Number of instructions committed
+system.cpu1.commit.COM:loads                  3545101                       # Number of loads committed
+system.cpu1.commit.COM:membars                  87127                       # Number of memory barriers committed
+system.cpu1.commit.COM:refs                   5853378                       # Number of memory references committed
+system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
+system.cpu1.commit.branchMispredicts           311146                       # The number of times a branch was mispredicted
+system.cpu1.commit.commitCommittedInsts      19624114                       # The number of committed instructions
+system.cpu1.commit.commitNonSpecStalls         255253                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.commitSquashedInsts        3733069                       # The number of squashed insts skipped by commit
+system.cpu1.committedInsts                   18492763                       # Number of Instructions Simulated
+system.cpu1.committedInsts_total             18492763                       # Number of Instructions Simulated
+system.cpu1.cpi                              2.312237                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.312237                       # CPI: Total CPI of All Threads
+system.cpu1.dcache.LoadLockedReq_accesses        72124                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14446.929646                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11200.613079                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits           59829                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency    177625000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate     0.170470                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses         12295                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_hits         2019                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency    115097500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate     0.142477                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_misses        10276                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses           3584183                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 15544.189729                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11996.806998                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_hits               2941941                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency    9983131500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate         0.179188                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses              642242                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_hits           211143                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_miss_latency   5171811500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate     0.120278                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_misses         431099                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency    283603500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.StoreCondReq_accesses        68163                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency 54675.738585                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51675.738585                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits            51408                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency    916092000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate     0.245808                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses          16755                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency    865827000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate     0.245808                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_misses        16755                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses          2232793                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency 49361.667333                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.267300                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_hits              1538625                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency  34265289889                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate        0.310897                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses             694168                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_hits          551549                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_miss_latency   7736833634                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate     0.063875                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_misses        142619                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    511356000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.avg_blocked_cycles_no_mshrs 14029.367204                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles_no_targets         5000                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_refs                  8.864535                       # Average number of references to valid blocks.
+system.cpu1.dcache.blocked_no_mshrs             31315                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_no_targets               1                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_mshrs    439329634                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_targets         5000                       # number of cycles access was blocked
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.demand_accesses            5816976                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 33109.914913                       # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.982803                       # average overall mshr miss latency
+system.cpu1.dcache.demand_hits                4480566                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency    44248421389                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate          0.229743                       # miss rate for demand accesses
+system.cpu1.dcache.demand_misses              1336410                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits            762692                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency  12908645134                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate     0.098628                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses          573718                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.overall_accesses           5816976                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 33109.914913                       # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.982803                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_hits               4480566                       # number of overall hits
+system.cpu1.dcache.overall_miss_latency   44248421389                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate         0.229743                       # miss rate for overall accesses
+system.cpu1.dcache.overall_misses             1336410                       # number of overall misses
+system.cpu1.dcache.overall_mshr_hits           762692                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency  12908645134                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate     0.098628                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses         573718                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency    794959500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu1.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu1.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.dcache.replacements                531824                       # number of replacements
+system.cpu1.dcache.sampled_refs                532336                       # Sample count of references to valid blocks.
+system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.tagsinuse               486.799078                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 4718911                       # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           39405721000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks                  158256                       # number of writebacks
+system.cpu1.decode.DECODE:BlockedCycles      17763600                       # Number of cycles decode is blocked
+system.cpu1.decode.DECODE:BranchMispred         18017                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DECODE:BranchResolved       245215                       # Number of times decode resolved a branch
+system.cpu1.decode.DECODE:DecodedInsts       26209907                       # Number of instructions handled by decode
+system.cpu1.decode.DECODE:IdleCycles         14707751                       # Number of cycles decode is idle
+system.cpu1.decode.DECODE:RunCycles           4714008                       # Number of cycles decode is running
+system.cpu1.decode.DECODE:SquashCycles         641031                       # Number of cycles decode is squashing
+system.cpu1.decode.DECODE:SquashedInsts         52760                       # Number of squashed instructions handled by decode
+system.cpu1.decode.DECODE:UnblockCycles        232077                       # Number of cycles decode is unblocking
+system.cpu1.dtb.accesses                       434054                       # DTB accesses
+system.cpu1.dtb.acv                                76                       # DTB access violations
+system.cpu1.dtb.hits                          6272530                       # DTB hits
+system.cpu1.dtb.misses                          17149                       # DTB misses
+system.cpu1.dtb.read_accesses                  314239                       # DTB read accesses
+system.cpu1.dtb.read_acv                           13                       # DTB read access violations
+system.cpu1.dtb.read_hits                     3866975                       # DTB read hits
+system.cpu1.dtb.read_misses                     13433                       # DTB read misses
+system.cpu1.dtb.write_accesses                 119815                       # DTB write accesses
+system.cpu1.dtb.write_acv                          63                       # DTB write access violations
+system.cpu1.dtb.write_hits                    2405555                       # DTB write hits
+system.cpu1.dtb.write_misses                     3716                       # DTB write misses
+system.cpu1.fetch.Branches                    5530798                       # Number of branches that fetch encountered
+system.cpu1.fetch.CacheLines                  3081765                       # Number of cache lines fetched
+system.cpu1.fetch.Cycles                      8119333                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.IcacheSquashes               192779                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.Insts                      26783088                       # Number of instructions fetch has processed
+system.cpu1.fetch.MiscStallCycles                1141                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.SquashCycles                 373445                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.branchRate                 0.129346                       # Number of branch fetches per cycle
+system.cpu1.fetch.icacheStallCycles           3081765                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.predictedBranches           2679042                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.rate                       0.626364                       # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist.start_dist                          # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist.samples           38058468                      
+system.cpu1.fetch.rateDist.min_value                0                      
+                               0     33027825   8678.18%           
+                               1       336540     88.43%           
+                               2       683303    179.54%           
+                               3       398795    104.78%           
+                               4       792602    208.26%           
+                               5       252574     66.36%           
+                               6       340311     89.42%           
+                               7       403731    106.08%           
+                               8      1822787    478.94%           
+system.cpu1.fetch.rateDist.max_value                8                      
+system.cpu1.fetch.rateDist.end_dist
+
+system.cpu1.icache.ReadReq_accesses           3081765                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 14557.233772                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.243441                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits               2613676                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency    6814080999                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate         0.151890                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses              468089                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_hits            20978                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_miss_latency   5188832000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate     0.145083                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_misses         447111                       # number of ReadReq MSHR misses
+system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_refs                  5.846378                       # Average number of references to valid blocks.
+system.cpu1.icache.blocked_no_mshrs                26                       # number of cycles access was blocked
+system.cpu1.icache.blocked_no_targets               0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_mshrs       287500                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.demand_accesses            3081765                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 14557.233772                       # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11605.243441                       # average overall mshr miss latency
+system.cpu1.icache.demand_hits                2613676                       # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency     6814080999                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate          0.151890                       # miss rate for demand accesses
+system.cpu1.icache.demand_misses               468089                       # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits             20978                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency   5188832000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate     0.145083                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses          447111                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.icache.overall_accesses           3081765                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 14557.233772                       # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11605.243441                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_hits               2613676                       # number of overall hits
+system.cpu1.icache.overall_miss_latency    6814080999                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate         0.151890                       # miss rate for overall accesses
+system.cpu1.icache.overall_misses              468089                       # number of overall misses
+system.cpu1.icache.overall_mshr_hits            20978                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency   5188832000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate     0.145083                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses         447111                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu1.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu1.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu1.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.icache.replacements                446548                       # number of replacements
+system.cpu1.icache.sampled_refs                447059                       # Sample count of references to valid blocks.
+system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.tagsinuse               504.476146                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 2613676                       # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle           54243392000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks                       0                       # number of writebacks
+system.cpu1.idleCycles                        4701181                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.iew.EXEC:branches                 3208895                       # Number of branches executed
+system.cpu1.iew.EXEC:nop                      1313637                       # number of nop insts executed
+system.cpu1.iew.EXEC:rate                    0.474750                       # Inst execution rate
+system.cpu1.iew.EXEC:refs                     6445371                       # number of memory reference insts executed
+system.cpu1.iew.EXEC:stores                   2416978                       # Number of stores executed
+system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
+system.cpu1.iew.WB:consumers                 12350061                       # num instructions consuming a value
+system.cpu1.iew.WB:count                     20043548                       # cumulative count of insts written-back
+system.cpu1.iew.WB:fanout                    0.731488                       # average fanout of values written-back
+system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.iew.WB:producers                  9033918                       # num instructions producing a value
+system.cpu1.iew.WB:rate                      0.468749                       # insts written-back per cycle
+system.cpu1.iew.WB:sent                      20085855                       # cumulative count of insts sent to commit
+system.cpu1.iew.branchMispredicts              338994                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewBlockCycles                2476901                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewDispLoadInsts              4240735                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispNonSpecInsts            782170                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewDispSquashedInsts           352959                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispStoreInsts             2555030                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispatchedInsts           23433163                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewExecLoadInsts              4028393                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           227109                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewExecutedInsts             20300122                       # Number of executed instructions
+system.cpu1.iew.iewIQFullEvents                 13056                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu1.iew.iewLSQFullEvents                 2312                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                641031                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewUnblockCycles                92389                       # Number of cycles IEW is unblocking
+system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu1.iew.lsq.thread.0.cacheBlocked        96439                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread.0.forwLoads         136590                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread.0.ignoredResponses         5874                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu1.iew.lsq.thread.0.memOrderViolation        18177                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread.0.rescheduledLoads         7528                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread.0.squashedLoads       695634                       # Number of loads squashed
+system.cpu1.iew.lsq.thread.0.squashedStores       246753                       # Number of stores squashed
+system.cpu1.iew.memOrderViolationEvents         18177                       # Number of memory order violations
+system.cpu1.iew.predictedNotTakenIncorrect       160429                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.predictedTakenIncorrect        178565                       # Number of branches that were predicted taken incorrectly
+system.cpu1.ipc                              0.432482                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.432482                       # IPC: Total IPC of All Threads
+system.cpu1.iq.ISSUE:FU_type_0               20527233                       # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0.start_dist
+                      No_OpClass         3984      0.02%            # Type of FU issued
+                          IntAlu     13446211     65.50%            # Type of FU issued
+                         IntMult        28837      0.14%            # Type of FU issued
+                          IntDiv            0      0.00%            # Type of FU issued
+                        FloatAdd        13702      0.07%            # Type of FU issued
+                        FloatCmp            0      0.00%            # Type of FU issued
+                        FloatCvt            0      0.00%            # Type of FU issued
+                       FloatMult            0      0.00%            # Type of FU issued
+                        FloatDiv         1986      0.01%            # Type of FU issued
+                       FloatSqrt            0      0.00%            # Type of FU issued
+                         MemRead      4170434     20.32%            # Type of FU issued
+                        MemWrite      2440876     11.89%            # Type of FU issued
+                       IprAccess       421203      2.05%            # Type of FU issued
+                    InstPrefetch            0      0.00%            # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0.end_dist
+system.cpu1.iq.ISSUE:fu_busy_cnt               220615                       # FU busy when requested
+system.cpu1.iq.ISSUE:fu_busy_rate            0.010747                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.ISSUE:fu_full.start_dist
+                      No_OpClass            0      0.00%            # attempts to use FU when none available
+                          IntAlu        16051      7.28%            # attempts to use FU when none available
+                         IntMult            0      0.00%            # attempts to use FU when none available
+                          IntDiv            0      0.00%            # attempts to use FU when none available
+                        FloatAdd            0      0.00%            # attempts to use FU when none available
+                        FloatCmp            0      0.00%            # attempts to use FU when none available
+                        FloatCvt            0      0.00%            # attempts to use FU when none available
+                       FloatMult            0      0.00%            # attempts to use FU when none available
+                        FloatDiv            0      0.00%            # attempts to use FU when none available
+                       FloatSqrt            0      0.00%            # attempts to use FU when none available
+                         MemRead       131548     59.63%            # attempts to use FU when none available
+                        MemWrite        73016     33.10%            # attempts to use FU when none available
+                       IprAccess            0      0.00%            # attempts to use FU when none available
+                    InstPrefetch            0      0.00%            # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full.end_dist
+system.cpu1.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle.samples     38058468                      
+system.cpu1.iq.ISSUE:issued_per_cycle.min_value            0                      
+                               0     28368883   7454.03%           
+                               1      4650018   1221.81%           
+                               2      1988549    522.50%           
+                               3      1356758    356.49%           
+                               4       973103    255.69%           
+                               5       468416    123.08%           
+                               6       186236     48.93%           
+                               7        54105     14.22%           
+                               8        12400      3.26%           
+system.cpu1.iq.ISSUE:issued_per_cycle.max_value            8                      
+system.cpu1.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu1.iq.ISSUE:rate                    0.480061                       # Inst issue rate
+system.cpu1.iq.iqInstsAdded                  21243619                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqInstsIssued                 20527233                       # Number of instructions issued
+system.cpu1.iq.iqNonSpecInstsAdded             875907                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqSquashedInstsExamined        3479594                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsIssued            16597                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedNonSpecRemoved        620654                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.iqSquashedOperandsExamined      1771927                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.itb.accesses                       525300                       # ITB accesses
+system.cpu1.itb.acv                               103                       # ITB acv
+system.cpu1.itb.hits                           518475                       # ITB hits
+system.cpu1.itb.misses                           6825                       # ITB misses
+system.cpu1.kern.callpal                        87347                       # number of callpals executed
+system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
+system.cpu1.kern.callpal_wripir                    17      0.02%      0.02% # number of callpals executed
+system.cpu1.kern.callpal_wrmces                     1      0.00%      0.02% # number of callpals executed
+system.cpu1.kern.callpal_wrfen                      1      0.00%      0.02% # number of callpals executed
+system.cpu1.kern.callpal_swpctx                  1838      2.10%      2.13% # number of callpals executed
+system.cpu1.kern.callpal_tbi                        3      0.00%      2.13% # number of callpals executed
+system.cpu1.kern.callpal_wrent                      7      0.01%      2.14% # number of callpals executed
+system.cpu1.kern.callpal_swpipl                 79676     91.22%     93.36% # number of callpals executed
+system.cpu1.kern.callpal_rdps                    2408      2.76%     96.11% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp                      1      0.00%     96.11% # number of callpals executed
+system.cpu1.kern.callpal_wrusp                      4      0.00%     96.12% # number of callpals executed
+system.cpu1.kern.callpal_whami                      3      0.00%     96.12% # number of callpals executed
+system.cpu1.kern.callpal_rti                     3206      3.67%     99.79% # number of callpals executed
+system.cpu1.kern.callpal_callsys                  136      0.16%     99.95% # number of callpals executed
+system.cpu1.kern.callpal_imb                       44      0.05%    100.00% # number of callpals executed
+system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.hwrei                     93957                       # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce                    3692                       # number of quiesce instructions executed
+system.cpu1.kern.ipl_count                      84907                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0                    34137     40.21%     40.21% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22                    1928      2.27%     42.48% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30                      96      0.11%     42.59% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31                   48746     57.41%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good                       68748                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0                     33410     48.60%     48.60% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22                     1928      2.80%     51.40% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30                       96      0.14%     51.54% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31                    33314     48.46%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks               1907704497000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0             1872145700000     98.14%     98.14% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22               351989500      0.02%     98.15% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30                39998500      0.00%     98.16% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31             35166809000      1.84%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used_0                  0.978703                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_31                 0.683420                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel                 521                      
+system.cpu1.kern.mode_good_user                   463                      
+system.cpu1.kern.mode_good_idle                    58                      
+system.cpu1.kern.mode_switch_kernel              2303                       # number of protection mode switches
+system.cpu1.kern.mode_switch_user                 463                       # number of protection mode switches
+system.cpu1.kern.mode_switch_idle                2035                       # number of protection mode switches
+system.cpu1.kern.mode_switch_good            1.254728                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel     0.226227                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_idle       0.028501                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel        46596073500      2.44%      2.44% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user           1015566000      0.05%      2.50% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle         1860092849500     97.50%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1839                       # number of times the context was actually changed
+system.cpu1.kern.syscall                          104                       # number of syscalls executed
+system.cpu1.kern.syscall_3                         11     10.58%     10.58% # number of syscalls executed
+system.cpu1.kern.syscall_6                         10      9.62%     20.19% # number of syscalls executed
+system.cpu1.kern.syscall_15                         1      0.96%     21.15% # number of syscalls executed
+system.cpu1.kern.syscall_17                         6      5.77%     26.92% # number of syscalls executed
+system.cpu1.kern.syscall_23                         3      2.88%     29.81% # number of syscalls executed
+system.cpu1.kern.syscall_24                         3      2.88%     32.69% # number of syscalls executed
+system.cpu1.kern.syscall_33                         4      3.85%     36.54% # number of syscalls executed
+system.cpu1.kern.syscall_45                        18     17.31%     53.85% # number of syscalls executed
+system.cpu1.kern.syscall_47                         3      2.88%     56.73% # number of syscalls executed
+system.cpu1.kern.syscall_59                         1      0.96%     57.69% # number of syscalls executed
+system.cpu1.kern.syscall_71                        31     29.81%     87.50% # number of syscalls executed
+system.cpu1.kern.syscall_74                        10      9.62%     97.12% # number of syscalls executed
+system.cpu1.kern.syscall_132                        3      2.88%    100.00% # number of syscalls executed
+system.cpu1.numCycles                        42759649                       # number of cpu cycles simulated
+system.cpu1.rename.RENAME:BlockCycles         3630480                       # Number of cycles rename is blocking
+system.cpu1.rename.RENAME:CommittedMaps      13162138                       # Number of HB maps that are committed
+system.cpu1.rename.RENAME:IQFullEvents         331495                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.RENAME:IdleCycles         15176070                       # Number of cycles rename is idle
+system.cpu1.rename.RENAME:LSQFullEvents        648663                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RENAME:ROBFullEvents          1231                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.RENAME:RenameLookups      29369210                       # Number of register rename lookups that rename has made
+system.cpu1.rename.RENAME:RenamedInsts       24481625                       # Number of instructions processed by rename
+system.cpu1.rename.RENAME:RenamedOperands     16150176                       # Number of destination operands rename has renamed
+system.cpu1.rename.RENAME:RunCycles           4323376                       # Number of cycles rename is running
+system.cpu1.rename.RENAME:SquashCycles         641031                       # Number of cycles rename is squashing
+system.cpu1.rename.RENAME:UnblockCycles       1811966                       # Number of cycles rename is unblocking
+system.cpu1.rename.RENAME:UndoneMaps          2988036                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.RENAME:serializeStallCycles     12475543                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RENAME:serializingInsts       728332                       # count of serializing insts renamed
+system.cpu1.rename.RENAME:skidInsts           4962004                       # count of insts added to the skid buffer
+system.cpu1.rename.RENAME:tempSerializingInsts        86297                       # count of temporary serializing insts renamed
+system.cpu1.timesIdled                         480243                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iocache.ReadReq_accesses                   175                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency  115245.702857                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63245.702857                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency          20167998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses                     175                       # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency     11067998                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate               1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_misses                175                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency 137815.912736                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85812.468906                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5726526806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
+system.iocache.WriteReq_mshr_miss_latency   3565679708                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_rate              1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
+system.iocache.avg_blocked_cycles_no_mshrs  6166.359533                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs                 10458                       # number of cycles access was blocked
+system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs       64487788                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.demand_accesses                  41727                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency   137721.254919                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85717.825533                       # average overall mshr miss latency
+system.iocache.demand_hits                          0                       # number of demand (read+write) hits
+system.iocache.demand_miss_latency         5746694804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
+system.iocache.demand_misses                    41727                       # number of demand (read+write) misses
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency    3576747706                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate                1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses               41727                       # number of demand (read+write) MSHR misses
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_accesses                 41727                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency  137721.254919                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85717.825533                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.iocache.overall_hits                         0                       # number of overall hits
+system.iocache.overall_miss_latency        5746694804                       # number of overall miss cycles
+system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
+system.iocache.overall_misses                   41727                       # number of overall misses
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency   3576747706                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate               1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses              41727                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements                     41697                       # number of replacements
+system.iocache.sampled_refs                     41713                       # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse                     0.387818                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.warmup_cycle              1717170509000                       # Cycle when the warmup percentage was hit.
+system.iocache.writebacks                       41522                       # number of writebacks
+system.l2c.ReadExReq_accesses                  317495                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency    52375.723397                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40223.099381                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency         16629030300                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses                    317495                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency    12770632938                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses               317495                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses                   2204283                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency      52067.320767                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40026.416785                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits                       1893933                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           16159093000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate                 0.140794                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses                      310350                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits                       17                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency      12421518000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate            0.140786                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                 310333                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    827055500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses                 141956                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency   51067.196822                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.595903                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency         7249294992                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses                   141956                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency    5691526500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses              141956                       # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency   1410123998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses                  455580                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits                      455580                       # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.l2c.avg_refs                          4.836093                       # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
+system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.demand_accesses                    2521778                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency       52223.276923                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency  40125.879919                       # average overall mshr miss latency
+system.l2c.demand_hits                        1893933                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            32788123300                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate                  0.248969                       # miss rate for demand accesses
+system.l2c.demand_misses                       627845                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                        17                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency       25192150938                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate             0.248962                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                  627828                       # number of demand (read+write) MSHR misses
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_accesses                   2521778                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency      52223.276923                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40125.879919                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_hits                       1893933                       # number of overall hits
+system.l2c.overall_miss_latency           32788123300                       # number of overall miss cycles
+system.l2c.overall_miss_rate                 0.248969                       # miss rate for overall accesses
+system.l2c.overall_misses                      627845                       # number of overall misses
+system.l2c.overall_mshr_hits                       17                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency      25192150938                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate            0.248962                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                 627828                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   2237179498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements                        402113                       # number of replacements
+system.l2c.sampled_refs                        433643                       # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse                     31146.703912                       # Cycle average of tags in use
+system.l2c.total_refs                         2097138                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                    9278348000                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                          124275                       # number of writebacks
+system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk    <err: div-0>                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr
new file mode 100755
index 000000000..4cafe060d
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr
@@ -0,0 +1,5 @@
+warn: kernel located at: /dist/m5/system/binaries/vmlinux
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: 125740500: Trying to launch CPU number 1!
+warn: be nice to actually delete the event here
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout
new file mode 100755
index 000000000..974343499
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout
@@ -0,0 +1,16 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Oct 20 2008 18:39:58
+M5 revision 5701:8ba6b8d32acac2674657b9f414b60d23fcb41fe6
+M5 commit date Sun Oct 19 22:50:53 2008 -0400
+M5 started Oct 20 2008 18:47:58
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 1907705350500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
new file mode 100644
index 000000000..d5c08c61f
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
@@ -0,0 +1,111 @@
+M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
+
+Got Configuration 623
+
+memsize 8000000 pages 4000 
+
+First free page after ROM 0xFFFFFC0000018000
+
+HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
+
+kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2
+
+CPU Clock at 2000 MHz IntrClockFrequency=1024 
+
+Booting with 2 processor(s) 
+
+KSP: 0x20043FE8 PTBR 0x20
+
+KSP: 0x20043FE8 PTBR 0x20
+
+Console Callback at 0x0, fixup at 0x0, crb offset: 0x790
+
+Memory cluster 0 [0 - 392]
+
+Memory cluster 1 [392 - 15992]
+
+Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 
+
+ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8
+
+Bootstraping CPU 1 with sp=0xFFFFFC0000076000
+
+unix_boot_mem ends at FFFFFC0000078000 
+
+k_argc = 0 
+
+jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
+CallbackFixup 0 18000, t7=FFFFFC000070C000
+
+Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
+
+Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
+
+Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
+
+Major Options: SMP LEGACY_START VERBOSE_MCHECK 
+
+Command line: root=/dev/hda1 console=ttyS0
+
+memcluster 0, usage 1, start        0, end      392
+
+memcluster 1, usage 0, start      392, end    16384
+
+freeing pages 1069:16384
+
+reserving pages 1069:1070
+
+4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
+
+SMP: 2 CPUs probed -- cpu_present_mask = 3
+
+Built 1 zonelists
+
+Kernel command line: root=/dev/hda1 console=ttyS0
+
+PID hash table entries: 1024 (order: 10, 32768 bytes)
+
+Using epoch = 1900
+
+Console: colour dummy device 80x25
+
+Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
+
+Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
+
+Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
+
+Mount-cache hash table entries: 512
+
+SMP starting up secondaries.
+
+Slave CPU 1 console command START
+SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
+
+Brought up 2 CPUs
+
+SMP: Total of 2 processors activated (8000.15 BogoMIPS).
+
+NET: Registered protocol family 16
+
+EISA bus registered
+
+pci: enabling save/restore of SRM state
+
+SCSI subsystem initialized
+
+srm_env: version 0.0.5 loaded successfully
+
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+
+Initializing Cryptographic API
+
+rtc: Standard PC (1900) epoch (1900) detected
+
+Real Time Clock Driver v1.12
+
+Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
+
+ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
+io scheduler noop registered
+
+io scheduler anticipatory registered
+
+io scheduler deadline registered
+
+io scheduler cfq registered
+
+loop: loaded (max 8 devices)
+
+nbd: registered device at major 43
+
+ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
+eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
+
+eth0: enabling optical transceiver
+
+eth0: using 64 bit addressing.
+
+eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
+
+tun: Universal TUN/TAP device driver, 1.6
+
+tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+
+Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+
+PIIX4: IDE controller at PCI slot 0000:00:00.0
+
+PIIX4: chipset revision 0
+
+PIIX4: 100% native mode on irq 31
+
+    ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
+
+    ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
+
+hda: M5 IDE Disk, ATA DISK drive
+
+hdb: M5 IDE Disk, ATA DISK drive
+
+ide0 at 0x8410-0x8417,0x8422 on irq 31
+
+hda: max request size: 128KiB
+
+hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
+
+hda: cache flushes not supported
+
+ hda: hda1
+
+hdb: max request size: 128KiB
+
+hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+
+hdb: cache flushes not supported
+
+ hdb: unknown partition table
+
+mice: PS/2 mouse device common for all mice
+
+NET: Registered protocol family 2
+
+IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
+
+TCP established hash table entries: 16384 (order: 5, 262144 bytes)
+
+TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
+
+TCP: Hash tables configured (established 16384 bind 16384)
+
+TCP reno registered
+
+ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
+
+ip_tables: (C) 2000-2002 Netfilter core team
+
+arp_tables: (C) 2002 David S. Miller
+
+TCP bic registered
+
+Initializing IPsec netlink socket
+
+NET: Registered protocol family 1
+
+NET: Registered protocol family 17
+
+NET: Registered protocol family 15
+
+Bridge firewalling registered
+
+802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
+
+All bugs added by David S. Miller <davem@redhat.com>
+
+VFS: Mounted root (ext2 filesystem) readonly.
+
+Freeing unused kernel memory: 224k freed
+
+init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
+mounting filesystems...
+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
+loading script...
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
new file mode 100644
index 000000000..808108731
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -0,0 +1,1049 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=LinuxAlphaSystem
+children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+boot_cpu_frequency=500
+boot_osflags=root=/dev/hda1 console=ttyS0
+console=/dist/m5/system/binaries/console
+init_param=0
+kernel=/dist/m5/system/binaries/vmlinux
+mem_mode=timing
+pal=/dist/m5/system/binaries/ts_osfpal
+physmem=system.physmem
+readfile=tests/halt.sh
+symbolfile=
+system_rev=1024
+system_type=34
+
+[system.bridge]
+type=Bridge
+delay=50000
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:8589934591
+nack_delay=4000
+req_size_a=16
+req_size_b=16
+resp_size_a=16
+resp_size_b=16
+write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu.interrupts
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=4
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList5.opList
+
+[system.cpu.fuPool.FUList5.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList7.opList
+
+[system.cpu.fuPool.FUList7.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=4
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.disk0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.disk0.image
+
+[system.disk0.image]
+type=CowDiskImage
+children=child
+child=system.disk0.image.child
+read_only=false
+table_size=65536
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.disk2]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.disk2.image
+
+[system.disk2.image]
+type=CowDiskImage
+children=child
+child=system.disk2.image.child
+read_only=false
+table_size=65536
+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=true
+width=64
+default=system.tsunami.pciconfig.pio
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+cpu_side_filter_ranges=549755813888:18446744073709551615
+hash_delay=1
+latency=50000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=0:18446744073709551615
+mshrs=20
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[2]
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=10000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=92
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[3]
+
+[system.membus]
+type=Bus
+children=responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+default=system.membus.responder.pio
+port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
+
+[system.membus.responder]
+type=IsaFake
+pio_addr=0
+pio_latency=1
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.default
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
+[system.simple_disk]
+type=SimpleDisk
+children=disk
+disk=system.simple_disk.disk
+system=system
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-latest.img
+read_only=true
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=Bus
+children=responder
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+default=system.toL2Bus.responder.pio
+port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.toL2Bus.responder]
+type=IsaFake
+pio_addr=0
+pio_latency=1
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.toL2Bus.default
+
+[system.tsunami]
+type=Tsunami
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+intrctrl=system.intrctrl
+system=system
+
+[system.tsunami.backdoor]
+type=AlphaBackdoor
+cpu=system.cpu
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[25]
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+pio_addr=8803072344064
+pio_latency=1000
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+pio=system.iobus.port[1]
+
+[system.tsunami.ethernet]
+type=NSGigE
+BAR0=1
+BAR0Size=256
+BAR1=0
+BAR1Size=4096
+BAR2=0
+BAR2Size=0
+BAR3=0
+BAR3Size=0
+BAR4=0
+BAR4Size=0
+BAR5=0
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=34
+ExpansionROM=0
+HeaderType=0
+InterruptLine=30
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=52
+MinimumGrant=176
+ProgIF=0
+Revision=0
+Status=656
+SubClassCode=0
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=4107
+clock=0
+config_latency=20000
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=10000000
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+rss=false
+rx_delay=1000000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=1000000
+tx_fifo_size=524288
+tx_thread=false
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
+pio=system.iobus.port[27]
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+pio_addr=8796093677568
+pio_latency=1000
+pio_size=393216
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[9]
+
+[system.tsunami.fake_ata0]
+type=IsaFake
+pio_addr=8804615848432
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[20]
+
+[system.tsunami.fake_ata1]
+type=IsaFake
+pio_addr=8804615848304
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[21]
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
+pio_addr=8804615848569
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[10]
+
+[system.tsunami.fake_pnp_read0]
+type=IsaFake
+pio_addr=8804615848451
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[12]
+
+[system.tsunami.fake_pnp_read1]
+type=IsaFake
+pio_addr=8804615848515
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[13]
+
+[system.tsunami.fake_pnp_read2]
+type=IsaFake
+pio_addr=8804615848579
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[14]
+
+[system.tsunami.fake_pnp_read3]
+type=IsaFake
+pio_addr=8804615848643
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[15]
+
+[system.tsunami.fake_pnp_read4]
+type=IsaFake
+pio_addr=8804615848707
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[16]
+
+[system.tsunami.fake_pnp_read5]
+type=IsaFake
+pio_addr=8804615848771
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[17]
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
+pio_addr=8804615848835
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[18]
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
+pio_addr=8804615848899
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[19]
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
+pio_addr=8804615850617
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[11]
+
+[system.tsunami.fake_ppc]
+type=IsaFake
+pio_addr=8804615848891
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[8]
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
+pio_addr=8804615848816
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[3]
+
+[system.tsunami.fake_uart1]
+type=IsaFake
+pio_addr=8804615848696
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[4]
+
+[system.tsunami.fake_uart2]
+type=IsaFake
+pio_addr=8804615848936
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[5]
+
+[system.tsunami.fake_uart3]
+type=IsaFake
+pio_addr=8804615848680
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[6]
+
+[system.tsunami.fake_uart4]
+type=IsaFake
+pio_addr=8804615848944
+pio_latency=1000
+pio_size=8
+platform=system.tsunami
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[7]
+
+[system.tsunami.fb]
+type=BadDevice
+devicename=FrameBuffer
+pio_addr=8804615848912
+pio_latency=1000
+platform=system.tsunami
+system=system
+pio=system.iobus.port[22]
+
+[system.tsunami.ide]
+type=IdeController
+BAR0=1
+BAR0Size=8
+BAR1=1
+BAR1Size=4
+BAR2=1
+BAR2Size=8
+BAR3=1
+BAR3Size=4
+BAR4=1
+BAR4Size=16
+BAR5=1
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+disks=system.disk0 system.disk2
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+system=system
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
+pio=system.iobus.port[26]
+
+[system.tsunami.io]
+type=TsunamiIO
+frequency=976562500
+pio_addr=8804615847936
+pio_latency=1000
+platform=system.tsunami
+system=system
+time=Thu Jan  1 00:00:00 2009
+tsunami=system.tsunami
+year_is_bcd=false
+pio=system.iobus.port[23]
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+pio_addr=8802535473152
+pio_latency=1000
+platform=system.tsunami
+system=system
+tsunami=system.tsunami
+pio=system.iobus.port[2]
+
+[system.tsunami.pciconfig]
+type=PciConfigAll
+bus=0
+pio_latency=1
+platform=system.tsunami
+size=16777216
+system=system
+pio=system.iobus.default
+
+[system.tsunami.uart]
+type=Uart8250
+pio_addr=8804615848952
+pio_latency=1000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.port[24]
+
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt
new file mode 100644
index 000000000..094233a29
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt
@@ -0,0 +1,674 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits                      6932487                       # Number of BTB hits
+global.BPredUnit.BTBLookups                  13324936                       # Number of BTB lookups
+global.BPredUnit.RASInCorrect                   41495                       # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect                 828381                       # Number of conditional branches incorrect
+global.BPredUnit.condPredicted               12127533                       # Number of conditional branches predicted
+global.BPredUnit.lookups                     14559443                       # Number of BP lookups
+global.BPredUnit.usedRAS                      1032470                       # Number of times the RAS was used to get a target.
+host_inst_rate                                 211094                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 290796                       # Number of bytes of host memory used
+host_seconds                                   251.32                       # Real time elapsed on the host
+host_tick_rate                             7430116049                       # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads            3072758                       # Number of conflicting loads.
+memdepunit.memDep.conflictingStores           2866670                       # Number of conflicting stores.
+memdepunit.memDep.insertedLoads              11041732                       # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores              7011041                       # Number of stores inserted to the mem dependence unit.
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                    53052618                       # Number of instructions simulated
+sim_seconds                                  1.867359                       # Number of seconds simulated
+sim_ticks                                1867358550500                       # Number of ticks simulated
+system.cpu.commit.COM:branches                8455188                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events            973838                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples    100543308                      
+system.cpu.commit.COM:committed_per_cycle.min_value            0                      
+                               0     76317924   7590.55%           
+                               1     10743540   1068.55%           
+                               2      5987880    595.55%           
+                               3      2987787    297.16%           
+                               4      2072579    206.14%           
+                               5       671161     66.75%           
+                               6       395328     39.32%           
+                               7       393271     39.11%           
+                               8       973838     96.86%           
+system.cpu.commit.COM:committed_per_cycle.max_value            8                      
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count                  56244351                       # Number of instructions committed
+system.cpu.commit.COM:loads                   9302477                       # Number of loads committed
+system.cpu.commit.COM:membars                  227741                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                   15692393                       # Number of memory references committed
+system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts            786910                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts       56244351                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls          667224                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts         9485751                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                    53052618                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              53052618                       # Number of Instructions Simulated
+system.cpu.cpi                               2.580282                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.580282                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses       214227                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 15534.014065                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11815.523733                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits           192045                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency    344575500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.103544                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses          22182                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits         4654                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency    207102500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.081820                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses        17528                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses            9334533                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 23887.280277                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.210749                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_hits                7801638                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    36616692500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.164218                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1532895                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            448100                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency  24694502000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.116213                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         1084795                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency    889982500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses        219741                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.938098                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.938098                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_hits            189758                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_latency   1689000500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_rate     0.136447                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses           29983                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_mshr_miss_latency   1599051500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_rate     0.136447                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_misses        29983                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.WriteReq_accesses           6155139                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 49031.922002                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.269570                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_hits               3924727                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency  109361387216                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.362366                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             2230412                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1833469                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency  21630324960                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.064490                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         396943                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1220847997                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.541558                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets        11500                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                   8.820405                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs             138181                       # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets                2                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs   1383128462                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets        23000                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses            15489672                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 38789.840881                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 31263.844863                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                11726365                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    145978079716                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.242956                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               3763307                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            2281569                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency  46324826960                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.095660                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1481738                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses           15489672                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 38789.840881                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 31263.844863                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits               11726365                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   145978079716                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.242956                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              3763307                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           2281569                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency  46324826960                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.095660                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1481738                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency   2110830497                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements                1402096                       # number of replacements
+system.cpu.dcache.sampled_refs                1402608                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse                511.995429                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 12371571                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               21439000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   430429                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       48380829                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          42524                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved        612955                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts        72702474                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          37949237                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           13063267                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         1645972                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts         134798                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        1149974                       # Number of cycles decode is unblocking
+system.cpu.dtb.accesses                       1229941                       # DTB accesses
+system.cpu.dtb.acv                                828                       # DTB access violations
+system.cpu.dtb.hits                          16757791                       # DTB hits
+system.cpu.dtb.misses                           44378                       # DTB misses
+system.cpu.dtb.read_accesses                   908364                       # DTB read accesses
+system.cpu.dtb.read_acv                           587                       # DTB read access violations
+system.cpu.dtb.read_hits                     10166755                       # DTB read hits
+system.cpu.dtb.read_misses                      36227                       # DTB read misses
+system.cpu.dtb.write_accesses                  321577                       # DTB write accesses
+system.cpu.dtb.write_acv                          241                       # DTB write access violations
+system.cpu.dtb.write_hits                     6591036                       # DTB write hits
+system.cpu.dtb.write_misses                      8151                       # DTB write misses
+system.cpu.fetch.Branches                    14559443                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                   8996158                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      23473306                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                455287                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                       74247726                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                 2478                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                  968839                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.106358                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles            8996158                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches            7964957                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        0.542387                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples           102189280                      
+system.cpu.fetch.rateDist.min_value                 0                      
+                               0     87752503   8587.25%           
+                               1      1049427    102.69%           
+                               2      2020193    197.69%           
+                               3       968502     94.78%           
+                               4      3001129    293.68%           
+                               5       683878     66.92%           
+                               6       831667     81.38%           
+                               7      1217349    119.13%           
+                               8      4664632    456.47%           
+system.cpu.fetch.rateDist.max_value                 8                      
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses            8996158                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 14905.477582                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.562270                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits                7948798                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency    15611401000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.116423                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses              1047360                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits             51971                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency  11852656500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.110646                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses          995389                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs 11366.071429                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs                   7.987119                       # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs                 56                       # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs       636500                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses             8996158                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 14905.477582                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11907.562270                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                 7948798                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency     15611401000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.116423                       # miss rate for demand accesses
+system.cpu.icache.demand_misses               1047360                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits              51971                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency  11852656500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.110646                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses           995389                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses            8996158                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 14905.477582                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11907.562270                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits                7948798                       # number of overall hits
+system.cpu.icache.overall_miss_latency    15611401000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.116423                       # miss rate for overall accesses
+system.cpu.icache.overall_misses              1047360                       # number of overall misses
+system.cpu.icache.overall_mshr_hits             51971                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency  11852656500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.110646                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses          995389                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements                 994691                       # number of replacements
+system.cpu.icache.sampled_refs                 995202                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse                509.772494                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  7948797                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle            25306164000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.idleCycles                        34701444                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                  9157080                       # Number of branches executed
+system.cpu.iew.EXEC:nop                       3677888                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.420385                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     17040949                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                    6614103                       # Number of stores executed
+system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
+system.cpu.iew.WB:consumers                  34509874                       # num instructions consuming a value
+system.cpu.iew.WB:count                      56954270                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.764112                       # average fanout of values written-back
+system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers                  26369407                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.416056                       # insts written-back per cycle
+system.cpu.iew.WB:sent                       57054995                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts               856295                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                 9703619                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              11041732                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts            1799303                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts           1049063                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts              7011041                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts            65859525                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              10426846                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            538501                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts              57546755                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                  50837                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents                  6569                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                1645972                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                550293                       # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked       311312                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads          426511                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses        11442                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation        45279                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads        15270                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads      1739255                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores       621125                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents          45279                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       380960                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect         475335                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               0.387555                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.387555                       # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0                58085258                       # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+                      No_OpClass         7284      0.01%            # Type of FU issued
+                          IntAlu     39585322     68.15%            # Type of FU issued
+                         IntMult        61995      0.11%            # Type of FU issued
+                          IntDiv            0      0.00%            # Type of FU issued
+                        FloatAdd        25609      0.04%            # Type of FU issued
+                        FloatCmp            0      0.00%            # Type of FU issued
+                        FloatCvt            0      0.00%            # Type of FU issued
+                       FloatMult            0      0.00%            # Type of FU issued
+                        FloatDiv         3636      0.01%            # Type of FU issued
+                       FloatSqrt            0      0.00%            # Type of FU issued
+                         MemRead     10781907     18.56%            # Type of FU issued
+                        MemWrite      6666291     11.48%            # Type of FU issued
+                       IprAccess       953214      1.64%            # Type of FU issued
+                    InstPrefetch            0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt                433947                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.007471                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+                      No_OpClass            0      0.00%            # attempts to use FU when none available
+                          IntAlu        52004     11.98%            # attempts to use FU when none available
+                         IntMult            0      0.00%            # attempts to use FU when none available
+                          IntDiv            0      0.00%            # attempts to use FU when none available
+                        FloatAdd            0      0.00%            # attempts to use FU when none available
+                        FloatCmp            0      0.00%            # attempts to use FU when none available
+                        FloatCvt            0      0.00%            # attempts to use FU when none available
+                       FloatMult            0      0.00%            # attempts to use FU when none available
+                        FloatDiv            0      0.00%            # attempts to use FU when none available
+                       FloatSqrt            0      0.00%            # attempts to use FU when none available
+                         MemRead       278726     64.23%            # attempts to use FU when none available
+                        MemWrite       103217     23.79%            # attempts to use FU when none available
+                       IprAccess            0      0.00%            # attempts to use FU when none available
+                    InstPrefetch            0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples    102189280                      
+system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
+                               0     73101546   7153.54%           
+                               1     14613738   1430.07%           
+                               2      6411296    627.39%           
+                               3      3930297    384.61%           
+                               4      2526857    247.27%           
+                               5      1033193    101.11%           
+                               6       443511     43.40%           
+                               7       107158     10.49%           
+                               8        21684      2.12%           
+system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate                     0.424318                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                   60130813                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                  58085258                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded             2050824                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined         8705374                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued             34364                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved        1383600                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined      4697017                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses                       1300570                       # ITB accesses
+system.cpu.itb.acv                                941                       # ITB acv
+system.cpu.itb.hits                           1261136                       # ITB hits
+system.cpu.itb.misses                           39434                       # ITB misses
+system.cpu.kern.callpal                        192636                       # number of callpals executed
+system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal_wrfen                       1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal_wrvptptr                    1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal_swpctx                   4177      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal_tbi                        54      0.03%      2.20% # number of callpals executed
+system.cpu.kern.callpal_wrent                       7      0.00%      2.20% # number of callpals executed
+system.cpu.kern.callpal_swpipl                 175664     91.19%     93.39% # number of callpals executed
+system.cpu.kern.callpal_rdps                     6794      3.53%     96.92% # number of callpals executed
+system.cpu.kern.callpal_wrkgp                       1      0.00%     96.92% # number of callpals executed
+system.cpu.kern.callpal_wrusp                       7      0.00%     96.92% # number of callpals executed
+system.cpu.kern.callpal_rdusp                       9      0.00%     96.93% # number of callpals executed
+system.cpu.kern.callpal_whami                       2      0.00%     96.93% # number of callpals executed
+system.cpu.kern.callpal_rti                      5221      2.71%     99.64% # number of callpals executed
+system.cpu.kern.callpal_callsys                   515      0.27%     99.91% # number of callpals executed
+system.cpu.kern.callpal_imb                       181      0.09%    100.00% # number of callpals executed
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.hwrei                     211796                       # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce                     6269                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count                      183013                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0                     74947     40.95%     40.95% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_21                      237      0.13%     41.08% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_22                     1890      1.03%     42.11% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31                   105939     57.89%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good                       149287                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0                      73580     49.29%     49.29% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_21                       237      0.16%     49.45% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_22                      1890      1.27%     50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31                     73580     49.29%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks                1867357676000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0              1824918402500     97.73%     97.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21                102745500      0.01%     97.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22                392410500      0.02%     97.75% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31              41944117500      2.25%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used_0                   0.981760                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_21                         1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_22                         1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_31                  0.694551                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel                 1911                      
+system.cpu.kern.mode_good_user                   1741                      
+system.cpu.kern.mode_good_idle                    170                      
+system.cpu.kern.mode_switch_kernel               5975                       # number of protection mode switches
+system.cpu.kern.mode_switch_user                 1741                       # number of protection mode switches
+system.cpu.kern.mode_switch_idle                 2095                       # number of protection mode switches
+system.cpu.kern.mode_switch_good             1.400978                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel      0.319833                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_user               1                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_idle        0.081146                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel         31310273000      1.68%      1.68% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user            3185721000      0.17%      1.85% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle          1832861674000     98.15%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
+system.cpu.kern.syscall                           326                       # number of syscalls executed
+system.cpu.kern.syscall_2                           8      2.45%      2.45% # number of syscalls executed
+system.cpu.kern.syscall_3                          30      9.20%     11.66% # number of syscalls executed
+system.cpu.kern.syscall_4                           4      1.23%     12.88% # number of syscalls executed
+system.cpu.kern.syscall_6                          42     12.88%     25.77% # number of syscalls executed
+system.cpu.kern.syscall_12                          1      0.31%     26.07% # number of syscalls executed
+system.cpu.kern.syscall_15                          1      0.31%     26.38% # number of syscalls executed
+system.cpu.kern.syscall_17                         15      4.60%     30.98% # number of syscalls executed
+system.cpu.kern.syscall_19                         10      3.07%     34.05% # number of syscalls executed
+system.cpu.kern.syscall_20                          6      1.84%     35.89% # number of syscalls executed
+system.cpu.kern.syscall_23                          4      1.23%     37.12% # number of syscalls executed
+system.cpu.kern.syscall_24                          6      1.84%     38.96% # number of syscalls executed
+system.cpu.kern.syscall_33                         11      3.37%     42.33% # number of syscalls executed
+system.cpu.kern.syscall_41                          2      0.61%     42.94% # number of syscalls executed
+system.cpu.kern.syscall_45                         54     16.56%     59.51% # number of syscalls executed
+system.cpu.kern.syscall_47                          6      1.84%     61.35% # number of syscalls executed
+system.cpu.kern.syscall_48                         10      3.07%     64.42% # number of syscalls executed
+system.cpu.kern.syscall_54                         10      3.07%     67.48% # number of syscalls executed
+system.cpu.kern.syscall_58                          1      0.31%     67.79% # number of syscalls executed
+system.cpu.kern.syscall_59                          7      2.15%     69.94% # number of syscalls executed
+system.cpu.kern.syscall_71                         54     16.56%     86.50% # number of syscalls executed
+system.cpu.kern.syscall_73                          3      0.92%     87.42% # number of syscalls executed
+system.cpu.kern.syscall_74                         16      4.91%     92.33% # number of syscalls executed
+system.cpu.kern.syscall_87                          1      0.31%     92.64% # number of syscalls executed
+system.cpu.kern.syscall_90                          3      0.92%     93.56% # number of syscalls executed
+system.cpu.kern.syscall_92                          9      2.76%     96.32% # number of syscalls executed
+system.cpu.kern.syscall_97                          2      0.61%     96.93% # number of syscalls executed
+system.cpu.kern.syscall_98                          2      0.61%     97.55% # number of syscalls executed
+system.cpu.kern.syscall_132                         4      1.23%     98.77% # number of syscalls executed
+system.cpu.kern.syscall_144                         2      0.61%     99.39% # number of syscalls executed
+system.cpu.kern.syscall_147                         2      0.61%    100.00% # number of syscalls executed
+system.cpu.numCycles                        136890724                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles         14253215                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps       38229138                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents         1097271                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          39542580                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        2236137                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents          15711                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups       83423826                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts        68665910                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands     46022424                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           12703530                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         1645972                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        5219245                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps           7793284                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles     28824736                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts      1704564                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           12805073                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts       256708                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                         1321430                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iocache.ReadReq_accesses                   173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency  115248.543353                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency          19937998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses                     173                       # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency     10941998                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate               1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_misses                173                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency 137791.894638                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85788.456248                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5725528806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
+system.iocache.WriteReq_mshr_miss_latency   3564681934                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_rate              1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
+system.iocache.avg_blocked_cycles_no_mshrs  6164.090493                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs                 10476                       # number of cycles access was blocked
+system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs       64575012                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.demand_accesses                  41725                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency   137698.425500                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85695.001366                       # average overall mshr miss latency
+system.iocache.demand_hits                          0                       # number of demand (read+write) hits
+system.iocache.demand_miss_latency         5745466804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
+system.iocache.demand_misses                    41725                       # number of demand (read+write) misses
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency    3575623932                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate                1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_accesses                 41725                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency  137698.425500                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85695.001366                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.iocache.overall_hits                         0                       # number of overall hits
+system.iocache.overall_miss_latency        5745466804                       # number of overall miss cycles
+system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
+system.iocache.overall_misses                   41725                       # number of overall misses
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency   3575623932                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate               1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements                     41685                       # number of replacements
+system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse                     1.267378                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.warmup_cycle              1716179930000                       # Cycle when the warmup percentage was hit.
+system.iocache.writebacks                       41512                       # number of writebacks
+system.l2c.ReadExReq_accesses                  300595                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency    52362.159484                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40213.629621                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency         15739803330                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses                    300595                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency    12088015996                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses               300595                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses                   2097337                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency      52066.027817                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40026.238880                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits                       1786309                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           16193992500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate                 0.148297                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses                      311028                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits                        1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency      12449241000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate            0.148296                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                 311027                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    797101500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses                 130242                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency   52272.511886                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.963790                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency         6808076493                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses                   130242                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency    5222439000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses              130242                       # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency   1102715998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses                  430429                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits                      430429                       # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.l2c.avg_refs                          4.598824                       # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
+system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.demand_accesses                    2397932                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency       52211.567959                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency  40118.336155                       # average overall mshr miss latency
+system.l2c.demand_hits                        1786309                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            31933795830                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate                  0.255063                       # miss rate for demand accesses
+system.l2c.demand_misses                       611623                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                         1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency       24537256996                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate             0.255062                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                  611622                       # number of demand (read+write) MSHR misses
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_accesses                   2397932                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency      52211.567959                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40118.336155                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_hits                       1786309                       # number of overall hits
+system.l2c.overall_miss_latency           31933795830                       # number of overall miss cycles
+system.l2c.overall_miss_rate                 0.255063                       # miss rate for overall accesses
+system.l2c.overall_misses                      611623                       # number of overall misses
+system.l2c.overall_mshr_hits                        1                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency      24537256996                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate            0.255062                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                 611622                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   1899817498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements                        396037                       # number of replacements
+system.l2c.sampled_refs                        427715                       # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse                     30684.696960                       # Cycle average of tags in use
+system.l2c.total_refs                         1966986                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                    5645091000                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                          119087                       # number of writebacks
+system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk    <err: div-0>                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr
new file mode 100755
index 000000000..1a557daf8
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr
@@ -0,0 +1,4 @@
+warn: kernel located at: /dist/m5/system/binaries/vmlinux
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout
new file mode 100755
index 000000000..3c523295b
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout
@@ -0,0 +1,16 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Oct 20 2008 18:39:58
+M5 revision 5701:8ba6b8d32acac2674657b9f414b60d23fcb41fe6
+M5 commit date Sun Oct 19 22:50:53 2008 -0400
+M5 started Oct 20 2008 18:47:58
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 1867358550500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
new file mode 100644
index 000000000..8a13d1a5e
--- /dev/null
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
@@ -0,0 +1,106 @@
+M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
+
+Got Configuration 623
+
+memsize 8000000 pages 4000 
+
+First free page after ROM 0xFFFFFC0000018000
+
+HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
+
+kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
+
+CPU Clock at 2000 MHz IntrClockFrequency=1024 
+
+Booting with 1 processor(s) 
+
+KSP: 0x20043FE8 PTBR 0x20
+
+Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
+
+Memory cluster 0 [0 - 392]
+
+Memory cluster 1 [392 - 15992]
+
+Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 
+
+ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
+
+unix_boot_mem ends at FFFFFC0000076000 
+
+k_argc = 0 
+
+jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
+
+CallbackFixup 0 18000, t7=FFFFFC000070C000
+
+Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
+
+Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
+
+Major Options: SMP LEGACY_START VERBOSE_MCHECK 
+
+Command line: root=/dev/hda1 console=ttyS0
+
+memcluster 0, usage 1, start        0, end      392
+
+memcluster 1, usage 0, start      392, end    16384
+
+freeing pages 1069:16384
+
+reserving pages 1069:1070
+
+4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
+
+SMP: 1 CPUs probed -- cpu_present_mask = 1
+
+Built 1 zonelists
+
+Kernel command line: root=/dev/hda1 console=ttyS0
+
+PID hash table entries: 1024 (order: 10, 32768 bytes)
+
+Using epoch = 1900
+
+Console: colour dummy device 80x25
+
+Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
+
+Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
+
+Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
+
+Mount-cache hash table entries: 512
+
+SMP mode deactivated.
+
+Brought up 1 CPUs
+
+SMP: Total of 1 processors activated (4002.20 BogoMIPS).
+
+NET: Registered protocol family 16
+
+EISA bus registered
+
+pci: enabling save/restore of SRM state
+
+SCSI subsystem initialized
+
+srm_env: version 0.0.5 loaded successfully
+
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+
+Initializing Cryptographic API
+
+rtc: Standard PC (1900) epoch (1900) detected
+
+Real Time Clock Driver v1.12
+
+Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
+
+ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+
+io scheduler noop registered
+
+io scheduler anticipatory registered
+
+io scheduler deadline registered
+
+io scheduler cfq registered
+
+loop: loaded (max 8 devices)
+
+nbd: registered device at major 43
+
+ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
+eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
+
+eth0: enabling optical transceiver
+
+eth0: using 64 bit addressing.
+
+eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
+
+tun: Universal TUN/TAP device driver, 1.6
+
+tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+
+Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+
+PIIX4: IDE controller at PCI slot 0000:00:00.0
+
+PIIX4: chipset revision 0
+
+PIIX4: 100% native mode on irq 31
+
+    ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
+
+    ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
+
+hda: M5 IDE Disk, ATA DISK drive
+
+hdb: M5 IDE Disk, ATA DISK drive
+
+ide0 at 0x8410-0x8417,0x8422 on irq 31
+
+hda: max request size: 128KiB
+
+hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
+
+hda: cache flushes not supported
+
+ hda: hda1
+
+hdb: max request size: 128KiB
+
+hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+
+hdb: cache flushes not supported
+
+ hdb: unknown partition table
+
+mice: PS/2 mouse device common for all mice
+
+NET: Registered protocol family 2
+
+IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
+
+TCP established hash table entries: 16384 (order: 5, 262144 bytes)
+
+TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
+
+TCP: Hash tables configured (established 16384 bind 16384)
+
+TCP reno registered
+
+ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
+
+ip_tables: (C) 2000-2002 Netfilter core team
+
+arp_tables: (C) 2002 David S. Miller
+
+TCP bic registered
+
+Initializing IPsec netlink socket
+
+NET: Registered protocol family 1
+
+NET: Registered protocol family 17
+
+NET: Registered protocol family 15
+
+Bridge firewalling registered
+
+802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
+
+All bugs added by David S. Miller <davem@redhat.com>
+
+VFS: Mounted root (ext2 filesystem) readonly.
+
+Freeing unused kernel memory: 224k freed
+
+init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
+mounting filesystems...
+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
+loading script...
diff --git a/tests/long/10.linux-boot/test.py b/tests/long/10.linux-boot/test.py
new file mode 100644
index 000000000..215d63700
--- /dev/null
+++ b/tests/long/10.linux-boot/test.py
@@ -0,0 +1,29 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+root.system.readfile = os.path.join(tests_root, 'halt.sh')
author	Ali Saidi <saidi@eecs.umich.edu>	2008-10-20 19:00:07 -0400
committer	Ali Saidi <saidi@eecs.umich.edu>	2008-10-20 19:00:07 -0400
commit	aac93b7d0ce5e8e0241c7299b49cc59a9d095f3e (patch)
tree	bbfdf01ccc199204dd2a385f1b4fab0b44c16a32
parent	b760b99f4d9f5469d88c67ae8a06e5f9543a43e7 (diff)
download	gem5-aac93b7d0ce5e8e0241c7299b49cc59a9d095f3e.tar.xz