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authorGabe Black <gblack@eecs.umich.edu>2007-11-21 00:04:15 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-11-21 00:04:15 -0800
commitab598eadbfeefceb6501d4cca13147b660642d9e (patch)
treedec2882f70c2205551469ac21e2a6da02dc34745
parentce26c3ccec32ac557e6f289a599d8ff2b522149f (diff)
downloadgem5-ab598eadbfeefceb6501d4cca13147b660642d9e.tar.xz
imported patch pagewalker.patch
--HG-- extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f
-rw-r--r--src/cpu/BaseCPU.py6
-rw-r--r--src/cpu/simple/base.cc2
2 files changed, 6 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 691f92e2e..ee5ed0774 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -101,6 +101,8 @@ class BaseCPU(SimObject):
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
_mem_ports = []
+ if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
+ _mem_ports = ["itb.walker.port", "dtb.walker.port"]
def connectMemPorts(self, bus):
for p in self._mem_ports:
@@ -108,12 +110,14 @@ class BaseCPU(SimObject):
exec('self.%s = bus.port' % p)
def addPrivateSplitL1Caches(self, ic, dc):
- assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
+ assert(len(self._mem_ports) < 6)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+ if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
+ self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
self.addPrivateSplitL1Caches(ic, dc)
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 010c21e4a..ad7b14be3 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -466,9 +466,9 @@ BaseSimpleCPU::advancePC(Fault fault)
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
predecoder.reset();
- fault->invoke(tc);
thread->setMicroPC(0);
thread->setNextMicroPC(1);
+ fault->invoke(tc);
} else {
//If we're at the last micro op for this instruction
if (curStaticInst && curStaticInst->isLastMicroop()) {