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authorAndreas Sandberg <andreas.sandberg@arm.com>2017-06-26 17:05:58 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-06-30 16:45:27 +0000
commitb2116de96d7b0a05c8916bc3f3fb0a3376356ef0 (patch)
treec9cfb61fe9b2e20adbe054f95dc96d543e8f87b9
parent637e1ec740b78bf063190c3068a9c50cf8207637 (diff)
downloadgem5-b2116de96d7b0a05c8916bc3f3fb0a3376356ef0.tar.xz
config: Make some MemConfig options optional
MemConfig currently assumes that all callers include the its full set of options in the command line parser. This is unnecessary and sometimes confusing. Make most of the options optional to avoid having to add all of them to example scripts. Change-Id: I2d73be2454427b00db16716edcfd96a47133c888 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3940 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
-rw-r--r--configs/common/MemConfig.py39
1 files changed, 24 insertions, 15 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index b625084cb..3605c2144 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2013 ARM Limited
+# Copyright (c) 2013, 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -152,7 +152,18 @@ def config_mem(options, system):
them.
"""
- if ( options.mem_type == "HMC_2500_1x32"):
+ # Mandatory options
+ opt_mem_type = options.mem_type
+ opt_mem_channels = options.mem_channels
+
+ # Optional options
+ opt_tlm_memory = getattr(options, "tlm_memory", None)
+ opt_external_memory_system = getattr(options, "external_memory_system",
+ None)
+ opt_elastic_trace_en = getattr(options, "elastic_trace_en", False)
+ opt_mem_ranks = getattr(options, "mem_ranks", None)
+
+ if opt_mem_type == "HMC_2500_1x32":
HMChost = HMC.config_host_hmc(options, system)
HMC.config_hmc(options, system, HMChost.hmc_host)
subsystem = system.hmc_dev
@@ -161,35 +172,34 @@ def config_mem(options, system):
subsystem = system
xbar = system.membus
- if options.tlm_memory:
+ if opt_tlm_memory:
system.external_memory = m5.objects.ExternalSlave(
port_type="tlm_slave",
- port_data=options.tlm_memory,
+ port_data=opt_tlm_memory,
port=system.membus.master,
addr_ranges=system.mem_ranges)
system.kernel_addr_check = False
return
- if options.external_memory_system:
+ if opt_external_memory_system:
subsystem.external_memory = m5.objects.ExternalSlave(
- port_type=options.external_memory_system,
+ port_type=opt_external_memory_system,
port_data="init_mem0", port=xbar.master,
addr_ranges=system.mem_ranges)
subsystem.kernel_addr_check = False
return
- nbr_mem_ctrls = options.mem_channels
+ nbr_mem_ctrls = opt_mem_channels
import math
from m5.util import fatal
intlv_bits = int(math.log(nbr_mem_ctrls, 2))
if 2 ** intlv_bits != nbr_mem_ctrls:
fatal("Number of memory channels must be a power of 2")
- cls = get(options.mem_type)
+ cls = get(opt_mem_type)
mem_ctrls = []
- if options.elastic_trace_en and not issubclass(cls, \
- m5.objects.SimpleMemory):
+ if opt_elastic_trace_en and not issubclass(cls, m5.objects.SimpleMemory):
fatal("When elastic trace is enabled, configure mem-type as "
"simple-mem.")
@@ -208,11 +218,10 @@ def config_mem(options, system):
intlv_size)
# Set the number of ranks based on the command-line
# options if it was explicitly set
- if issubclass(cls, m5.objects.DRAMCtrl) and \
- options.mem_ranks:
- mem_ctrl.ranks_per_channel = options.mem_ranks
+ if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
+ mem_ctrl.ranks_per_channel = opt_mem_ranks
- if options.elastic_trace_en:
+ if opt_elastic_trace_en:
mem_ctrl.latency = '1ns'
print "For elastic trace, over-riding Simple Memory " \
"latency to 1ns."
@@ -223,7 +232,7 @@ def config_mem(options, system):
# Connect the controllers to the membus
for i in xrange(len(subsystem.mem_ctrls)):
- if (options.mem_type == "HMC_2500_1x32"):
+ if opt_mem_type == "HMC_2500_1x32":
subsystem.mem_ctrls[i].port = xbar[i/4].master
else:
subsystem.mem_ctrls[i].port = xbar.master