implement taint propagation

6 files changed, 27 insertions, 9 deletions

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 756a5aa9f..d533ad9bf 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -478,11 +478,15 @@ class BaseDynInst : public ExecContext, public RefCounted
         _prevDestRegIdx[idx] = previous_rename;
     }
 
-    void taintDestRegs(void)
+    void taintDestRegs(bool istaint)
     {
         for (size_t i = 0; i < numDestRegs(); i++) {
             auto dstreg = _destRegIdx[i];
-            cpu->setTaint(dstreg);
+            if (istaint) {
+                cpu->setTaint(dstreg);
+            } else {
+                cpu->clearTaint(dstreg);
+            }
         }
     }
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index ad4e6d549..4cbbd0ec6 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1282,7 +1282,14 @@ template <class Impl>
 void
 FullO3CPU<Impl>::setTaint(PhysRegIdPtr phys_reg)
 {
-    regFile.setTaint(phys_reg);
+    regFile.setTaint(phys_reg, true);
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::clearTaint(PhysRegIdPtr phys_reg)
+{
+    regFile.setTaint(phys_reg, false);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 131655ecd..c231d4a18 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -401,6 +401,7 @@ class FullO3CPU : public BaseO3CPU
 
     /** taint a register */
     void setTaint(PhysRegIdPtr phys_reg);
+    void clearTaint(PhysRegIdPtr phys_reg);
     bool regTainted(PhysRegIdPtr phys_reg);
 
     uint64_t readIntReg(PhysRegIdPtr phys_reg);
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index ee6e76ddd..6adbda7fc 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1328,6 +1328,12 @@ DefaultIEW<Impl>::executeInsts()
                     inst->forwardOldRegs();
             }
 
+            if (inst->srcTainted()) {
+                inst->taintDestRegs(true);
+            } else {
+                inst->taintDestRegs(false);
+            }
+
             inst->setExecuted();
 
             instToCommit(inst);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 14256e382..3edbe4761 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1053,7 +1053,7 @@ LSQUnit<Impl>::updateVisibleState()
                 }
 #endif
                 /* set taint for dst registers */
-                inst->taintDestRegs();
+                inst->taintDestRegs(true);
                 /* if the load depends on tainted registers, set
                    readyToExpose to false, otherwise set it to true
                 */
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 4d54acc2f..b835a7dd8 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -183,20 +183,20 @@ class PhysRegFile
     }
 
     /** Set a physical register as tainted */
-    void setTaint(PhysRegIdPtr phys_reg) {
+    void setTaint(PhysRegIdPtr phys_reg, bool taintvalue) {
       RegIndex idx = phys_reg->index();
       switch (phys_reg->classValue()) {
       case IntRegClass:
-        intTaintMap[idx] = true;
+        intTaintMap[idx] = taintvalue;
         break;
       case FloatRegClass:
-        floatTaintMap[idx] = true;
+        floatTaintMap[idx] = taintvalue;
         break;
       case CCRegClass:
-        ccTaintMap[idx] = true;
+        ccTaintMap[idx] = taintvalue;
         break;
       case MiscRegClass:
-        miscTaintMap[idx] = true;
+        miscTaintMap[idx] = taintvalue;
         break;
       default:
         warn_once("taint for vector registers not supported yet\n");