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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-07-17 15:28:48 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-07-17 15:28:48 -0700 |
| commit | cf846d5205c021a04ab1a8e830d9cb86be0bda6e (patch) | |
| tree | a66947d2d5dd49f1be72f5154963b325445bd116 | |
| parent | bbf7163dd9a9c2a17cb8873f7620f2b17841ac26 (diff) | |
| download | gem5-cf846d5205c021a04ab1a8e830d9cb86be0bda6e.tar.xz | |
Add in operand which holds the condition code bits of the flag register.
--HG--
extra : convert_revision : 416052f41fccc8286b3bdbe8d559512a761224f2
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index b2ac17d66..83df583ea 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -103,5 +103,6 @@ def operands {{ 'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5), 'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6), 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10), + 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; |