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authorSteve Reinhardt <stever@gmail.com>2013-08-24 12:03:10 -0400
committerSteve Reinhardt <stever@gmail.com>2013-08-24 12:03:10 -0400
commitdc18352e3c5f35352341bb783e1d630eb1e810f4 (patch)
tree09e6a33c9db072fa58c4e87f3dea789aec93a7b0
parentecfe7dc3efb2622fef10a8be39c477148ded3d29 (diff)
downloadgem5-dc18352e3c5f35352341bb783e1d630eb1e810f4.tar.xz
stats: update eio stats
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini70
-rwxr-xr-xtests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout4
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt84
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini160
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout4
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt872
6 files changed, 664 insertions, 530 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index dc819fce5..c06c84e34 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -29,12 +30,17 @@ work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
@@ -62,10 +68,10 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -76,22 +82,31 @@ prefetcher=Null
response_latency=2
size=262144
system=system
+tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -102,12 +117,21 @@ prefetcher=Null
response_latency=2
size=131072
system=system
+tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
[system.cpu.interrupts]
type=AlphaInterrupts
@@ -120,10 +144,10 @@ size=48
[system.cpu.l2cache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -134,16 +158,24 @@ prefetcher=Null
response_latency=20
size=2097152
system=system
+tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
[system.cpu.toL2Bus]
type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -164,10 +196,14 @@ max_stack_size=67108864
output=cout
system=system
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
[system.membus]
type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -178,8 +214,8 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
@@ -187,3 +223,7 @@ null=false
range=0:134217727
port=system.membus.master[0]
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
index a4d5a6332..fa0029313 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 8 2013 10:00:13
-gem5 started Jun 8 2013 10:00:28
+gem5 compiled Aug 24 2013 11:53:30
+gem5 started Aug 24 2013 12:01:38
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index a1275a141..ba5bfdaa0 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000727 # Nu
sim_ticks 727072000 # Number of ticks simulated
final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1476552 # Simulator instruction rate (inst/s)
-host_op_rate 1476467 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2146892777 # Simulator tick rate (ticks/s)
-host_mem_usage 226332 # Number of bytes of host memory used
-host_seconds 0.34 # Real time elapsed on the host
+host_inst_rate 1590478 # Simulator instruction rate (inst/s)
+host_op_rate 1590395 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2312543024 # Simulator tick rate (ticks/s)
+host_mem_usage 227540 # Number of bytes of host memory used
+host_seconds 0.31 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
@@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 718 # Tr
system.membus.trans_dist::ReadResp 718 # Transaction distribution
system.membus.trans_dist::ReadExReq 139 # Transaction distribution
system.membus.trans_dist::ReadExResp 139 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 1714 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 54848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 54848 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 857000 # Layer occupancy (ticks)
@@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 1454144 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 0 # number of replacements
+system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
@@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 481.542013 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 481.542013 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
@@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 287.259400 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 287.259400 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
@@ -397,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 718 # Tr
system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 806 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 908 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 1714 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 25792 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 29056 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25792 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29056 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 54848 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks)
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index e7ce04e2d..1b0504991 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain
boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -27,14 +28,19 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.slave[1]
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
branchPred=Null
checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
@@ -62,10 +68,10 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -76,22 +82,31 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu0.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu0.dtb]
type=AlphaTLB
size=64
[system.cpu0.icache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -102,12 +117,21 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu0.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu0.interrupts]
type=AlphaInterrupts
@@ -136,7 +160,7 @@ type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
branchPred=Null
checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
cpu_id=1
do_checkpoint_insts=true
do_quiesce=true
@@ -164,10 +188,10 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -178,22 +202,31 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu1.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[3]
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu1.dtb]
type=AlphaTLB
size=64
[system.cpu1.icache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -204,12 +237,21 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu1.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[2]
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu1.interrupts]
type=AlphaInterrupts
@@ -238,7 +280,7 @@ type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
branchPred=Null
checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
cpu_id=2
do_checkpoint_insts=true
do_quiesce=true
@@ -266,10 +308,10 @@ icache_port=system.cpu2.icache.cpu_side
[system.cpu2.dcache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -280,22 +322,31 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu2.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
mem_side=system.toL2Bus.slave[5]
+[system.cpu2.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu2.dtb]
type=AlphaTLB
size=64
[system.cpu2.icache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -306,12 +357,21 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu2.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.slave[4]
+[system.cpu2.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu2.interrupts]
type=AlphaInterrupts
@@ -340,7 +400,7 @@ type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
branchPred=Null
checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
cpu_id=3
do_checkpoint_insts=true
do_quiesce=true
@@ -368,10 +428,10 @@ icache_port=system.cpu3.icache.cpu_side
[system.cpu3.dcache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -382,22 +442,31 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu3.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
mem_side=system.toL2Bus.slave[7]
+[system.cpu3.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu3.dtb]
type=AlphaTLB
size=64
[system.cpu3.icache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -408,12 +477,21 @@ prefetcher=Null
response_latency=2
size=32768
system=system
+tags=system.cpu3.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.slave[6]
+[system.cpu3.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
[system.cpu3.interrupts]
type=AlphaInterrupts
@@ -437,12 +515,17 @@ max_stack_size=67108864
output=cout
system=system
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
[system.l2c]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -453,28 +536,36 @@ prefetcher=Null
response_latency=20
size=4194304
system=system
+tags=system.l2c.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
+mem_side=system.membus.slave[1]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
[system.membus]
type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
+slave=system.system_port system.l2c.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
in_addr_map=true
latency=30000
latency_var=0
@@ -484,8 +575,7 @@ port=system.membus.master[0]
[system.toL2Bus]
type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -493,3 +583,7 @@ width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index de7797416..8dc0648e9 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 8 2013 10:00:13
-gem5 started Jun 8 2013 10:00:28
+gem5 compiled Aug 24 2013 11:53:30
+gem5 started Aug 24 2013 12:01:38
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 201c425a7..1f00329e8 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000729 # Nu
sim_ticks 729024000 # Number of ticks simulated
final_tick 729024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1420709 # Simulator instruction rate (inst/s)
-host_op_rate 1420692 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 517863701 # Simulator tick rate (ticks/s)
-host_mem_usage 236964 # Number of bytes of host memory used
-host_seconds 1.41 # Real time elapsed on the host
+host_inst_rate 1392779 # Simulator instruction rate (inst/s)
+host_op_rate 1392763 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 507683499 # Simulator tick rate (ticks/s)
+host_mem_usage 238176 # Number of bytes of host memory used
+host_seconds 1.44 # Real time elapsed on the host
sim_insts 1999959 # Number of instructions simulated
sim_ops 1999959 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
@@ -62,40 +62,393 @@ system.membus.trans_dist::ReadReq 2872 # Tr
system.membus.trans_dist::ReadResp 2872 # Transaction distribution
system.membus.trans_dist::ReadExReq 556 # Transaction distribution
system.membus.trans_dist::ReadExResp 556 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 6856 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 219392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 219392 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 4229968 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 31051500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 4.3 # Layer utilization (%)
+system.l2c.tags.replacements 0 # number of replacements
+system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use
+system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
+system.l2c.Writeback_hits::total 116 # number of Writeback hits
+system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::total 276 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu0.data 9 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu1.data 9 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu2.data 9 # number of overall hits
+system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu3.data 9 # number of overall hits
+system.l2c.overall_hits::total 276 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
+system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
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+system.l2c.overall_misses::cpu0.data 454 # number of overall misses
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+system.l2c.overall_misses::cpu1.data 454 # number of overall misses
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+system.l2c.overall_misses::cpu2.data 454 # number of overall misses
+system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
+system.l2c.overall_misses::cpu3.data 454 # number of overall misses
+system.l2c.overall_misses::total 3428 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst 21101500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 16409500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 21110000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 16409500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 21118500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 16409500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst 21129500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.data 16412000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 150100000 # number of ReadReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 7252500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 7252500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 7252500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data 7252500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 29010000 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 21101500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 23662000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 21110000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 23662000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 21118500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 23662000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst 21129500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data 23664500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 179110000 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 21101500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 23662000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 21110000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 23662000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 21118500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 23662000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst 21129500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data 23664500 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 179110000 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
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system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
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+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 244480 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 2374000 # Layer occupancy (ticks)
@@ -171,15 +524,15 @@ system.cpu0.num_idle_cycles 0 # Nu
system.cpu0.num_busy_cycles 1458048 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.icache.tags.replacements 152 # number of replacements
-system.cpu0.icache.tags.tagsinuse 216.376897 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.replacements 152 # number of replacements
+system.cpu0.icache.tags.tagsinuse 216.376897 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.422611 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.422611 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
@@ -249,15 +602,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 47883.369330
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 61 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 273.500146 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.replacements 61 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 273.500146 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.534180 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.534180 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
@@ -404,15 +757,15 @@ system.cpu1.num_idle_cycles 0 # Nu
system.cpu1.num_busy_cycles 1458048 # Number of busy cycles
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0 # Percentage of idle cycles
-system.cpu1.icache.tags.replacements 152 # number of replacements
-system.cpu1.icache.tags.tagsinuse 216.373058 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 499549 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 1078.939525 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.replacements 152 # number of replacements
+system.cpu1.icache.tags.tagsinuse 216.373058 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 499549 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 1078.939525 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.422604 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.422604 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits
@@ -482,15 +835,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 47902.807775
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 61 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 273.495183 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.replacements 61 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 273.495183 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.534170 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.534170 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits
@@ -637,15 +990,15 @@ system.cpu2.num_idle_cycles 0 # Nu
system.cpu2.num_busy_cycles 1458048 # Number of busy cycles
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0 # Percentage of idle cycles
-system.cpu2.icache.tags.replacements 152 # number of replacements
-system.cpu2.icache.tags.tagsinuse 216.369218 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 499542 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 1078.924406 # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.icache.tags.replacements 152 # number of replacements
+system.cpu2.icache.tags.tagsinuse 216.369218 # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs 499542 # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs 1078.924406 # Average number of references to valid blocks.
+system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.422596 # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total 0.422596 # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits
@@ -715,15 +1068,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 47922.246220
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.tags.replacements 61 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 273.490220 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 180309 # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.tags.replacements 61 # number of replacements
+system.cpu2.dcache.tags.tagsinuse 273.490220 # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs 180309 # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks.
+system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.534161 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total 0.534161 # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits
@@ -870,15 +1223,15 @@ system.cpu3.num_idle_cycles 0 # Nu
system.cpu3.num_busy_cycles 1458048 # Number of busy cycles
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.icache.tags.replacements 152 # number of replacements
-system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 1078.909287 # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.icache.tags.replacements 152 # number of replacements
+system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs 1078.909287 # Average number of references to valid blocks.
+system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.422589 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total 0.422589 # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits
@@ -948,15 +1301,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.dcache.tags.tagsinuse 273.485257 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 180307 # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 389.431965 # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.tags.replacements 61 # number of replacements
+system.cpu3.dcache.tags.tagsinuse 273.485257 # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs 180307 # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs 389.431965 # Average number of references to valid blocks.
+system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.534151 # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total 0.534151 # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
@@ -1048,358 +1401,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52306.695464
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor
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-system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
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-system.l2c.Writeback_hits::total 116 # number of Writeback hits
-system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40176.258993 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40132.194245 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------