diff options
| author | Polina Dudnik <pdudnik@gmail.com> | 2009-07-16 15:40:48 -0500 |
|---|---|---|
| committer | Polina Dudnik <pdudnik@gmail.com> | 2009-07-16 15:40:48 -0500 |
| commit | e557b4beb570c2019d01da6cb1036dad5853cb60 (patch) | |
| tree | ed81eecfcb6bf3ded59e5bc269550b398deefc47 | |
| parent | 23a405f5d8f025784bf447f49a3d1e938577ef2b (diff) | |
| parent | e9eccf722575ff6a46165f3e6a4872e767f475b8 (diff) | |
| download | gem5-e557b4beb570c2019d01da6cb1036dad5853cb60.tar.xz | |
merge
25 files changed, 616 insertions, 613 deletions
diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh index e0545761d..16bcee47a 100644 --- a/src/arch/arm/linux/linux.hh +++ b/src/arch/arm/linux/linux.hh @@ -47,22 +47,22 @@ class ArmLinux : public Linux //@{ /// open(2) flag values. - static const int TGT_O_RDONLY = 0x00000000; //!< O_RDONLY - static const int TGT_O_WRONLY = 0x00000001; //!< O_WRONLY - static const int TGT_O_RDWR = 0x00000002; //!< O_RDWR - static const int TGT_O_CREAT = 0x00000100; //!< O_CREAT - static const int TGT_O_EXCL = 0x00000200; //!< O_EXCL - static const int TGT_O_NOCTTY = 0x00000400; //!< O_NOCTTY - static const int TGT_O_TRUNC = 0x00001000; //!< O_TRUNC - static const int TGT_O_APPEND = 0x00002000; //!< O_APPEND - static const int TGT_O_NONBLOCK = 0x00004000; //!< O_NONBLOCK - static const int TGT_O_SYNC = 0x00010000; //!< O_SYNC - static const int TGT_FASYNC = 0x00020000; //!< FASYNC - static const int TGT_O_DIRECT = 0x00040000; //!< O_DIRECT - static const int TGT_O_LARGEFILE = 0x00100000; //!< O_LARGEFILE - static const int TGT_O_DIRECTORY = 0x00200000; //!< O_DIRECTORY - static const int TGT_O_NOFOLLOW = 0x00400000; //!< O_NOFOLLOW - static const int TGT_O_NOATIME = 0x01000000; //!< O_NOATIME + static const int TGT_O_RDONLY = 00000000; //!< O_RDONLY + static const int TGT_O_WRONLY = 00000001; //!< O_WRONLY + static const int TGT_O_RDWR = 00000002; //!< O_RDWR + static const int TGT_O_CREAT = 00000100; //!< O_CREAT + static const int TGT_O_EXCL = 00000200; //!< O_EXCL + static const int TGT_O_NOCTTY = 00000400; //!< O_NOCTTY + static const int TGT_O_TRUNC = 00001000; //!< O_TRUNC + static const int TGT_O_APPEND = 00002000; //!< O_APPEND + static const int TGT_O_NONBLOCK = 00004000; //!< O_NONBLOCK + static const int TGT_O_SYNC = 00010000; //!< O_SYNC + static const int TGT_FASYNC = 00020000; //!< FASYNC + static const int TGT_O_DIRECTORY = 00040000; //!< O_DIRECTORY + static const int TGT_O_NOFOLLOW = 00100000; //!< O_NOFOLLOW + static const int TGT_O_DIRECT = 00200000; //!< O_DIRECT + static const int TGT_O_LARGEFILE = 00400000; //!< O_LARGEFILE + static const int TGT_O_NOATIME = 01000000; //!< O_NOATIME //@} /// For mmap(). @@ -70,13 +70,13 @@ class ArmLinux : public Linux //@{ /// For getsysinfo(). - static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string - static const unsigned GSI_CPU_INFO = 59; //!< CPU information - static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type - static const unsigned GSI_MAX_CPU = 30; //!< max # cpu's on this machine - static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system - static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB - static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz + static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string + static const unsigned GSI_CPU_INFO = 59; //!< CPU information + static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type + static const unsigned GSI_MAX_CPU = 30; //!< max # cpu's on this machine + static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system + static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB + static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz //@} //@{ diff --git a/src/arch/x86/floatregs.hh b/src/arch/x86/floatregs.hh index dc9867c42..2108db8d5 100644 --- a/src/arch/x86/floatregs.hh +++ b/src/arch/x86/floatregs.hh @@ -166,7 +166,7 @@ namespace X86ISA static inline FloatRegIndex FLOATREG_STACK(int index, int top) { - return (FloatRegIndex)(NUM_FLOATREGS + ((top + index + 8) % 8)); + return FLOATREG_FPR((top + index + 8) % 8); } }; diff --git a/src/arch/x86/insts/microfpop.hh b/src/arch/x86/insts/microfpop.hh index 2e01cadbc..d3cecd67b 100644 --- a/src/arch/x86/insts/microfpop.hh +++ b/src/arch/x86/insts/microfpop.hh @@ -80,13 +80,13 @@ namespace X86ISA const char *mnem, const char *_instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _src1, RegIndex _src2, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, int8_t _spm, OpClass __opClass) : X86MicroopBase(_machInst, mnem, _instMnem, isMicro, isDelayed, isFirst, isLast, __opClass), - src1(_src1), src2(_src2), dest(_dest), + src1(_src1.idx), src2(_src2.idx), dest(_dest.idx), dataSize(_dataSize), spm(_spm) {} /* diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh index ec9cb52b3..309a2e6b7 100644 --- a/src/arch/x86/insts/microldstop.hh +++ b/src/arch/x86/insts/microldstop.hh @@ -93,20 +93,21 @@ namespace X86ISA LdStOp(ExtMachInst _machInst, const char * mnem, const char * _instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - uint8_t _scale, RegIndex _index, RegIndex _base, - uint64_t _disp, uint8_t _segment, - RegIndex _data, + uint8_t _scale, InstRegIndex _index, InstRegIndex _base, + uint64_t _disp, InstRegIndex _segment, + InstRegIndex _data, uint8_t _dataSize, uint8_t _addressSize, Request::FlagsType _memFlags, OpClass __opClass) : X86MicroopBase(machInst, mnem, _instMnem, isMicro, isDelayed, isFirst, isLast, __opClass), - scale(_scale), index(_index), base(_base), - disp(_disp), segment(_segment), - data(_data), + scale(_scale), index(_index.idx), base(_base.idx), + disp(_disp), segment(_segment.idx), + data(_data.idx), dataSize(_dataSize), addressSize(_addressSize), - memFlags(_memFlags | _segment) + memFlags(_memFlags | _segment.idx) { + assert(_segment.idx < NUM_SEGMENTREGS); foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0; foldABit = (addressSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0; diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh index d805adb33..16e1afc0a 100644 --- a/src/arch/x86/insts/microregop.hh +++ b/src/arch/x86/insts/microregop.hh @@ -79,13 +79,13 @@ namespace X86ISA const char *mnem, const char *_instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _src1, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext, OpClass __opClass) : X86MicroopBase(_machInst, mnem, _instMnem, isMicro, isDelayed, isFirst, isLast, __opClass), - src1(_src1), dest(_dest), + src1(_src1.idx), dest(_dest.idx), dataSize(_dataSize), ext(_ext) { foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0; @@ -107,14 +107,14 @@ namespace X86ISA const char *mnem, const char *_instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _src1, RegIndex _src2, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext, OpClass __opClass) : RegOpBase(_machInst, mnem, _instMnem, isMicro, isDelayed, isFirst, isLast, _src1, _dest, _dataSize, _ext, __opClass), - src2(_src2) + src2(_src2.idx) { } @@ -132,7 +132,7 @@ namespace X86ISA const char * mnem, const char *_instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _src1, uint8_t _imm8, RegIndex _dest, + InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext, OpClass __opClass) : RegOpBase(_machInst, mnem, _instMnem, diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh index 8480f2713..4ca7a4984 100644 --- a/src/arch/x86/insts/static_inst.hh +++ b/src/arch/x86/insts/static_inst.hh @@ -64,6 +64,18 @@ namespace X86ISA { /** + * Class for register indices passed to instruction constructors. Using a + * wrapper struct for these lets take advantage of the compiler's type + * checking. + */ + struct InstRegIndex + { + RegIndex idx; + explicit InstRegIndex(RegIndex _idx) : idx(_idx) + {} + }; + + /** * Base class for all X86 static instructions. */ diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 3ac9cd4f9..78046c0c8 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -109,6 +109,8 @@ output header {{ #include "cpu/static_inst.hh" #include "mem/packet.hh" #include "sim/faults.hh" + +using X86ISA::InstRegIndex; }}; output decoder {{ diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py index 22364e038..da10d8478 100644 --- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py @@ -84,7 +84,7 @@ microcode = ''' def macroop BSR_R_R { # Determine if the input was zero, and also move it to a temp reg. - movi t1, t1, t0, dataSize=8 + mov t1, t1, t0, dataSize=8 and t1, regm, regm, flags=(ZF,) br label("end"), flags=(CZF,) @@ -132,7 +132,7 @@ end: def macroop BSR_R_M { - movi t1, t1, t0, dataSize=8 + mov t1, t1, t0, dataSize=8 ld t1, seg, sib, disp # Determine if the input was zero, and also move it to a temp reg. @@ -184,7 +184,7 @@ end: def macroop BSR_R_P { rdip t7 - movi t1, t1, t0, dataSize=8 + mov t1, t1, t0, dataSize=8 ld t1, seg, riprel, disp # Determine if the input was zero, and also move it to a temp reg. diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py index 358fe43c8..a9ad611b7 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py @@ -143,7 +143,7 @@ processCSDescriptor: # appropriate/other RIP checks. # if temp_RIP > CS.limit throw #GP(0) rdlimit t6, cs, dataSize=8 - subi t0, t1, t6, flags=(ECF,) + sub t0, t1, t6, flags=(ECF,) fault "new GeneralProtection(0)", flags=(CECF,) #(temp_CPL!=CPL) diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py index 4f0cdf770..461861b0d 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py @@ -118,7 +118,7 @@ def macroop JMP_FAR_I limm t2, imm, dataSize=8 # Figure out the width of the offset. limm t3, dsz, dataSize=8 - sll t3, t3, 3, dataSize=8 + slli t3, t3, 3, dataSize=8 # Get the selector into t1. sll t1, t2, t3, dataSize=8 mov t1, t0, t1, dataSize=2 @@ -178,7 +178,7 @@ def macroop JMP_FAR_REAL_I limm t2, imm, dataSize=8 # Figure out the width of the offset. limm t3, dsz, dataSize=8 - sll t3, t3, 3, dataSize=8 + slli t3, t3, 3, dataSize=8 # Get the selector into t1. sll t1, t2, t3, dataSize=8 mov t1, t0, t1, dataSize=2 diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py index 82fdffc63..f4c8a4663 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py @@ -163,7 +163,7 @@ def macroop ENTER_I_I { # Pull the different components out of the immediate limm t1, imm zexti t2, t1, 15, dataSize=8 - srl t1, t1, 16 + srli t1, t1, 16 zexti t1, t1, 5, dataSize=8 # t1 is now the masked nesting level, and t2 is the amount of storage. @@ -174,7 +174,7 @@ def macroop ENTER_I_I { mov t6, t6, rsp, dataSize=asz # If the nesting level is zero, skip all this stuff. - subi t0, t1, t0, flags=(EZF,), dataSize=2 + sub t0, t1, t0, flags=(EZF,), dataSize=2 br label("skipLoop"), flags=(CEZF,) # If the level was 1, only push the saved rbp diff --git a/src/arch/x86/isa/insts/general_purpose/system_calls.py b/src/arch/x86/isa/insts/general_purpose/system_calls.py index 9501116d9..31184eae7 100644 --- a/src/arch/x86/isa/insts/general_purpose/system_calls.py +++ b/src/arch/x86/isa/insts/general_purpose/system_calls.py @@ -65,7 +65,7 @@ def macroop SYSCALL_64 # Stick rflags with RF masked into r11. rflags t2 limm t3, "~RFBit", dataSize=8 - andi r11, t2, t3, dataSize=8 + and r11, t2, t3, dataSize=8 rdval t3, star srli t3, t3, 32, dataSize=8 @@ -118,7 +118,7 @@ def macroop SYSCALL_COMPAT # Stick rflags with RF masked into r11. rflags t2 limm t3, "~RFBit", dataSize=8 - andi r11, t2, t3, dataSize=8 + and r11, t2, t3, dataSize=8 rdval t3, star srli t3, t3, 32, dataSize=8 diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py index 82811bb07..da105e411 100644 --- a/src/arch/x86/isa/insts/system/control_registers.py +++ b/src/arch/x86/isa/insts/system/control_registers.py @@ -28,58 +28,58 @@ microcode = ''' def macroop CLTS { - rdcr t1, 0, dataSize=8 + rdcr t1, regIdx(0), dataSize=8 andi t1, t1, 0xF7, dataSize=1 - wrcr 0, t1, dataSize=8 + wrcr regIdx(0), t1, dataSize=8 }; def macroop LMSW_R { - rdcr t1, 0, dataSize=8 + rdcr t1, regIdx(0), dataSize=8 # This logic sets MP, EM, and TS to whatever is in the operand. It will # set PE but not clear it. limm t2, "~ULL(0xe)", dataSize=8 and t1, t1, t2, dataSize=8 andi t2, reg, 0xf, dataSize=8 or t1, t1, t2, dataSize=8 - wrcr 0, t1, dataSize=8 + wrcr regIdx(0), t1, dataSize=8 }; def macroop LMSW_M { ld t3, seg, sib, disp, dataSize=2 - rdcr t1, 0, dataSize=8 + rdcr t1, regIdx(0), dataSize=8 # This logic sets MP, EM, and TS to whatever is in the operand. It will # set PE but not clear it. limm t2, "~ULL(0xe)", dataSize=8 and t1, t1, t2, dataSize=8 andi t2, t3, 0xf, dataSize=8 or t1, t1, t2, dataSize=8 - wrcr 0, t1, dataSize=8 + wrcr regIdx(0), t1, dataSize=8 }; def macroop LMSW_P { rdip t7, dataSize=asz ld t3, seg, riprel, disp, dataSize=2 - rdcr t1, 0, dataSize=8 + rdcr t1, regIdx(0), dataSize=8 # This logic sets MP, EM, and TS to whatever is in the operand. It will # set PE but not clear it. limm t2, "~ULL(0xe)", dataSize=8 and t1, t1, t2, dataSize=8 andi t2, t3, 0xf, dataSize=8 or t1, t1, t2, dataSize=8 - wrcr 0, t1, dataSize=8 + wrcr regIdx(0), t1, dataSize=8 }; def macroop SMSW_R { - rdcr reg, 0 + rdcr reg, regIdx(0) }; def macroop SMSW_M { - rdcr t1, 0 + rdcr t1, regIdx(0) st t1, seg, sib, disp, dataSize=2 }; def macroop SMSW_P { - rdcr t1, 0 + rdcr t1, regIdx(0) rdip t7, dataSize=asz st t1, seg, riprel, disp, dataSize=2 }; diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index c7c6dae2e..0cc72bf7b 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -75,14 +75,22 @@ let {{ from micro_asm import MicroAssembler, Rom_Macroop mainRom = X86MicrocodeRom('main ROM') assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop) + + def regIdx(idx): + return "InstRegIndex(%s)" % idx + + assembler.symbols["regIdx"] = regIdx + # Add in symbols for the microcode registers for num in range(16): - assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num + assembler.symbols["t%d" % num] = regIdx("NUM_INTREGS+%d" % num) for num in range(8): - assembler.symbols["ufp%d" % num] = "FLOATREG_MICROFP(%d)" % num + assembler.symbols["ufp%d" % num] = \ + regIdx("FLOATREG_MICROFP(%d)" % num) # Add in symbols for the segment descriptor registers for letter in ("C", "D", "E", "F", "G", "H", "S"): - assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter + assembler.symbols["%ss" % letter.lower()] = \ + regIdx("SEGMENT_REG_%sS" % letter) # Add in symbols for the various checks of segment selectors. for check in ("NoCheck", "CSCheck", "CallGateCheck", "IntGateCheck", @@ -91,25 +99,25 @@ let {{ assembler.symbols[check] = "Seg%s" % check for reg in ("TR", "IDTR"): - assembler.symbols[reg.lower()] = "SYS_SEGMENT_REG_%s" % reg + assembler.symbols[reg.lower()] = regIdx("SYS_SEGMENT_REG_%s" % reg) for reg in ("TSL", "TSG"): - assembler.symbols[reg.lower()] = "SEGMENT_REG_%s" % reg + assembler.symbols[reg.lower()] = regIdx("SEGMENT_REG_%s" % reg) # Miscellaneous symbols symbols = { - "reg" : "env.reg", - "xmml" : "FLOATREG_XMM_LOW(env.reg)", - "xmmh" : "FLOATREG_XMM_HIGH(env.reg)", - "regm" : "env.regm", - "xmmlm" : "FLOATREG_XMM_LOW(env.regm)", - "xmmhm" : "FLOATREG_XMM_HIGH(env.regm)", + "reg" : regIdx("env.reg"), + "xmml" : regIdx("FLOATREG_XMM_LOW(env.reg)"), + "xmmh" : regIdx("FLOATREG_XMM_HIGH(env.reg)"), + "regm" : regIdx("env.regm"), + "xmmlm" : regIdx("FLOATREG_XMM_LOW(env.regm)"), + "xmmhm" : regIdx("FLOATREG_XMM_HIGH(env.regm)"), "imm" : "adjustedImm", "disp" : "adjustedDisp", - "seg" : "env.seg", + "seg" : regIdx("env.seg"), "scale" : "env.scale", - "index" : "env.index", - "base" : "env.base", + "index" : regIdx("env.index"), + "base" : regIdx("env.base"), "dsz" : "env.dataSize", "asz" : "env.addressSize", "ssz" : "env.stackSize" @@ -133,17 +141,18 @@ let {{ # This segment selects an internal address space mapped to MSRs, # CPUID info, etc. - assembler.symbols["intseg"] = "SEGMENT_REG_MS" + assembler.symbols["intseg"] = regIdx("SEGMENT_REG_MS") # This segment always has base 0, and doesn't imply any special handling # like the internal segment above - assembler.symbols["flatseg"] = "SEGMENT_REG_LS" + assembler.symbols["flatseg"] = regIdx("SEGMENT_REG_LS") for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di', \ '8', '9', '10', '11', '12', '13', '14', '15'): - assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() + assembler.symbols["r%s" % reg] = \ + regIdx("INTREG_R%s" % reg.upper()) for reg in range(16): - assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg + assembler.symbols["cr%d" % reg] = regIdx("MISCREG_CR%d" % reg) for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF', \ 'TF', 'IF', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'): @@ -164,7 +173,7 @@ let {{ for reg in ('sysenter_cs', 'sysenter_esp', 'sysenter_eip', 'star', 'lstar', 'cstar', 'sf_mask', 'kernel_gs_base'): - assembler.symbols[reg] = "MISCREG_%s" % reg.upper() + assembler.symbols[reg] = regIdx("MISCREG_%s" % reg.upper()) # Code literal which forces a default 64 bit operand size in 64 bit mode. assembler.symbols["oszIn64Override"] = ''' @@ -201,7 +210,7 @@ let {{ assembler.symbols["rom_local_label"] = rom_local_labeler def stack_index(index): - return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index + return regIdx("NUM_FLOATREGS + (((%s) + 8) %% 8)" % index) assembler.symbols["st"] = stack_index diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index f1007bf71..8541df831 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -86,7 +86,7 @@ let {{ const EmulEnv &env = macroop ? macroop->getEmulEnv() : dummyEmulEnv; // env may not be used in the microop's constructor. - RegIndex reg = env.reg; + InstRegIndex reg(env.reg); reg = reg; using namespace RomLabels; return %s; diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index d4acfdbf4..e49bd8a20 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -99,12 +99,12 @@ def template MicroFpOpDeclare {{ %(class_name)s(ExtMachInst _machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _src1, RegIndex _src2, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, int8_t _spm); %(class_name)s(ExtMachInst _machInst, const char * instMnem, - RegIndex _src1, RegIndex _src2, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, int8_t _spm); %(BasicExecDeclare)s @@ -120,7 +120,7 @@ def template MicroFpOpConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, - RegIndex _src1, RegIndex _src2, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, int8_t _spm) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, false, false, false, false, @@ -133,7 +133,7 @@ def template MicroFpOpConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _src1, RegIndex _src2, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, int8_t _spm) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, isMicro, isDelayed, isFirst, isLast, @@ -256,9 +256,9 @@ let {{ "spm" : self.spm} class Movfp(FpOp): - def __init__(self, dest, src1, flags=0, spm=0, \ + def __init__(self, dest, src1, spm=0, \ SetStatus=False, dataSize="env.dataSize"): - super(Movfp, self).__init__(dest, src1, flags, \ + super(Movfp, self).__init__(dest, src1, "InstRegIndex(0)", \ spm, SetStatus, dataSize) code = 'FpDestReg.uqw = FpSrcReg1.uqw;' else_code = 'FpDestReg.uqw = FpDestReg.uqw;' @@ -274,7 +274,8 @@ let {{ class ConvOp(FpOp): abstract = True def __init__(self, dest, src1): - super(ConvOp, self).__init__(dest, src1, "(int)FLOATREG_MICROFP0") + super(ConvOp, self).__init__(dest, src1, \ + "InstRegIndex(FLOATREG_MICROFP0)") # These probably shouldn't look at the ExtMachInst directly to figure # out what size to use and should instead delegate that to the macroop's @@ -318,7 +319,7 @@ let {{ class Compfp(FpOp): def __init__(self, src1, src2, spm=0, setStatus=False, \ dataSize="env.dataSize"): - super(Compfp, self).__init__("(int)FLOATREG_MICROFP0", \ + super(Compfp, self).__init__("InstRegIndex(FLOATREG_MICROFP0)", \ src1, src2, spm, setStatus, dataSize) # This class sets the condition codes in rflags according to the # rules for comparing floating point. diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index c4c57a954..94c707f73 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -121,17 +121,17 @@ def template MicroLeaDeclare {{ %(class_name)s(ExtMachInst _machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - uint8_t _scale, RegIndex _index, RegIndex _base, - uint64_t _disp, uint8_t _segment, - RegIndex _data, + uint8_t _scale, InstRegIndex _index, InstRegIndex _base, + uint64_t _disp, InstRegIndex _segment, + InstRegIndex _data, uint8_t _dataSize, uint8_t _addressSize, Request::FlagsType _memFlags); %(class_name)s(ExtMachInst _machInst, const char * instMnem, - uint8_t _scale, RegIndex _index, RegIndex _base, - uint64_t _disp, uint8_t _segment, - RegIndex _data, + uint8_t _scale, InstRegIndex _index, InstRegIndex _base, + uint64_t _disp, InstRegIndex _segment, + InstRegIndex _data, uint8_t _dataSize, uint8_t _addressSize, Request::FlagsType _memFlags); @@ -297,17 +297,17 @@ def template MicroLdStOpDeclare {{ %(class_name)s(ExtMachInst _machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - uint8_t _scale, RegIndex _index, RegIndex _base, - uint64_t _disp, uint8_t _segment, - RegIndex _data, + uint8_t _scale, InstRegIndex _index, InstRegIndex _base, + uint64_t _disp, InstRegIndex _segment, + InstRegIndex _data, uint8_t _dataSize, uint8_t _addressSize, Request::FlagsType _memFlags); %(class_name)s(ExtMachInst _machInst, const char * instMnem, - uint8_t _scale, RegIndex _index, RegIndex _base, - uint64_t _disp, uint8_t _segment, - RegIndex _data, + uint8_t _scale, InstRegIndex _index, InstRegIndex _base, + uint64_t _disp, InstRegIndex _segment, + InstRegIndex _data, uint8_t _dataSize, uint8_t _addressSize, Request::FlagsType _memFlags); @@ -328,9 +328,9 @@ def template MicroLdStOpConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, - uint8_t _scale, RegIndex _index, RegIndex _base, - uint64_t _disp, uint8_t _segment, - RegIndex _data, + uint8_t _scale, InstRegIndex _index, InstRegIndex _base, + uint64_t _disp, InstRegIndex _segment, + InstRegIndex _data, uint8_t _dataSize, uint8_t _addressSize, Request::FlagsType _memFlags) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, @@ -345,9 +345,9 @@ def template MicroLdStOpConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - uint8_t _scale, RegIndex _index, RegIndex _base, - uint64_t _disp, uint8_t _segment, - RegIndex _data, + uint8_t _scale, InstRegIndex _index, InstRegIndex _base, + uint64_t _disp, InstRegIndex _segment, + InstRegIndex _data, uint8_t _dataSize, uint8_t _addressSize, Request::FlagsType _memFlags) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, @@ -517,7 +517,7 @@ let {{ def __init__(self, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize"): - super(TiaOp, self).__init__("NUM_INTREGS", segment, + super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, addr, disp, dataSize, addressSize, "0", False, False) self.className = "Tia" self.mnemonic = "tia" @@ -528,7 +528,7 @@ let {{ def __init__(self, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize", atCPL0=False): - super(CdaOp, self).__init__("NUM_INTREGS", segment, + super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, addr, disp, dataSize, addressSize, "0", atCPL0, False) self.className = "Cda" self.mnemonic = "cda" diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index 4e75ab8b0..f7e7728ab 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -88,11 +88,11 @@ def template MicroLimmOpDeclare {{ %(class_name)s(ExtMachInst _machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _dest, uint64_t _imm, uint8_t _dataSize); + InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize); %(class_name)s(ExtMachInst _machInst, const char * instMnem, - RegIndex _dest, uint64_t _imm, uint8_t _dataSize); + InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize); %(BasicExecDeclare)s }; @@ -122,10 +122,10 @@ def template MicroLimmOpConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, - RegIndex _dest, uint64_t _imm, uint8_t _dataSize) : + InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, false, false, false, false, %(op_class)s), - dest(_dest), imm(_imm), dataSize(_dataSize) + dest(_dest.idx), imm(_imm), dataSize(_dataSize) { buildMe(); } @@ -133,10 +133,10 @@ def template MicroLimmOpConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _dest, uint64_t _imm, uint8_t _dataSize) : + InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, isMicro, isDelayed, isFirst, isLast, %(op_class)s), - dest(_dest), imm(_imm), dataSize(_dataSize) + dest(_dest.idx), imm(_imm), dataSize(_dataSize) { buildMe(); } diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index dfa10587a..cabdc2172 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -126,12 +126,12 @@ def template MicroRegOpDeclare {{ %(class_name)s(ExtMachInst _machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _src1, RegIndex _src2, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext); %(class_name)s(ExtMachInst _machInst, const char * instMnem, - RegIndex _src1, RegIndex _src2, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext); %(BasicExecDeclare)s @@ -149,12 +149,12 @@ def template MicroRegOpImmDeclare {{ %(class_name)s(ExtMachInst _machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _src1, uint16_t _imm8, RegIndex _dest, + InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext); %(class_name)s(ExtMachInst _machInst, const char * instMnem, - RegIndex _src1, uint16_t _imm8, RegIndex _dest, + InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext); %(BasicExecDeclare)s @@ -170,7 +170,7 @@ def template MicroRegOpConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, - RegIndex _src1, RegIndex _src2, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, false, false, false, false, @@ -183,7 +183,7 @@ def template MicroRegOpConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _src1, RegIndex _src2, RegIndex _dest, + InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, isMicro, isDelayed, isFirst, isLast, @@ -203,7 +203,7 @@ def template MicroRegOpImmConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, - RegIndex _src1, uint16_t _imm8, RegIndex _dest, + InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, false, false, false, false, @@ -216,7 +216,7 @@ def template MicroRegOpImmConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - RegIndex _src1, uint16_t _imm8, RegIndex _dest, + InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, isMicro, isDelayed, isFirst, isLast, @@ -481,12 +481,14 @@ let {{ def __init__(self, dest, src1=None, dataSize="env.dataSize"): if not src1: src1 = dest - super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) + super(RdRegOp, self).__init__(dest, src1, \ + "InstRegIndex(NUM_INTREGS)", None, dataSize) class WrRegOp(RegOp): abstract = True def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): - super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) + super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ + src1, src2, flags, dataSize) class Add(FlagRegOp): code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' @@ -553,7 +555,8 @@ let {{ def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): if not src1: src1 = dest - super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize) + super(RdRegOp, self).__init__(dest, src1, \ + "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' flag_code = ''' if (ProdHi) @@ -885,7 +888,7 @@ let {{ def __init__(self, dest, imm, flags=None, \ dataSize="env.dataSize"): super(Ruflag, self).__init__(dest, \ - "NUM_INTREGS", imm, flags, dataSize) + "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) class Rflag(RegOp): code = ''' @@ -899,7 +902,7 @@ let {{ def __init__(self, dest, imm, flags=None, \ dataSize="env.dataSize"): super(Rflag, self).__init__(dest, \ - "NUM_INTREGS", imm, flags, dataSize) + "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) class Sext(RegOp): code = ''' @@ -926,7 +929,7 @@ let {{ class Rddr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Rddr, self).__init__(dest, \ - src1, "NUM_INTREGS", flags, dataSize) + src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = ''' CR4 cr4 = CR4Op; DR7 dr7 = DR7Op; @@ -942,14 +945,13 @@ let {{ class Wrdr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Wrdr, self).__init__(dest, \ - src1, "NUM_INTREGS", flags, dataSize) + src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = ''' CR4 cr4 = CR4Op; DR7 dr7 = DR7Op; if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { fault = new InvalidOpcode(); - } else if ((dest == 6 || dest == 7) && - bits(psrc1, 63, 32) && + } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && machInst.mode.mode == LongMode) { fault = new GeneralProtection(0); } else if (dr7.gd) { @@ -962,7 +964,7 @@ let {{ class Rdcr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Rdcr, self).__init__(dest, \ - src1, "NUM_INTREGS", flags, dataSize) + src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = ''' if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { fault = new InvalidOpcode(); @@ -974,7 +976,7 @@ let {{ class Wrcr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Wrcr, self).__init__(dest, \ - src1, "NUM_INTREGS", flags, dataSize) + src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = ''' if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { fault = new InvalidOpcode(); @@ -1028,7 +1030,7 @@ let {{ abstract = True def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(SegOp, self).__init__(dest, \ - src1, "NUM_INTREGS", flags, dataSize) + src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) class Wrbase(SegOp): code = ''' @@ -1072,16 +1074,16 @@ let {{ class Rdval(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): - super(Rdval, self).__init__(dest, \ - src1, "NUM_INTREGS", flags, dataSize) + super(Rdval, self).__init__(dest, src1, \ + "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = ''' DestReg = MiscRegSrc1; ''' class Wrval(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): - super(Wrval, self).__init__(dest, \ - src1, "NUM_INTREGS", flags, dataSize) + super(Wrval, self).__init__(dest, src1, \ + "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = ''' MiscRegDest = SrcReg1; ''' diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh index 106996848..2dc4587e3 100644 --- a/src/arch/x86/miscregs.hh +++ b/src/arch/x86/miscregs.hh @@ -165,8 +165,9 @@ namespace X86ISA MISCREG_MTRR_PHYS_BASE_5, MISCREG_MTRR_PHYS_BASE_6, MISCREG_MTRR_PHYS_BASE_7, + MISCREG_MTRR_PHYS_BASE_END, - MISCREG_MTRR_PHYS_MASK_BASE, + MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END, MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, MISCREG_MTRR_PHYS_MASK_1, MISCREG_MTRR_PHYS_MASK_2, @@ -175,8 +176,9 @@ namespace X86ISA MISCREG_MTRR_PHYS_MASK_5, MISCREG_MTRR_PHYS_MASK_6, MISCREG_MTRR_PHYS_MASK_7, + MISCREG_MTRR_PHYS_MASK_END, - MISCREG_MTRR_FIX_64K_00000, + MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, MISCREG_MTRR_FIX_16K_80000, MISCREG_MTRR_FIX_16K_A0000, MISCREG_MTRR_FIX_4K_C0000, @@ -201,8 +203,9 @@ namespace X86ISA MISCREG_MC5_CTL, MISCREG_MC6_CTL, MISCREG_MC7_CTL, + MISCREG_MC_CTL_END, - MISCREG_MC_STATUS_BASE, + MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, MISCREG_MC1_STATUS, MISCREG_MC2_STATUS, @@ -211,8 +214,9 @@ namespace X86ISA MISCREG_MC5_STATUS, MISCREG_MC6_STATUS, MISCREG_MC7_STATUS, + MISCREG_MC_STATUS_END, - MISCREG_MC_ADDR_BASE, + MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, MISCREG_MC1_ADDR, MISCREG_MC2_ADDR, @@ -221,8 +225,9 @@ namespace X86ISA MISCREG_MC5_ADDR, MISCREG_MC6_ADDR, MISCREG_MC7_ADDR, + MISCREG_MC_ADDR_END, - MISCREG_MC_MISC_BASE, + MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, MISCREG_MC1_MISC, MISCREG_MC2_MISC, @@ -231,9 +236,10 @@ namespace X86ISA MISCREG_MC5_MISC, MISCREG_MC6_MISC, MISCREG_MC7_MISC, + MISCREG_MC_MISC_END, // Extended feature enable register - MISCREG_EFER, + MISCREG_EFER = MISCREG_MC_MISC_END, MISCREG_STAR, MISCREG_LSTAR, @@ -250,24 +256,28 @@ namespace X86ISA MISCREG_PERF_EVT_SEL1, MISCREG_PERF_EVT_SEL2, MISCREG_PERF_EVT_SEL3, + MISCREG_PERF_EVT_SEL_END, - MISCREG_PERF_EVT_CTR_BASE, + MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END, MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, MISCREG_PERF_EVT_CTR1, MISCREG_PERF_EVT_CTR2, MISCREG_PERF_EVT_CTR3, + MISCREG_PERF_EVT_CTR_END, - MISCREG_SYSCFG, + MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, MISCREG_IORR_BASE_BASE, MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, MISCREG_IORR_BASE1, + MISCREG_IORR_BASE_END, - MISCREG_IORR_MASK_BASE, + MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, MISCREG_IORR_MASK1, + MISCREG_IORR_MASK_END, - MISCREG_TOP_MEM, + MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, MISCREG_TOP_MEM2, MISCREG_VM_CR, @@ -377,102 +387,129 @@ namespace X86ISA static inline MiscRegIndex MISCREG_CR(int index) { + assert(index >= 0 && index < NumCRegs); return (MiscRegIndex)(MISCREG_CR_BASE + index); } static inline MiscRegIndex MISCREG_DR(int index) { + assert(index >= 0 && index < NumDRegs); return (MiscRegIndex)(MISCREG_DR_BASE + index); } static inline MiscRegIndex MISCREG_MTRR_PHYS_BASE(int index) { + assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END - + MISCREG_MTRR_PHYS_BASE_BASE)); return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); } static inline MiscRegIndex MISCREG_MTRR_PHYS_MASK(int index) { + assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END - + MISCREG_MTRR_PHYS_MASK_BASE)); return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); } static inline MiscRegIndex MISCREG_MC_CTL(int index) { + assert(index >= 0 && index < (MISCREG_MC_CTL_END - + MISCREG_MC_CTL_BASE)); return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); } static inline MiscRegIndex MISCREG_MC_STATUS(int index) { + assert(index >= 0 && index < (MISCREG_MC_STATUS_END - + MISCREG_MC_STATUS_BASE)); return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); } static inline MiscRegIndex MISCREG_MC_ADDR(int index) { + assert(index >= 0 && index < (MISCREG_MC_ADDR_END - + MISCREG_MC_ADDR_BASE)); return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); } static inline MiscRegIndex MISCREG_MC_MISC(int index) { + assert(index >= 0 && index < (MISCREG_MC_MISC_END - + MISCREG_MC_MISC_BASE)); return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); } static inline MiscRegIndex MISCREG_PERF_EVT_SEL(int index) { + assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END - + MISCREG_PERF_EVT_SEL_BASE)); return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); } static inline MiscRegIndex MISCREG_PERF_EVT_CTR(int index) { + assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END - + MISCREG_PERF_EVT_CTR_BASE)); return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); } static inline MiscRegIndex MISCREG_IORR_BASE(int index) { + assert(index >= 0 && index < (MISCREG_IORR_BASE_END - + MISCREG_IORR_BASE_BASE)); return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); } static inline MiscRegIndex MISCREG_IORR_MASK(int index) { + assert(index >= 0 && index < (MISCREG_IORR_MASK_END - + MISCREG_IORR_MASK_BASE)); return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); } static inline MiscRegIndex MISCREG_SEG_SEL(int index) { + assert(index >= 0 && index < NUM_SEGMENTREGS); return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); } static inline MiscRegIndex MISCREG_SEG_BASE(int index) { + assert(index >= 0 && index < NUM_SEGMENTREGS); return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); } static inline MiscRegIndex MISCREG_SEG_EFF_BASE(int index) { + assert(index >= 0 && index < NUM_SEGMENTREGS); return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); } static inline MiscRegIndex MISCREG_SEG_LIMIT(int index) { + assert(index >= 0 && index < NUM_SEGMENTREGS); return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); } static inline MiscRegIndex MISCREG_SEG_ATTR(int index) { + assert(index >= 0 && index < NUM_SEGMENTREGS); return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); } diff --git a/src/mem/ruby/config/defaults.rb b/src/mem/ruby/config/defaults.rb index 9143cb21e..e54b148e0 100644 --- a/src/mem/ruby/config/defaults.rb +++ b/src/mem/ruby/config/defaults.rb @@ -146,7 +146,7 @@ class RubySystem # Random seed used by the simulation. If set to "rand", the seed # will be set to the current wall clock at libruby # initialization. Otherwise, set this to an integer. - default_param :random_seed, Object, "rand" + default_param :random_seed, Object, 1234 #"rand" # When set to true, the simulation will insert random delays on # message enqueue times. Note that even if this is set to false, diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index 0d6dc8795..f3de8638c 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -2,7 +2,7 @@ ================ Begin RubySystem Configuration Print ================ RubySystem config: - random_seed: 580633 + random_seed: 1234 randomization: 0 tech_nm: 45 freq_mhz: 3000 @@ -14,7 +14,7 @@ DMA_Controller config: DMAController_0 version: 0 buffer_size: 32 dma_sequencer: DMASequencer_0 - number_of_TBEs: 128 + number_of_TBEs: 256 transitions_per_cycle: 32 Directory_Controller config: DirectoryController_0 version: 0 @@ -23,7 +23,7 @@ Directory_Controller config: DirectoryController_0 directory_name: DirectoryMemory_0 memory_controller_name: MemoryControl_0 memory_latency: 158 - number_of_TBEs: 128 + number_of_TBEs: 256 recycle_latency: 10 to_mem_ctrl_latency: 1 transitions_per_cycle: 32 @@ -33,7 +33,7 @@ L1Cache_Controller config: L1CacheController_0 cache: l1u_0 cache_response_latency: 12 issue_latency: 2 - number_of_TBEs: 128 + number_of_TBEs: 256 sequencer: Sequencer_0 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_1 @@ -42,7 +42,7 @@ L1Cache_Controller config: L1CacheController_1 cache: l1u_1 cache_response_latency: 12 issue_latency: 2 - number_of_TBEs: 128 + number_of_TBEs: 256 sequencer: Sequencer_1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_2 @@ -51,7 +51,7 @@ L1Cache_Controller config: L1CacheController_2 cache: l1u_2 cache_response_latency: 12 issue_latency: 2 - number_of_TBEs: 128 + number_of_TBEs: 256 sequencer: Sequencer_2 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_3 @@ -60,7 +60,7 @@ L1Cache_Controller config: L1CacheController_3 cache: l1u_3 cache_response_latency: 12 issue_latency: 2 - number_of_TBEs: 128 + number_of_TBEs: 256 sequencer: Sequencer_3 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_4 @@ -69,7 +69,7 @@ L1Cache_Controller config: L1CacheController_4 cache: l1u_4 cache_response_latency: 12 issue_latency: 2 - number_of_TBEs: 128 + number_of_TBEs: 256 sequencer: Sequencer_4 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_5 @@ -78,7 +78,7 @@ L1Cache_Controller config: L1CacheController_5 cache: l1u_5 cache_response_latency: 12 issue_latency: 2 - number_of_TBEs: 128 + number_of_TBEs: 256 sequencer: Sequencer_5 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_6 @@ -87,7 +87,7 @@ L1Cache_Controller config: L1CacheController_6 cache: l1u_6 cache_response_latency: 12 issue_latency: 2 - number_of_TBEs: 128 + number_of_TBEs: 256 sequencer: Sequencer_6 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_7 @@ -96,7 +96,7 @@ L1Cache_Controller config: L1CacheController_7 cache: l1u_7 cache_response_latency: 12 issue_latency: 2 - number_of_TBEs: 128 + number_of_TBEs: 256 sequencer: Sequencer_7 transitions_per_cycle: 32 Cache config: l1u_0 @@ -376,27 +376,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/06/2009 11:20:36 +Real time: Jul/13/2009 11:35:28 Profiler Stats -------------- -Elapsed_time_in_seconds: 569 -Elapsed_time_in_minutes: 9.48333 -Elapsed_time_in_hours: 0.158056 -Elapsed_time_in_days: 0.00658565 +Elapsed_time_in_seconds: 2022 +Elapsed_time_in_minutes: 33.7 +Elapsed_time_in_hours: 0.561667 +Elapsed_time_in_days: 0.0234028 -Virtual_time_in_seconds: 568.45 -Virtual_time_in_minutes: 9.47417 -Virtual_time_in_hours: 0.157903 -Virtual_time_in_days: 0.157903 +Virtual_time_in_seconds: 2021.58 +Virtual_time_in_minutes: 33.693 +Virtual_time_in_hours: 0.56155 +Virtual_time_in_days: 0.56155 -Ruby_current_time: 31772572 +Ruby_current_time: 31820151 Ruby_start_time: 1 -Ruby_cycles: 31772571 +Ruby_cycles: 31820150 -mbytes_resident: 152.301 -mbytes_total: 1465.35 -resident_ratio: 0.103937 +mbytes_resident: 150.715 +mbytes_total: 1502.57 +resident_ratio: 0.10031 Total_misses: 0 total_misses: 0 [ 0 0 0 0 0 0 0 0 ] @@ -404,8 +404,8 @@ user_misses: 0 [ 0 0 0 0 0 0 0 0 ] supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ] instruction_executed: 8 [ 1 1 1 1 1 1 1 1 ] -ruby_cycles_executed: 254180576 [ 31772572 31772572 31772572 31772572 31772572 31772572 31772572 31772572 ] -cycles_per_instruction: 3.17726e+07 [ 3.17726e+07 3.17726e+07 3.17726e+07 3.17726e+07 3.17726e+07 3.17726e+07 3.17726e+07 3.17726e+07 ] +ruby_cycles_executed: 254561208 [ 31820151 31820151 31820151 31820151 31820151 31820151 31820151 31820151 ] +cycles_per_instruction: 3.18202e+07 [ 3.18202e+07 3.18202e+07 3.18202e+07 3.18202e+07 3.18202e+07 3.18202e+07 3.18202e+07 3.18202e+07 ] misses_per_thousand_instructions: 0 [ 0 0 0 0 0 0 0 0 ] transactions_started: 0 [ 0 0 0 0 0 0 0 0 ] @@ -452,27 +452,27 @@ L2_cache cache stats: Memory control: - memory_total_requests: 1386652 - memory_reads: 693391 - memory_writes: 693137 - memory_refreshes: 66193 - memory_total_request_delays: 425383597 - memory_delays_per_request: 306.77 - memory_delays_in_input_queue: 87505480 - memory_delays_behind_head_of_bank_queue: 257647415 - memory_delays_stalled_at_head_of_bank_queue: 80230702 - memory_stalls_for_bank_busy: 12120239 + memory_total_requests: 1388715 + memory_reads: 694429 + memory_writes: 694183 + memory_refreshes: 66292 + memory_total_request_delays: 425693933 + memory_delays_per_request: 306.538 + memory_delays_in_input_queue: 88373140 + memory_delays_behind_head_of_bank_queue: 256981406 + memory_delays_stalled_at_head_of_bank_queue: 80339387 + memory_stalls_for_bank_busy: 12139365 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 24602446 - memory_stalls_for_arbitration: 15581979 - memory_stalls_for_bus: 20484518 + memory_stalls_for_anti_starvation: 24629486 + memory_stalls_for_arbitration: 15620225 + memory_stalls_for_bus: 20514147 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 5997915 - memory_stalls_for_read_read_turnaround: 1443605 - accesses_per_bank: 43227 43770 43588 43651 43802 43745 43711 43760 43603 43212 43434 43102 43434 43422 43256 43302 43196 43303 43310 43252 43452 42855 43145 43038 43112 43034 43388 42984 43208 43144 43317 42895 + memory_stalls_for_read_write_turnaround: 5993792 + memory_stalls_for_read_read_turnaround: 1442372 + accesses_per_bank: 43402 43980 43964 43739 43710 43747 43506 43532 43547 43624 43342 43416 43254 43432 43341 43250 43106 42949 43234 43065 43413 43176 43043 43299 43329 43484 43093 43217 43454 43098 43443 43526 Busy Controller Counts: -L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:1 L1Cache-7:0 +L1Cache-0:1 L1Cache-1:0 L1Cache-2:0 L1Cache-3:1 L1Cache-4:0 L1Cache-5:1 L1Cache-6:0 L1Cache-7:1 Directory-0:0 DMA-0:0 @@ -480,17 +480,17 @@ DMA-0:0 Busy Bank Count:0 L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -L2TBE_usage: [binsize: 1 max: 41 count: 1440815 average: 18.4457 | standard deviation: 7.12583 | 1873 4135 6801 9875 13162 16875 21071 25498 30277 35703 41476 47234 53104 58918 64131 68752 72371 74737 75823 75450 74014 71134 67287 62894 58093 52984 47909 43558 39550 35395 30307 23965 16658 10087 5476 2567 1043 416 156 45 8 3 ] +L2TBE_usage: [binsize: 4 max: 138 count: 2136422 average: 36.2389 | standard deviation: 28.1349 | 22715 77616 157380 245532 298784 278507 205386 131825 40504 9739 11231 15799 21344 28483 36739 45490 53163 60852 65683 67036 63571 56722 46590 35450 25175 16208 9482 5035 2491 1142 469 171 72 29 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 747282 average: 11.806 | standard deviation: 3.40201 | 0 1002 2816 5419 9403 15581 23827 33488 44954 55155 63893 69711 72180 71798 69044 65458 143553 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 747605 average: 11.7824 | standard deviation: 3.40678 | 0 997 2734 5419 9667 16098 24151 33909 44874 55287 64490 70115 72444 71660 68466 64469 142825 ] store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 22580 count: 747194 average: 3867.5 | standard deviation: 2354.99 | 21535 1972 3656 6661 8836 8395 7586 8534 10272 11799 13885 13644 12134 13137 16118 17390 16320 16141 17180 16917 16977 18248 18899 16678 15870 17672 18251 16191 15742 16573 15646 14127 14576 15467 13603 12280 12802 13515 11634 10747 11479 11014 9459 9506 10097 9085 7694 7799 8370 7046 6434 6737 6821 5704 5328 5656 5336 4327 4234 4669 4050 3400 3449 3599 3052 2651 2644 2669 2175 1979 2103 1959 1494 1455 1602 1251 1058 1077 1030 938 720 788 720 592 502 555 506 395 375 403 344 261 248 239 215 218 216 188 132 135 144 129 88 96 97 81 52 65 67 53 37 50 40 25 32 30 27 32 24 17 17 10 19 18 11 11 8 9 11 7 11 8 6 4 8 6 3 5 8 7 1 2 3 0 0 3 1 1 2 5 1 1 2 2 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 128 max: 20316 count: 486115 average: 3867.51 | standard deviation: 2355.78 | 14004 1287 2374 4317 5819 5471 4963 5567 6673 7691 8934 8760 7806 8555 10555 11280 10582 10542 11223 11065 11078 11885 12461 10861 10313 11551 11930 10376 10304 10686 10209 9162 9418 10103 8902 7919 8357 8800 7489 7050 7485 7179 6147 6192 6463 5897 5070 5055 5439 4577 4161 4371 4428 3725 3371 3684 3521 2835 2775 3058 2629 2240 2274 2312 1994 1706 1702 1739 1448 1269 1368 1264 970 952 1052 776 699 693 656 628 483 508 459 376 332 368 327 249 247 263 228 172 165 165 137 150 144 117 80 93 93 87 64 62 58 50 33 37 50 39 27 32 26 13 24 22 18 21 20 11 10 8 15 13 4 7 6 5 9 4 8 5 2 3 3 2 2 4 6 5 1 1 0 0 0 2 1 1 2 4 0 1 1 2 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 128 max: 22580 count: 261079 average: 3867.49 | standard deviation: 2353.54 | 7531 685 1282 2344 3017 2924 2623 2967 3599 4108 4951 4884 4328 4582 5563 6110 5738 5599 5957 5852 5899 6363 6438 5817 5557 6121 6321 5815 5438 5887 5437 4965 5158 5364 4701 4361 4445 4715 4145 3697 3994 3835 3312 3314 3634 3188 2624 2744 2931 2469 2273 2366 2393 1979 1957 1972 1815 1492 1459 1611 1421 1160 1175 1287 1058 945 942 930 727 710 735 695 524 503 550 475 359 384 374 310 237 280 261 216 170 187 179 146 128 140 116 89 83 74 78 68 72 71 52 42 51 42 24 34 39 31 19 28 17 14 10 18 14 12 8 8 9 11 4 6 7 2 4 5 7 4 2 4 2 3 3 3 4 1 5 4 1 1 2 2 0 1 3 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 20830 count: 747528 average: 3863.27 | standard deviation: 2352.2 | 21197 1955 3662 6575 8813 8466 7701 8621 10114 11916 13705 13785 12268 13061 16083 17253 16187 16362 17426 17486 17061 18610 19198 16898 15842 17763 18373 16107 15849 16696 15292 13911 14597 15479 13585 11985 12812 13601 11408 10656 11428 10946 9456 9397 9955 9349 7687 8042 8461 7253 6426 6656 6870 5596 5078 5702 5311 4329 4222 4357 4026 3301 3344 3639 2991 2681 2723 2690 2146 1949 2075 1944 1561 1439 1490 1277 1090 1076 1107 889 733 862 724 613 514 543 494 370 351 377 357 283 268 267 209 179 175 209 158 130 155 108 86 75 90 81 51 69 45 48 52 44 45 41 24 34 36 25 24 25 23 22 18 11 11 15 10 11 9 11 10 10 12 14 6 5 5 3 4 2 2 1 0 3 1 3 0 1 3 0 2 0 3 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 128 max: 20500 count: 485823 average: 3861.58 | standard deviation: 2351.5 | 13803 1269 2389 4255 5726 5414 5043 5609 6667 7717 8866 8913 7980 8569 10484 11191 10527 10646 11361 11421 11081 12192 12531 10960 10325 11558 11878 10584 10224 10716 9989 9010 9440 10102 8765 7759 8324 8806 7395 6843 7441 7190 6180 6082 6482 6098 5072 5224 5537 4711 4121 4343 4393 3630 3273 3660 3469 2812 2734 2825 2660 2125 2150 2328 1950 1773 1783 1766 1382 1289 1318 1248 994 946 961 846 730 719 747 605 453 544 463 398 333 331 302 252 222 246 235 182 168 169 148 122 112 138 102 78 101 65 53 55 51 53 37 44 24 35 37 25 29 23 16 20 22 15 17 19 13 11 13 8 8 12 4 7 7 10 6 8 7 9 2 3 3 3 4 1 2 1 0 3 1 2 0 0 2 0 1 0 2 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 128 max: 20830 count: 261705 average: 3866.39 | standard deviation: 2353.52 | 7394 686 1273 2320 3087 3052 2658 3012 3447 4199 4839 4872 4288 4492 5599 6062 5660 5716 6065 6065 5980 6418 6667 5938 5517 6205 6495 5523 5625 5980 5303 4901 5157 5377 4820 4226 4488 4795 4013 3813 3987 3756 3276 3315 3473 3251 2615 2818 2924 2542 2305 2313 2477 1966 1805 2042 1842 1517 1488 1532 1366 1176 1194 1311 1041 908 940 924 764 660 757 696 567 493 529 431 360 357 360 284 280 318 261 215 181 212 192 118 129 131 122 101 100 98 61 57 63 71 56 52 54 43 33 20 39 28 14 25 21 13 15 19 16 18 8 14 14 10 7 6 10 11 5 3 3 3 6 4 2 1 4 2 5 5 4 2 2 0 0 1 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle SW Prefetch Requests @@ -510,11 +510,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 28 count: 1494483 average: 0.00199668 | standard deviation: 0.174223 | 1494276 0 3 0 1 0 1 0 4 0 22 0 33 0 35 0 62 0 45 0 0 0 0 0 0 0 0 0 1 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 28 count: 1494483 average: 0.00199668 | standard deviation: 0.174223 | 1494276 0 3 0 1 0 1 0 4 0 22 0 33 0 35 0 62 0 45 0 0 0 0 0 0 0 0 0 1 ] +Total_delay_cycles: [binsize: 1 max: 28 count: 1495176 average: 0.00219238 | standard deviation: 0.181055 | 1494944 0 4 0 1 0 2 0 2 0 29 0 36 0 53 0 68 0 35 0 0 0 0 0 0 0 0 0 2 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 28 count: 1495176 average: 0.00219238 | standard deviation: 0.181055 | 1494944 0 4 0 1 0 2 0 2 0 29 0 36 0 53 0 68 0 35 0 0 0 0 0 0 0 0 0 2 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 747194 average: 0 | standard deviation: 0 | 747194 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 28 count: 747289 average: 0.0039931 | standard deviation: 0.246365 | 747082 0 3 0 1 0 1 0 4 0 22 0 33 0 35 0 62 0 45 0 0 0 0 0 0 0 0 0 1 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 747528 average: 0 | standard deviation: 0 | 747528 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 28 count: 747648 average: 0.00438442 | standard deviation: 0.256021 | 747416 0 4 0 1 0 2 0 2 0 29 0 36 0 53 0 68 0 35 0 0 0 0 0 0 0 0 0 2 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -522,123 +522,123 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 28 count: 1494483 average: 0.00199668 Resource Usage -------------- page_size: 4096 -user_time: 568 +user_time: 2020 system_time: 0 -page_reclaims: 39706 +page_reclaims: 39806 page_faults: 0 swaps: 0 -block_inputs: 8 -block_outputs: 152 +block_inputs: 0 +block_outputs: 0 Network Stats ------------- switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.018376 - links_utilized_percent_switch_0_link_0: 0.00734962 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.0294024 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.0183509 + links_utilized_percent_switch_0_link_0: 0.00733981 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.0293619 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 93403 747224 [ 0 93403 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 93410 747280 [ 0 0 93410 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 93415 747320 [ 93415 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 86732 693856 [ 86732 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 6691 53528 [ 0 6691 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 93420 747360 [ 0 93420 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 93423 747384 [ 0 0 93423 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 93427 747416 [ 93427 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 87006 696048 [ 87006 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 6427 51416 [ 0 6427 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0183719 - links_utilized_percent_switch_1_link_0: 0.00734816 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.0293956 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.018351 + links_utilized_percent_switch_1_link_0: 0.00733985 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.0293621 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 93382 747056 [ 0 93382 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 93394 747152 [ 0 0 93394 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 93392 747136 [ 93392 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Data: 86505 692040 [ 86505 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 6898 55184 [ 0 6898 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 93416 747328 [ 0 93416 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 93428 747424 [ 0 0 93428 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 93424 747392 [ 93424 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Data: 86798 694384 [ 86798 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 6639 53112 [ 0 6639 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.0183854 - links_utilized_percent_switch_2_link_0: 0.00735332 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.0294175 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.018354 + links_utilized_percent_switch_2_link_0: 0.00734114 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.0293669 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 93445 747560 [ 0 93445 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 93462 747696 [ 0 0 93462 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 93459 747672 [ 93459 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 86854 694832 [ 86854 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 6621 52968 [ 0 6621 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 93431 747448 [ 0 93431 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 93446 747568 [ 0 0 93446 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 93439 747512 [ 93439 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 86779 694232 [ 86779 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 6674 53392 [ 0 6674 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.0183732 - links_utilized_percent_switch_3_link_0: 0.00734887 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.0293975 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.0183589 + links_utilized_percent_switch_3_link_0: 0.00734326 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.0293746 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 93391 747128 [ 0 93391 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 93403 747224 [ 0 0 93403 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 93397 747176 [ 93397 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Data: 86604 692832 [ 86604 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 6806 54448 [ 0 6806 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 93455 747640 [ 0 93455 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 93476 747808 [ 0 0 93476 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 93460 747680 [ 93460 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Data: 86672 693376 [ 86672 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 6809 54472 [ 0 6809 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.0183723 - links_utilized_percent_switch_4_link_0: 0.00734871 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.0293958 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.0183551 + links_utilized_percent_switch_4_link_0: 0.00734142 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.0293688 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 93389 747112 [ 0 93389 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 93401 747208 [ 0 0 93401 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 93390 747120 [ 93390 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Data: 86681 693448 [ 86681 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 6725 53800 [ 0 6725 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 93432 747456 [ 0 93432 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 93452 747616 [ 0 0 93452 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 93443 747544 [ 93443 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Data: 86903 695224 [ 86903 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 6558 52464 [ 0 6558 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.0183691 - links_utilized_percent_switch_5_link_0: 0.00734702 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.0293912 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.0183621 + links_utilized_percent_switch_5_link_0: 0.0073446 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.0293797 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 93369 746952 [ 0 93369 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 93378 747024 [ 0 0 93378 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 93378 747024 [ 93378 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Data: 86787 694296 [ 86787 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 6602 52816 [ 0 6602 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 93473 747784 [ 0 93473 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 93492 747936 [ 0 0 93492 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 93479 747832 [ 93479 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Data: 86734 693872 [ 86734 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 6760 54080 [ 0 6760 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.0183742 - links_utilized_percent_switch_6_link_0: 0.00734918 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.0293993 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.0183551 + links_utilized_percent_switch_6_link_0: 0.00734146 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.0293688 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 93393 747144 [ 0 93393 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 93409 747272 [ 0 0 93409 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 93400 747200 [ 93400 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Data: 86807 694456 [ 86807 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 6611 52888 [ 0 6611 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 93437 747496 [ 0 93437 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 93448 747584 [ 0 0 93448 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 93447 747576 [ 93447 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Data: 86886 695088 [ 86886 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 6571 52568 [ 0 6571 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.0183789 - links_utilized_percent_switch_7_link_0: 0.00735123 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.0294067 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.0183603 + links_utilized_percent_switch_7_link_0: 0.00734389 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.0293767 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 93422 747376 [ 0 93422 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 93432 747456 [ 0 0 93432 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 93426 747408 [ 93426 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Data: 86588 692704 [ 86588 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 6851 54808 [ 0 6851 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 93464 747712 [ 0 93464 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 93483 747864 [ 0 0 93483 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 93469 747752 [ 93469 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Data: 86818 694544 [ 86818 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 6667 53336 [ 0 6667 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.141701 - links_utilized_percent_switch_8_link_0: 0.0566845 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.226717 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.141626 + links_utilized_percent_switch_8_link_0: 0.0566537 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.226597 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 747255 5978040 [ 747255 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Data: 693556 5548448 [ 693556 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 693389 5547112 [ 0 693389 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 747289 5978312 [ 0 0 747289 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 747588 5980704 [ 747588 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Data: 694596 5556768 [ 694596 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 694424 5555392 [ 0 694424 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 747648 5981184 [ 0 0 747648 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 @@ -649,36 +649,36 @@ links_utilized_percent_switch_9: 0 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.0461923 - links_utilized_percent_switch_10_link_0: 0.0293985 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.0293926 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.0294133 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.0293955 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.0293949 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.0293881 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.0293967 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.0294049 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.226738 bw: 160000 base_latency: 1 +links_utilized_percent_switch_10: 0.0461557 + links_utilized_percent_switch_10_link_0: 0.0293592 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.0293595 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.0293646 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.0293731 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.0293657 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.0293784 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.0293658 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.0293756 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 0.226615 bw: 160000 base_latency: 1 links_utilized_percent_switch_10_link_9: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 93403 747224 [ 0 93403 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Writeback_Control: 93410 747280 [ 0 0 93410 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 93382 747056 [ 0 93382 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Writeback_Control: 93394 747152 [ 0 0 93394 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 93445 747560 [ 0 93445 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Writeback_Control: 93462 747696 [ 0 0 93462 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 93391 747128 [ 0 93391 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Writeback_Control: 93403 747224 [ 0 0 93403 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 93389 747112 [ 0 93389 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Writeback_Control: 93401 747208 [ 0 0 93401 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 93369 746952 [ 0 93369 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Writeback_Control: 93378 747024 [ 0 0 93378 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 93393 747144 [ 0 93393 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Writeback_Control: 93409 747272 [ 0 0 93409 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 93422 747376 [ 0 93422 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Writeback_Control: 93432 747456 [ 0 0 93432 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 747256 5978048 [ 747256 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Data: 693557 5548456 [ 693557 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 93420 747360 [ 0 93420 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Control: 93423 747384 [ 0 0 93423 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 93417 747336 [ 0 93417 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Writeback_Control: 93428 747424 [ 0 0 93428 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 93431 747448 [ 0 93431 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Writeback_Control: 93446 747568 [ 0 0 93446 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 93455 747640 [ 0 93455 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Writeback_Control: 93476 747808 [ 0 0 93476 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 93432 747456 [ 0 93432 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Writeback_Control: 93452 747616 [ 0 0 93452 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 93473 747784 [ 0 93473 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Writeback_Control: 93492 747936 [ 0 0 93492 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 93437 747496 [ 0 93437 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Writeback_Control: 93448 747584 [ 0 0 93448 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 93464 747712 [ 0 93464 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Writeback_Control: 93483 747864 [ 0 0 93483 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Control: 747588 5980704 [ 747588 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Data: 694596 5556768 [ 694596 0 0 0 0 0 ] base_latency: 1 --- DMA --- - Event Counts - @@ -697,24 +697,24 @@ BUSY_WR Ack 0 <-- --- Directory --- - Event Counts - -GETX 7346943 +GETX 7271682 GETS 0 -PUTX 693205 -PUTX_NotOwner 351 +PUTX 694236 +PUTX_NotOwner 360 DMA_READ 0 DMA_WRITE 0 -Memory_Data 693390 -Memory_Ack 693133 +Memory_Data 694424 +Memory_Ack 694183 - Transitions - -I GETX 693447 +I GETX 694479 I PUTX_NotOwner 0 <-- I DMA_READ 0 <-- I DMA_WRITE 0 <-- -M GETX 53805 -M PUTX 693205 -M PUTX_NotOwner 351 +M GETX 53105 +M PUTX 694236 +M PUTX_NotOwner 360 M DMA_READ 0 <-- M DMA_WRITE 0 <-- @@ -726,21 +726,21 @@ M_DWR PUTX 0 <-- M_DWRI Memory_Ack 0 <-- -IM GETX 3167967 +IM GETX 3129578 IM GETS 0 <-- IM PUTX 0 <-- IM PUTX_NotOwner 0 <-- IM DMA_READ 0 <-- IM DMA_WRITE 0 <-- -IM Memory_Data 693390 +IM Memory_Data 694424 -MI GETX 3431724 +MI GETX 3394520 MI GETS 0 <-- MI PUTX 0 <-- MI PUTX_NotOwner 0 <-- MI DMA_READ 0 <-- MI DMA_WRITE 0 <-- -MI Memory_Ack 693133 +MI Memory_Ack 694183 ID GETX 0 <-- ID GETS 0 <-- @@ -760,289 +760,289 @@ ID_W Memory_Ack 0 <-- --- L1Cache --- - Event Counts - -Load 486166 +Load 485858 Ifetch 0 -Store 261091 -Data 747194 -Fwd_GETX 53805 +Store 261731 +Data 747528 +Fwd_GETX 53105 Inv 0 -Replacement 747001 -Writeback_Ack 693133 -Writeback_Nack 351 +Replacement 747333 +Writeback_Ack 694183 +Writeback_Nack 360 - Transitions - -I Load 486166 +I Load 485858 I Ifetch 0 <-- -I Store 261091 +I Store 261731 I Inv 0 <-- -I Replacement 53443 +I Replacement 52736 -II Writeback_Nack 351 +II Writeback_Nack 360 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 53454 +M Fwd_GETX 52745 M Inv 0 <-- -M Replacement 693558 +M Replacement 694597 -MI Fwd_GETX 351 +MI Fwd_GETX 360 MI Inv 0 <-- -MI Writeback_Ack 693133 +MI Writeback_Ack 694183 -IS Data 486115 +IS Data 485823 -IM Data 261079 +IM Data 261705 --- L1Cache --- - Event Counts - -Load 486166 +Load 485858 Ifetch 0 -Store 261091 -Data 747194 -Fwd_GETX 53805 +Store 261731 +Data 747528 +Fwd_GETX 53105 Inv 0 -Replacement 747001 -Writeback_Ack 693133 -Writeback_Nack 351 +Replacement 747333 +Writeback_Ack 694183 +Writeback_Nack 360 - Transitions - -I Load 486166 +I Load 485858 I Ifetch 0 <-- -I Store 261091 +I Store 261731 I Inv 0 <-- -I Replacement 53443 +I Replacement 52736 -II Writeback_Nack 351 +II Writeback_Nack 360 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 53454 +M Fwd_GETX 52745 M Inv 0 <-- -M Replacement 693558 +M Replacement 694597 -MI Fwd_GETX 351 +MI Fwd_GETX 360 MI Inv 0 <-- -MI Writeback_Ack 693133 +MI Writeback_Ack 694183 -IS Data 486115 +IS Data 485823 -IM Data 261079 +IM Data 261705 --- L1Cache --- - Event Counts - -Load 486166 +Load 485858 Ifetch 0 -Store 261091 -Data 747194 -Fwd_GETX 53805 +Store 261731 +Data 747528 +Fwd_GETX 53105 Inv 0 -Replacement 747001 -Writeback_Ack 693133 -Writeback_Nack 351 +Replacement 747333 +Writeback_Ack 694183 +Writeback_Nack 360 - Transitions - -I Load 486166 +I Load 485858 I Ifetch 0 <-- -I Store 261091 +I Store 261731 I Inv 0 <-- -I Replacement 53443 +I Replacement 52736 -II Writeback_Nack 351 +II Writeback_Nack 360 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 53454 +M Fwd_GETX 52745 M Inv 0 <-- -M Replacement 693558 +M Replacement 694597 -MI Fwd_GETX 351 +MI Fwd_GETX 360 MI Inv 0 <-- -MI Writeback_Ack 693133 +MI Writeback_Ack 694183 -IS Data 486115 +IS Data 485823 -IM Data 261079 +IM Data 261705 --- L1Cache --- - Event Counts - -Load 486166 +Load 485858 Ifetch 0 -Store 261091 -Data 747194 -Fwd_GETX 53805 +Store 261731 +Data 747528 +Fwd_GETX 53105 Inv 0 -Replacement 747001 -Writeback_Ack 693133 -Writeback_Nack 351 +Replacement 747333 +Writeback_Ack 694183 +Writeback_Nack 360 - Transitions - -I Load 486166 +I Load 485858 I Ifetch 0 <-- -I Store 261091 +I Store 261731 I Inv 0 <-- -I Replacement 53443 +I Replacement 52736 -II Writeback_Nack 351 +II Writeback_Nack 360 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 53454 +M Fwd_GETX 52745 M Inv 0 <-- -M Replacement 693558 +M Replacement 694597 -MI Fwd_GETX 351 +MI Fwd_GETX 360 MI Inv 0 <-- -MI Writeback_Ack 693133 +MI Writeback_Ack 694183 -IS Data 486115 +IS Data 485823 -IM Data 261079 +IM Data 261705 --- L1Cache --- - Event Counts - -Load 486166 +Load 485858 Ifetch 0 -Store 261091 -Data 747194 -Fwd_GETX 53805 +Store 261731 +Data 747528 +Fwd_GETX 53105 Inv 0 -Replacement 747001 -Writeback_Ack 693133 -Writeback_Nack 351 +Replacement 747333 +Writeback_Ack 694183 +Writeback_Nack 360 - Transitions - -I Load 486166 +I Load 485858 I Ifetch 0 <-- -I Store 261091 +I Store 261731 I Inv 0 <-- -I Replacement 53443 +I Replacement 52736 -II Writeback_Nack 351 +II Writeback_Nack 360 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 53454 +M Fwd_GETX 52745 M Inv 0 <-- -M Replacement 693558 +M Replacement 694597 -MI Fwd_GETX 351 +MI Fwd_GETX 360 MI Inv 0 <-- -MI Writeback_Ack 693133 +MI Writeback_Ack 694183 -IS Data 486115 +IS Data 485823 -IM Data 261079 +IM Data 261705 --- L1Cache --- - Event Counts - -Load 486166 +Load 485858 Ifetch 0 -Store 261091 -Data 747194 -Fwd_GETX 53805 +Store 261731 +Data 747528 +Fwd_GETX 53105 Inv 0 -Replacement 747001 -Writeback_Ack 693133 -Writeback_Nack 351 +Replacement 747333 +Writeback_Ack 694183 +Writeback_Nack 360 - Transitions - -I Load 486166 +I Load 485858 I Ifetch 0 <-- -I Store 261091 +I Store 261731 I Inv 0 <-- -I Replacement 53443 +I Replacement 52736 -II Writeback_Nack 351 +II Writeback_Nack 360 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 53454 +M Fwd_GETX 52745 M Inv 0 <-- -M Replacement 693558 +M Replacement 694597 -MI Fwd_GETX 351 +MI Fwd_GETX 360 MI Inv 0 <-- -MI Writeback_Ack 693133 +MI Writeback_Ack 694183 -IS Data 486115 +IS Data 485823 -IM Data 261079 +IM Data 261705 --- L1Cache --- - Event Counts - -Load 486166 +Load 485858 Ifetch 0 -Store 261091 -Data 747194 -Fwd_GETX 53805 +Store 261731 +Data 747528 +Fwd_GETX 53105 Inv 0 -Replacement 747001 -Writeback_Ack 693133 -Writeback_Nack 351 +Replacement 747333 +Writeback_Ack 694183 +Writeback_Nack 360 - Transitions - -I Load 486166 +I Load 485858 I Ifetch 0 <-- -I Store 261091 +I Store 261731 I Inv 0 <-- -I Replacement 53443 +I Replacement 52736 -II Writeback_Nack 351 +II Writeback_Nack 360 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 53454 +M Fwd_GETX 52745 M Inv 0 <-- -M Replacement 693558 +M Replacement 694597 -MI Fwd_GETX 351 +MI Fwd_GETX 360 MI Inv 0 <-- -MI Writeback_Ack 693133 +MI Writeback_Ack 694183 -IS Data 486115 +IS Data 485823 -IM Data 261079 +IM Data 261705 --- L1Cache --- - Event Counts - -Load 486166 +Load 485858 Ifetch 0 -Store 261091 -Data 747194 -Fwd_GETX 53805 +Store 261731 +Data 747528 +Fwd_GETX 53105 Inv 0 -Replacement 747001 -Writeback_Ack 693133 -Writeback_Nack 351 +Replacement 747333 +Writeback_Ack 694183 +Writeback_Nack 360 - Transitions - -I Load 486166 +I Load 485858 I Ifetch 0 <-- -I Store 261091 +I Store 261731 I Inv 0 <-- -I Replacement 53443 +I Replacement 52736 -II Writeback_Nack 351 +II Writeback_Nack 360 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 53454 +M Fwd_GETX 52745 M Inv 0 <-- -M Replacement 693558 +M Replacement 694597 -MI Fwd_GETX 351 +MI Fwd_GETX 360 MI Inv 0 <-- -MI Writeback_Ack 693133 +MI Writeback_Ack 694183 -IS Data 486115 +IS Data 485823 -IM Data 261079 +IM Data 261705 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr index 003f1ebfc..49e0168cd 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -1,136 +1,76 @@ ["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "8", "-m", "1", "-s", "1024"] print config: 1 -Creating new MessageBuffer for 0 0 -Creating new MessageBuffer for 0 1 -Creating new MessageBuffer for 0 2 -Creating new MessageBuffer for 0 3 -Creating new MessageBuffer for 0 4 -Creating new MessageBuffer for 0 5 -Creating new MessageBuffer for 1 0 -Creating new MessageBuffer for 1 1 -Creating new MessageBuffer for 1 2 -Creating new MessageBuffer for 1 3 -Creating new MessageBuffer for 1 4 -Creating new MessageBuffer for 1 5 -Creating new MessageBuffer for 2 0 -Creating new MessageBuffer for 2 1 -Creating new MessageBuffer for 2 2 -Creating new MessageBuffer for 2 3 -Creating new MessageBuffer for 2 4 -Creating new MessageBuffer for 2 5 -Creating new MessageBuffer for 3 0 -Creating new MessageBuffer for 3 1 -Creating new MessageBuffer for 3 2 -Creating new MessageBuffer for 3 3 -Creating new MessageBuffer for 3 4 -Creating new MessageBuffer for 3 5 -Creating new MessageBuffer for 4 0 -Creating new MessageBuffer for 4 1 -Creating new MessageBuffer for 4 2 -Creating new MessageBuffer for 4 3 -Creating new MessageBuffer for 4 4 -Creating new MessageBuffer for 4 5 -Creating new MessageBuffer for 5 0 -Creating new MessageBuffer for 5 1 -Creating new MessageBuffer for 5 2 -Creating new MessageBuffer for 5 3 -Creating new MessageBuffer for 5 4 -Creating new MessageBuffer for 5 5 -Creating new MessageBuffer for 6 0 -Creating new MessageBuffer for 6 1 -Creating new MessageBuffer for 6 2 -Creating new MessageBuffer for 6 3 -Creating new MessageBuffer for 6 4 -Creating new MessageBuffer for 6 5 -Creating new MessageBuffer for 7 0 -Creating new MessageBuffer for 7 1 -Creating new MessageBuffer for 7 2 -Creating new MessageBuffer for 7 3 -Creating new MessageBuffer for 7 4 -Creating new MessageBuffer for 7 5 -Creating new MessageBuffer for 8 0 -Creating new MessageBuffer for 8 1 -Creating new MessageBuffer for 8 2 -Creating new MessageBuffer for 8 3 -Creating new MessageBuffer for 8 4 -Creating new MessageBuffer for 8 5 -Creating new MessageBuffer for 9 0 -Creating new MessageBuffer for 9 1 -Creating new MessageBuffer for 9 2 -Creating new MessageBuffer for 9 3 -Creating new MessageBuffer for 9 4 -Creating new MessageBuffer for 9 5 -system.cpu3: completed 10000 read accesses @3640772 -system.cpu7: completed 10000 read accesses @3649542 -system.cpu0: completed 10000 read accesses @3656374 -system.cpu1: completed 10000 read accesses @3667859 -system.cpu4: completed 10000 read accesses @3675222 -system.cpu5: completed 10000 read accesses @3679111 -system.cpu6: completed 10000 read accesses @3710014 -system.cpu2: completed 10000 read accesses @3743556 -system.cpu3: completed 20000 read accesses @6768103 -system.cpu7: completed 20000 read accesses @6771442 -system.cpu5: completed 20000 read accesses @6772946 -system.cpu1: completed 20000 read accesses @6792072 -system.cpu0: completed 20000 read accesses @6792088 -system.cpu4: completed 20000 read accesses @6847561 -system.cpu6: completed 20000 read accesses @6853396 -system.cpu2: completed 20000 read accesses @6881032 -system.cpu3: completed 30000 read accesses @9874625 -system.cpu7: completed 30000 read accesses @9875111 -system.cpu1: completed 30000 read accesses @9912008 -system.cpu0: completed 30000 read accesses @9916494 -system.cpu6: completed 30000 read accesses @9946066 -system.cpu5: completed 30000 read accesses @9946502 -system.cpu2: completed 30000 read accesses @9972472 -system.cpu4: completed 30000 read accesses @9982022 -system.cpu7: completed 40000 read accesses @12977880 -system.cpu3: completed 40000 read accesses @13034394 -system.cpu0: completed 40000 read accesses @13037610 -system.cpu1: completed 40000 read accesses @13037678 -system.cpu6: completed 40000 read accesses @13044482 -system.cpu2: completed 40000 read accesses @13075158 -system.cpu5: completed 40000 read accesses @13090802 -system.cpu4: completed 40000 read accesses @13091547 -system.cpu7: completed 50000 read accesses @16073284 -system.cpu0: completed 50000 read accesses @16126074 -system.cpu6: completed 50000 read accesses @16130742 -system.cpu3: completed 50000 read accesses @16157406 -system.cpu1: completed 50000 read accesses @16165456 -system.cpu4: completed 50000 read accesses @16201749 -system.cpu5: completed 50000 read accesses @16220008 -system.cpu2: completed 50000 read accesses @16275764 -system.cpu7: completed 60000 read accesses @19232340 -system.cpu3: completed 60000 read accesses @19250699 -system.cpu1: completed 60000 read accesses @19276836 -system.cpu0: completed 60000 read accesses @19287336 -system.cpu6: completed 60000 read accesses @19294047 -system.cpu4: completed 60000 read accesses @19349695 -system.cpu5: completed 60000 read accesses @19406282 -system.cpu2: completed 60000 read accesses @19413090 -system.cpu7: completed 70000 read accesses @22371848 -system.cpu0: completed 70000 read accesses @22393000 -system.cpu3: completed 70000 read accesses @22397454 -system.cpu6: completed 70000 read accesses @22412286 -system.cpu1: completed 70000 read accesses @22421258 -system.cpu4: completed 70000 read accesses @22467490 -system.cpu5: completed 70000 read accesses @22524837 -system.cpu2: completed 70000 read accesses @22560722 -system.cpu3: completed 80000 read accesses @25508623 -system.cpu1: completed 80000 read accesses @25510110 -system.cpu7: completed 80000 read accesses @25511616 -system.cpu0: completed 80000 read accesses @25539501 -system.cpu6: completed 80000 read accesses @25558545 -system.cpu4: completed 80000 read accesses @25588582 -system.cpu2: completed 80000 read accesses @25645348 -system.cpu5: completed 80000 read accesses @25649504 -system.cpu0: completed 90000 read accesses @28620081 -system.cpu1: completed 90000 read accesses @28664699 -system.cpu6: completed 90000 read accesses @28681534 -system.cpu3: completed 90000 read accesses @28684736 -system.cpu7: completed 90000 read accesses @28698368 -system.cpu4: completed 90000 read accesses @28757223 -system.cpu2: completed 90000 read accesses @28817704 -system.cpu5: completed 90000 read accesses @28833888 -system.cpu1: completed 100000 read accesses @31772571 +system.cpu1: completed 10000 read accesses @3641101 +system.cpu6: completed 10000 read accesses @3657885 +system.cpu0: completed 10000 read accesses @3682054 +system.cpu4: completed 10000 read accesses @3686756 +system.cpu3: completed 10000 read accesses @3686791 +system.cpu2: completed 10000 read accesses @3714721 +system.cpu5: completed 10000 read accesses @3718986 +system.cpu7: completed 10000 read accesses @3739388 +system.cpu1: completed 20000 read accesses @6773990 +system.cpu4: completed 20000 read accesses @6790313 +system.cpu0: completed 20000 read accesses @6796672 +system.cpu3: completed 20000 read accesses @6797278 +system.cpu6: completed 20000 read accesses @6823694 +system.cpu2: completed 20000 read accesses @6833547 +system.cpu5: completed 20000 read accesses @6854676 +system.cpu7: completed 20000 read accesses @6875905 +system.cpu1: completed 30000 read accesses @9853256 +system.cpu3: completed 30000 read accesses @9906665 +system.cpu0: completed 30000 read accesses @9931557 +system.cpu4: completed 30000 read accesses @9952518 +system.cpu5: completed 30000 read accesses @9976242 +system.cpu2: completed 30000 read accesses @9981306 +system.cpu6: completed 30000 read accesses @10008066 +system.cpu7: completed 30000 read accesses @10011960 +system.cpu1: completed 40000 read accesses @13015878 +system.cpu3: completed 40000 read accesses @13040111 +system.cpu5: completed 40000 read accesses @13079687 +system.cpu0: completed 40000 read accesses @13099309 +system.cpu2: completed 40000 read accesses @13115004 +system.cpu4: completed 40000 read accesses @13143910 +system.cpu6: completed 40000 read accesses @13150020 +system.cpu7: completed 40000 read accesses @13161356 +system.cpu3: completed 50000 read accesses @16125452 +system.cpu1: completed 50000 read accesses @16181745 +system.cpu5: completed 50000 read accesses @16184066 +system.cpu0: completed 50000 read accesses @16216286 +system.cpu2: completed 50000 read accesses @16257216 +system.cpu4: completed 50000 read accesses @16263973 +system.cpu6: completed 50000 read accesses @16288792 +system.cpu7: completed 50000 read accesses @16318993 +system.cpu3: completed 60000 read accesses @19283536 +system.cpu0: completed 60000 read accesses @19309937 +system.cpu1: completed 60000 read accesses @19317676 +system.cpu2: completed 60000 read accesses @19325470 +system.cpu5: completed 60000 read accesses @19327514 +system.cpu6: completed 60000 read accesses @19417822 +system.cpu4: completed 60000 read accesses @19447479 +system.cpu7: completed 60000 read accesses @19480386 +system.cpu0: completed 70000 read accesses @22411174 +system.cpu3: completed 70000 read accesses @22411178 +system.cpu2: completed 70000 read accesses @22414508 +system.cpu5: completed 70000 read accesses @22453684 +system.cpu1: completed 70000 read accesses @22473724 +system.cpu4: completed 70000 read accesses @22564254 +system.cpu6: completed 70000 read accesses @22590390 +system.cpu7: completed 70000 read accesses @22646034 +system.cpu3: completed 80000 read accesses @25536114 +system.cpu0: completed 80000 read accesses @25565410 +system.cpu2: completed 80000 read accesses @25581306 +system.cpu1: completed 80000 read accesses @25643150 +system.cpu5: completed 80000 read accesses @25659302 +system.cpu4: completed 80000 read accesses @25672250 +system.cpu6: completed 80000 read accesses @25729734 +system.cpu7: completed 80000 read accesses @25780094 +system.cpu3: completed 90000 read accesses @28701520 +system.cpu2: completed 90000 read accesses @28736898 +system.cpu0: completed 90000 read accesses @28740612 +system.cpu5: completed 90000 read accesses @28751484 +system.cpu1: completed 90000 read accesses @28768980 +system.cpu4: completed 90000 read accesses @28819348 +system.cpu6: completed 90000 read accesses @28888794 +system.cpu7: completed 90000 read accesses @28938947 +system.cpu3: completed 100000 read accesses @31820150 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout index 7de08f059..8fd09328a 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:07 -M5 executing on maize +M5 compiled Jul 13 2009 11:01:42 +M5 revision 57650468aff1+ 6297+ default +M5 started Jul 13 2009 11:01:45 +M5 executing on clover-01.cs.wisc.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000000 ticks per second - Debug: Adding to filter: 'q' (Queue) info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 31772571 because maximum number of loads reached +Exiting @ tick 31820150 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 1746ef696..060ced5b9 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 1500524 # Number of bytes of host memory used -host_seconds 568.45 # Real time elapsed on the host -host_tick_rate 55893 # Simulator tick rate (ticks/s) +host_mem_usage 1538632 # Number of bytes of host memory used +host_seconds 2021.99 # Real time elapsed on the host +host_tick_rate 15737 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 31772571 # Number of ticks simulated +sim_ticks 31820150 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99945 # number of read accesses completed -system.cpu0.num_writes 53478 # number of write accesses completed +system.cpu0.num_reads 99856 # number of read accesses completed +system.cpu0.num_writes 53852 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 53531 # number of write accesses completed +system.cpu1.num_reads 99692 # number of read accesses completed +system.cpu1.num_writes 53561 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99361 # number of read accesses completed -system.cpu2.num_writes 53707 # number of write accesses completed +system.cpu2.num_reads 99805 # number of read accesses completed +system.cpu2.num_writes 53565 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99846 # number of read accesses completed -system.cpu3.num_writes 53546 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 53663 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99583 # number of read accesses completed -system.cpu4.num_writes 53626 # number of write accesses completed +system.cpu4.num_reads 99420 # number of read accesses completed +system.cpu4.num_writes 53889 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99623 # number of read accesses completed -system.cpu5.num_writes 53679 # number of write accesses completed +system.cpu5.num_reads 99788 # number of read accesses completed +system.cpu5.num_writes 53529 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99912 # number of read accesses completed -system.cpu6.num_writes 53508 # number of write accesses completed +system.cpu6.num_reads 99210 # number of read accesses completed +system.cpu6.num_writes 53902 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99813 # number of read accesses completed -system.cpu7.num_writes 53717 # number of write accesses completed +system.cpu7.num_reads 99182 # number of read accesses completed +system.cpu7.num_writes 54075 # number of write accesses completed ---------- End Simulation Statistics ---------- |