Assign traceData to be NULL at BaseSimpleCPU constructor.

Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls.
exec tracing isn't needed for m5.fast binaries
Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead.

src/arch/sparc/miscregfile.cc:
    Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead.
src/cpu/simple/base.cc:
    Assign traceData to be NULL at BaseSimpleCPU constructor.
    Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls.
    exec tracing isn't needed for m5.fast binaries

--HG--
extra : convert_revision : 5dc92fff05c9bde994f1e0f1bb40e11c44eb72c6

2 files changed, 46 insertions, 30 deletions

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index f511ef454..0300694cc 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -142,27 +142,38 @@ void MiscRegFile::clear()
 
 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 {
-    switch (miscReg) {
-      case MISCREG_TLB_DATA:
-        /* Package up all the data for the tlb:
-         * 6666555555555544444444443333333333222222222211111111110000000000
-         * 3210987654321098765432109876543210987654321098765432109876543210
-         *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
-         *                                                           ||||^red
-         *                                                           |||^priv
-         *                                                           ||^am
-         *                                                           |^lsuim
-         *                                                           ^lsudm
-         */
-        return bits((uint64_t)hpstate,2,2) |
-               bits((uint64_t)hpstate,5,5) << 1 |
-               bits((uint64_t)pstate,3,2) << 2 |
-               bits((uint64_t)lsuCtrlReg,3,2) << 4 |
-               bits((uint64_t)partId,7,0) << 8 |
-               bits((uint64_t)tl,2,0) << 16 |
-               (uint64_t)priContext << 32 |
-               (uint64_t)secContext << 48;
 
+  // The three miscRegs are moved up from the switch statement
+  // due to more frequent calls.
+
+  if (miscReg == MISCREG_GL)
+    return gl;
+  if (miscReg == MISCREG_CWP)
+    return cwp;
+  if (miscReg == MISCREG_TLB_DATA) {
+    /* Package up all the data for the tlb:
+     * 6666555555555544444444443333333333222222222211111111110000000000
+     * 3210987654321098765432109876543210987654321098765432109876543210
+     *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
+     *                                                           ||||^red
+     *                                                           |||^priv
+     *                                                           ||^am
+     *                                                           |^lsuim
+     *                                                           ^lsudm
+     */
+    return bits((uint64_t)hpstate,2,2) |
+           bits((uint64_t)hpstate,5,5) << 1 |
+           bits((uint64_t)pstate,3,2) << 2 |
+           bits((uint64_t)lsuCtrlReg,3,2) << 4 |
+           bits((uint64_t)partId,7,0) << 8 |
+           bits((uint64_t)tl,2,0) << 16 |
+                (uint64_t)priContext << 32 |
+                (uint64_t)secContext << 48;
+  }
+
+    switch (miscReg) {
+      //case MISCREG_TLB_DATA:
+      //  [original contents see above]
       //case MISCREG_Y:
       //  return y;
       //case MISCREG_CCR:
@@ -207,8 +218,9 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
         return tl;
       case MISCREG_PIL:
         return pil;
-      case MISCREG_CWP:
-        return cwp;
+      //CWP, GL moved
+      //case MISCREG_CWP:
+      //  return cwp;
       //case MISCREG_CANSAVE:
       //  return cansave;
       //case MISCREG_CANRESTORE:
@@ -219,8 +231,8 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
       //  return otherwin;
       //case MISCREG_WSTATE:
       //  return wstate;
-      case MISCREG_GL:
-        return gl;
+      //case MISCREG_GL:
+      //  return gl;
 
         /** Hyper privileged registers */
       case MISCREG_HPSTATE:
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 4fed2059b..aa341487c 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -70,7 +70,7 @@ using namespace std;
 using namespace TheISA;
 
 BaseSimpleCPU::BaseSimpleCPU(Params *p)
-    : BaseCPU(p), thread(NULL), predecoder(NULL)
+    : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
 {
 #if FULL_SYSTEM
     thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
@@ -326,18 +326,20 @@ BaseSimpleCPU::checkForInterrupts()
 Fault
 BaseSimpleCPU::setupFetchRequest(Request *req)
 {
+    uint64_t threadPC = thread->readPC();
+
     // set up memory request for instruction fetch
 #if ISA_HAS_DELAY_SLOT
-    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
+    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
             thread->readNextPC(),thread->readNextNPC());
 #else
-    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
+    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",threadPC,
             thread->readNextPC());
 #endif
 
-    req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
-                 (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0,
-                 thread->readPC());
+    req->setVirt(0, threadPC & ~3, sizeof(MachInst),
+                 (FULL_SYSTEM && (threadPC & 1)) ? PHYSICAL : 0,
+                 threadPC);
 
     Fault fault = thread->translateInstReq(req);
 
@@ -396,6 +398,7 @@ BaseSimpleCPU::preExecute()
             fetchMicroOp(thread->readMicroPC());
     }
 
+#if TRACING_ON
     //If we decoded an instruction this "tick", record information about it.
     if(curStaticInst)
     {
@@ -409,6 +412,7 @@ BaseSimpleCPU::preExecute()
         thread->setInst(inst);
 #endif // FULL_SYSTEM
     }
+#endif // TRACING_ON
 }
 
 void