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authorAndreas Hansson <andreas.hansson@arm.com>2013-11-15 03:47:10 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2013-11-15 03:47:10 -0500
commitf028da7af7792bec226372ef23c1d103ad68ad30 (patch)
tree7ecf1b4df77cd850bacb8b327e96401172bc709a
parenta2c21d47a8cd6a1a633491fb58b9d3b1c45c965d (diff)
downloadgem5-f028da7af7792bec226372ef23c1d103ad68ad30.tar.xz
cpu: Fix Checker register index use
This patch fixes an issue in the checker CPU register indexing. The code will not even compile using LTO as deep inlining causes the used index to be outside the array bounds.
-rw-r--r--src/cpu/checker/cpu_impl.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 73bacdc05..23e9c103e 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -607,10 +607,10 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
thread->setIntReg(idx, mismatch_val);
break;
case FloatRegClass:
- thread->setFloatRegBits(idx, mismatch_val);
+ thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, mismatch_val);
break;
case CCRegClass:
- thread->setCCReg(idx, mismatch_val);
+ thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val);
break;
case MiscRegClass:
thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
@@ -628,10 +628,10 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
thread->setIntReg(idx, res);
break;
case FloatRegClass:
- thread->setFloatRegBits(idx, res);
+ thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
break;
case CCRegClass:
- thread->setCCReg(idx, res);
+ thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
break;
case MiscRegClass:
// Try to get the proper misc register index for ARM here...