diff options
author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-02-13 08:09:09 -0800 |
---|---|---|
committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-02-13 08:09:09 -0800 |
commit | f55fd68f884d07c65ff78cd0b5a762dba61ce690 (patch) | |
tree | 2c01ead62810f34e7324972c77ac03c1fcf786c8 | |
parent | ca5cd68df4967b306625723c13eab9282c0f2372 (diff) | |
download | gem5-f55fd68f884d07c65ff78cd0b5a762dba61ce690.tar.xz |
Update MIPS ISA description to work with new write result interface
for store conditional.
--HG--
extra : convert_revision : 73efd2ca17994e0e19c08746441874a2ac8183af
-rw-r--r-- | src/arch/mips/isa/decoder.isa | 3 | ||||
-rw-r--r-- | src/arch/mips/isa/formats/mem.isa | 69 | ||||
-rw-r--r-- | src/arch/mips/isa/formats/util.isa | 6 |
3 files changed, 74 insertions, 4 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 99c9e1604..3a8688797 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -1093,6 +1093,9 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, {{ uint64_t tmp = write_result; Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; + if (tmp == 1) { + xc->setStCondFailures(0); + } }}, mem_flags=LOCKED, inst_flags = IsStoreConditional); format StoreMemory { diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index c365edd0a..df80e7a1f 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -325,6 +325,41 @@ def template StoreMemAccExecute {{ { Addr EA; Fault fault = NoFault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + EA = xc->getEA(); + + if (fault == NoFault) { + %(memacc_code)s; + } + + if (fault == NoFault) { + fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + memAccessFlags, NULL); + if (traceData) { traceData->setData(Mem); } + } + + if (fault == NoFault) { + %(postacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + + return fault; + } +}}; + +def template StoreCondMemAccExecute {{ + Fault + %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; uint64_t write_result = 0; %(fp_enable_check)s; @@ -361,6 +396,40 @@ def template StoreExecute {{ { Addr EA; Fault fault = NoFault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + + if (fault == NoFault) { + %(memacc_code)s; + } + + if (fault == NoFault) { + fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + memAccessFlags, NULL); + if (traceData) { traceData->setData(Mem); } + } + + if (fault == NoFault) { + %(postacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + + return fault; + } +}}; + +def template StoreCondExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; uint64_t write_result = 0; %(fp_enable_check)s; diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa index ec524113d..884e6f727 100644 --- a/src/arch/mips/isa/formats/util.isa +++ b/src/arch/mips/isa/formats/util.isa @@ -66,10 +66,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, # select templates - # define aliases... most StoreCond templates are the same as the - # corresponding Store templates (only CompleteAcc is different). - StoreCondMemAccExecute = StoreMemAccExecute - StoreCondExecute = StoreExecute + # The InitiateAcc template is the same for StoreCond templates as the + # corresponding Store template.. StoreCondInitiateAcc = StoreInitiateAcc memAccExecTemplate = eval(exec_template_base + 'MemAccExecute') |