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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-08-11 20:29:15 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-08-11 20:29:15 -0400 |
| commit | fc8b4f52537dafdfe10a9be912fe3f069d8a570d (patch) | |
| tree | 9db067defca7db052549a33cb6523fc07e168d37 | |
| parent | 95dc8e4d57d32f30ef86d40c24b4d78c3505f450 (diff) | |
| download | gem5-fc8b4f52537dafdfe10a9be912fe3f069d8a570d.tar.xz | |
Started to add support for O3 for sparc.
--HG--
extra : convert_revision : 3f94bda14024a09b9fbd7a5d13284d4987349ddf
| -rwxr-xr-x | src/cpu/o3/SConscript | 13 | ||||
| -rw-r--r-- | src/cpu/o3/dyn_inst.hh | 4 |
2 files changed, 10 insertions, 7 deletions
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index 44882e5ec..afbd4c533 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -59,13 +59,12 @@ elif env['TARGET_ISA'] == 'mips': mips/cpu_builder.cc ''') elif env['TARGET_ISA'] == 'sparc': - sys.exit('O3 CPU does not support Sparc') - #sources += Split(''' - # sparc/dyn_inst.cc - # sparc/cpu.cc - # sparc/thread_context.cc - # sparc/cpu_builder.cc - # ''') + sources += Split(''' + sparc/dyn_inst.cc + sparc/cpu.cc + sparc/thread_context.cc + sparc/cpu_builder.cc + ''') else: sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA']) diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 5f7caf79f..279513493 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -41,6 +41,10 @@ template <class Impl> class MipsDynInst; struct MipsSimpleImpl; typedef MipsDynInst<MipsSimpleImpl> O3DynInst; +#elif THE_ISA == SPARC_ISA + template <class Impl> class SparcDynInst; + struct SparcSimpleImpl; + typedef SparcDynInst<SparcSimpleImpl> O3DynInst; #else #error "O3DynInst not defined for this ISA" #endif |