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| author | Nathan Binkert <binkertn@umich.edu> | 2004-02-29 14:54:52 -0500 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2004-02-29 14:54:52 -0500 |
| commit | 27960f6d858e92572d37604e92747d0b45591665 (patch) | |
| tree | dd8ab574d000d74ebdf31269e017b992ab7d9a9a | |
| parent | c79deda8cd404565bbd277e67b3533b6c13fac74 (diff) | |
| download | gem5-27960f6d858e92572d37604e92747d0b45591665.tar.xz | |
fix rpcc
arch/alpha/ev5.cc:
actually implement the cycle count register
arch/alpha/isa_desc:
the rpcc instruction really just reads the cycle count
register
--HG--
extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1
| -rw-r--r-- | arch/alpha/ev5.cc | 5 | ||||
| -rw-r--r-- | arch/alpha/isa_desc | 3 |
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 96c51a2aa..551cbdabf 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -237,6 +237,11 @@ ExecContext::readIpr(int idx, Fault &fault) retval = ipr[idx]; break; + case AlphaISA::IPR_CC: + retval |= ipr[idx] & ULL(0xffffffff00000000); + retval |= curTick & ULL(0x00000000ffffffff); + break; + case AlphaISA::IPR_VA: // SFX: unlocks interrupt status registers retval = ipr[idx]; diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index c4d367211..0cfe5b452 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2390,8 +2390,7 @@ decode OPCODE default Unknown::unknown() { format BasicOperate { 0xc000: rpcc({{ #ifdef FULL_SYSTEM - uint64_t cc = xc->readIpr(AlphaISA::IPR_CC, fault); - Ra = (cc<63:32> | curTick<31:0>); + Ra = xc->readIpr(AlphaISA::IPR_CC, fault); #else Ra = curTick; #endif |