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| author | Malek Musleh <malek.musleh@gmail.com> | 2012-09-28 09:35:25 -0400 |
|---|---|---|
| committer | Malek Musleh <malek.musleh@gmail.com> | 2012-09-28 09:35:25 -0400 |
| commit | 3fc23b9b96769b8274e93f5cf14bb29b0ba044f0 (patch) | |
| tree | 592329eac9aafad7e0ab43033689f3bc530700d1 | |
| parent | 6596059d058d783205f6570206c1088fad18817d (diff) | |
| download | gem5-3fc23b9b96769b8274e93f5cf14bb29b0ba044f0.tar.xz | |
Configs: SE script fix for Alpha and Ruby simulations
PIO interrupt port is only present for x86. Do not attempt to connect
for other ISAs.
| -rw-r--r-- | configs/example/se.py | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index b60baf041..adebab1e2 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -190,15 +190,17 @@ if options.ruby: ruby_port = system.ruby._cpu_ruby_ports[i] # Create the interrupt controller and connect its ports to Ruby + # Note that the interrupt controller is always present but only + # in x86 does it have message ports that need to be connected system.cpu[i].createInterruptController() - system.cpu[i].interrupts.pio = ruby_port.master - system.cpu[i].interrupts.int_master = ruby_port.slave - system.cpu[i].interrupts.int_slave = ruby_port.master # Connect the cpu's cache ports to Ruby system.cpu[i].icache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave if buildEnv['TARGET_ISA'] == 'x86': + system.cpu[i].interrupts.pio = ruby_port.master + system.cpu[i].interrupts.int_master = ruby_port.slave + system.cpu[i].interrupts.int_slave = ruby_port.master system.cpu[i].itb.walker.port = ruby_port.slave system.cpu[i].dtb.walker.port = ruby_port.slave else: |