diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-03-09 15:33:07 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-03-09 15:33:07 -0500 |
| commit | 470051345af2a78425730bd790000530b1b8a1f5 (patch) | |
| tree | d2bdfb09a2cfc4c96a5fcd9c4399610fbf4206a3 | |
| parent | 9a9a4a0780865dc722b7564ea1c1bf8bacb4e5ce (diff) | |
| download | gem5-470051345af2a78425730bd790000530b1b8a1f5.tar.xz | |
ARM: Update stats for CBNZ fix.
86 files changed, 7323 insertions, 7282 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index b50c47979..51386a35a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:34:27 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:47:04 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker The currently selected ARM platforms doesn't support the amount of DRAM you've selected. Please try another platform Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503289265500 because m5_exit instruction encountered +Exiting @ tick 2503099557500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 3749ebea8..d91423395 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503289 # Number of seconds simulated -sim_ticks 2503289265500 # Number of ticks simulated -final_tick 2503289265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503100 # Number of seconds simulated +sim_ticks 2503099557500 # Number of ticks simulated +final_tick 2503099557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55466 # Simulator instruction rate (inst/s) -host_op_rate 71644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2335415954 # Simulator tick rate (ticks/s) -host_mem_usage 389340 # Number of bytes of host memory used -host_seconds 1071.88 # Real time elapsed on the host -sim_insts 59452703 # Number of instructions simulated -sim_ops 76793713 # Number of ops (including micro ops) simulated +host_inst_rate 68083 # Simulator instruction rate (inst/s) +host_op_rate 87941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2866621111 # Simulator tick rate (ticks/s) +host_mem_usage 384248 # Number of bytes of host memory used +host_seconds 873.19 # Real time elapsed on the host +sim_insts 59449445 # Number of instructions simulated +sim_ops 76789092 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,148 +20,148 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130753040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1118144 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9587720 # Number of bytes written to this memory -system.physmem.num_reads 15117482 # Number of read requests responded to by this memory -system.physmem.num_writes 856700 # Number of write requests responded to by this memory +system.physmem.bytes_read 130740776 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1120320 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9586312 # Number of bytes written to this memory +system.physmem.num_reads 15115704 # Number of read requests responded to by this memory +system.physmem.num_writes 856678 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52232493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 446670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3830049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56062542 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119784 # number of replacements -system.l2c.tagsinuse 26074.057253 # Cycle average of tags in use -system.l2c.total_refs 1841990 # Total number of references to valid blocks. -system.l2c.sampled_refs 150687 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.223948 # Average number of references to valid blocks. +system.physmem.bw_read 52231553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 447573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3829777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56061329 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119794 # number of replacements +system.l2c.tagsinuse 26073.611012 # Cycle average of tags in use +system.l2c.total_refs 1840774 # Total number of references to valid blocks. +system.l2c.sampled_refs 150725 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.212798 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14309.337346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 64.598044 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.929730 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6189.709081 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5509.483052 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.218343 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 14308.761179 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 64.610993 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.928498 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6189.887268 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5509.423074 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.218334 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000986 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.094447 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.084068 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.397859 # 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miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.017089 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.048289 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.985507 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu.data 246237 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246237 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 152995 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11668 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1016254 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 642702 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1823619 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 152995 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11668 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1016254 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 642702 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1823619 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001028 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.017104 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.048292 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.986893 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.569735 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001039 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131763880500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131769387500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348463263 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32348463263 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164109739763 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164115246763 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048087 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164112343763 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164117850763 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048093 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986893 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569735 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 42000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40202.394001 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40139.489143 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40392.857143 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569963 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40141.545282 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40125.609692 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40391.488077 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40166.922014 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40161.646930 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -278,9 +278,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15017434 # DTB read hits -system.cpu.checker.dtb.read_misses 7313 # DTB read misses -system.cpu.checker.dtb.write_hits 11274974 # DTB write hits +system.cpu.checker.dtb.read_hits 15016256 # DTB read hits +system.cpu.checker.dtb.read_misses 7312 # DTB read misses +system.cpu.checker.dtb.write_hits 11274185 # DTB write hits system.cpu.checker.dtb.write_misses 2190 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -291,13 +291,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15024747 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11277164 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15023568 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11276375 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26292408 # DTB hits -system.cpu.checker.dtb.misses 9503 # DTB misses -system.cpu.checker.dtb.accesses 26301911 # DTB accesses -system.cpu.checker.itb.inst_hits 60619265 # ITB inst hits +system.cpu.checker.dtb.hits 26290441 # DTB hits +system.cpu.checker.dtb.misses 9502 # DTB misses +system.cpu.checker.dtb.accesses 26299943 # DTB accesses +system.cpu.checker.itb.inst_hits 60615999 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -314,36 +314,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 60623736 # ITB inst accesses -system.cpu.checker.itb.hits 60619265 # DTB hits +system.cpu.checker.itb.inst_accesses 60620470 # ITB inst accesses +system.cpu.checker.itb.hits 60615999 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 60623736 # DTB accesses -system.cpu.checker.numCycles 77072082 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 60620470 # DTB accesses +system.cpu.checker.numCycles 77067453 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51991464 # DTB read hits -system.cpu.dtb.read_misses 102104 # DTB read misses -system.cpu.dtb.write_hits 11910179 # DTB write hits -system.cpu.dtb.write_misses 24558 # DTB write misses +system.cpu.dtb.read_hits 51948606 # DTB read hits +system.cpu.dtb.read_misses 101816 # DTB read misses +system.cpu.dtb.write_hits 11910706 # DTB write hits +system.cpu.dtb.write_misses 24423 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8002 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5528 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 717 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7999 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5598 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 665 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2750 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52093568 # DTB read accesses -system.cpu.dtb.write_accesses 11934737 # DTB write accesses +system.cpu.dtb.perms_faults 2849 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52050422 # DTB read accesses +system.cpu.dtb.write_accesses 11935129 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63901643 # DTB hits -system.cpu.dtb.misses 126662 # DTB misses -system.cpu.dtb.accesses 64028305 # DTB accesses -system.cpu.itb.inst_hits 13706914 # ITB inst hits -system.cpu.itb.inst_misses 11634 # ITB inst misses +system.cpu.dtb.hits 63859312 # DTB hits +system.cpu.dtb.misses 126239 # DTB misses +system.cpu.dtb.accesses 63985551 # DTB accesses +system.cpu.itb.inst_hits 13611127 # ITB inst hits +system.cpu.itb.inst_misses 11794 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -352,504 +352,504 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5188 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5224 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 6661 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 6917 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13718548 # ITB inst accesses -system.cpu.itb.hits 13706914 # DTB hits -system.cpu.itb.misses 11634 # DTB misses -system.cpu.itb.accesses 13718548 # DTB accesses -system.cpu.numCycles 414369636 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13622921 # ITB inst accesses +system.cpu.itb.hits 13611127 # DTB hits +system.cpu.itb.misses 11794 # DTB misses +system.cpu.itb.accesses 13622921 # DTB accesses +system.cpu.numCycles 414035717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15625474 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12104785 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 954505 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11141912 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8550078 # Number of BTB hits +system.cpu.BPredUnit.lookups 15526652 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12489737 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 928336 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10678484 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8212324 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1319848 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 195832 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33026569 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 102466950 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15625474 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9869926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22757995 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6647547 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 147850 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92972764 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2992 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133718 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 218178 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 532 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13699500 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 999735 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6482 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 153797054 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.827732 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.202835 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1312295 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 195061 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32929499 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 102163781 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15526652 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9524619 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22440538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6579937 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 148688 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93080203 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 137545 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 217702 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13603433 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 995292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6599 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153452703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.827416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.209875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131058833 85.22% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1482677 0.96% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2033464 1.32% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2746838 1.79% 89.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2006274 1.30% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1249103 0.81% 91.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2843395 1.85% 93.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 830139 0.54% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9546331 6.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131028378 85.39% 85.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1463837 0.95% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1832687 1.19% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2690815 1.75% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1870921 1.22% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1178749 0.77% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2936419 1.91% 93.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 835625 0.54% 93.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9615272 6.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 153797054 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037709 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.247284 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35048577 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92898724 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20403369 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090511 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4355873 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2264859 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 184542 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119404764 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 595579 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4355873 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37137128 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36905254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49913788 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19399307 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6085704 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 111719644 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3150 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 969173 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3986800 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 44721 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 116183301 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 513866964 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 513772287 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 94677 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77497386 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38685914 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1179207 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1074915 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12764218 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21542479 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14020388 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1893002 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2399626 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101427658 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1855104 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 125968969 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 213520 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25665704 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69757934 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 355346 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 153797054 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819060 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523592 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 153452703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037501 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.246751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34954549 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92988756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20078806 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1116855 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4313737 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2248287 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 185454 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119076129 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 599477 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4313737 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37045133 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36926846 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49909637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19098925 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6158425 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 111441141 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3427 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 975111 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4036126 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 44783 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115828569 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 512776978 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 512681517 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 95461 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77492759 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38335809 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1177287 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1072928 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13010963 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21488170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14015818 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1893787 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2361029 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101216530 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1853504 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 125772492 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 220452 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25469081 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69618284 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 353864 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153452703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.525568 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108075061 70.27% 70.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14788281 9.62% 79.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7369782 4.79% 84.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5814520 3.78% 88.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12712346 8.27% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2776756 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693530 1.10% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 431004 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135774 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107878797 70.30% 70.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14731235 9.60% 79.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7302555 4.76% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5766685 3.76% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12704866 8.28% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797979 1.82% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1703854 1.11% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 430247 0.28% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 136485 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 153797054 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153452703 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 56704 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8414937 94.55% 95.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 428693 4.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 55588 0.63% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8410763 94.57% 95.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 427006 4.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59520968 47.25% 47.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95881 0.08% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 42 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 37 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2281 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53674365 42.61% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12568853 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59380040 47.21% 47.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95959 0.08% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 34 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 46 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2266 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53622551 42.63% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12565056 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 125968969 # Type of FU issued -system.cpu.iq.rate 0.304001 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8900337 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070655 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 414950878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128966853 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86636419 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24045 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13082 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10392 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134749943 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12833 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 592097 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 125772492 # Type of FU issued +system.cpu.iq.rate 0.303772 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8893360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070710 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 414213065 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128557320 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86496982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24084 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13214 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10457 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134546484 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12838 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 592105 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5860643 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10887 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32446 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2240776 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5807721 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11311 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32412 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2237013 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34115661 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1150165 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34115378 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1150417 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4355873 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28439880 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 429508 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103498796 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 345453 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21542479 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14020388 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1231045 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 92628 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11369 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32446 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 597024 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332843 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 929867 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122679068 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52684410 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3289901 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4313737 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28451597 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 431255 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103286909 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 337253 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21488170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14015818 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1227531 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 94319 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11225 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32412 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 548239 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 349587 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 897826 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122535537 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52641416 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3236955 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 216034 # number of nop insts executed -system.cpu.iew.exec_refs 65104045 # number of memory reference insts executed -system.cpu.iew.exec_branches 11571925 # Number of branches executed -system.cpu.iew.exec_stores 12419635 # Number of stores executed -system.cpu.iew.exec_rate 0.296062 # Inst execution rate -system.cpu.iew.wb_sent 121147574 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86646811 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46911516 # num instructions producing a value -system.cpu.iew.wb_consumers 86713430 # num instructions consuming a value +system.cpu.iew.exec_nop 216875 # number of nop insts executed +system.cpu.iew.exec_refs 65061832 # number of memory reference insts executed +system.cpu.iew.exec_branches 11533456 # Number of branches executed +system.cpu.iew.exec_stores 12420416 # Number of stores executed +system.cpu.iew.exec_rate 0.295954 # Inst execution rate +system.cpu.iew.wb_sent 121007788 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86507439 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46901063 # num instructions producing a value +system.cpu.iew.wb_consumers 86866563 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.209105 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.540995 # average fanout of values written-back +system.cpu.iew.wb_rate 0.208937 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.539921 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59603084 # The number of committed instructions -system.cpu.commit.commitCommittedOps 76944094 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26377882 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1499758 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 817257 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149523536 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514595 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.479322 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59599826 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76939473 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26171914 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499640 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 790317 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149221313 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.515606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.482610 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121178940 81.04% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14398423 9.63% 90.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4065564 2.72% 93.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2131324 1.43% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1770497 1.18% 96.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1046764 0.70% 96.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1546784 1.03% 97.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657861 0.44% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2727379 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120951257 81.05% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14347270 9.61% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4034652 2.70% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2127712 1.43% 94.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1768055 1.18% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1033434 0.69% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1556613 1.04% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657865 0.44% 98.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2744455 1.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149523536 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59603084 # Number of instructions committed -system.cpu.commit.committedOps 76944094 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149221313 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59599826 # Number of instructions committed +system.cpu.commit.committedOps 76939473 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27461448 # Number of memory references committed -system.cpu.commit.loads 15681836 # Number of loads committed -system.cpu.commit.membars 413071 # Number of memory barriers committed -system.cpu.commit.branches 9891470 # Number of branches committed +system.cpu.commit.refs 27459254 # Number of memory references committed +system.cpu.commit.loads 15680449 # Number of loads committed +system.cpu.commit.membars 413031 # Number of memory barriers committed +system.cpu.commit.branches 9890920 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68496808 # Number of committed integer instructions. -system.cpu.commit.function_calls 995631 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2727379 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68492585 # Number of committed integer instructions. +system.cpu.commit.function_calls 995546 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2744455 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 248361579 # The number of ROB reads -system.cpu.rob.rob_writes 211126300 # The number of ROB writes -system.cpu.timesIdled 1891134 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260572582 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592120905 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59452703 # Number of Instructions Simulated -system.cpu.committedOps 76793713 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59452703 # Number of Instructions Simulated -system.cpu.cpi 6.969736 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.969736 # CPI: Total CPI of All Threads -system.cpu.ipc 0.143477 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.143477 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556236615 # number of integer regfile reads -system.cpu.int_regfile_writes 88987616 # number of integer regfile writes -system.cpu.fp_regfile_reads 8813 # number of floating regfile reads -system.cpu.fp_regfile_writes 2942 # number of floating regfile writes -system.cpu.misc_regfile_reads 134801411 # number of misc regfile reads -system.cpu.misc_regfile_writes 912350 # number of misc regfile writes -system.cpu.icache.replacements 1015901 # number of replacements -system.cpu.icache.tagsinuse 511.619298 # Cycle average of tags in use -system.cpu.icache.total_refs 12592690 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1016413 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.389344 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 247831805 # The number of ROB reads +system.cpu.rob.rob_writes 210661614 # The number of ROB writes +system.cpu.timesIdled 1891867 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260583014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592075418 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59449445 # Number of Instructions Simulated +system.cpu.committedOps 76789092 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59449445 # Number of Instructions Simulated +system.cpu.cpi 6.964501 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.964501 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143585 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143585 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 555570057 # number of integer regfile reads +system.cpu.int_regfile_writes 88783659 # number of integer regfile writes +system.cpu.fp_regfile_reads 8868 # number of floating regfile reads +system.cpu.fp_regfile_writes 2963 # number of floating regfile writes +system.cpu.misc_regfile_reads 134383864 # number of misc regfile reads +system.cpu.misc_regfile_writes 912266 # number of misc regfile writes +system.cpu.icache.replacements 1016880 # number of replacements +system.cpu.icache.tagsinuse 511.619498 # Cycle average of tags in use +system.cpu.icache.total_refs 12495254 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1017392 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.281652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.619298 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999256 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999256 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12592690 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12592690 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12592690 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12592690 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12592690 # number of overall hits -system.cpu.icache.overall_hits::total 12592690 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1106667 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1106667 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1106667 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1106667 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1106667 # number of overall misses -system.cpu.icache.overall_misses::total 1106667 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16295196980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16295196980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16295196980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16295196980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16295196980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16295196980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13699357 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13699357 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13699357 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13699357 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13699357 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13699357 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080782 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.080782 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.080782 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.571149 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2918982 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 511.619498 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999257 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999257 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12495254 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12495254 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12495254 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12495254 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12495254 # number of overall hits +system.cpu.icache.overall_hits::total 12495254 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1108036 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1108036 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1108036 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1108036 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1108036 # number of overall misses +system.cpu.icache.overall_misses::total 1108036 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16316535479 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16316535479 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16316535479 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16316535479 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16316535479 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16316535479 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13603290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13603290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13603290 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13603290 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13603290 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13603290 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081454 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081454 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081454 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14725.636603 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2951482 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 405 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7427.435115 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7287.609877 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 58562 # number of writebacks -system.cpu.icache.writebacks::total 58562 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90216 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 90216 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 90216 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 90216 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 90216 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 90216 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1016451 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1016451 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1016451 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1016451 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1016451 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1016451 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12139346482 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12139346482 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12139346482 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12139346482 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12139346482 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12139346482 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 58719 # number of writebacks +system.cpu.icache.writebacks::total 58719 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90611 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90611 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90611 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90611 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90611 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90611 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017425 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1017425 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1017425 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1017425 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1017425 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1017425 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12153604482 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12153604482 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12153604482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12153604482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12153604482 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12153604482 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7398500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7398500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7398500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7398500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11942.874258 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11945.454930 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645034 # number of replacements -system.cpu.dcache.tagsinuse 511.991558 # Cycle average of tags in use -system.cpu.dcache.total_refs 22002707 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645546 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.083872 # Average number of references to valid blocks. +system.cpu.dcache.replacements 644925 # number of replacements +system.cpu.dcache.tagsinuse 511.991557 # Cycle average of tags in use +system.cpu.dcache.total_refs 21957407 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645437 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.019443 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 49249000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991558 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.991557 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # 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mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.905595 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35775.415014 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13422.045841 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency @@ -868,14 +868,14 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307962166200 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307962166200 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307788731818 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307788731818 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 87991 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87981 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index fcc2fd3aa..231285393 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:35:13 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:49:08 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual The currently selected ARM platforms doesn't support the amount of DRAM you've selected. Please try another platform Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2572328372500 because m5_exit instruction encountered +Exiting @ tick 2572151538500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index da2515fe9..3baa592c1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.572328 # Number of seconds simulated -sim_ticks 2572328372500 # Number of ticks simulated -final_tick 2572328372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.572152 # Number of seconds simulated +sim_ticks 2572151538500 # Number of ticks simulated +final_tick 2572151538500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66069 # Simulator instruction rate (inst/s) -host_op_rate 85341 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2748514196 # Simulator tick rate (ticks/s) -host_mem_usage 389880 # Number of bytes of host memory used -host_seconds 935.90 # Real time elapsed on the host -sim_insts 61834256 # Number of instructions simulated -sim_ops 79870174 # Number of ops (including micro ops) simulated +host_inst_rate 81031 # Simulator instruction rate (inst/s) +host_op_rate 104662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3370719075 # Simulator tick rate (ticks/s) +host_mem_usage 387768 # Number of bytes of host memory used +host_seconds 763.09 # Real time elapsed on the host +sim_insts 61833482 # Number of instructions simulated +sim_ops 79866272 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,249 +20,249 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 131402148 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1183168 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10205776 # Number of bytes written to this memory -system.physmem.num_reads 15127689 # Number of read requests responded to by this memory -system.physmem.num_writes 869419 # Number of write requests responded to by this memory +system.physmem.bytes_read 131401380 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1182400 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10205328 # Number of bytes written to this memory +system.physmem.num_reads 15127677 # Number of read requests responded to by this memory +system.physmem.num_writes 869412 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51082960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 459960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3967525 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55050485 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 130931 # number of replacements -system.l2c.tagsinuse 27519.920349 # Cycle average of tags in use -system.l2c.total_refs 1850900 # Total number of references to valid blocks. -system.l2c.sampled_refs 160584 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.526055 # Average number of references to valid blocks. +system.physmem.bw_read 51086174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 459693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3967623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 55053797 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 130950 # number of replacements +system.l2c.tagsinuse 27519.569663 # Cycle average of tags in use +system.l2c.total_refs 1851108 # Total number of references to valid blocks. +system.l2c.sampled_refs 160575 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.527996 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15169.797230 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 19.693620 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.048154 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2916.118065 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8468888000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123493886000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131970436000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 744869980 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31777552693 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32522422673 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123493861000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131970428500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 744865480 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31777562693 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32522428173 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5748500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9213740480 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9213753480 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155271438693 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164492858673 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061886 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051213 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.853463 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.860697 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784615 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.602506 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.643564 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.556987 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40058.384213 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155271423693 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164492856673 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061805 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051237 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.853021 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.854551 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.781633 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.600912 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.643655 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.557358 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.300306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244301 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.300306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244301 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40056.762362 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40057.226675 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.141518 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.031069 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.522876 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.094518 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.774502 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40099.766211 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40057.871708 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.350620 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.770641 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.775457 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40047.438330 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.215702 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40098.701698 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40035.196784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40093.404946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40035.196784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40093.404946 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -455,27 +452,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7800657 # DTB read hits -system.cpu0.dtb.read_misses 37871 # DTB read misses -system.cpu0.dtb.write_hits 4594363 # DTB write hits -system.cpu0.dtb.write_misses 6405 # DTB write misses +system.cpu0.dtb.read_hits 7779192 # DTB read hits +system.cpu0.dtb.read_misses 37115 # DTB read misses +system.cpu0.dtb.write_hits 4594295 # DTB write hits +system.cpu0.dtb.write_misses 6419 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 4617 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2014 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 4597 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 804 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7838528 # DTB read accesses -system.cpu0.dtb.write_accesses 4600768 # DTB write accesses +system.cpu0.dtb.perms_faults 800 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7816307 # DTB read accesses +system.cpu0.dtb.write_accesses 4600714 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12395020 # DTB hits -system.cpu0.dtb.misses 44276 # DTB misses -system.cpu0.dtb.accesses 12439296 # DTB accesses -system.cpu0.itb.inst_hits 4047811 # ITB inst hits -system.cpu0.itb.inst_misses 4513 # ITB inst misses +system.cpu0.dtb.hits 12373487 # DTB hits +system.cpu0.dtb.misses 43534 # DTB misses +system.cpu0.dtb.accesses 12417021 # DTB accesses +system.cpu0.itb.inst_hits 4018220 # ITB inst hits +system.cpu0.itb.inst_misses 4575 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -484,122 +481,122 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1822 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1835 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4052324 # ITB inst accesses -system.cpu0.itb.hits 4047811 # DTB hits -system.cpu0.itb.misses 4513 # DTB misses -system.cpu0.itb.accesses 4052324 # DTB accesses -system.cpu0.numCycles 58217040 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4022795 # ITB inst accesses +system.cpu0.itb.hits 4018220 # DTB hits +system.cpu0.itb.misses 4575 # DTB misses +system.cpu0.itb.accesses 4022795 # DTB accesses +system.cpu0.numCycles 58073431 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 5494906 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4166450 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 326433 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3744504 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2784648 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5437293 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4256353 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 316271 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3600228 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2674120 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 487236 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 65325 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 11075516 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 28672475 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5494906 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3271884 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 6845901 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1471988 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 58967 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 18678527 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 6609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 30991 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 80316 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4045687 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 176720 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3125 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 37812790 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.988034 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.366493 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 485080 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 65250 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11048158 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 28487074 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5437293 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3159200 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 6739880 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1438397 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 59633 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 18694595 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 6724 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 30266 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 80153 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 218 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4016097 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 175657 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3180 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 37672027 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.986348 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.372863 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30973406 81.91% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 543248 1.44% 83.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 812383 2.15% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 623093 1.65% 87.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 608176 1.61% 88.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 518047 1.37% 90.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 610247 1.61% 91.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 354921 0.94% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2769269 7.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30938102 82.12% 82.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 539295 1.43% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 754456 2.00% 85.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 605374 1.61% 87.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 572205 1.52% 88.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 499727 1.33% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 619840 1.65% 91.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 357335 0.95% 92.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2785693 7.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 37812790 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.094387 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.492510 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 11408065 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18778956 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6151939 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 496838 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 976992 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 873407 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 60147 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 35984632 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 191719 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 976992 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 11949753 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 4623091 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12461431 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6096265 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1705258 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 34697309 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 704 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 354137 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 881144 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 56 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 34828806 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 157685767 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 157645150 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 40617 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 26885345 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7943461 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 453210 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 414972 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4454682 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6732960 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5163615 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 859688 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 866427 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 32711333 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 727944 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 32879139 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 79039 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5868829 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13573267 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 126473 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 37812790 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.869524 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.504625 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 37672027 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.093628 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.490535 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 11376766 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18792478 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6048489 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 500890 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 953404 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 867804 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 60437 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 35787038 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 193524 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 953404 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 11914000 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 4629145 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12457249 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6001220 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1717009 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 34527596 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 766 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 354930 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 888723 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 49 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 34587688 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 157020073 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 156979210 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 40863 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 26885692 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7701996 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 453005 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 414730 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4495926 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6704710 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5162827 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 858153 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 869893 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 32576471 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 727676 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 32778157 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81649 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5740307 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13396786 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 126207 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 37672027 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.870093 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.506550 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 24425873 64.60% 64.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5253388 13.89% 78.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2719158 7.19% 85.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2012461 5.32% 91.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1865520 4.93% 95.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 793449 2.10% 98.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 530235 1.40% 99.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 162331 0.43% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 50375 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 24340985 64.61% 64.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5232872 13.89% 78.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2696429 7.16% 85.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2005933 5.32% 90.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1857666 4.93% 95.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 789251 2.10% 98.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 535159 1.42% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 163101 0.43% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 50631 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 37812790 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 37672027 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 17246 1.80% 1.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 470 0.05% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 17215 1.80% 1.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 476 0.05% 1.85% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available @@ -627,391 +624,388 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 745499 77.99% 79.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 192658 20.16% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 744103 77.93% 79.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 193089 20.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 14281 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 19663366 59.80% 59.85% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 43374 0.13% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 5 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1004 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8245355 25.08% 85.06% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4911741 14.94% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 19588840 59.76% 59.81% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 43482 0.13% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 8 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1004 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.94% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8219170 25.08% 85.02% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4911355 14.98% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 32879139 # Type of FU issued -system.cpu0.iq.rate 0.564768 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 955873 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.029072 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 104638650 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 39311978 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 30147071 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 10735 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5504 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4409 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 33814871 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5860 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 258705 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 32778157 # Type of FU issued +system.cpu0.iq.rate 0.564426 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 954883 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.029132 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 104296789 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 39048181 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 30070598 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 10781 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5570 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4438 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 33712886 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5873 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 258573 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1302867 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 9804 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 555393 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1274599 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3983 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 9698 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 554608 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1948839 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5274 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1948828 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5242 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 976992 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 3526747 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 77009 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 33493958 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 132151 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6732960 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5163615 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 457776 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 36292 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4432 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 9804 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 205793 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118466 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 324259 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 32446755 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8074532 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 432384 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 953404 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 3530697 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 77233 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 33359153 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 131395 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 6704710 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5162827 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 457179 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 36756 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4503 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 9698 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 188494 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 122646 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 311140 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 32365577 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8053232 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 412580 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 54681 # number of nop insts executed -system.cpu0.iew.exec_refs 12932399 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4282280 # Number of branches executed -system.cpu0.iew.exec_stores 4857867 # Number of stores executed -system.cpu0.iew.exec_rate 0.557341 # Inst execution rate -system.cpu0.iew.wb_sent 32234818 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 30151480 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 16076835 # num instructions producing a value -system.cpu0.iew.wb_consumers 31416355 # num instructions consuming a value +system.cpu0.iew.exec_nop 55006 # number of nop insts executed +system.cpu0.iew.exec_refs 12911062 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4264405 # Number of branches executed +system.cpu0.iew.exec_stores 4857830 # Number of stores executed +system.cpu0.iew.exec_rate 0.557322 # Inst execution rate +system.cpu0.iew.wb_sent 32156724 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 30075036 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 16051487 # num instructions producing a value +system.cpu0.iew.wb_consumers 31416706 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.517915 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.511735 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.517879 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.510922 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 20629504 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 27347391 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 5995379 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 601471 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 285121 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 36866578 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.741794 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.700144 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 20629701 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 27347563 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 5860569 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 601469 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 274713 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 36749403 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.744163 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.705264 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 26502705 71.89% 71.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5217604 14.15% 86.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1684301 4.57% 90.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 813710 2.21% 92.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 652862 1.77% 94.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 391356 1.06% 95.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 444768 1.21% 96.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 190957 0.52% 97.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 968315 2.63% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 26406070 71.85% 71.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5210331 14.18% 86.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1671532 4.55% 90.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 813872 2.21% 92.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 646917 1.76% 94.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 387096 1.05% 95.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 442946 1.21% 96.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 193384 0.53% 97.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 977255 2.66% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 36866578 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 20629504 # Number of instructions committed -system.cpu0.commit.committedOps 27347391 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 36749403 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 20629701 # Number of instructions committed +system.cpu0.commit.committedOps 27347563 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10038315 # Number of memory references committed -system.cpu0.commit.loads 5430093 # Number of loads committed +system.cpu0.commit.refs 10038330 # Number of memory references committed +system.cpu0.commit.loads 5430111 # Number of loads committed system.cpu0.commit.membars 201113 # Number of memory barriers committed -system.cpu0.commit.branches 3777887 # Number of branches committed +system.cpu0.commit.branches 3777893 # Number of branches committed system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 24270652 # Number of committed integer instructions. -system.cpu0.commit.function_calls 441072 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 968315 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 24270810 # Number of committed integer instructions. +system.cpu0.commit.function_calls 441070 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 977255 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 68594693 # The number of ROB reads -system.cpu0.rob.rob_writes 67665332 # The number of ROB writes -system.cpu0.timesIdled 379309 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 20404250 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5085681345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 20604950 # Number of Instructions Simulated -system.cpu0.committedOps 27322837 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 20604950 # Number of Instructions Simulated -system.cpu0.cpi 2.825391 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.825391 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.353933 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.353933 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 151241601 # number of integer regfile reads -system.cpu0.int_regfile_writes 29619273 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4540 # number of floating regfile reads -system.cpu0.fp_regfile_writes 420 # number of floating regfile writes -system.cpu0.misc_regfile_reads 40596238 # number of misc regfile reads -system.cpu0.misc_regfile_writes 457019 # number of misc regfile writes -system.cpu0.icache.replacements 364224 # number of replacements -system.cpu0.icache.tagsinuse 511.052791 # Cycle average of tags in use -system.cpu0.icache.total_refs 3649617 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 364736 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.006188 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 68333926 # The number of ROB reads +system.cpu0.rob.rob_writes 67371686 # The number of ROB writes +system.cpu0.timesIdled 379272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 20401404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5085475083 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 20605147 # Number of Instructions Simulated +system.cpu0.committedOps 27323009 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 20605147 # Number of Instructions Simulated +system.cpu0.cpi 2.818394 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.818394 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.354812 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.354812 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 150871425 # number of integer regfile reads +system.cpu0.int_regfile_writes 29495246 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4612 # number of floating regfile reads +system.cpu0.fp_regfile_writes 442 # number of floating regfile writes +system.cpu0.misc_regfile_reads 40364553 # number of misc regfile reads +system.cpu0.misc_regfile_writes 457015 # number of misc regfile writes +system.cpu0.icache.replacements 364779 # number of replacements +system.cpu0.icache.tagsinuse 511.052726 # Cycle average of tags in use +system.cpu0.icache.total_refs 3619396 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 365291 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.908254 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6333280000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.052791 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.052726 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998150 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998150 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3649617 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3649617 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3649617 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3649617 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3649617 # number of overall hits -system.cpu0.icache.overall_hits::total 3649617 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 395923 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 395923 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 395923 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 395923 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 395923 # number of overall misses -system.cpu0.icache.overall_misses::total 395923 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6038304987 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6038304987 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6038304987 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6038304987 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6038304987 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6038304987 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4045540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4045540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4045540 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4045540 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4045540 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4045540 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097867 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097867 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097867 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15251.210430 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1459990 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3619396 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3619396 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3619396 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3619396 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3619396 # number of overall hits +system.cpu0.icache.overall_hits::total 3619396 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 396554 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 396554 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 396554 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 396554 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 396554 # number of overall misses +system.cpu0.icache.overall_misses::total 396554 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6048062987 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6048062987 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6048062987 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6048062987 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6048062987 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6048062987 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4015950 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4015950 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4015950 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4015950 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4015950 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4015950 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.189393 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14169.402684 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41047.579950 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11439.884393 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10770.553257 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4293490 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2319000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 358 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 107 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11992.988827 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21672.897196 # average number of cycles each access was blocked +system.cpu0.dcache.demand_misses::cpu0.data 1804300 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1804300 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1804300 # number of overall misses +system.cpu0.dcache.overall_misses::total 1804300 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4785519500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4785519500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60142300903 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60142300903 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99268000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 99268000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83415000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 83415000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 64927820403 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 64927820403 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 64927820403 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 64927820403 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5324661 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5324661 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4177156 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4177156 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167434 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 167434 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 164045 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 164045 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9501817 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9501817 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9501817 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9501817 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063464 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351046 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051734 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047158 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.189890 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.189890 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14161.442150 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41014.298469 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11460.170861 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10782.704240 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35985.047056 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35985.047056 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4268990 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2272500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 373 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 104 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11445.013405 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21850.961538 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 213312 # number of writebacks -system.cpu0.dcache.writebacks::total 213312 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 173688 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 173688 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1346623 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1346623 # number of WriteReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 213485 # number of writebacks +system.cpu0.dcache.writebacks::total 213485 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174573 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 174573 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1346571 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1346571 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 614 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1520311 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1520311 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1520311 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1520311 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 163420 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 163420 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119833 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 119833 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8036 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8036 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1521144 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1521144 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1521144 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1521144 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 163353 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 163353 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119803 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 119803 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8048 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8048 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7735 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 7735 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 283253 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 283253 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 283253 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 283253 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2117873500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2117873500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4308779989 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4308779989 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66427000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66427000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60070500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60070500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426653489 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6426653489 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426653489 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6426653489 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9482117000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9482117000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 884866891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 884866891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10366983891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10366983891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030570 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028688 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047988 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047150 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12959.695876 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35956.539426 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8266.177203 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7766.063348 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_misses::cpu0.data 283156 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 283156 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 283156 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 283156 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2116822500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2116822500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4307053989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4307053989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66689500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66689500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60159000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60159000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6423876489 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6423876489 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6423876489 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6423876489 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9482121000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9482121000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 884869891 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 884869891 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10366990891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10366990891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030679 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028681 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048067 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047152 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029800 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029800 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12958.577437 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35951.136357 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8286.468688 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7777.504848 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22686.704463 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22686.704463 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 44928224 # DTB read hits -system.cpu1.dtb.read_misses 73602 # DTB read misses -system.cpu1.dtb.write_hits 7780505 # DTB write hits -system.cpu1.dtb.write_misses 20150 # DTB write misses +system.cpu1.dtb.read_hits 44907962 # DTB read hits +system.cpu1.dtb.read_misses 73330 # DTB read misses +system.cpu1.dtb.write_hits 7780018 # DTB write hits +system.cpu1.dtb.write_misses 20100 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2631 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 7056 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 592 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2652 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 7203 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 561 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 1808 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 45001826 # DTB read accesses -system.cpu1.dtb.write_accesses 7800655 # DTB write accesses +system.cpu1.dtb.perms_faults 1824 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 44981292 # DTB read accesses +system.cpu1.dtb.write_accesses 7800118 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 52708729 # DTB hits -system.cpu1.dtb.misses 93752 # DTB misses -system.cpu1.dtb.accesses 52802481 # DTB accesses -system.cpu1.itb.inst_hits 10224529 # ITB inst hits -system.cpu1.itb.inst_misses 7346 # ITB inst misses +system.cpu1.dtb.hits 52687980 # DTB hits +system.cpu1.dtb.misses 93430 # DTB misses +system.cpu1.dtb.accesses 52781410 # DTB accesses +system.cpu1.itb.inst_hits 10156376 # ITB inst hits +system.cpu1.itb.inst_misses 7457 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1024,503 +1018,503 @@ system.cpu1.itb.flush_entries 1545 # Nu system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 4985 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 5007 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10231875 # ITB inst accesses -system.cpu1.itb.hits 10224529 # DTB hits -system.cpu1.itb.misses 7346 # DTB misses -system.cpu1.itb.accesses 10231875 # DTB accesses -system.cpu1.numCycles 361675233 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10163833 # ITB inst accesses +system.cpu1.itb.hits 10156376 # DTB hits +system.cpu1.itb.misses 7457 # DTB misses +system.cpu1.itb.accesses 10163833 # DTB accesses +system.cpu1.numCycles 361463197 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 10827639 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 8483405 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 651414 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7693556 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 6128118 # Number of BTB hits +system.cpu1.BPredUnit.lookups 10782508 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 8772381 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 635923 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7402063 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5909244 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 880194 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 140008 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 23684849 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 77430542 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 10827639 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 7008312 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 16767403 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 5372389 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 95383 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 76264591 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5418 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 105344 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 159017 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 10219281 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 840043 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3905 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 120738841 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.782294 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.150601 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 873700 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 139717 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 23605299 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 77286787 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 10782508 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6782944 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 16557542 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 5336622 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 96051 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 76350866 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 106359 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 159348 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 263 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10151102 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 836280 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 4015 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 120517405 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.782275 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.157111 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 103983967 86.12% 86.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 1000458 0.83% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1336299 1.11% 88.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2219256 1.84% 89.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1499731 1.24% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 782401 0.65% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2303716 1.91% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 514923 0.43% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 7098090 5.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 103969658 86.27% 86.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 987113 0.82% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1198247 0.99% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2181121 1.81% 89.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1404675 1.17% 91.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 731318 0.61% 91.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2384511 1.98% 93.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 517678 0.43% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 7143084 5.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 120738841 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029937 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.214089 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 25308158 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76213029 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15039933 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 636285 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3541436 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1506236 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 117566 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 87857465 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 382082 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3541436 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 26899042 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32453857 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 39247498 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 14094152 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4502856 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 81303435 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2397 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 630313 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3163900 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 46270 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 85880003 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 375960450 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 375911455 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 48995 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 53654703 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 32225299 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 777903 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 702371 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8742657 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15637648 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 9415892 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1206366 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1577382 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 72765269 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1195198 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 96700645 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 136833 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 20828043 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 58949605 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 235739 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 120738841 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.800908 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.525223 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 120517405 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029830 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.213816 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 25233877 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76283550 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 14821072 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 657863 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3521043 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1494975 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 117774 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 87693964 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 382895 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3521043 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 26831414 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32478721 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 39236731 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 13889721 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4559775 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 81167341 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2581 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 635823 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3200516 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 46226 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 85740662 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 375398775 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 375349065 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 49710 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 53651640 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 32089021 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 776045 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 700116 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8935980 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15610664 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 9406979 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1201620 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1579608 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 72666150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1193677 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 96590201 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 142158 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 20735703 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 58926609 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 234264 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 120517405 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.801463 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.526860 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 86966093 72.03% 72.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10006677 8.29% 80.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4983433 4.13% 84.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4114228 3.41% 87.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 11017570 9.13% 96.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 2069642 1.71% 98.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1195614 0.99% 99.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 292428 0.24% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 93156 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86833748 72.05% 72.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9975019 8.28% 80.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4940804 4.10% 84.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4069487 3.38% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 11024826 9.15% 96.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 2090694 1.73% 98.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1200483 1.00% 99.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 289311 0.24% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 93033 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 120738841 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 120517405 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 40933 0.51% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 999 0.01% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7708137 95.31% 95.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 337009 4.17% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 40307 0.50% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 997 0.01% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7705811 95.37% 95.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 333073 4.12% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 92785 0.10% 0.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 42154384 43.59% 43.69% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 68643 0.07% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 27 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 32 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1443 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.76% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 46199078 47.78% 91.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 8184247 8.46% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 92768 0.10% 0.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 42073039 43.56% 43.65% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 68661 0.07% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 25 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 44 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1453 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 46174618 47.80% 91.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 8179589 8.47% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 96700645 # Type of FU issued -system.cpu1.iq.rate 0.267369 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 8087078 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.083630 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 322445450 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 94804325 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 60018746 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12063 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6724 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 104688665 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6273 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 377137 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 96590201 # Type of FU issued +system.cpu1.iq.rate 0.267220 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 8080188 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.083654 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 322001182 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 94611209 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 59943384 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12160 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6852 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5542 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 104571300 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6321 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 377653 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4715368 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6098 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 23303 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1781253 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4689619 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6336 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 23311 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1773508 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 32175806 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1149693 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 32175805 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1149678 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3541436 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25051723 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 357920 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 74130311 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 221482 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15637648 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 9415892 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 813116 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 58494 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 8530 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 23303 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 417083 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 225221 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 642304 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 93796024 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 45359703 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2904621 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3521043 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25065136 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 359091 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 74029865 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 214492 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15610664 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 9406979 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 810165 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 59786 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 8576 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 23311 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 385716 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 238696 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 624412 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 93721321 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 45339640 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2868880 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 169844 # number of nop insts executed -system.cpu1.iew.exec_refs 53443268 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7814764 # Number of branches executed -system.cpu1.iew.exec_stores 8083565 # Number of stores executed -system.cpu1.iew.exec_rate 0.259338 # Inst execution rate -system.cpu1.iew.wb_sent 92469231 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 60024243 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 32803499 # num instructions producing a value -system.cpu1.iew.wb_consumers 59096106 # num instructions consuming a value +system.cpu1.iew.exec_nop 170038 # number of nop insts executed +system.cpu1.iew.exec_refs 53422835 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7793526 # Number of branches executed +system.cpu1.iew.exec_stores 8083195 # Number of stores executed +system.cpu1.iew.exec_rate 0.259283 # Inst execution rate +system.cpu1.iew.wb_sent 92395030 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 59948926 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 32815937 # num instructions producing a value +system.cpu1.iew.wb_consumers 59243985 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.165962 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.555087 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.165851 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.553912 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 41355133 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 52673164 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 21398329 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 959459 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 564799 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 117251310 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.449233 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.403225 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 41354162 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 52669090 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 21302262 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 959413 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 549125 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 117050265 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.449970 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.406060 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 98126146 83.69% 83.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9730536 8.30% 91.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2573774 2.20% 94.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1441495 1.23% 95.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1191073 1.02% 96.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 709985 0.61% 97.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1084141 0.92% 97.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 501748 0.43% 98.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1892412 1.61% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97973751 83.70% 83.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9696174 8.28% 91.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2557084 2.18% 94.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1440070 1.23% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1185226 1.01% 96.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 698819 0.60% 97.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1094067 0.93% 97.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 501455 0.43% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1903619 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 117251310 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41355133 # Number of instructions committed -system.cpu1.commit.committedOps 52673164 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 117050265 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41354162 # Number of instructions committed +system.cpu1.commit.committedOps 52669090 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 18556919 # Number of memory references committed -system.cpu1.commit.loads 10922280 # Number of loads committed -system.cpu1.commit.membars 235767 # Number of memory barriers committed -system.cpu1.commit.branches 6572492 # Number of branches committed +system.cpu1.commit.refs 18554516 # Number of memory references committed +system.cpu1.commit.loads 10921045 # Number of loads committed +system.cpu1.commit.membars 235754 # Number of memory barriers committed +system.cpu1.commit.branches 6572629 # Number of branches committed system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 46935651 # Number of committed integer instructions. -system.cpu1.commit.function_calls 612387 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1892412 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 46931412 # Number of committed integer instructions. +system.cpu1.commit.function_calls 612362 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1903619 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 188242511 # The number of ROB reads -system.cpu1.rob.rob_writes 151809339 # The number of ROB writes -system.cpu1.timesIdled 1543775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 240936392 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4782922080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41229306 # Number of Instructions Simulated -system.cpu1.committedOps 52547337 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 41229306 # Number of Instructions Simulated -system.cpu1.cpi 8.772285 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.772285 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.113995 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.113995 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 421917398 # number of integer regfile reads -system.cpu1.int_regfile_writes 62840714 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4256 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1992 # number of floating regfile writes -system.cpu1.misc_regfile_reads 99685734 # number of misc regfile reads -system.cpu1.misc_regfile_writes 498572 # number of misc regfile writes -system.cpu1.icache.replacements 696666 # number of replacements -system.cpu1.icache.tagsinuse 498.774287 # Cycle average of tags in use -system.cpu1.icache.total_refs 9464320 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 697178 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.575185 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 187930171 # The number of ROB reads +system.cpu1.rob.rob_writes 151588010 # The number of ROB writes +system.cpu1.timesIdled 1544590 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 240945792 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4782780444 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41228335 # Number of Instructions Simulated +system.cpu1.committedOps 52543263 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 41228335 # Number of Instructions Simulated +system.cpu1.cpi 8.767349 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.767349 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.114060 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.114060 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 421568276 # number of integer regfile reads +system.cpu1.int_regfile_writes 62748878 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4369 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2038 # number of floating regfile writes +system.cpu1.misc_regfile_reads 99504542 # number of misc regfile reads +system.cpu1.misc_regfile_writes 498546 # number of misc regfile writes +system.cpu1.icache.replacements 696735 # number of replacements +system.cpu1.icache.tagsinuse 498.773379 # Cycle average of tags in use +system.cpu1.icache.total_refs 9395224 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 697247 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.474743 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74291126000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.774287 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974169 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974169 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 9464320 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9464320 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9464320 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9464320 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9464320 # number of overall hits -system.cpu1.icache.overall_hits::total 9464320 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 754908 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 754908 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 754908 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 754908 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 754908 # number of overall misses -system.cpu1.icache.overall_misses::total 754908 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11029274493 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11029274493 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11029274493 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11029274493 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11029274493 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11029274493 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10219228 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10219228 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10219228 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10219228 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10219228 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10219228 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073871 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073871 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073871 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14610.090889 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14610.090889 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14610.090889 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1452995 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 498.773379 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974167 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974167 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 9395224 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9395224 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9395224 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9395224 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9395224 # number of overall hits +system.cpu1.icache.overall_hits::total 9395224 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 755826 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 755826 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 755826 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 755826 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 755826 # number of overall misses +system.cpu1.icache.overall_misses::total 755826 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11037584991 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11037584991 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11037584991 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11037584991 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11037584991 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11037584991 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10151050 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10151050 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10151050 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10151050 # 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number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8247682495 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8247682495 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8247682495 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8247682495 # number of overall MSHR miss cycles +system.cpu1.icache.writebacks::writebacks 33229 # number of writebacks +system.cpu1.icache.writebacks::total 33229 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 58554 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 58554 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 58554 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 58554 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 58554 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8249763494 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8249763494 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11829.654585 # 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number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16653546 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16653546 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16653546 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16653546 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044559 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263430 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102854 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.079826 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.129335 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.129335 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15033.206785 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33391.295681 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12045.425645 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8474.183976 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29516.320008 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29516.320008 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 14003056 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5014500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3116 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 133 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4493.920411 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37703.007519 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 337861 # number of writebacks -system.cpu1.dcache.writebacks::total 337861 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 189374 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 189374 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1526129 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1526129 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1128 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1128 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1715503 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1715503 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1715503 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1715503 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 262523 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 262523 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 174609 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 174609 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12981 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12981 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10116 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10116 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 437132 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 437132 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 437132 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 437132 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3281013000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3281013000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5495017558 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5495017558 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 116690000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 116690000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55378500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 55378500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 337879 # number of writebacks +system.cpu1.dcache.writebacks::total 337879 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 192117 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 192117 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1524857 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1524857 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1136 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1136 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1716974 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1716974 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1716974 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1716974 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 262519 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 262519 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 174391 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 174391 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13019 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13019 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10105 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10105 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 436910 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 436910 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 436910 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 436910 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3282878000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3282878000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5492297055 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5492297055 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 117597000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 117597000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55303500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 55303500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2501 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2501 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8776030558 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8776030558 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8776030558 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8776030558 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137933382500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137933382500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41618386548 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41618386548 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179551769048 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179551769048 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025678 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094243 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.079867 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12498.002080 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31470.414228 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8989.292042 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5474.347568 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8775175055 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8775175055 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8775175055 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8775175055 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137933377000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137933377000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41618372048 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41618372048 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179551749048 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179551749048 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025729 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027035 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094600 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.079786 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12505.296759 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31494.154257 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.721407 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.884711 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20084.628539 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20084.628539 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -1539,16 +1533,16 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1308182536142 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1308182536142 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308183454966 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1308183454966 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308183454966 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1308183454966 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 38025 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 38029 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 59433 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 59437 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status index e41fe50a6..696134c20 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status @@ -1 +1 @@ -build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED! +build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED! diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 5275111e5..e0ab5975e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,13 +10,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.realview.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c7a1b63e2..9c3dda86e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:34:20 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:45:32 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 The currently selected ARM platforms doesn't support the amount of DRAM you've selected. Please try another platform Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503289265500 because m5_exit instruction encountered +Exiting @ tick 2503099557500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index c91fe0ed5..f897e20de 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503289 # Number of seconds simulated -sim_ticks 2503289265500 # Number of ticks simulated -final_tick 2503289265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503100 # Number of seconds simulated +sim_ticks 2503099557500 # Number of ticks simulated +final_tick 2503099557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65661 # Simulator instruction rate (inst/s) -host_op_rate 84813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2764710189 # Simulator tick rate (ticks/s) -host_mem_usage 389064 # Number of bytes of host memory used -host_seconds 905.44 # Real time elapsed on the host -sim_insts 59452703 # Number of instructions simulated -sim_ops 76793713 # Number of ops (including micro ops) simulated +host_inst_rate 80117 # Simulator instruction rate (inst/s) +host_op_rate 103484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3373282088 # Simulator tick rate (ticks/s) +host_mem_usage 383952 # Number of bytes of host memory used +host_seconds 742.04 # Real time elapsed on the host +sim_insts 59449445 # Number of instructions simulated +sim_ops 76789092 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,148 +20,148 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130753040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1118144 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9587720 # Number of bytes written to this memory -system.physmem.num_reads 15117482 # Number of read requests responded to by this memory -system.physmem.num_writes 856700 # Number of write requests responded to by this memory +system.physmem.bytes_read 130740776 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1120320 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9586312 # Number of bytes written to this memory +system.physmem.num_reads 15115704 # Number of read requests responded to by this memory +system.physmem.num_writes 856678 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52232493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 446670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3830049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56062542 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119784 # number of replacements -system.l2c.tagsinuse 26074.057253 # Cycle average of tags in use -system.l2c.total_refs 1841990 # Total number of references to valid blocks. -system.l2c.sampled_refs 150687 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.223948 # Average number of references to valid blocks. +system.physmem.bw_read 52231553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 447573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3829777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56061329 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119794 # number of replacements +system.l2c.tagsinuse 26073.611012 # Cycle average of tags in use +system.l2c.total_refs 1840774 # Total number of references to valid blocks. +system.l2c.sampled_refs 150725 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.212798 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14309.337346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 64.598044 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.929730 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6189.709081 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5509.483052 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.218343 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 14308.761179 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 64.610993 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.928498 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6189.887268 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5509.423074 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.218334 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000986 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(read+write) misses +system.l2c.ReadExReq_misses::cpu.data 140346 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140346 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 147 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 17347 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 159478 # number of demand (read+write) misses -system.l2c.demand_misses::total 176987 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 150 # number of overall misses +system.l2c.demand_misses::cpu.inst 17382 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 159492 # number of demand (read+write) misses +system.l2c.demand_misses::total 177033 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 147 # number of overall misses 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177033 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7686500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 617000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 910008500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1001033000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1919345000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1206000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1206000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7379766500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7379766500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 7686500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 617000 # number of demand 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accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 396465 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1577382 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 633173 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 633173 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3357 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246311 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246311 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 152723 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11555 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1015125 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 642800 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1822203 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 152723 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11555 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1015125 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 642800 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1822203 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001039 # miss rate for ReadReq accesses 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52295.753682 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 302.971188 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52587.905823 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52200 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 53583.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52411.771488 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52552.831739 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52200 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 53583.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52411.771488 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52552.831739 # average overall miss latency +system.l2c.ReadExReq_miss_rate::cpu.data 0.569963 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001028 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.017104 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.248159 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001028 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.017104 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.248159 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52289.115646 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 51416.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52353.497871 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52284.184686 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.020525 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52582.663560 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency 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(read+write) MSHR misses system.l2c.demand_mshr_misses::cpu.itb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 17335 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 159398 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 176894 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 150 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 17369 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 159413 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176940 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 147 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 17335 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 159398 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176894 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 6012000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 462000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 696908500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 765299500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1468682000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 134589000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 134589000 # number of UpgradeReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu.inst 17369 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 159413 # number of overall MSHR misses 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-system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636704500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5636704500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 6012000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 462000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 696908500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6402004000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7105386500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 6012000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 462000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 696908500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6402004000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7105386500 # number of overall MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636526500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5636526500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 442000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 697218500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6401601500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7105166000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5904000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 442000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 697218500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6401601500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7105166000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5507000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131761112000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131766619000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348627763 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32348627763 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131763880500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131769387500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348463263 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32348463263 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164109739763 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164115246763 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048087 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164112343763 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164117850763 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048093 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986893 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569735 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 42000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40202.394001 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40139.489143 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40392.857143 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569963 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40141.545282 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40125.609692 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40391.488077 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40166.922014 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40161.646930 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -278,27 +278,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51991464 # DTB read hits -system.cpu.dtb.read_misses 102104 # DTB read misses -system.cpu.dtb.write_hits 11910179 # DTB write hits -system.cpu.dtb.write_misses 24558 # DTB write misses +system.cpu.dtb.read_hits 51948606 # DTB read hits +system.cpu.dtb.read_misses 101816 # DTB read misses +system.cpu.dtb.write_hits 11910706 # DTB write hits +system.cpu.dtb.write_misses 24423 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4433 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5528 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 717 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4440 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5598 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 665 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2750 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52093568 # DTB read accesses -system.cpu.dtb.write_accesses 11934737 # DTB write accesses +system.cpu.dtb.perms_faults 2849 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52050422 # DTB read accesses +system.cpu.dtb.write_accesses 11935129 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63901643 # DTB hits -system.cpu.dtb.misses 126662 # DTB misses -system.cpu.dtb.accesses 64028305 # DTB accesses -system.cpu.itb.inst_hits 13706914 # ITB inst hits -system.cpu.itb.inst_misses 11634 # ITB inst misses +system.cpu.dtb.hits 63859312 # DTB hits +system.cpu.dtb.misses 126239 # DTB misses +system.cpu.dtb.accesses 63985551 # DTB accesses +system.cpu.itb.inst_hits 13611127 # ITB inst hits +system.cpu.itb.inst_misses 11794 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -307,504 +307,504 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2596 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2614 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 6661 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 6917 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13718548 # ITB inst accesses -system.cpu.itb.hits 13706914 # DTB hits -system.cpu.itb.misses 11634 # DTB misses -system.cpu.itb.accesses 13718548 # DTB accesses -system.cpu.numCycles 414369636 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13622921 # ITB inst accesses +system.cpu.itb.hits 13611127 # DTB hits +system.cpu.itb.misses 11794 # DTB misses +system.cpu.itb.accesses 13622921 # DTB accesses +system.cpu.numCycles 414035717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15625474 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12104785 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 954505 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11141912 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8550078 # Number of BTB hits +system.cpu.BPredUnit.lookups 15526652 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12489737 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 928336 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10678484 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8212324 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1319848 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 195832 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33026569 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 102466950 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15625474 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9869926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22757995 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6647547 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 147850 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92972764 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2992 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133718 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 218178 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 532 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13699500 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 999735 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6482 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 153797054 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.827732 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.202835 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1312295 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 195061 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32929499 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 102163781 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15526652 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9524619 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22440538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6579937 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 148688 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93080203 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 137545 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 217702 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13603433 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 995292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6599 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153452703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.827416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.209875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131058833 85.22% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1482677 0.96% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2033464 1.32% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2746838 1.79% 89.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2006274 1.30% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1249103 0.81% 91.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2843395 1.85% 93.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 830139 0.54% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9546331 6.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131028378 85.39% 85.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1463837 0.95% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1832687 1.19% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2690815 1.75% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1870921 1.22% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1178749 0.77% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2936419 1.91% 93.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 835625 0.54% 93.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9615272 6.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 153797054 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037709 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.247284 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35048577 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92898724 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20403369 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090511 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4355873 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2264859 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 184542 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119404764 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 595579 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4355873 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37137128 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36905254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49913788 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19399307 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6085704 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 111719644 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3150 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 969173 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3986800 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 44721 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 116183301 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 513866964 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 513772287 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 94677 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77497386 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38685914 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1179207 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1074915 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12764218 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21542479 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14020388 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1893002 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2399626 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101427658 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1855104 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 125968969 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 213520 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25665704 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69757934 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 355346 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 153797054 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819060 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523592 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 153452703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037501 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.246751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34954549 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92988756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20078806 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1116855 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4313737 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2248287 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 185454 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119076129 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 599477 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4313737 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37045133 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36926846 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49909637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19098925 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6158425 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 111441141 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3427 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 975111 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4036126 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 44783 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115828569 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 512776978 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 512681517 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 95461 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77492759 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38335809 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1177287 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1072928 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13010963 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21488170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14015818 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1893787 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2361029 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101216530 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1853504 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 125772492 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 220452 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25469081 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69618284 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 353864 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153452703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.525568 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108075061 70.27% 70.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14788281 9.62% 79.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7369782 4.79% 84.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5814520 3.78% 88.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12712346 8.27% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2776756 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693530 1.10% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 431004 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135774 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107878797 70.30% 70.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14731235 9.60% 79.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7302555 4.76% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5766685 3.76% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12704866 8.28% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797979 1.82% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1703854 1.11% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 430247 0.28% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 136485 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 153797054 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153452703 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 56704 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8414937 94.55% 95.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 428693 4.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 55588 0.63% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8410763 94.57% 95.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 427006 4.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59520968 47.25% 47.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95881 0.08% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 42 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 37 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2281 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53674365 42.61% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12568853 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59380040 47.21% 47.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95959 0.08% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 34 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 46 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2266 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53622551 42.63% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12565056 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 125968969 # Type of FU issued -system.cpu.iq.rate 0.304001 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8900337 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070655 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 414950878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128966853 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86636419 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24045 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13082 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10392 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134749943 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12833 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 592097 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 125772492 # Type of FU issued +system.cpu.iq.rate 0.303772 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8893360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070710 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 414213065 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128557320 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86496982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24084 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13214 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10457 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134546484 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12838 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 592105 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5860643 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10887 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32446 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2240776 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5807721 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11311 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32412 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2237013 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34115661 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1150165 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34115378 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1150417 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4355873 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28439880 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 429508 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103498796 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 345453 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21542479 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14020388 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1231045 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 92628 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11369 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32446 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 597024 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332843 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 929867 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122679068 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52684410 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3289901 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4313737 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28451597 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 431255 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103286909 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 337253 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21488170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14015818 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1227531 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 94319 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11225 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32412 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 548239 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 349587 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 897826 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122535537 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52641416 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3236955 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 216034 # number of nop insts executed -system.cpu.iew.exec_refs 65104045 # number of memory reference insts executed -system.cpu.iew.exec_branches 11571925 # Number of branches executed -system.cpu.iew.exec_stores 12419635 # Number of stores executed -system.cpu.iew.exec_rate 0.296062 # Inst execution rate -system.cpu.iew.wb_sent 121147574 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86646811 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46911516 # num instructions producing a value -system.cpu.iew.wb_consumers 86713430 # num instructions consuming a value +system.cpu.iew.exec_nop 216875 # number of nop insts executed +system.cpu.iew.exec_refs 65061832 # number of memory reference insts executed +system.cpu.iew.exec_branches 11533456 # Number of branches executed +system.cpu.iew.exec_stores 12420416 # Number of stores executed +system.cpu.iew.exec_rate 0.295954 # Inst execution rate +system.cpu.iew.wb_sent 121007788 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86507439 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46901063 # num instructions producing a value +system.cpu.iew.wb_consumers 86866563 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.209105 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.540995 # average fanout of values written-back +system.cpu.iew.wb_rate 0.208937 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.539921 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59603084 # The number of committed instructions -system.cpu.commit.commitCommittedOps 76944094 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26377882 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1499758 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 817257 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149523536 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514595 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.479322 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59599826 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76939473 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26171914 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499640 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 790317 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149221313 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.515606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.482610 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121178940 81.04% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14398423 9.63% 90.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4065564 2.72% 93.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2131324 1.43% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1770497 1.18% 96.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1046764 0.70% 96.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1546784 1.03% 97.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657861 0.44% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2727379 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120951257 81.05% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14347270 9.61% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4034652 2.70% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2127712 1.43% 94.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1768055 1.18% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1033434 0.69% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1556613 1.04% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657865 0.44% 98.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2744455 1.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149523536 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59603084 # Number of instructions committed -system.cpu.commit.committedOps 76944094 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149221313 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59599826 # Number of instructions committed +system.cpu.commit.committedOps 76939473 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27461448 # Number of memory references committed -system.cpu.commit.loads 15681836 # Number of loads committed -system.cpu.commit.membars 413071 # Number of memory barriers committed -system.cpu.commit.branches 9891470 # Number of branches committed +system.cpu.commit.refs 27459254 # Number of memory references committed +system.cpu.commit.loads 15680449 # Number of loads committed +system.cpu.commit.membars 413031 # Number of memory barriers committed +system.cpu.commit.branches 9890920 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68496808 # Number of committed integer instructions. -system.cpu.commit.function_calls 995631 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2727379 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68492585 # Number of committed integer instructions. +system.cpu.commit.function_calls 995546 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2744455 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 248361579 # The number of ROB reads -system.cpu.rob.rob_writes 211126300 # The number of ROB writes -system.cpu.timesIdled 1891134 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260572582 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592120905 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59452703 # Number of Instructions Simulated -system.cpu.committedOps 76793713 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59452703 # Number of Instructions Simulated -system.cpu.cpi 6.969736 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.969736 # CPI: Total CPI of All Threads -system.cpu.ipc 0.143477 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.143477 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556236612 # number of integer regfile reads -system.cpu.int_regfile_writes 88987615 # number of integer regfile writes -system.cpu.fp_regfile_reads 8813 # number of floating regfile reads -system.cpu.fp_regfile_writes 2942 # number of floating regfile writes -system.cpu.misc_regfile_reads 134801411 # number of misc regfile reads -system.cpu.misc_regfile_writes 912350 # number of misc regfile writes -system.cpu.icache.replacements 1015901 # number of replacements -system.cpu.icache.tagsinuse 511.619298 # Cycle average of tags in use -system.cpu.icache.total_refs 12592690 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1016413 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.389344 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 247831805 # The number of ROB reads +system.cpu.rob.rob_writes 210661614 # The number of ROB writes +system.cpu.timesIdled 1891867 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260583014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592075418 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59449445 # Number of Instructions Simulated +system.cpu.committedOps 76789092 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59449445 # Number of Instructions Simulated +system.cpu.cpi 6.964501 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.964501 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143585 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143585 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 555570054 # number of integer regfile reads +system.cpu.int_regfile_writes 88783658 # number of integer regfile writes +system.cpu.fp_regfile_reads 8868 # number of floating regfile reads +system.cpu.fp_regfile_writes 2963 # number of floating regfile writes +system.cpu.misc_regfile_reads 134383864 # number of misc regfile reads +system.cpu.misc_regfile_writes 912266 # number of misc regfile writes +system.cpu.icache.replacements 1016880 # number of replacements +system.cpu.icache.tagsinuse 511.619498 # Cycle average of tags in use +system.cpu.icache.total_refs 12495254 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1017392 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.281652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.619298 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999256 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999256 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12592690 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12592690 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12592690 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12592690 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12592690 # number of overall hits -system.cpu.icache.overall_hits::total 12592690 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1106667 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1106667 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1106667 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1106667 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1106667 # number of overall misses -system.cpu.icache.overall_misses::total 1106667 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16295196980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16295196980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16295196980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16295196980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16295196980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16295196980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13699357 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13699357 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13699357 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13699357 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13699357 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13699357 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080782 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.080782 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.080782 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.571149 # 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+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37229.421935 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.828938 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 23437.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.404643 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.404643 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16049941 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7647500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2833 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5665.351571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27910.583942 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16342936 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7612500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2868 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5698.373780 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28404.850746 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 574496 # number of writebacks -system.cpu.dcache.writebacks::total 574496 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346626 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 346626 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716633 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2716633 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1361 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1361 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3063259 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3063259 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3063259 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3063259 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387019 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387019 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249570 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249570 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12339 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12339 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 574454 # number of writebacks +system.cpu.dcache.writebacks::total 574454 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 348401 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 348401 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716534 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2716534 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1379 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064935 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064935 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064935 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064935 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386972 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386972 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249476 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249476 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12347 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12347 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636589 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636589 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636589 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636589 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265487500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265487500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926165441 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926165441 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165358500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165358500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 636448 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636448 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636448 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636448 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265104500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265104500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8925107436 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8925107436 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165722000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165722000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191652941 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14191652941 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191652941 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14191652941 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147155039500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147155039500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42275098470 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42275098470 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189430137970 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189430137970 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041128 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14190211936 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14190211936 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14190211936 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14190211936 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147157757000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147157757000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42274928970 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42274928970 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189432685970 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189432685970 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026054 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024385 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041200 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025335 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025335 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.242895 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35766.179593 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13401.288597 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.905595 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35775.415014 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13422.045841 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency @@ -823,14 +823,14 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307962166200 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307962166200 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307788731818 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307788731818 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 87991 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87981 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index c24180c55..5d521d8ff 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 4180d507c..2783a8301 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:00:24 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:17:26 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164280509500 because target called exit() +Exiting @ tick 164277874000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 65753c5e3..46c526502 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164281 # Number of seconds simulated -sim_ticks 164280509500 # Number of ticks simulated -final_tick 164280509500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164278 # Number of seconds simulated +sim_ticks 164277874000 # Number of ticks simulated +final_tick 164277874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 203818 # Simulator instruction rate (inst/s) -host_op_rate 215370 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58737354 # Simulator tick rate (ticks/s) -host_mem_usage 223536 # Number of bytes of host memory used -host_seconds 2796.87 # Real time elapsed on the host -sim_insts 570051663 # Number of instructions simulated -sim_ops 602359870 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5845888 # Number of bytes read from this memory -system.physmem.bytes_inst_read 49408 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3721728 # Number of bytes written to this memory -system.physmem.num_reads 91342 # Number of read requests responded to by this memory -system.physmem.num_writes 58152 # Number of write requests responded to by this memory +host_inst_rate 203470 # Simulator instruction rate (inst/s) +host_op_rate 215002 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58636208 # Simulator tick rate (ticks/s) +host_mem_usage 227276 # Number of bytes of host memory used +host_seconds 2801.65 # Real time elapsed on the host +sim_insts 570051643 # Number of instructions simulated +sim_ops 602359850 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 5845952 # Number of bytes read from this memory +system.physmem.bytes_inst_read 50048 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3721408 # Number of bytes written to this memory +system.physmem.num_reads 91343 # Number of read requests responded to by this memory +system.physmem.num_writes 58147 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 35584793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 300754 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 22654714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 58239508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 35585754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 304655 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 22653130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 58238884 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,141 +64,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 328561020 # number of cpu cycles simulated +system.cpu.numCycles 328555749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85502166 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80303538 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2364558 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47128818 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46810492 # Number of BTB hits +system.cpu.BPredUnit.lookups 85495228 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80299392 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2363839 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47188450 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46808758 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1441322 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2014 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68931697 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669727391 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85502166 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48251814 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130042659 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13473975 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 117702916 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67497554 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 807456 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 327710434 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.177756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.200257 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1441266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2064 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68932526 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669692235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85495228 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48250024 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130038876 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13469589 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117716369 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 673 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67498352 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 807371 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 327717199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.177607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.200173 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 197667987 60.32% 60.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20955558 6.39% 66.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4944545 1.51% 68.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14317291 4.37% 72.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8979833 2.74% 75.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9404994 2.87% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4387469 1.34% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5814392 1.77% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61238365 18.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 197678537 60.32% 60.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20955398 6.39% 66.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4944268 1.51% 68.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14317146 4.37% 72.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8982056 2.74% 75.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9405272 2.87% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4386310 1.34% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5814100 1.77% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61234112 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 327710434 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260232 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.038365 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93127005 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94874868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108614475 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20063382 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11030704 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4784748 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1773 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 706010986 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5362 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11030704 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107410901 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13982712 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 118932 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114322879 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80844306 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697216799 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 201 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59255173 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19368550 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 660 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723821711 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241352610 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241352482 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 327717199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260215 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.038291 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93143264 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94872868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108628769 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20045238 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11027060 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4784060 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1759 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 705973468 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5432 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11027060 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107429081 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13945008 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 118563 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114317154 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80880333 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697178999 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 231 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59283430 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 19375407 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 624 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723780453 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241174730 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241174602 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417498 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96404213 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11542 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11540 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169974240 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172906537 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80619433 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21532364 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 27969964 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681972253 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9148 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646841509 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1424100 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79435960 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197814866 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2789 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 327710434 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.973820 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.737996 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417466 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96362987 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11553 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11552 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169904976 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172902366 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80616631 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21434396 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 27805052 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681951411 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 9116 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646829241 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1424329 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79415012 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197703011 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2761 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 327717199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.973742 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.738606 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68514298 20.91% 20.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 84850419 25.89% 46.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75242172 22.96% 69.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40564366 12.38% 82.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28638763 8.74% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15215694 4.64% 95.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5886369 1.80% 97.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6524912 1.99% 99.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2273441 0.69% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68508405 20.90% 20.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84956160 25.92% 46.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75144846 22.93% 69.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40581693 12.38% 82.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28626833 8.74% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15169754 4.63% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5928523 1.81% 97.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6496810 1.98% 99.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2304175 0.70% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 327710434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 327717199 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205233 5.10% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2909479 72.37% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 905756 22.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 204843 5.11% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2907010 72.53% 77.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 896423 22.36% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403929410 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6579 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403920439 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -226,153 +226,153 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166116267 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76789250 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166108811 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76793420 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646841509 # Type of FU issued -system.cpu.iq.rate 1.968710 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4020468 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006216 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1626837984 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761428768 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638548229 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646829241 # Type of FU issued +system.cpu.iq.rate 1.968705 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4008276 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006197 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1626808250 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761386923 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638549644 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650861957 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650837497 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30419634 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30424903 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23953929 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 128648 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11649 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10398406 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23949762 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 129784 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11648 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10395608 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12846 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12456 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12818 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12531 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11030704 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 854813 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 57677 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682047620 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 663984 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172906537 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80619433 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7812 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12999 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4667 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11649 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1314819 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1584401 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2899220 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642689835 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163986431 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4151674 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11027060 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 853408 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 62572 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682026706 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 660555 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172902366 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80616631 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7782 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13060 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6245 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11648 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1315368 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1582506 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2897874 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642687405 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163985784 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4141836 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66219 # number of nop insts executed -system.cpu.iew.exec_refs 239991845 # number of memory reference insts executed -system.cpu.iew.exec_branches 74670108 # Number of branches executed -system.cpu.iew.exec_stores 76005414 # Number of stores executed -system.cpu.iew.exec_rate 1.956075 # Inst execution rate -system.cpu.iew.wb_sent 640041427 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638548245 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420154647 # num instructions producing a value -system.cpu.iew.wb_consumers 654937446 # num instructions consuming a value +system.cpu.iew.exec_nop 66179 # number of nop insts executed +system.cpu.iew.exec_refs 239997187 # number of memory reference insts executed +system.cpu.iew.exec_branches 74667058 # Number of branches executed +system.cpu.iew.exec_stores 76011403 # Number of stores executed +system.cpu.iew.exec_rate 1.956098 # Inst execution rate +system.cpu.iew.wb_sent 640040588 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638549660 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420197588 # num instructions producing a value +system.cpu.iew.wb_consumers 654962025 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.943469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.641519 # average fanout of values written-back +system.cpu.iew.wb_rate 1.943505 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641560 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 570051714 # The number of committed instructions -system.cpu.commit.commitCommittedOps 602359921 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 79697124 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6359 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2424958 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 316679731 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.902111 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.239397 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 570051694 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602359901 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 79676133 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6355 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2424230 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 316690140 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.902048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.239406 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 92723381 29.28% 29.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103992421 32.84% 62.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43071500 13.60% 75.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8912974 2.81% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25679598 8.11% 86.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13104188 4.14% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7581196 2.39% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1156714 0.37% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20457759 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92731092 29.28% 29.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104002875 32.84% 62.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43058477 13.60% 75.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8922442 2.82% 78.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25674548 8.11% 86.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13103987 4.14% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7582493 2.39% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1154147 0.36% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20460079 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 316679731 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570051714 # Number of instructions committed -system.cpu.commit.committedOps 602359921 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 316690140 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570051694 # Number of instructions committed +system.cpu.commit.committedOps 602359901 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173635 # Number of memory references committed -system.cpu.commit.loads 148952608 # Number of loads committed +system.cpu.commit.refs 219173627 # Number of memory references committed +system.cpu.commit.loads 148952604 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828615 # Number of branches committed +system.cpu.commit.branches 70828611 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522695 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522679 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20457759 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20460079 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 978278405 # The number of ROB reads -system.cpu.rob.rob_writes 1375177371 # The number of ROB writes -system.cpu.timesIdled 40898 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 850586 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570051663 # Number of Instructions Simulated -system.cpu.committedOps 602359870 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570051663 # Number of Instructions Simulated -system.cpu.cpi 0.576371 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.576371 # CPI: Total CPI of All Threads -system.cpu.ipc 1.734995 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.734995 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210435772 # number of integer regfile reads -system.cpu.int_regfile_writes 664215714 # number of integer regfile writes +system.cpu.rob.rob_reads 978265483 # The number of ROB reads +system.cpu.rob.rob_writes 1375131668 # The number of ROB writes +system.cpu.timesIdled 36876 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 838550 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570051643 # Number of Instructions Simulated +system.cpu.committedOps 602359850 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570051643 # Number of Instructions Simulated +system.cpu.cpi 0.576361 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.576361 # CPI: Total CPI of All Threads +system.cpu.ipc 1.735023 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.735023 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210434144 # number of integer regfile reads +system.cpu.int_regfile_writes 664206400 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905058829 # number of misc regfile reads -system.cpu.misc_regfile_writes 2684 # number of misc regfile writes -system.cpu.icache.replacements 57 # number of replacements -system.cpu.icache.tagsinuse 691.796995 # Cycle average of tags in use -system.cpu.icache.total_refs 67496461 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 810 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 83328.964198 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905030713 # number of misc regfile reads +system.cpu.misc_regfile_writes 2676 # number of misc regfile writes +system.cpu.icache.replacements 62 # number of replacements +system.cpu.icache.tagsinuse 695.805278 # Cycle average of tags in use +system.cpu.icache.total_refs 67497251 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 819 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 82414.225885 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 691.796995 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.337792 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.337792 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67496461 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67496461 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67496461 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67496461 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67496461 # number of overall hits -system.cpu.icache.overall_hits::total 67496461 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1093 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1093 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1093 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1093 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1093 # number of overall misses -system.cpu.icache.overall_misses::total 1093 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37450500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37450500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37450500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37450500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37450500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37450500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67497554 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67497554 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67497554 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67497554 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67497554 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67497554 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 695.805278 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.339749 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.339749 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67497251 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67497251 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67497251 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67497251 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67497251 # number of overall hits +system.cpu.icache.overall_hits::total 67497251 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1101 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1101 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1101 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1101 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1101 # number of overall misses +system.cpu.icache.overall_misses::total 1101 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37785500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37785500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37785500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37785500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37785500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37785500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67498352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67498352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67498352 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67498352 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67498352 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67498352 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34263.952425 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34263.952425 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34263.952425 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34319.255223 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34319.255223 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34319.255223 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,264 +387,260 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 282 system.cpu.icache.demand_mshr_hits::total 282 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 282 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 282 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 811 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 811 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 811 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 811 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 811 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 811 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27589000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27589000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27589000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27589000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27589000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27589000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27945500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27945500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27945500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27945500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27945500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27945500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34018.495684 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34018.495684 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34018.495684 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34121.489621 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34121.489621 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34121.489621 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440437 # number of replacements -system.cpu.dcache.tagsinuse 4094.648264 # Cycle average of tags in use -system.cpu.dcache.total_refs 199949450 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444533 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 449.796641 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 88384000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.648264 # Average occupied blocks per requestor +system.cpu.dcache.replacements 440502 # number of replacements +system.cpu.dcache.tagsinuse 4094.647718 # Cycle average of tags in use +system.cpu.dcache.total_refs 199930074 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444598 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 449.687300 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 88231000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.647718 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999670 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999670 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 132073030 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 132073030 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 67873619 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 67873619 # number of WriteReq hits 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249429 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 249429 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1556685 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1556685 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 16 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 16 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1793244 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1793244 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1793244 # number of overall misses -system.cpu.dcache.overall_misses::total 1793244 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286822500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3286822500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27023570462 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27023570462 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 163000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 163000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30310392962 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30310392962 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30310392962 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30310392962 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 132322362 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 132322362 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1806114 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1806114 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1806114 # number of overall misses +system.cpu.dcache.overall_misses::total 1806114 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3287429500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3287429500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27038709023 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27038709023 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 163500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 163500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30326138523 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30326138523 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30326138523 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30326138523 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 132315854 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 132315854 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1473 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1473 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1341 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1341 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201739893 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201739893 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201739893 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201739893 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022241 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.010862 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008889 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008889 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13182.513677 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17503.310073 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16902.548098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16902.548098 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9610962 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1482 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1482 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1337 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1337 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201733385 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201733385 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201733385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201733385 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001885 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022425 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.010796 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008953 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13179.820711 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17369.415793 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10218.750000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16790.821910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16790.821910 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9531023 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2243 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2188 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4284.869371 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4356.043419 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 394903 # number of writebacks -system.cpu.dcache.writebacks::total 394903 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51902 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51902 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1296808 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1296808 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 394920 # number of writebacks +system.cpu.dcache.writebacks::total 394920 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51943 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51943 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1309572 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1309572 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 16 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 16 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1348710 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1348710 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1348710 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1348710 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197430 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197430 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247104 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247104 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444534 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444534 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444534 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444534 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1628736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1628736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2539917962 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2539917962 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4168653962 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4168653962 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4168653962 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4168653962 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1361515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1361515 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1361515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1361515 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197486 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197486 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247113 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247113 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444599 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444599 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444599 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444599 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1627372000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1627372000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2541087023 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2541087023 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4168459023 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4168459023 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4168459023 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4168459023 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001493 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8249.688497 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10278.740781 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9377.581832 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9377.581832 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.442360 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10283.097300 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9375.772377 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9375.772377 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73146 # number of replacements -system.cpu.l2cache.tagsinuse 17814.384262 # Cycle average of tags in use -system.cpu.l2cache.total_refs 421358 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88668 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.752086 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73147 # number of replacements +system.cpu.l2cache.tagsinuse 17814.593774 # Cycle average of tags in use +system.cpu.l2cache.total_refs 421447 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88664 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.753305 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15926.079835 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 36.897354 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1851.407073 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.486025 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001126 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.056500 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average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31117.647059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31172.894513 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31117.647059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31172.894513 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index 35f1e8fcc..f06b9ec67 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index 80be44c4e..f3821c915 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu sim_ticks 301191370000 # Number of ticks simulated final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3224710 # Simulator instruction rate (inst/s) -host_op_rate 3407474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1703801368 # Simulator tick rate (ticks/s) -host_mem_usage 212692 # Number of bytes of host memory used -host_seconds 176.78 # Real time elapsed on the host +host_inst_rate 3323130 # Simulator instruction rate (inst/s) +host_op_rate 3511472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1755802369 # Simulator tick rate (ticks/s) +host_mem_usage 216428 # Number of bytes of host memory used +host_seconds 171.54 # Real time elapsed on the host sim_insts 570051644 # Number of instructions simulated sim_ops 602359851 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2680160157 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 602359851 # Nu system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67018854 # number of instructions that are conditional controls system.cpu.num_int_insts 533522639 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index ce56af1f4..14843a60a 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 4b6f6b404..52945d306 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.796763 # Nu sim_ticks 796762926000 # Number of ticks simulated final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1806630 # Simulator instruction rate (inst/s) -host_op_rate 1907867 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2531848956 # Simulator tick rate (ticks/s) -host_mem_usage 221588 # Number of bytes of host memory used -host_seconds 314.70 # Real time elapsed on the host +host_inst_rate 1880906 # Simulator instruction rate (inst/s) +host_op_rate 1986306 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2635941289 # Simulator tick rate (ticks/s) +host_mem_usage 225340 # Number of bytes of host memory used +host_seconds 302.27 # Real time elapsed on the host sim_insts 568539343 # Number of instructions simulated sim_ops 600398281 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5759488 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 600398281 # Nu system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67018854 # number of instructions that are conditional controls system.cpu.num_int_insts 533522639 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index ae17312a7..f9650cc7f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:268435455 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 2b7b5d7d4..bd690b9dd 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:09:43 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:17:26 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 30872383000 because target called exit() +Exiting @ tick 30004011500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 8b866508b..c606c0251 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.030872 # Number of seconds simulated -sim_ticks 30872383000 # Number of ticks simulated -final_tick 30872383000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.030004 # Number of seconds simulated +sim_ticks 30004011500 # Number of ticks simulated +final_tick 30004011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 191980 # Simulator instruction rate (inst/s) -host_op_rate 193358 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65418525 # Simulator tick rate (ticks/s) -host_mem_usage 356268 # Number of bytes of host memory used -host_seconds 471.92 # Real time elapsed on the host -sim_insts 90599371 # Number of instructions simulated -sim_ops 91249925 # Number of ops (including micro ops) simulated +host_inst_rate 194545 # Simulator instruction rate (inst/s) +host_op_rate 195941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64427791 # Simulator tick rate (ticks/s) +host_mem_usage 360100 # Number of bytes of host memory used +host_seconds 465.70 # Real time elapsed on the host +sim_insts 90599351 # Number of instructions simulated +sim_ops 91249905 # Number of ops (including micro ops) simulated system.physmem.bytes_read 997760 # Number of bytes read from this memory -system.physmem.bytes_inst_read 44992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read 45184 # Number of instructions bytes read from this memory system.physmem.bytes_written 2048 # Number of bytes written to this memory system.physmem.num_reads 15590 # Number of read requests responded to by this memory system.physmem.num_writes 32 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 32318853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1457354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 66338 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 32385190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 33254220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1505932 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 68258 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 33322478 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 61744767 # number of cpu cycles simulated +system.cpu.numCycles 60008024 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27625975 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21961767 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1057803 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12484908 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 12217504 # Number of BTB hits +system.cpu.BPredUnit.lookups 26814888 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22097408 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 908993 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11644795 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11349875 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 63839 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 9989 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14937013 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 131159638 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27625975 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12281343 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25187217 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5166004 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 17501831 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 60971 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 9988 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14353439 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128015722 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26814888 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11410846 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24114191 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4769366 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 17672895 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 968 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14529102 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 404990 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 61714285 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.143323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.095410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1085 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 13983254 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 369829 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 59980295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.152543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.127200 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 36568128 59.25% 59.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3588248 5.81% 65.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2263683 3.67% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1635825 2.65% 71.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2193562 3.55% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3029199 4.91% 79.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1536493 2.49% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1081808 1.75% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9817339 15.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 35906918 59.86% 59.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3423177 5.71% 65.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2008077 3.35% 68.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1555866 2.59% 71.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1665852 2.78% 74.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2959461 4.93% 79.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1530954 2.55% 81.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1083113 1.81% 83.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9846877 16.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 61714285 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.447422 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.124223 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17894765 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15294092 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23449441 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 997710 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4078277 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4446063 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 9028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 129128963 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42641 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4078277 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19986704 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1990048 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8372890 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 22331092 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4955274 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124988307 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 34 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 274534 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3719943 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 334 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145477524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 543658099 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 543650283 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7816 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429503 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38048021 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 624217 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 628906 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13326064 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29929002 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5552922 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1387770 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 675384 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118695204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 614278 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105786177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 44246 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27759340 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68809466 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 59426 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 61714285 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.714128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.857544 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 59980295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.446855 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.133310 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17244522 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15439127 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22437836 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1028996 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3829814 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4444165 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8973 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126393401 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 43020 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3829814 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19245787 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2026344 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8384525 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21437306 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5056519 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122679258 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 280519 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3795375 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 142938307 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 534568737 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 534562281 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6456 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429471 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35508836 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 621620 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 624255 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13585300 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29418557 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5501060 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1379571 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 681227 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 117000498 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 611217 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 104991352 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 35829 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26158745 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 64243821 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 56369 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 59980295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.750431 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.873941 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21784376 35.30% 35.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13573552 21.99% 57.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8691007 14.08% 71.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6574195 10.65% 82.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4926850 7.98% 90.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2861627 4.64% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2480649 4.02% 98.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 367635 0.60% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 454394 0.74% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20705588 34.52% 34.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13184290 21.98% 56.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8487470 14.15% 70.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6459646 10.77% 81.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4931435 8.22% 89.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2870978 4.79% 94.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2481638 4.14% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 391274 0.65% 99.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 467976 0.78% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 61714285 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 59980295 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 29792 4.51% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 350883 53.15% 57.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 279419 42.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31457 4.81% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 343779 52.58% 57.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 278563 42.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74674896 70.59% 70.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10966 0.01% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 250 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 304 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25913310 24.50% 95.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5186446 4.90% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74214604 70.69% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10958 0.01% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 201 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 251 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25591383 24.37% 95.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5173950 4.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105786177 # Type of FU issued -system.cpu.iq.rate 1.713282 # Inst issue rate -system.cpu.iq.fu_busy_cnt 660121 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006240 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 273989825 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 147067719 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102775878 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1181 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1722 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 504 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106445710 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 588 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 360974 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 104991352 # Type of FU issued +system.cpu.iq.rate 1.749622 # Inst issue rate +system.cpu.iq.fu_busy_cnt 653826 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006227 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 270651681 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 143770389 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102345485 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 973 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1384 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 418 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105644695 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 483 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 378050 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7353122 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24732 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 910 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 806165 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6842681 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 23943 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1595 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 754307 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 206 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30723 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 497 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30477 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4078277 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 189303 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 32978 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119345782 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 472137 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29929002 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5552922 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 610367 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13002 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 909 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 910 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 660488 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 474136 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1134624 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104503498 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25461820 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1282679 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3829814 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 196269 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 34070 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 117648153 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 398714 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29418557 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5501060 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 607315 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13787 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1140 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1595 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 486496 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 484094 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 970590 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 103957070 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25266637 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1034282 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 36300 # number of nop insts executed -system.cpu.iew.exec_refs 30578127 # number of memory reference insts executed -system.cpu.iew.exec_branches 21320345 # Number of branches executed -system.cpu.iew.exec_stores 5116307 # Number of stores executed -system.cpu.iew.exec_rate 1.692508 # Inst execution rate -system.cpu.iew.wb_sent 103143555 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102776382 # cumulative count of insts written-back -system.cpu.iew.wb_producers 60808791 # num instructions producing a value -system.cpu.iew.wb_consumers 98854571 # num instructions consuming a value +system.cpu.iew.exec_nop 36438 # number of nop insts executed +system.cpu.iew.exec_refs 30369134 # number of memory reference insts executed +system.cpu.iew.exec_branches 21275406 # Number of branches executed +system.cpu.iew.exec_stores 5102497 # Number of stores executed +system.cpu.iew.exec_rate 1.732386 # Inst execution rate +system.cpu.iew.wb_sent 102646599 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102345903 # cumulative count of insts written-back +system.cpu.iew.wb_producers 60560786 # num instructions producing a value +system.cpu.iew.wb_consumers 98602756 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.664536 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.615134 # average fanout of values written-back +system.cpu.iew.wb_rate 1.705537 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.614190 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 90611980 # The number of committed instructions -system.cpu.commit.commitCommittedOps 91262534 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 28084875 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554852 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1060689 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 57636009 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.583429 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.316969 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 90611960 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91262514 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26386952 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 554848 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 912021 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 56150482 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.625320 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.343724 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25053220 43.47% 43.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15762866 27.35% 70.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4731133 8.21% 79.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3928107 6.82% 85.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1673357 2.90% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 949808 1.65% 90.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 650100 1.13% 91.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 189331 0.33% 91.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4698087 8.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23848704 42.47% 42.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15483848 27.58% 70.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4738925 8.44% 78.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3887159 6.92% 85.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1619823 2.88% 88.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 955795 1.70% 90.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 662165 1.18% 91.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 224422 0.40% 91.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4729641 8.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 57636009 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611980 # Number of instructions committed -system.cpu.commit.committedOps 91262534 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 56150482 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611960 # Number of instructions committed +system.cpu.commit.committedOps 91262514 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322637 # Number of memory references committed -system.cpu.commit.loads 22575880 # Number of loads committed +system.cpu.commit.refs 27322629 # Number of memory references committed +system.cpu.commit.loads 22575876 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722474 # Number of branches committed +system.cpu.commit.branches 18722470 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533334 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533318 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4698087 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4729641 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 172279597 # The number of ROB reads -system.cpu.rob.rob_writes 242795229 # The number of ROB writes -system.cpu.timesIdled 1482 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30482 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599371 # Number of Instructions Simulated -system.cpu.committedOps 91249925 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599371 # Number of Instructions Simulated -system.cpu.cpi 0.681514 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.681514 # CPI: Total CPI of All Threads -system.cpu.ipc 1.467321 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.467321 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 496888008 # number of integer regfile reads -system.cpu.int_regfile_writes 120864998 # number of integer regfile writes -system.cpu.fp_regfile_reads 242 # number of floating regfile reads -system.cpu.fp_regfile_writes 665 # number of floating regfile writes -system.cpu.misc_regfile_reads 184727514 # number of misc regfile reads -system.cpu.misc_regfile_writes 11610 # number of misc regfile writes +system.cpu.rob.rob_reads 169064573 # The number of ROB reads +system.cpu.rob.rob_writes 239150312 # The number of ROB writes +system.cpu.timesIdled 1544 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27729 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599351 # Number of Instructions Simulated +system.cpu.committedOps 91249905 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599351 # Number of Instructions Simulated +system.cpu.cpi 0.662345 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.662345 # CPI: Total CPI of All Threads +system.cpu.ipc 1.509787 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.509787 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 494492343 # number of integer regfile reads +system.cpu.int_regfile_writes 120192106 # number of integer regfile writes +system.cpu.fp_regfile_reads 207 # number of floating regfile reads +system.cpu.fp_regfile_writes 538 # number of floating regfile writes +system.cpu.misc_regfile_reads 181239075 # number of misc regfile reads +system.cpu.misc_regfile_writes 11602 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 619.944154 # Cycle average of tags in use -system.cpu.icache.total_refs 14528145 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 728 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19956.243132 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 625.228438 # Cycle average of tags in use +system.cpu.icache.total_refs 13982297 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 731 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19127.629275 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 619.944154 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.302707 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.302707 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14528145 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14528145 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14528145 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14528145 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14528145 # number of overall hits -system.cpu.icache.overall_hits::total 14528145 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 625.228438 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.305287 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.305287 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13982297 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13982297 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13982297 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13982297 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13982297 # number of overall hits +system.cpu.icache.overall_hits::total 13982297 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses system.cpu.icache.overall_misses::total 957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33256500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33256500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33256500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33256500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33256500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33256500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14529102 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14529102 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14529102 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14529102 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14529102 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14529102 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34750.783699 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34750.783699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34750.783699 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33318000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33318000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33318000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33318000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33318000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33318000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13983254 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13983254 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13983254 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13983254 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13983254 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13983254 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000068 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000068 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000068 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34815.047022 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34815.047022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34815.047022 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,214 +382,214 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 229 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 229 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 229 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 728 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 728 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 728 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 728 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 728 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 728 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24950500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24950500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24950500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24950500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24950500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24950500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000050 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000050 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000050 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34272.664835 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34272.664835 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34272.664835 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 226 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 226 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 226 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 226 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 731 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 731 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 731 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 731 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 731 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 731 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25047000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25047000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25047000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25047000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25047000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25047000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34264.021888 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34264.021888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34264.021888 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943467 # number of replacements -system.cpu.dcache.tagsinuse 3573.833384 # Cycle average of tags in use -system.cpu.dcache.total_refs 28543530 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947563 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.123095 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11199321000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3573.833384 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.872518 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.872518 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23972222 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23972222 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4559610 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4559610 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5898 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5898 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5800 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5800 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28531832 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28531832 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28531832 # number of overall hits -system.cpu.dcache.overall_hits::total 28531832 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 990009 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 990009 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 175371 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 175371 # number of WriteReq misses +system.cpu.dcache.replacements 943524 # number of replacements +system.cpu.dcache.tagsinuse 3583.229064 # Cycle average of tags in use +system.cpu.dcache.total_refs 28391066 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947620 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.960391 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10655820000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3583.229064 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.874812 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.874812 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23819030 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23819030 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4560353 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4560353 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5796 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5796 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28379383 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28379383 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28379383 # number of overall hits +system.cpu.dcache.overall_hits::total 28379383 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 991638 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 991638 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 174628 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 174628 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1165380 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1165380 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1165380 # number of overall misses -system.cpu.dcache.overall_misses::total 1165380 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5599290000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5599290000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4531637443 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4531637443 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 127000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10130927443 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10130927443 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10130927443 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10130927443 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24962231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24962231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1166266 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1166266 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1166266 # number of overall misses +system.cpu.dcache.overall_misses::total 1166266 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5615598500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5615598500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4530256968 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4530256968 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 129500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10145855468 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10145855468 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10145855468 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10145855468 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24810668 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24810668 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5906 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5800 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5800 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29697212 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29697212 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29697212 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29697212 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039660 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037037 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039242 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039242 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5655.797069 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25840.289689 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15875 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8693.239495 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8693.239495 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23215506 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5796 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5796 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29545649 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29545649 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29545649 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29545649 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039968 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036880 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001357 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039473 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039473 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5662.952106 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25942.328653 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8699.435179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8699.435179 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23124041 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8117 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8085 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.109154 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.116388 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942867 # number of writebacks -system.cpu.dcache.writebacks::total 942867 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86758 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 86758 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131059 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 131059 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942876 # number of writebacks +system.cpu.dcache.writebacks::total 942876 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87943 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 87943 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 130703 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 130703 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 217817 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 217817 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 217817 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 217817 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903251 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903251 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 44312 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 44312 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947563 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947563 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947563 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947563 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2324909500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2324909500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1081042568 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1081042568 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3405952068 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3405952068 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3405952068 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3405952068 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036185 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031907 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031907 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2573.935152 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24396.158332 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3594.433371 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3594.433371 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 218646 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 218646 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 218646 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 218646 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903695 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903695 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43925 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43925 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947620 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947620 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947620 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947620 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2331156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2331156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1079888101 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1079888101 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3411044601 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3411044601 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3411044601 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3411044601 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036424 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032073 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032073 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2579.583266 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24584.817325 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3599.591187 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3599.591187 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 755 # number of replacements -system.cpu.l2cache.tagsinuse 9376.851207 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1597250 # Total number of references to valid blocks. +system.cpu.l2cache.replacements 759 # number of replacements +system.cpu.l2cache.tagsinuse 9484.092590 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1597486 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15574 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 102.558752 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 102.573905 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8984.898235 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 195.884523 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 196.068450 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.274197 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.005978 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.005984 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.286159 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 9095.853613 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 194.259268 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 193.979709 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.277583 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.005928 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.005920 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.289432 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 901676 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 901700 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942867 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942867 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 30990 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 30990 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 902114 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 902138 # number of ReadReq hits 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number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 360 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1064 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 14537 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14537 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 704 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14897 # number of demand (read+write) misses +system.cpu.l2cache.overall_hits::cpu.data 932726 # number of overall hits +system.cpu.l2cache.overall_hits::total 932750 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 707 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 356 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1063 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses 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948291 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967033 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000399 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319305 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967033 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015721 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967033 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015721 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.857955 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34241.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34357.363968 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.857955 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34354.568034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.857955 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34354.568034 # average overall miss latency +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24231000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12178500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 36409500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499418000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 499418000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24231000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 511596500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 535827500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24231000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 511596500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 535827500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 731 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 902470 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 903201 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942876 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942876 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 45150 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 45150 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 731 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947620 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948351 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 731 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947620 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948351 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967168 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000394 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.321993 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967168 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015717 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967168 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015717 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34272.984441 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34209.269663 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.593204 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34272.984441 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.167450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34272.984441 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.167450 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -609,42 +609,42 @@ system.cpu.l2cache.demand_mshr_hits::total 11 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 350 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1053 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14537 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14537 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 703 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14887 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 706 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 346 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1052 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 706 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14884 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15590 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14887 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 706 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14884 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15590 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21846000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10912500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32758500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21846000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 463281500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 485127500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21846000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463281500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 485127500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000388 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319305 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31075.391181 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31178.571429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31118.456353 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31075.391181 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31119.869685 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31075.391181 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31119.869685 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21938500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10782000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32720500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452176000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452176000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21938500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462958000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 484896500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21938500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462958000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 484896500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000383 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.321993 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015707 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015707 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31074.362606 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.849711 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.040308 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31074.362606 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31104.407417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31074.362606 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31104.407417 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 75c90b82c..4140383de 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:268435455 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 393a58e49..336dcb8a1 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu sim_ticks 54240666000 # Number of ticks simulated final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3177444 # Simulator instruction rate (inst/s) -host_op_rate 3200257 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1902228216 # Simulator tick rate (ticks/s) -host_mem_usage 345536 # Number of bytes of host memory used -host_seconds 28.51 # Real time elapsed on the host +host_inst_rate 2969105 # Simulator instruction rate (inst/s) +host_op_rate 2990423 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1777502999 # Simulator tick rate (ticks/s) +host_mem_usage 349280 # Number of bytes of host memory used +host_seconds 30.52 # Real time elapsed on the host sim_insts 90602415 # Number of instructions simulated sim_ops 91252969 # Number of ops (including micro ops) simulated system.physmem.bytes_read 521339715 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 91252969 # Nu system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 96832 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15564339 # number of instructions that are conditional controls system.cpu.num_int_insts 72525682 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 14eb2c781..3779c19fc 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:268435455 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 27b93150e..4a03aab99 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.148086 # Nu sim_ticks 148086239000 # Number of ticks simulated final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1696896 # Simulator instruction rate (inst/s) -host_op_rate 1709063 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2774293546 # Simulator tick rate (ticks/s) -host_mem_usage 354444 # Number of bytes of host memory used -host_seconds 53.38 # Real time elapsed on the host +host_inst_rate 1772363 # Simulator instruction rate (inst/s) +host_op_rate 1785070 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2897675173 # Simulator tick rate (ticks/s) +host_mem_usage 358192 # Number of bytes of host memory used +host_seconds 51.11 # Real time elapsed on the host sim_insts 90576869 # Number of instructions simulated sim_ops 91226321 # Number of ops (including micro ops) simulated system.physmem.bytes_read 986112 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 91226321 # Nu system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 96832 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15564339 # number of instructions that are conditional controls system.cpu.num_int_insts 72525682 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 0afad448e..9cdb8964a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index e45cd058f..b4d96e4ea 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 4e6ce5d2a..af8c70dcf 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:11:33 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:18:33 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 237773144000 because target called exit() +Exiting @ tick 234107886500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 86edba92e..95047c0ce 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.237773 # Number of seconds simulated -sim_ticks 237773144000 # Number of ticks simulated -final_tick 237773144000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.234108 # Number of seconds simulated +sim_ticks 234107886500 # Number of ticks simulated +final_tick 234107886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146125 # Simulator instruction rate (inst/s) -host_op_rate 164611 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68266787 # Simulator tick rate (ticks/s) -host_mem_usage 228468 # Number of bytes of host memory used -host_seconds 3483.00 # Real time elapsed on the host -sim_insts 508954831 # Number of instructions simulated -sim_ops 573341392 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15219328 # Number of bytes read from this memory -system.physmem.bytes_inst_read 242816 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10954048 # Number of bytes written to this memory -system.physmem.num_reads 237802 # Number of read requests responded to by this memory -system.physmem.num_writes 171157 # Number of write requests responded to by this memory +host_inst_rate 148403 # Simulator instruction rate (inst/s) +host_op_rate 167177 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68261843 # Simulator tick rate (ticks/s) +host_mem_usage 232040 # Number of bytes of host memory used +host_seconds 3429.56 # Real time elapsed on the host +sim_insts 508954871 # Number of instructions simulated +sim_ops 573341432 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 15193216 # Number of bytes read from this memory +system.physmem.bytes_inst_read 241280 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10938560 # Number of bytes written to this memory +system.physmem.num_reads 237394 # Number of read requests responded to by this memory +system.physmem.num_writes 170915 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 64007767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1021209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 46069324 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 110077091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 64898352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1030636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 46724440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 111622792 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,315 +64,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 475546289 # number of cpu cycles simulated +system.cpu.numCycles 468215774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 201118526 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 157326791 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 13717812 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 115015344 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 100642141 # Number of BTB hits +system.cpu.BPredUnit.lookups 200061766 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 161279268 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 13261114 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 110371027 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 98350021 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10773560 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2444561 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 139270247 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 897566716 # Number of instructions fetch has processed -system.cpu.fetch.Branches 201118526 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 111415701 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 200565082 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 55484178 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 92468709 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 57772 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 128673930 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3900313 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 471730156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.235169 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.071802 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 10012114 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2451761 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 136559610 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 898175750 # Number of instructions fetch has processed +system.cpu.fetch.Branches 200061766 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 108362135 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 197576941 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 54094157 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 91756620 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 80 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 71734 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 126283016 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3812130 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 464400798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.257289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.102621 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 271176826 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 15439241 3.27% 60.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22205632 4.71% 65.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23455924 4.97% 70.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27555464 5.84% 76.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13622297 2.89% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13443686 2.85% 82.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 13465943 2.85% 84.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 71365143 15.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 266835612 57.46% 57.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 16224757 3.49% 60.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21301662 4.59% 65.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22971866 4.95% 70.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 24200733 5.21% 75.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13160700 2.83% 78.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13387272 2.88% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12932496 2.78% 84.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 73385700 15.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 471730156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.422921 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.887443 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 155306709 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 88053503 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 184585127 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4622182 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 39162635 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 30800384 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 208217 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 978321020 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 232355 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 39162635 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 168791117 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6653114 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 68132598 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 175576746 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13413946 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 897480764 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1345 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2815262 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7531261 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 34 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1053491537 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3898621593 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3898617258 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4335 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672199664 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 381291873 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6229815 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6227679 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 73783257 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 185038415 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 74452080 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 16894922 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11270431 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 807931986 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7507071 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 704469902 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1695850 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 239081434 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 584885410 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3628831 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 471730156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.493375 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.700371 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 464400798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.427285 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.918295 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 151819691 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 87315779 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 182356495 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4679019 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 38229814 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32058950 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 208727 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 978247672 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304018 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 38229814 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 165098123 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6680773 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 67210378 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 173611976 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13569734 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 900335199 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1400 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2808611 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7742666 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1050683608 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3921835451 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3921830870 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4581 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672199728 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 378483880 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6257639 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6252483 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 74230305 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 187204403 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74981295 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17030714 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11234948 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 805916100 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7086662 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 700681614 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1544151 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 236754435 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 596849341 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3208414 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 464400798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.508786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.706470 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 199497504 42.29% 42.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 75863834 16.08% 58.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 72319693 15.33% 73.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 60290896 12.78% 86.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 35341126 7.49% 93.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15480356 3.28% 97.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7623365 1.62% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3919536 0.83% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1393846 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 194454987 41.87% 41.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75651609 16.29% 58.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69485384 14.96% 73.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 61139015 13.17% 86.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 35296693 7.60% 93.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15466096 3.33% 97.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7603561 1.64% 98.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3924050 0.84% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1379403 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 471730156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 464400798 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 439890 4.44% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6794232 68.56% 73.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2675170 27.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 453814 4.63% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6693711 68.30% 72.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2653315 27.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 475256485 67.46% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 387188 0.05% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 152 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 163321629 23.18% 90.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65504445 9.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 472302081 67.41% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 386521 0.06% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 170 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 162598638 23.21% 90.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65394201 9.33% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 704469902 # Type of FU issued -system.cpu.iq.rate 1.481391 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9909292 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014066 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1892274762 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1054577614 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 670769172 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 736 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 700681614 # Type of FU issued +system.cpu.iq.rate 1.496493 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9800840 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013988 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1877108639 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1049814796 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 668235184 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 378 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 714379022 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9015037 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 710482264 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 190 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9094204 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 58265439 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 44467 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 61251 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16848183 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 60431419 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 43883 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 61918 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17377390 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 21514 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 20851 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 399 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 39162635 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2883414 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 177046 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 825140786 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8538399 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 185038415 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 74452080 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6018302 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 86541 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8726 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 61251 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11204470 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 7715069 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18919539 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 684747680 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 156362538 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19722222 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 38229814 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2886721 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 175953 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 821878596 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 9525062 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 187204403 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74981295 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5597916 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 86243 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8756 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 61918 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10539331 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 7737636 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18276967 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 681941706 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 155293366 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18739908 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9701729 # number of nop insts executed -system.cpu.iew.exec_refs 220343005 # number of memory reference insts executed -system.cpu.iew.exec_branches 142216769 # Number of branches executed -system.cpu.iew.exec_stores 63980467 # Number of stores executed -system.cpu.iew.exec_rate 1.439918 # Inst execution rate -system.cpu.iew.wb_sent 675765261 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 670769188 # cumulative count of insts written-back -system.cpu.iew.wb_producers 382570075 # num instructions producing a value -system.cpu.iew.wb_consumers 656640651 # num instructions consuming a value +system.cpu.iew.exec_nop 8875834 # number of nop insts executed +system.cpu.iew.exec_refs 219203468 # number of memory reference insts executed +system.cpu.iew.exec_branches 142018558 # Number of branches executed +system.cpu.iew.exec_stores 63910102 # Number of stores executed +system.cpu.iew.exec_rate 1.456469 # Inst execution rate +system.cpu.iew.wb_sent 673034239 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 668235200 # cumulative count of insts written-back +system.cpu.iew.wb_producers 381399199 # num instructions producing a value +system.cpu.iew.wb_consumers 655303832 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.410523 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.582617 # average fanout of values written-back +system.cpu.iew.wb_rate 1.427195 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.582019 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 510298715 # The number of committed instructions -system.cpu.commit.commitCommittedOps 574685276 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 250472455 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3878240 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15860538 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 432567522 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.328545 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.050034 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 510298755 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685316 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 247211019 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3878248 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15402240 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 426170985 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.065618 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 212834429 49.20% 49.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104865988 24.24% 73.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 39942503 9.23% 82.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19801516 4.58% 87.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17404518 4.02% 91.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7252453 1.68% 92.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7574279 1.75% 94.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3930965 0.91% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 18960871 4.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 207821757 48.76% 48.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103278684 24.23% 73.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 40154361 9.42% 82.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19502589 4.58% 87.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17446456 4.09% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7236627 1.70% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7721645 1.81% 94.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3779614 0.89% 95.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 19229252 4.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 432567522 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510298715 # Number of instructions committed -system.cpu.commit.committedOps 574685276 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 426170985 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510298755 # Number of instructions committed +system.cpu.commit.committedOps 574685316 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376873 # Number of memory references committed -system.cpu.commit.loads 126772976 # Number of loads committed +system.cpu.commit.refs 184376889 # Number of memory references committed +system.cpu.commit.loads 126772984 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192161 # Number of branches committed +system.cpu.commit.branches 120192169 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701381 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701413 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 18960871 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 19229252 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1238757244 # The number of ROB reads -system.cpu.rob.rob_writes 1689633153 # The number of ROB writes -system.cpu.timesIdled 98384 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3816133 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508954831 # Number of Instructions Simulated -system.cpu.committedOps 573341392 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508954831 # Number of Instructions Simulated -system.cpu.cpi 0.934359 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.934359 # CPI: Total CPI of All Threads -system.cpu.ipc 1.070253 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.070253 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3178301840 # number of integer regfile reads -system.cpu.int_regfile_writes 781282618 # number of integer regfile writes +system.cpu.rob.rob_reads 1228830930 # The number of ROB reads +system.cpu.rob.rob_writes 1682168121 # The number of ROB writes +system.cpu.timesIdled 98147 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3814976 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508954871 # Number of Instructions Simulated +system.cpu.committedOps 573341432 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508954871 # Number of Instructions Simulated +system.cpu.cpi 0.919955 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.919955 # CPI: Total CPI of All Threads +system.cpu.ipc 1.087009 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.087009 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3163894948 # number of integer regfile reads +system.cpu.int_regfile_writes 777442018 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1130957302 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463924 # number of misc regfile writes -system.cpu.icache.replacements 15572 # number of replacements -system.cpu.icache.tagsinuse 1101.255140 # Cycle average of tags in use -system.cpu.icache.total_refs 128654642 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17427 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7382.489356 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1131493621 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463940 # number of misc regfile writes +system.cpu.icache.replacements 16054 # number of replacements +system.cpu.icache.tagsinuse 1101.947975 # Cycle average of tags in use +system.cpu.icache.total_refs 126263236 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17918 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7046.725974 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1101.255140 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537722 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537722 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 128654644 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 128654644 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 128654644 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 128654644 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 128654644 # number of overall hits -system.cpu.icache.overall_hits::total 128654644 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19286 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19286 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19286 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19286 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19286 # number of overall misses -system.cpu.icache.overall_misses::total 19286 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 260902000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 260902000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 260902000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 260902000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 260902000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 260902000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 128673930 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 128673930 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 128673930 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 128673930 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 128673930 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 128673930 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13528.051436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13528.051436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13528.051436 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1101.947975 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.538061 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.538061 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 126263236 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 126263236 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 126263236 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 126263236 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 126263236 # number of overall hits +system.cpu.icache.overall_hits::total 126263236 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19780 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19780 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19780 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19780 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19780 # number of overall misses +system.cpu.icache.overall_misses::total 19780 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 264112500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 264112500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 264112500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 264112500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 264112500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 264112500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 126283016 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 126283016 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 126283016 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 126283016 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 126283016 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 126283016 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13352.502528 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13352.502528 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13352.502528 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,226 +381,224 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 2 # number of writebacks -system.cpu.icache.writebacks::total 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1714 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1714 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1714 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1714 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1714 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1714 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17572 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17572 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17572 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17572 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17572 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17572 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168050000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168050000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168050000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168050000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168050000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168050000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9563.510130 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9563.510130 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9563.510130 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1738 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1738 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1738 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1738 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1738 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1738 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18042 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 18042 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 18042 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 18042 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 18042 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 18042 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168794500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168794500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9355.642390 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9355.642390 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9355.642390 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1204759 # number of replacements -system.cpu.dcache.tagsinuse 4053.244205 # Cycle average of tags in use -system.cpu.dcache.total_refs 198410390 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1208855 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 164.130843 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5569662000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4053.244205 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989562 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989562 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 141155461 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 141155461 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52782371 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52782371 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2240321 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2240321 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2231961 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2231961 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 193937832 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 193937832 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 193937832 # number of overall hits -system.cpu.dcache.overall_hits::total 193937832 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1317563 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1317563 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1456935 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1456935 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 75 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 75 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2774498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2774498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2774498 # number of overall misses -system.cpu.dcache.overall_misses::total 2774498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15319546000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15319546000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25044558500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25044558500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 722500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 722500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40364104500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40364104500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40364104500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40364104500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 142473024 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 142473024 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1204439 # number of replacements +system.cpu.dcache.tagsinuse 4053.213241 # Cycle average of tags in use +system.cpu.dcache.total_refs 197393966 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1208535 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.333264 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5508997000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4053.213241 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989554 # Average percentage of cache occupancy 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+system.cpu.dcache.overall_hits::total 192921115 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1321702 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1321702 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1462063 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1462063 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 79 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 79 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2783765 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2783765 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2783765 # number of overall misses +system.cpu.dcache.overall_misses::total 2783765 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15361891000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15361891000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24945206993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24945206993 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 848000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 848000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40307097993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40307097993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40307097993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40307097993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 141465574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 141465574 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2240396 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2240396 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231961 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2231961 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 196712330 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 196712330 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 196712330 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 196712330 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009248 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026861 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000033 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014104 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014104 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11627.182913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17189.894196 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9633.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14548.255036 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14548.255036 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2240713 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2240713 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231969 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2231969 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 195704880 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 195704880 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 195704880 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 195704880 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009343 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026956 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014224 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014224 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11622.809832 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17061.649869 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10734.177215 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14479.346494 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14479.346494 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 563000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 557000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 6119.565217 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 6054.347826 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1073285 # number of writebacks -system.cpu.dcache.writebacks::total 1073285 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 449185 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 449185 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1116316 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1116316 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 75 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 75 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1565501 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1565501 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1565501 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1565501 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 868378 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 868378 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 340619 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 340619 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1208997 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1208997 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1208997 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1208997 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242009000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242009000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4355675500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4355675500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597684500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10597684500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597684500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10597684500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006095 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006280 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7188.124296 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12787.529468 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8765.683041 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8765.683041 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1073316 # number of writebacks +system.cpu.dcache.writebacks::total 1073316 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 452437 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 452437 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1122680 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1122680 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 79 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 79 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1575117 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1575117 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1575117 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1575117 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 869265 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 869265 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 339383 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 339383 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1208648 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1208648 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1208648 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1208648 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6267661500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6267661500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319283499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319283499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10586944999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10586944999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10586944999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10586944999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006145 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006257 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7210.300081 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12726.870524 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8759.328604 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8759.328604 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 218559 # number of replacements -system.cpu.l2cache.tagsinuse 20991.845074 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1557585 # Total number of references to valid blocks. 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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117154500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7247661500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7364816000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.210040 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.145371 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.275229 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.315815 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.210040 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193314 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.210040 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193314 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31075.464191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.696049 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31006.082453 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31075.464191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31022.628143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31075.464191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31022.628143 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index 4fff23cb4..a927ae45c 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 52a899319..3614f4202 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu sim_ticks 290498972000 # Number of ticks simulated final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2958479 # Simulator instruction rate (inst/s) -host_op_rate 3334501 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1696537892 # Simulator tick rate (ticks/s) -host_mem_usage 216124 # Number of bytes of host memory used -host_seconds 171.23 # Real time elapsed on the host +host_inst_rate 3161801 # Simulator instruction rate (inst/s) +host_op_rate 3563665 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1813132581 # Simulator tick rate (ticks/s) +host_mem_usage 219872 # Number of bytes of host memory used +host_seconds 160.22 # Real time elapsed on the host sim_insts 506581615 # Number of instructions simulated sim_ops 570968176 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2489298238 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 570968176 # Nu system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 15725605 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 98480815 # number of instructions that are conditional controls system.cpu.num_int_insts 470727703 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 4d41782e0..61506a548 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 3a1edbeaa..b2e0bf661 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:54:39 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:18:46 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index d73359a08..1dce1fffd 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.722234 # Nu sim_ticks 722234364000 # Number of ticks simulated final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1769028 # Simulator instruction rate (inst/s) -host_op_rate 1993395 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2530070907 # Simulator tick rate (ticks/s) -host_mem_usage 225284 # Number of bytes of host memory used -host_seconds 285.46 # Real time elapsed on the host +host_inst_rate 1812748 # Simulator instruction rate (inst/s) +host_op_rate 2042661 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2592600297 # Simulator tick rate (ticks/s) +host_mem_usage 228776 # Number of bytes of host memory used +host_seconds 278.58 # Real time elapsed on the host sim_insts 504986861 # Number of instructions simulated sim_ops 569034848 # Number of ops (including micro ops) simulated system.physmem.bytes_read 14797056 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 569034848 # Nu system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 15725605 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 98480815 # number of instructions that are conditional controls system.cpu.num_int_insts 470727703 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 3b6ae18fc..20b788768 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 6a43cd1d6..fc4913b5c 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:20:40 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:18:58 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -12,5 +12,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.100000 -Exiting @ tick 106128099500 because target called exit() +OO-style eon Time= 0.090000 +Exiting @ tick 99661890000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 47e84b8b4..db6cb13f6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.106128 # Number of seconds simulated -sim_ticks 106128099500 # Number of ticks simulated -final_tick 106128099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.099662 # Number of seconds simulated +sim_ticks 99661890000 # Number of ticks simulated +final_tick 99661890000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157297 # Simulator instruction rate (inst/s) -host_op_rate 201096 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61140107 # Simulator tick rate (ticks/s) -host_mem_usage 232128 # Number of bytes of host memory used -host_seconds 1735.82 # Real time elapsed on the host -sim_insts 273038358 # Number of instructions simulated -sim_ops 349066134 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 467776 # Number of bytes read from this memory -system.physmem.bytes_inst_read 196608 # Number of instructions bytes read from this memory +host_inst_rate 162959 # Simulator instruction rate (inst/s) +host_op_rate 208335 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59481796 # Simulator tick rate (ticks/s) +host_mem_usage 235924 # Number of bytes of host memory used +host_seconds 1675.50 # Real time elapsed on the host +sim_insts 273037886 # Number of instructions simulated +sim_ops 349065611 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 467712 # Number of bytes read from this memory +system.physmem.bytes_inst_read 196352 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7309 # Number of read requests responded to by this memory +system.physmem.num_reads 7308 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 4407655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1852554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 4407655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 4692987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1970181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 4692987 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,315 +63,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 212256200 # number of cpu cycles simulated +system.cpu.numCycles 199323781 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 38600701 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20829729 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3463171 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 24539034 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 19977747 # Number of BTB hits +system.cpu.BPredUnit.lookups 36425277 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21814093 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2195714 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 21857400 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 17699652 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7676103 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 50709 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 45583571 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349929862 # Number of instructions fetch has processed -system.cpu.fetch.Branches 38600701 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27653850 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 79742933 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11999643 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 78327340 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3689 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 43047745 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 991560 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 212145839 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.131606 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.210594 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6983514 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 50540 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40843667 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 325977974 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36425277 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24683166 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 73206871 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8096294 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 79308750 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3272 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 39251627 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 692341 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 199214408 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.104516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.205209 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133058921 62.72% 62.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9120644 4.30% 67.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5867847 2.77% 69.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6815573 3.21% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5485208 2.59% 75.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4655113 2.19% 77.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3623686 1.71% 79.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4201022 1.98% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39317825 18.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 126685996 63.59% 63.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7392332 3.71% 67.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5861965 2.94% 70.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6253075 3.14% 73.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4927164 2.47% 75.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4136176 2.08% 77.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3211031 1.61% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4254661 2.14% 81.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36492008 18.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 212145839 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.181859 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.648620 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 53244552 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73538238 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 73218017 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3725881 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8419151 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7680933 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69313 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 439362017 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 203984 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8419151 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 60748190 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1237136 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57632287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 69638027 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14471048 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 424701352 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 42052 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7943055 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 65 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 460812549 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2479929544 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1407452570 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1072476974 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384568759 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 76243790 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3964610 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4028744 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48494722 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 109274429 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 96208348 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3462613 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2507488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 400084611 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3851975 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 382840510 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1563616 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 52114616 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 153570381 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 296314 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 212145839 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.804610 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.994995 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 199214408 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.182744 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.635419 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 48091997 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 74157554 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 67325954 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3856814 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5782089 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7547074 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69910 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 411121431 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 208451 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5782089 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 55063328 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1232045 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57746804 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 64402683 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14987459 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 399689928 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 40994 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8558988 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 23 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 436461452 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2357603268 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1290965650 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1066637618 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384568055 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 51893397 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3989281 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4086766 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48885430 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104583194 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 92996995 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2832218 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4219793 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383881743 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3901955 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 374859266 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1372272 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 37676176 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 103140014 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 346328 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 199214408 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.881688 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.014261 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 84176099 39.68% 39.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 34982222 16.49% 56.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24755932 11.67% 67.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18634598 8.78% 76.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22073169 10.40% 87.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15324157 7.22% 94.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8735583 4.12% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2596961 1.22% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 867118 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 75091477 37.69% 37.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 33471491 16.80% 54.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 23546496 11.82% 66.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17816115 8.94% 75.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22176914 11.13% 86.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15007629 7.53% 93.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8468208 4.25% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2797235 1.40% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 838843 0.42% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 212145839 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 199214408 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2806 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 40388 0.23% 0.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 3425 0.02% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 360 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 70580 0.40% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 658 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 165111 0.94% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9772061 55.35% 56.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7595169 43.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3057 0.02% 0.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5025 0.03% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 40437 0.24% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 3591 0.02% 0.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 364 0.00% 0.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 63031 0.37% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 1376 0.01% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 149950 0.89% 1.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8836509 52.25% 53.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7809442 46.17% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 132056726 34.49% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2147658 0.56% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 35.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6773802 1.77% 36.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8676385 2.27% 39.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3409492 0.89% 39.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1588042 0.41% 40.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21173468 5.53% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7175134 1.87% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7113298 1.86% 49.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175289 0.05% 49.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 104144752 27.20% 76.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88406462 23.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 127218722 33.94% 33.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2147662 0.57% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 1 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6752754 1.80% 36.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8445549 2.25% 38.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3419085 0.91% 39.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1579460 0.42% 39.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20849528 5.56% 45.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172342 1.91% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7118324 1.90% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101990541 27.21% 76.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 87990007 23.47% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 382840510 # Type of FU issued -system.cpu.iq.rate 1.803672 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17655604 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.046117 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 748490100 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 326330004 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 254739452 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 248555979 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 129729375 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118008670 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 272729101 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 127767013 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7377796 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374859266 # Type of FU issued +system.cpu.iq.rate 1.880655 # Inst issue rate +system.cpu.iq.fu_busy_cnt 16912785 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.045118 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 719593529 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 296504031 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250306667 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 247624468 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 128964922 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117586691 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 264413654 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 127358397 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8761278 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14625409 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 156782 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8434 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13832497 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9934214 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 114912 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 9298 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10621174 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 161 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12907 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 180 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8419151 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18839 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 495 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 403985333 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2312327 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 109274429 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 96208348 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3840849 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 111 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 202 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8434 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3230502 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 526451 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3756953 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 375755558 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 102316904 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7084952 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5782089 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25749 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2296 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 387833269 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1480942 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104583194 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 92996995 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3890825 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 225 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 9298 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1748842 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 550283 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2299125 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370161123 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100475616 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4698143 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 48747 # number of nop insts executed -system.cpu.iew.exec_refs 188828362 # number of memory reference insts executed -system.cpu.iew.exec_branches 32585670 # Number of branches executed -system.cpu.iew.exec_stores 86511458 # Number of stores executed -system.cpu.iew.exec_rate 1.770292 # Inst execution rate -system.cpu.iew.wb_sent 373866507 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 372748122 # cumulative count of insts written-back -system.cpu.iew.wb_producers 177468543 # num instructions producing a value -system.cpu.iew.wb_consumers 349211993 # num instructions consuming a value +system.cpu.iew.exec_nop 49571 # number of nop insts executed +system.cpu.iew.exec_refs 187121240 # number of memory reference insts executed +system.cpu.iew.exec_branches 32102790 # Number of branches executed +system.cpu.iew.exec_stores 86645624 # Number of stores executed +system.cpu.iew.exec_rate 1.857085 # Inst execution rate +system.cpu.iew.wb_sent 368581318 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 367893358 # cumulative count of insts written-back +system.cpu.iew.wb_producers 175547849 # num instructions producing a value +system.cpu.iew.wb_consumers 345820695 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.756124 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.508197 # average fanout of values written-back +system.cpu.iew.wb_rate 1.845707 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.507627 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 273038970 # The number of committed instructions -system.cpu.commit.commitCommittedOps 349066746 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 54918764 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3555661 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3435880 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 203726689 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.713407 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.315617 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 273038498 # The number of committed instructions +system.cpu.commit.commitCommittedOps 349066223 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 38767213 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3555627 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2167826 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 193432320 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.804591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.360078 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 92152533 45.23% 45.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 39786932 19.53% 64.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 18046593 8.86% 73.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13175994 6.47% 80.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14586259 7.16% 87.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7495826 3.68% 90.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3332635 1.64% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3360666 1.65% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11789251 5.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83176077 43.00% 43.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 39065690 20.20% 63.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17086597 8.83% 72.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13450710 6.95% 78.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14290443 7.39% 86.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7491330 3.87% 90.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3442946 1.78% 92.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3229105 1.67% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 12199422 6.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 203726689 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273038970 # Number of instructions committed -system.cpu.commit.committedOps 349066746 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 193432320 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273038498 # Number of instructions committed +system.cpu.commit.committedOps 349066223 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024871 # Number of memory references committed -system.cpu.commit.loads 94649020 # Number of loads committed +system.cpu.commit.refs 177024801 # Number of memory references committed +system.cpu.commit.loads 94648980 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30521899 # Number of branches committed +system.cpu.commit.branches 30521876 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279586009 # Number of committed integer instructions. -system.cpu.commit.function_calls 6225114 # Number of function calls committed. -system.cpu.commit.bw_lim_events 11789251 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 279585540 # Number of committed integer instructions. +system.cpu.commit.function_calls 6225112 # Number of function calls committed. +system.cpu.commit.bw_lim_events 12199422 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 595920425 # The number of ROB reads -system.cpu.rob.rob_writes 816392505 # The number of ROB writes -system.cpu.timesIdled 2445 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 110361 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273038358 # Number of Instructions Simulated -system.cpu.committedOps 349066134 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273038358 # Number of Instructions Simulated -system.cpu.cpi 0.777386 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.777386 # CPI: Total CPI of All Threads -system.cpu.ipc 1.286362 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.286362 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1793972904 # number of integer regfile reads -system.cpu.int_regfile_writes 239970573 # number of integer regfile writes -system.cpu.fp_regfile_reads 188856116 # number of floating regfile reads -system.cpu.fp_regfile_writes 132824047 # number of floating regfile writes -system.cpu.misc_regfile_reads 1016778379 # number of misc regfile reads -system.cpu.misc_regfile_writes 34422233 # number of misc regfile writes -system.cpu.icache.replacements 14013 # number of replacements -system.cpu.icache.tagsinuse 1856.982815 # Cycle average of tags in use -system.cpu.icache.total_refs 43030970 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15905 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2705.499528 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 569063811 # The number of ROB reads +system.cpu.rob.rob_writes 781450888 # The number of ROB writes +system.cpu.timesIdled 2411 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 109373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273037886 # Number of Instructions Simulated +system.cpu.committedOps 349065611 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273037886 # Number of Instructions Simulated +system.cpu.cpi 0.730022 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.730022 # CPI: Total CPI of All Threads +system.cpu.ipc 1.369821 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.369821 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1768986911 # number of integer regfile reads +system.cpu.int_regfile_writes 233848403 # number of integer regfile writes +system.cpu.fp_regfile_reads 187568002 # number of floating regfile reads +system.cpu.fp_regfile_writes 132321236 # number of floating regfile writes +system.cpu.misc_regfile_reads 981099777 # number of misc regfile reads +system.cpu.misc_regfile_writes 34422237 # number of misc regfile writes +system.cpu.icache.replacements 14037 # number of replacements +system.cpu.icache.tagsinuse 1859.121830 # Cycle average of tags in use +system.cpu.icache.total_refs 39234784 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15929 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2463.104024 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1856.982815 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.906730 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.906730 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 43030972 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 43030972 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 43030972 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 43030972 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 43030972 # number of overall hits -system.cpu.icache.overall_hits::total 43030972 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16773 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16773 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16773 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16773 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16773 # number of overall misses -system.cpu.icache.overall_misses::total 16773 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207159500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207159500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207159500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207159500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207159500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207159500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 43047745 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 43047745 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 43047745 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 43047745 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 43047745 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 43047745 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000390 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000390 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12350.772074 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12350.772074 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12350.772074 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1859.121830 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.907774 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.907774 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39234786 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39234786 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39234786 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39234786 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39234786 # number of overall hits +system.cpu.icache.overall_hits::total 39234786 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16841 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16841 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16841 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16841 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16841 # number of overall misses +system.cpu.icache.overall_misses::total 16841 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 208423500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 208423500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 208423500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 208423500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 208423500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 208423500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39251627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39251627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39251627 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39251627 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39251627 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39251627 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000429 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000429 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000429 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12375.957485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12375.957485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12375.957485 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles 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317500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26454.545455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22678.571429 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks -system.cpu.dcache.writebacks::total 1039 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1604 # number of ReadReq MSHR hits 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of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 380.682257 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2812.020473 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 769.761121 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011618 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.085816 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.023491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.120925 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 293 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13147 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1038 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88103500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95355500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132636500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 227992000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95355500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132636500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 227992000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807147 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992259 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193135 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921889 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193135 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921889 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31064.127604 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31291.107975 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993651 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192605 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922140 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192605 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922140 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.671447 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31295.151089 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31263.652482 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31064.127604 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31272.834553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31064.127604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31272.834553 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31275.647852 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.671447 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31282.193396 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.671447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31282.193396 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 2d58b9952..a60b9f94a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 24bfa1f56..cbd6c2617 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu sim_ticks 212344048000 # Number of ticks simulated final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2097833 # Simulator instruction rate (inst/s) -host_op_rate 2681977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1631504750 # Simulator tick rate (ticks/s) -host_mem_usage 220728 # Number of bytes of host memory used -host_seconds 130.15 # Real time elapsed on the host +host_inst_rate 2182036 # Simulator instruction rate (inst/s) +host_op_rate 2789626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1696989772 # Simulator tick rate (ticks/s) +host_mem_usage 224464 # Number of bytes of host memory used +host_seconds 125.13 # Real time elapsed on the host sim_insts 273037671 # Number of instructions simulated sim_ops 349065408 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1875350709 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 349065408 # Nu system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12433363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 16271154 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 18102314 # number of instructions that are conditional controls system.cpu.num_int_insts 279584926 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index bc61fa4c6..8414937bc 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index bcea217f3..4bf4fdf3e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525854 # Nu sim_ticks 525854475000 # Number of ticks simulated final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1153060 # Simulator instruction rate (inst/s) -host_op_rate 1474144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2223154070 # Simulator tick rate (ticks/s) -host_mem_usage 229624 # Number of bytes of host memory used -host_seconds 236.54 # Real time elapsed on the host +host_inst_rate 1224247 # Simulator instruction rate (inst/s) +host_op_rate 1565155 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2360407719 # Simulator tick rate (ticks/s) +host_mem_usage 233372 # Number of bytes of host memory used +host_seconds 222.78 # Real time elapsed on the host sim_insts 272739291 # Number of instructions simulated sim_ops 348687131 # Number of ops (including micro ops) simulated system.physmem.bytes_read 437312 # Number of bytes read from this memory @@ -71,7 +71,7 @@ system.cpu.committedOps 348687131 # Nu system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12433363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 16271153 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 18102313 # number of instructions that are conditional controls system.cpu.num_int_insts 279584925 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 3a59e4035..b8945b754 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 47a0b85a1..d16dcf9af 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:29:25 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:22:39 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 733277720500 because target called exit() +Exiting @ tick 736384204000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index ed14e8975..a4d9e3173 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.733278 # Number of seconds simulated -sim_ticks 733277720500 # Number of ticks simulated -final_tick 733277720500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.736384 # Number of seconds simulated +sim_ticks 736384204000 # Number of ticks simulated +final_tick 736384204000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105807 # Simulator instruction rate (inst/s) -host_op_rate 144094 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56043664 # Simulator tick rate (ticks/s) -host_mem_usage 229440 # Number of bytes of host memory used -host_seconds 13084.04 # Real time elapsed on the host -sim_insts 1384379038 # Number of instructions simulated -sim_ops 1885333791 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94834048 # Number of bytes read from this memory -system.physmem.bytes_inst_read 211584 # Number of instructions bytes read from this memory +host_inst_rate 107029 # Simulator instruction rate (inst/s) +host_op_rate 145759 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56931535 # Simulator tick rate (ticks/s) +host_mem_usage 233236 # Number of bytes of host memory used +host_seconds 12934.56 # Real time elapsed on the host +sim_insts 1384379033 # Number of instructions simulated +sim_ops 1885333786 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 94833536 # Number of bytes read from this memory +system.physmem.bytes_inst_read 209216 # Number of instructions bytes read from this memory system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1481782 # Number of read requests responded to by this memory +system.physmem.num_reads 1481774 # Number of read requests responded to by this memory system.physmem.num_writes 66099 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 129328964 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 288546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5769078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 135098042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 128782686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 284113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5744740 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 134527427 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1466555442 # number of cpu cycles simulated +system.cpu.numCycles 1472768409 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 521605883 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 398295805 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 35472641 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 324070281 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 281628461 # Number of BTB hits +system.cpu.BPredUnit.lookups 522739689 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 397666770 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 35592388 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 329507474 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 283194756 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 60884201 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2837075 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 442389760 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2602751444 # Number of instructions fetch has processed -system.cpu.fetch.Branches 521605883 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 342512662 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 710958340 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 222650773 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 102112433 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2045 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 27281 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 413558926 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12436668 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1437090852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.547593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.158778 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 59112231 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2837995 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 446610303 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2608281266 # Number of instructions fetch has processed +system.cpu.fetch.Branches 522739689 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 342306987 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 709905843 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 224599686 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 101691904 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 28872 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 415462379 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10233497 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1441668699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.553094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.169508 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 726180548 50.53% 50.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 55293209 3.85% 54.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 113089207 7.87% 62.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71780914 4.99% 67.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 85098858 5.92% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 53585663 3.73% 76.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 33501630 2.33% 79.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33512244 2.33% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 265048579 18.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 731812218 50.76% 50.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 54028478 3.75% 54.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 112774395 7.82% 62.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 69112712 4.79% 67.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 82239849 5.70% 72.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 54732676 3.80% 76.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35582945 2.47% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33403067 2.32% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 267982359 18.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1437090852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.355667 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.774738 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 490749730 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 81942012 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 671828843 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10983114 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 181587153 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 78430944 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 14399 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3525428920 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31224 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 181587153 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 528591839 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 29769579 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3592366 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 643071064 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50478851 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3416214159 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 111 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4185905 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40940283 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 71 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3334777668 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16188662039 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15531956325 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 656705714 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153607 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1341624061 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 276669 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 271964 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 142813939 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1064118913 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 569792794 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 34207890 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 39464438 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3183095569 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 272489 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2713070131 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 26125821 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1297647909 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3029004541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 61158 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1437090852 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.887890 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.908228 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1441668699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.354937 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.771006 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 492629108 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 81861101 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 672684141 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 11080003 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 183414346 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 82040809 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 15532 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3552890515 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32736 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 183414346 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 530589836 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 29829797 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3588754 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 644081795 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50164171 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3435316942 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 112 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4205507 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40993124 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 37 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3332970891 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16270156364 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15618651087 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 651505277 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1339817292 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 273156 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 268372 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 142469911 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1057917040 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 579962844 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 32519670 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 39211966 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3198933227 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 269334 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2725360235 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 26814777 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1313459573 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3048227605 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 58004 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1441668699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.890421 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.914096 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 520966392 36.25% 36.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196978260 13.71% 49.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217896132 15.16% 65.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 179000352 12.46% 77.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 155500191 10.82% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 101390463 7.06% 95.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48751651 3.39% 98.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11023722 0.77% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5583689 0.39% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 524357405 36.37% 36.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 197522511 13.70% 50.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 215009168 14.91% 64.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 179008270 12.42% 77.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 156604882 10.86% 88.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 103164450 7.16% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 49203607 3.41% 98.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11056090 0.77% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5742316 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1437090852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1441668699 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1973852 2.08% 2.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23832 0.03% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 56484939 59.46% 61.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36512276 38.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2118699 2.21% 2.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23832 0.02% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56614089 59.02% 61.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37163288 38.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1254030566 46.22% 46.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11231291 0.41% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876617 0.25% 46.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5503438 0.20% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 51 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23339517 0.86% 48.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 904708245 33.35% 81.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 506005116 18.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1266333715 46.46% 46.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11230148 0.41% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876563 0.25% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5503497 0.20% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 38 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23211520 0.85% 48.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 900219934 33.03% 81.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 510609530 18.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2713070131 # Type of FU issued -system.cpu.iq.rate 1.849961 # Inst issue rate -system.cpu.iq.fu_busy_cnt 94994899 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035014 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6850643246 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4377903008 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2485399987 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 133708588 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 103168081 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 59868624 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2739540927 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 68524103 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 73975735 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2725360235 # Type of FU issued +system.cpu.iq.rate 1.850502 # Inst issue rate +system.cpu.iq.fu_busy_cnt 95919908 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035195 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6880679936 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4410033557 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2496172626 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 134443918 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 102684223 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 60255652 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2752299483 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 68980660 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 71230775 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 432730043 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 290479 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1327592 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 292795809 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 426528171 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 281369 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1323673 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 302965860 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 77 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 92 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 181587153 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16026457 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1578003 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3183438661 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7039132 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1064118913 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 569792794 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 261469 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1577202 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 221 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1327592 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 36771149 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9229244 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 46000393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2613620752 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 848933154 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 99449379 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 183414346 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16249953 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1608700 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3199274316 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7370103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1057917040 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 579962844 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 258370 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1607775 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 215 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1323673 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 37204877 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8928711 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 46133588 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2624820303 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 845791055 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 100539932 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 70603 # number of nop insts executed -system.cpu.iew.exec_refs 1326104884 # number of memory reference insts executed -system.cpu.iew.exec_branches 359304869 # Number of branches executed -system.cpu.iew.exec_stores 477171730 # Number of stores executed -system.cpu.iew.exec_rate 1.782149 # Inst execution rate -system.cpu.iew.wb_sent 2573682929 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2545268611 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1471406784 # num instructions producing a value -system.cpu.iew.wb_consumers 2751379282 # num instructions consuming a value +system.cpu.iew.exec_nop 71755 # number of nop insts executed +system.cpu.iew.exec_refs 1327328363 # number of memory reference insts executed +system.cpu.iew.exec_branches 362158100 # Number of branches executed +system.cpu.iew.exec_stores 481537308 # Number of stores executed +system.cpu.iew.exec_rate 1.782236 # Inst execution rate +system.cpu.iew.wb_sent 2584846968 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2556428278 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1474733618 # num instructions producing a value +system.cpu.iew.wb_consumers 2760579704 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.735542 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534789 # average fanout of values written-back +system.cpu.iew.wb_rate 1.735798 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534212 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1384390054 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1885344807 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1298094205 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 211331 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 40996327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1255503701 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.501664 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.213150 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1313929852 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 41115032 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1258254355 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.498381 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.211057 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 576634792 45.93% 45.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 315329042 25.12% 71.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 102673368 8.18% 79.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 78981369 6.29% 85.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 52937200 4.22% 89.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24029706 1.91% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17032250 1.36% 93.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9453700 0.75% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78432274 6.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 578553729 45.98% 45.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 316892144 25.19% 71.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 101707631 8.08% 79.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79187361 6.29% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 52970249 4.21% 89.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24190672 1.92% 91.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17058373 1.36% 93.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9262849 0.74% 93.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78431347 6.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1255503701 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384390054 # Number of instructions committed -system.cpu.commit.committedOps 1885344807 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1258254355 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384390049 # Number of instructions committed +system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385855 # Number of memory references committed -system.cpu.commit.loads 631388870 # Number of loads committed +system.cpu.commit.refs 908385853 # Number of memory references committed +system.cpu.commit.loads 631388869 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350233 # Number of branches committed +system.cpu.commit.branches 291350232 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705627 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 78432274 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 78431347 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4360492094 # The number of ROB reads -system.cpu.rob.rob_writes 6548474997 # The number of ROB writes -system.cpu.timesIdled 1306597 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29464590 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384379038 # Number of Instructions Simulated -system.cpu.committedOps 1885333791 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384379038 # Number of Instructions Simulated -system.cpu.cpi 1.059360 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.059360 # CPI: Total CPI of All Threads -system.cpu.ipc 0.943966 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.943966 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12901082944 # number of integer regfile reads -system.cpu.int_regfile_writes 2417885668 # number of integer regfile writes -system.cpu.fp_regfile_reads 70910494 # number of floating regfile reads -system.cpu.fp_regfile_writes 51358984 # number of floating regfile writes -system.cpu.misc_regfile_reads 4077651963 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776278 # number of misc regfile writes -system.cpu.icache.replacements 29135 # number of replacements -system.cpu.icache.tagsinuse 1664.054518 # Cycle average of tags in use -system.cpu.icache.total_refs 413522379 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30834 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13411.246643 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4379079317 # The number of ROB reads +system.cpu.rob.rob_writes 6581974646 # The number of ROB writes +system.cpu.timesIdled 1328714 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31099710 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384379033 # Number of Instructions Simulated +system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated +system.cpu.cpi 1.063848 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.063848 # CPI: Total CPI of All Threads +system.cpu.ipc 0.939984 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.939984 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12935043618 # number of integer regfile reads +system.cpu.int_regfile_writes 2425775909 # number of integer regfile writes +system.cpu.fp_regfile_reads 71439411 # number of floating regfile reads +system.cpu.fp_regfile_writes 51051626 # number of floating regfile writes +system.cpu.misc_regfile_reads 4084910091 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes +system.cpu.icache.replacements 28501 # number of replacements +system.cpu.icache.tagsinuse 1662.292931 # Cycle average of tags in use +system.cpu.icache.total_refs 415426412 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30198 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13756.752500 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1664.054518 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.812527 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.812527 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 413522385 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 413522385 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 413522385 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 413522385 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 413522385 # number of overall hits -system.cpu.icache.overall_hits::total 413522385 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 36541 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 36541 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 36541 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 36541 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 36541 # number of overall misses -system.cpu.icache.overall_misses::total 36541 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 319633500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 319633500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 319633500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 319633500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 319633500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 319633500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 413558926 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 413558926 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 413558926 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 413558926 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 413558926 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 413558926 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8747.256506 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8747.256506 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8747.256506 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1662.292931 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.811666 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.811666 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 415426419 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 415426419 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 415426419 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 415426419 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 415426419 # number of overall hits +system.cpu.icache.overall_hits::total 415426419 # number of overall hits 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of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3306 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412396 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1415702 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4885 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4885 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 31 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412425 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1415694 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4973 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4973 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3306 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1478476 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1481782 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3306 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1478476 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1481782 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 102729500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43881583500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43984313000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 151435000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 151435000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048541500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048541500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 102729500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45930125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46032854500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 102729500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45930125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46032854500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964859 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908803 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962207 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962207 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.653962 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.895338 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3269 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1478505 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1481774 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3269 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1478505 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1481774 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 101602500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43882479500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43984082000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 154163000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 154163000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048540000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048540000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101602500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931019500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46032622000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101602500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931019500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46032622000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964956 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998996 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908816 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962299 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962299 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.605690 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.891800 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.930690 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.653962 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.857680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.653962 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.857680 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.907990 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.605690 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.853345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.605690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.853345 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 3b0020443..9ae0bbe5f 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index a0e247e5f..5256776b5 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu sim_ticks 945613131000 # Number of ticks simulated final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2494982 # Simulator instruction rate (inst/s) -host_op_rate 3397821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1704217996 # Simulator tick rate (ticks/s) -host_mem_usage 217680 # Number of bytes of host memory used -host_seconds 554.87 # Real time elapsed on the host +host_inst_rate 2461578 # Simulator instruction rate (inst/s) +host_op_rate 3352328 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1681400523 # Simulator tick rate (ticks/s) +host_mem_usage 221408 # Number of bytes of host memory used +host_seconds 562.40 # Real time elapsed on the host sim_insts 1384381614 # Number of instructions simulated sim_ops 1885336367 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8025491315 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 1885336367 # Nu system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 223764558 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698876 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 62f983a26..4f1c04844 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 70fd39037..17c70c66c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.369902 # Nu sim_ticks 2369901960000 # Number of ticks simulated final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1307856 # Simulator instruction rate (inst/s) -host_op_rate 1774200 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2243399723 # Simulator tick rate (ticks/s) -host_mem_usage 226844 # Number of bytes of host memory used -host_seconds 1056.39 # Real time elapsed on the host +host_inst_rate 1323415 # Simulator instruction rate (inst/s) +host_op_rate 1795307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2270088736 # Simulator tick rate (ticks/s) +host_mem_usage 230320 # Number of bytes of host memory used +host_seconds 1043.97 # Real time elapsed on the host sim_insts 1381604347 # Number of instructions simulated sim_ops 1874244950 # Number of ops (including micro ops) simulated system.physmem.bytes_read 94696320 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 1874244950 # Nu system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 223764558 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698876 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 1d9e3541a..466d8993c 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 2abcbcd2a..bc6c11a64 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:47:12 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:25:21 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 30746529500 because target called exit() +Exiting @ tick 30755543500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index a9b05e877..324eff178 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.030747 # Number of seconds simulated -sim_ticks 30746529500 # Number of ticks simulated -final_tick 30746529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.030756 # Number of seconds simulated +sim_ticks 30755543500 # Number of ticks simulated +final_tick 30755543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146131 # Simulator instruction rate (inst/s) -host_op_rate 207370 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63356016 # Simulator tick rate (ticks/s) -host_mem_usage 232084 # Number of bytes of host memory used -host_seconds 485.30 # Real time elapsed on the host -sim_insts 70917047 # Number of instructions simulated -sim_ops 100636295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8680064 # Number of bytes read from this memory -system.physmem.bytes_inst_read 363776 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5661120 # Number of bytes written to this memory -system.physmem.num_reads 135626 # Number of read requests responded to by this memory -system.physmem.num_writes 88455 # Number of write requests responded to by this memory +host_inst_rate 147147 # Simulator instruction rate (inst/s) +host_op_rate 208812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63815156 # Simulator tick rate (ticks/s) +host_mem_usage 235936 # Number of bytes of host memory used +host_seconds 481.95 # Real time elapsed on the host +sim_insts 70917252 # Number of instructions simulated +sim_ops 100636500 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 8681216 # Number of bytes read from this memory +system.physmem.bytes_inst_read 364288 # Number of instructions bytes read from this memory +system.physmem.bytes_written 5661440 # Number of bytes written to this memory +system.physmem.num_reads 135644 # Number of read requests responded to by this memory +system.physmem.num_writes 88460 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 282310366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 11831449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 184122244 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 466432610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 282265082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 11844629 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 184078685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 466343767 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 61493060 # number of cpu cycles simulated +system.cpu.numCycles 61511088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17207683 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11124675 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 739996 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12413226 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8258713 # Number of BTB hits +system.cpu.BPredUnit.lookups 17165899 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 13150342 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 741670 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12130394 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8128680 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1860363 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 182681 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13006035 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87629176 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17207683 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10119076 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21952285 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2766047 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 23185818 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2820 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12232999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 233597 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 60095316 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.044969 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.137732 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1854457 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 183977 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13000354 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87655737 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17165899 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9983137 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21873848 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2772277 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 23278441 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2074 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12226708 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 230090 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 60107424 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.046912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.144766 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 38160956 63.50% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2271093 3.78% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1990023 3.31% 70.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2119724 3.53% 74.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1647401 2.74% 76.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1441763 2.40% 79.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1000150 1.66% 80.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1230223 2.05% 82.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10233983 17.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 38251797 63.64% 63.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2252747 3.75% 67.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1977441 3.29% 70.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2053713 3.42% 74.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1587290 2.64% 76.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1440263 2.40% 79.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 985496 1.64% 80.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1267048 2.11% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10291629 17.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 60095316 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.279831 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.425025 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14817180 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 21950690 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20398412 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1086428 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1842606 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3463605 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108661 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119794628 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 354485 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1842606 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16634867 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1966833 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15615217 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19642472 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4393321 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116600703 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4194 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3033361 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 70 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 116869923 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536821347 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536814358 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6989 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99147741 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17722182 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 787670 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786973 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12493394 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29971388 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22471181 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2503550 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3551864 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111668104 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 780017 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107789312 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 331076 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11606029 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28797672 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 76559 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 60095316 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.793639 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.921516 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 60107424 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.279070 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.425040 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14856562 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 22001240 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20371729 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1031804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1846089 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3466450 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109251 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119897530 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 366577 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1846089 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16668221 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1965297 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15638738 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19567499 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4421580 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116607925 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4528 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3022237 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 40 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 116831766 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536941360 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536932869 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8491 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99148069 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 17683697 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 794887 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 794929 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12663863 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29905745 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22497839 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2550433 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3605599 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111646205 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 783462 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107783359 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 315194 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11596172 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28526322 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 79963 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 60107424 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.793179 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.923398 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21617080 35.97% 35.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11242625 18.71% 54.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8368043 13.92% 68.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7334755 12.21% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4853612 8.08% 88.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3598814 5.99% 94.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1699571 2.83% 97.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 846136 1.41% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 534680 0.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21602316 35.94% 35.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11403464 18.97% 54.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8200759 13.64% 68.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7319332 12.18% 80.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4922118 8.19% 88.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3558954 5.92% 94.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1700735 2.83% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 865239 1.44% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 534507 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 60095316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 60107424 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 104237 3.89% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 1 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1507488 56.31% 60.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1065632 39.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 107169 4.01% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1504678 56.36% 60.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1057992 39.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56897133 52.79% 52.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 88643 0.08% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 206 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29161823 27.05% 79.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21641500 20.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56937666 52.83% 52.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 88934 0.08% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 306 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29100662 27.00% 79.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21655782 20.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107789312 # Type of FU issued -system.cpu.iq.rate 1.752870 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2677358 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024839 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 278681648 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124068735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105618069 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 726 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1184 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 180 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110466305 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 365 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1905391 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107783359 # Type of FU issued +system.cpu.iq.rate 1.752259 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2669841 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024770 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 278658374 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124040880 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105647232 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 803 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1299 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 239 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110452800 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 400 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1897681 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2662397 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4708 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16942 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1913561 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2596713 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5092 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1940178 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 60 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 48 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 61 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1842606 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 954066 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 28419 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112530590 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 448477 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29971388 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22471181 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 763809 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1185 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1150 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16942 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 525308 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 249263 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 774571 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106544172 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28789537 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1245140 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1846089 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 949061 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 28680 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112509386 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 471926 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29905745 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22497839 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 767420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1122 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1174 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17660 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 518600 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 257124 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 775724 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106553535 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28745908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1229824 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 82469 # number of nop insts executed -system.cpu.iew.exec_refs 50119660 # number of memory reference insts executed -system.cpu.iew.exec_branches 14611553 # Number of branches executed -system.cpu.iew.exec_stores 21330123 # Number of stores executed -system.cpu.iew.exec_rate 1.732621 # Inst execution rate -system.cpu.iew.wb_sent 105962456 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105618249 # cumulative count of insts written-back -system.cpu.iew.wb_producers 52610922 # num instructions producing a value -system.cpu.iew.wb_consumers 101691142 # num instructions consuming a value +system.cpu.iew.exec_nop 79719 # number of nop insts executed +system.cpu.iew.exec_refs 50100729 # number of memory reference insts executed +system.cpu.iew.exec_branches 14610772 # Number of branches executed +system.cpu.iew.exec_stores 21354821 # Number of stores executed +system.cpu.iew.exec_rate 1.732265 # Inst execution rate +system.cpu.iew.wb_sent 105985847 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105647471 # cumulative count of insts written-back +system.cpu.iew.wb_producers 52628676 # num instructions producing a value +system.cpu.iew.wb_consumers 101773898 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.717564 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.517360 # average fanout of values written-back +system.cpu.iew.wb_rate 1.717535 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.517114 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 70922599 # The number of committed instructions -system.cpu.commit.commitCommittedOps 100641847 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11889102 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 703458 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 696794 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 58252711 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.727677 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.445395 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 70922804 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100642052 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 11867683 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 703499 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 697454 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 58261336 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.727424 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.444675 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25477544 43.74% 43.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14542293 24.96% 68.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4151131 7.13% 75.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3607676 6.19% 82.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2313094 3.97% 85.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1905802 3.27% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 675667 1.16% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 497156 0.85% 91.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5082348 8.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25494739 43.76% 43.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14514509 24.91% 68.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4165612 7.15% 75.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3613399 6.20% 82.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2299623 3.95% 85.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1924742 3.30% 89.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 677832 1.16% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 500112 0.86% 91.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5070768 8.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 58252711 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70922599 # Number of instructions committed -system.cpu.commit.committedOps 100641847 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 58261336 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70922804 # Number of instructions committed +system.cpu.commit.committedOps 100642052 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47866611 # Number of memory references committed -system.cpu.commit.loads 27308991 # Number of loads committed +system.cpu.commit.refs 47866693 # Number of memory references committed +system.cpu.commit.loads 27309032 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13670510 # Number of branches committed +system.cpu.commit.branches 13670551 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91480315 # Number of committed integer instructions. +system.cpu.commit.int_insts 91480479 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5082348 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5070768 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 165676013 # The number of ROB reads -system.cpu.rob.rob_writes 226913156 # The number of ROB writes -system.cpu.timesIdled 61654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1397744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70917047 # Number of Instructions Simulated -system.cpu.committedOps 100636295 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70917047 # Number of Instructions Simulated -system.cpu.cpi 0.867113 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.867113 # CPI: Total CPI of All Threads -system.cpu.ipc 1.153253 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.153253 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 512941825 # number of integer regfile reads -system.cpu.int_regfile_writes 103506893 # number of integer regfile writes -system.cpu.fp_regfile_reads 822 # number of floating regfile reads -system.cpu.fp_regfile_writes 678 # number of floating regfile writes -system.cpu.misc_regfile_reads 145707136 # number of misc regfile reads -system.cpu.misc_regfile_writes 35604 # number of misc regfile writes -system.cpu.icache.replacements 30139 # number of replacements -system.cpu.icache.tagsinuse 1825.169858 # Cycle average of tags in use -system.cpu.icache.total_refs 12199552 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 32178 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379.127105 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 165675004 # The number of ROB reads +system.cpu.rob.rob_writes 226873042 # The number of ROB writes +system.cpu.timesIdled 61564 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1403664 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70917252 # Number of Instructions Simulated +system.cpu.committedOps 100636500 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70917252 # Number of Instructions Simulated +system.cpu.cpi 0.867364 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.867364 # CPI: Total CPI of All Threads +system.cpu.ipc 1.152918 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.152918 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 512909735 # number of integer regfile reads +system.cpu.int_regfile_writes 103521788 # number of integer regfile writes +system.cpu.fp_regfile_reads 1198 # number of floating regfile reads +system.cpu.fp_regfile_writes 998 # number of floating regfile writes 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0.002642 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002642 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002642 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11935.669618 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11935.669618 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11935.669618 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,224 +382,224 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes 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32216 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 32216 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262568000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 262568000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262568000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 262568000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262568000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 262568000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 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-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33312.127449 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33312.127449 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18894 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18894 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 17842 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 17842 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46436760 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46436760 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46436760 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46436760 # number of overall (read+write) accesses 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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 210500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 199000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19136.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19900 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123777 # number of writebacks -system.cpu.dcache.writebacks::total 123777 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54544 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54544 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432641 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1432641 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1487185 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1487185 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1487185 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1487185 # number of overall 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3665143000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4711142000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4711142000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4711142000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4711142000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003506 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003506 # mshr miss rate for overall accesses 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overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.798156 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34243.122481 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34226.581586 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1172.413793 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34296.034353 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34243.122481 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34281.383167 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34243.122481 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34281.383167 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3518172500 # number of ReadExReq miss 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+system.cpu.l2cache.Writeback_accesses::writebacks 123771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 123771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 50 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 50 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 106909 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 106909 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 30950 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 162835 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 193785 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 30950 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 162835 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 193785 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.184653 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.490380 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959648 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.184653 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.798477 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.184653 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.798477 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34240.594926 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34230.082042 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 871.794872 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34291.851455 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34240.594926 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.822489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34240.594926 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.822489 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -608,59 +608,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88455 # number of writebacks -system.cpu.l2cache.writebacks::total 88455 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 88460 # number of writebacks +system.cpu.l2cache.writebacks::total 88460 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 23 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5684 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27361 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33045 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 29 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102581 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102581 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5684 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 129942 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 135626 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5684 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 129942 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 135626 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176568000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 850424500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1026992500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 901000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 901000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3193612500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3193612500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176568000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4044037000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4220605000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176568000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4044037000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 4220605000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488677 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959661 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797763 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31064.039409 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31081.630788 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31068.965517 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31132.592780 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31064.039409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31121.862062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31064.039409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31121.862062 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 90 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5692 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33050 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102595 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102595 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5692 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 129953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 135645 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5692 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 129953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 135645 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176784500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 850283000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027067500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1211000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1211000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3193896000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3193896000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4044179000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4220963500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4044179000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4220963500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.489182 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959648 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.798066 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.798066 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31058.415320 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31079.866949 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31051.282051 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31131.107754 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31058.415320 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31120.320424 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31058.415320 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31120.320424 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index e57dda708..fc20c8ede 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 89b488ea9..34e49ce66 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932162000 # Number of ticks simulated final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2464229 # Simulator instruction rate (inst/s) -host_op_rate 3496968 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1874136829 # Simulator tick rate (ticks/s) -host_mem_usage 220180 # Number of bytes of host memory used -host_seconds 28.78 # Real time elapsed on the host +host_inst_rate 2398112 # Simulator instruction rate (inst/s) +host_op_rate 3403143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1823852749 # Simulator tick rate (ticks/s) +host_mem_usage 223920 # Number of bytes of host memory used +host_seconds 29.57 # Real time elapsed on the host sim_insts 70913189 # Number of instructions simulated sim_ops 100632437 # Number of ops (including micro ops) simulated system.physmem.bytes_read 419153654 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 100632437 # Nu system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 10735849 # number of instructions that are conditional controls system.cpu.num_int_insts 91472788 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index a85bd162d..69f507d60 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 0f7cee094..37dcac738 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133117 # Nu sim_ticks 133117442000 # Number of ticks simulated final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1269489 # Simulator instruction rate (inst/s) -host_op_rate 1800168 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2401339947 # Simulator tick rate (ticks/s) -host_mem_usage 229088 # Number of bytes of host memory used -host_seconds 55.43 # Real time elapsed on the host +host_inst_rate 1310173 # Simulator instruction rate (inst/s) +host_op_rate 1857860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2478297620 # Simulator tick rate (ticks/s) +host_mem_usage 232836 # Number of bytes of host memory used +host_seconds 53.71 # Real time elapsed on the host sim_insts 70373636 # Number of instructions simulated sim_ops 99791663 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8570688 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 99791663 # Nu system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 10735849 # number of instructions that are conditional controls system.cpu.num_int_insts 91472788 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 51e908aa2..cdbe03d5f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr index e45cd058f..b4d96e4ea 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 8fb7001b0..d23947013 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:51:32 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:27:07 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 464073050000 because target called exit() +Exiting @ tick 464094642500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 9e645d1ea..b46ca3b4f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.464073 # Number of seconds simulated -sim_ticks 464073050000 # Number of ticks simulated -final_tick 464073050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.464095 # Number of seconds simulated +sim_ticks 464094642500 # Number of ticks simulated +final_tick 464094642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176271 # Simulator instruction rate (inst/s) -host_op_rate 196643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52961695 # Simulator tick rate (ticks/s) -host_mem_usage 223676 # Number of bytes of host memory used -host_seconds 8762.43 # Real time elapsed on the host -sim_insts 1544563056 # Number of instructions simulated -sim_ops 1723073869 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 189754368 # Number of bytes read from this memory -system.physmem.bytes_inst_read 48448 # Number of instructions bytes read from this memory -system.physmem.bytes_written 78230272 # Number of bytes written to this memory -system.physmem.num_reads 2964912 # Number of read requests responded to by this memory -system.physmem.num_writes 1222348 # Number of write requests responded to by this memory +host_inst_rate 178110 # Simulator instruction rate (inst/s) +host_op_rate 198694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53516537 # Simulator tick rate (ticks/s) +host_mem_usage 227392 # Number of bytes of host memory used +host_seconds 8671.99 # Real time elapsed on the host +sim_insts 1544563041 # Number of instructions simulated +sim_ops 1723073854 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 189817088 # Number of bytes read from this memory +system.physmem.bytes_inst_read 48640 # Number of instructions bytes read from this memory +system.physmem.bytes_written 78237376 # Number of bytes written to this memory +system.physmem.num_reads 2965892 # Number of read requests responded to by this memory +system.physmem.num_writes 1222459 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 408889006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 104397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 168573185 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 577462190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 409005127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 104806 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 168580649 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 577585776 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,107 +64,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 928146101 # number of cpu cycles simulated +system.cpu.numCycles 928189286 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 300566019 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 246342426 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16106991 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 172736235 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156347078 # Number of BTB hits +system.cpu.BPredUnit.lookups 300558884 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 246363041 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16110008 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 171748174 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156362542 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18335765 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 410 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 292802110 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2158556881 # Number of instructions fetch has processed -system.cpu.fetch.Branches 300566019 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174682843 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 429264774 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83785432 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 129176492 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 309 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 283792946 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5380579 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 918501449 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.613879 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.238743 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18325675 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 390 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 292832773 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2158671516 # Number of instructions fetch has processed +system.cpu.fetch.Branches 300558884 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174688217 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 429285540 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83802150 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 129138530 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 283809493 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5370008 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 918527985 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.613925 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.238783 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 489236723 53.26% 53.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23024875 2.51% 55.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38786234 4.22% 59.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47824320 5.21% 65.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40756189 4.44% 69.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46964078 5.11% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39095628 4.26% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18144974 1.98% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174668428 19.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 489242491 53.26% 53.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23031671 2.51% 55.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38788083 4.22% 59.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47826065 5.21% 65.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40763412 4.44% 69.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46954546 5.11% 74.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39099426 4.26% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18124481 1.97% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174697810 19.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 918501449 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323835 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325665 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 322112975 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 109206216 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403275742 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16649458 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 67257058 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46176709 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 759 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2347040926 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2511 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 67257058 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 343744693 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50775772 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22198 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397120131 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 59581597 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2290149919 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23251 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4667919 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 46275027 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2264746735 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10570831764 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10570827058 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4706 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319983 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 558426752 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5766 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 136911238 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624866711 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 218769389 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86004799 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66542105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2190647853 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1858 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016093743 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4890618 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462875235 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1075025863 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1351 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 918501449 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.194982 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.923350 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 918527985 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323812 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325680 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 322137890 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 109173401 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403303983 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16642613 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 67270098 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46182318 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 747 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2347171741 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2550 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 67270098 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 343773810 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50758192 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21988 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397138305 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 59565592 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2290275122 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23158 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4666704 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 46265569 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 2 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2264842596 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10571584644 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10571581459 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3185 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319959 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 558522637 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5679 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5674 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 136915079 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624891325 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 218844969 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86018221 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66187056 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2190772661 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1712 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2016120341 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4885308 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 463006686 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1075673735 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1208 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 918527985 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.194947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.923224 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 251234212 27.35% 27.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 138874484 15.12% 42.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158306174 17.24% 59.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116338080 12.67% 72.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125703968 13.69% 86.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75541719 8.22% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39131512 4.26% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10691268 1.16% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2680032 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 251260735 27.35% 27.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 138867546 15.12% 42.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158222967 17.23% 59.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116427032 12.68% 72.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125736326 13.69% 86.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75508875 8.22% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39162431 4.26% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10675084 1.16% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2666989 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 918501449 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 918527985 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 823704 3.29% 3.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4653 0.02% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 822239 3.28% 3.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4824 0.02% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available @@ -192,13 +192,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18995164 75.78% 79.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5243478 20.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19001190 75.81% 79.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5234373 20.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234318256 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 931291 0.05% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234297815 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 931066 0.05% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued @@ -220,160 +220,160 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 86 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 50 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 19 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587032832 29.12% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193811220 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587044073 29.12% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193847304 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016093743 # Type of FU issued -system.cpu.iq.rate 2.172173 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25066999 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4980646048 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2653710289 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1958144551 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 870 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 197 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2041160487 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 255 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63652463 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2016120341 # Type of FU issued +system.cpu.iq.rate 2.172100 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25062626 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4980716257 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2653967070 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1958162011 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 344 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2041182792 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 175 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63608263 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138939936 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 281971 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189096 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43922339 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138964553 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 284704 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189296 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43997922 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 450534 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 451252 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 67257058 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23170910 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1317099 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2190657684 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5590225 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624866711 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 218769389 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1791 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 207758 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 50528 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189096 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8640354 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10202609 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18842963 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986590915 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 572448085 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29502828 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 67270098 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23165985 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1316827 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2190782552 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5581738 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624891325 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 218844969 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1648 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 207697 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 50017 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189296 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8647984 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10198062 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18846046 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986617242 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 572452659 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29503099 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 7973 # number of nop insts executed -system.cpu.iew.exec_refs 763288309 # number of memory reference insts executed -system.cpu.iew.exec_branches 238204396 # Number of branches executed -system.cpu.iew.exec_stores 190840224 # Number of stores executed -system.cpu.iew.exec_rate 2.140386 # Inst execution rate -system.cpu.iew.wb_sent 1967133109 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1958144748 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296172102 # num instructions producing a value -system.cpu.iew.wb_consumers 2068722658 # num instructions consuming a value +system.cpu.iew.exec_nop 8179 # number of nop insts executed +system.cpu.iew.exec_refs 763318356 # number of memory reference insts executed +system.cpu.iew.exec_branches 238198091 # Number of branches executed +system.cpu.iew.exec_stores 190865697 # Number of stores executed +system.cpu.iew.exec_rate 2.140315 # Inst execution rate +system.cpu.iew.wb_sent 1967150761 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1958162143 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296167059 # num instructions producing a value +system.cpu.iew.wb_consumers 2068734310 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.109738 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626557 # average fanout of values written-back +system.cpu.iew.wb_rate 2.109658 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626551 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1544563074 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1723073887 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 467651163 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 507 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16106465 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 851244392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.024182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.756273 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1544563059 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073872 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 467775476 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 504 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16109498 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 851257888 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.024150 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.756084 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 363008407 42.64% 42.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192701589 22.64% 65.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73550522 8.64% 73.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35106838 4.12% 78.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18707332 2.20% 80.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30658705 3.60% 83.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19651115 2.31% 86.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10957875 1.29% 87.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106902009 12.56% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 363004636 42.64% 42.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192697561 22.64% 65.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73553862 8.64% 73.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35091204 4.12% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18733793 2.20% 80.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30684966 3.60% 83.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19668934 2.31% 86.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10962087 1.29% 87.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106860845 12.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 851244392 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563074 # Number of instructions committed -system.cpu.commit.committedOps 1723073887 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 851257888 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563059 # Number of instructions committed +system.cpu.commit.committedOps 1723073872 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773825 # Number of memory references committed -system.cpu.commit.loads 485926775 # Number of loads committed +system.cpu.commit.refs 660773819 # Number of memory references committed +system.cpu.commit.loads 485926772 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462369 # Number of branches committed +system.cpu.commit.branches 213462366 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941869 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106902009 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106860845 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2935066834 # The number of ROB reads -system.cpu.rob.rob_writes 4448881416 # The number of ROB writes -system.cpu.timesIdled 899412 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9644652 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563056 # Number of Instructions Simulated -system.cpu.committedOps 1723073869 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563056 # Number of Instructions Simulated -system.cpu.cpi 0.600912 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.600912 # CPI: Total CPI of All Threads -system.cpu.ipc 1.664138 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.664138 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9951907734 # number of integer regfile reads -system.cpu.int_regfile_writes 1938294940 # number of integer regfile writes -system.cpu.fp_regfile_reads 210 # number of floating regfile reads -system.cpu.fp_regfile_writes 230 # number of floating regfile writes -system.cpu.misc_regfile_reads 2898206993 # number of misc regfile reads -system.cpu.misc_regfile_writes 134 # number of misc regfile writes -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 634.912102 # Cycle average of tags in use -system.cpu.icache.total_refs 283791788 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 361058.254453 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2935245792 # The number of ROB reads +system.cpu.rob.rob_writes 4449143808 # The number of ROB writes +system.cpu.timesIdled 899784 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9661301 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563041 # Number of Instructions Simulated +system.cpu.committedOps 1723073854 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563041 # Number of Instructions Simulated +system.cpu.cpi 0.600940 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600940 # CPI: Total CPI of All Threads +system.cpu.ipc 1.664060 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.664060 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9952061686 # number of integer regfile reads +system.cpu.int_regfile_writes 1938314522 # number of integer regfile writes +system.cpu.fp_regfile_reads 132 # number of floating regfile reads +system.cpu.fp_regfile_writes 135 # number of floating regfile writes +system.cpu.misc_regfile_reads 2898335768 # number of misc regfile reads +system.cpu.misc_regfile_writes 128 # number of misc regfile writes +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.tagsinuse 636.409684 # Cycle average of tags in use +system.cpu.icache.total_refs 283808312 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 793 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 357891.944515 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 634.912102 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.310016 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.310016 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 283791788 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 283791788 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 283791788 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 283791788 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 283791788 # number of overall hits -system.cpu.icache.overall_hits::total 283791788 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses -system.cpu.icache.overall_misses::total 1158 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38624000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38624000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38624000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38624000 # number of demand (read+write) miss cycles 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(read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27049500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27049500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 388 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 388 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 388 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 388 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 388 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 793 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 793 # number of demand (read+write) MSHR misses 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demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318498003794 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 318498003794 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 504107290 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 504107290 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 66 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 66 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 676644624 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 676644624 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 676644624 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 676644624 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021219 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.041237 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 91 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 91 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 63 # number of StoreCondReq accesses(hits+misses) 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17681.102760 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24885.656309 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 270494777 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 161000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 91798 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.630395 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16100 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.990108 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24839.592141 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20025.490931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20025.490931 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 271743722 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 161500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 91838 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2958.946427 # average number of cycles each access was blocked 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MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 757 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2048504 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2049261 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915651 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 915651 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2964155 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2964912 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2964155 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2964912 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23603500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63886529000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63910132500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922104500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922104500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23603500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92808633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 92832237000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23603500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92808633500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 92832237000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265059 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483449 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31180.317041 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.919332 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.384441 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1222459 # number of writebacks +system.cpu.l2cache.writebacks::total 1222459 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 760 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2049470 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2050230 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915662 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 915662 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 760 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2965132 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2965892 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 760 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2965132 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2965892 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63915816500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63939496500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922990000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922990000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92838806500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 92862486500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23680000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92838806500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 92862486500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265146 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483481 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308114 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308114 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.894737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.509927 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.972049 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.894737 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.176579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.894737 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.176579 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 6c19f0c57..9508b6eff 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 1bd7f49d7..bd3b0790d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu sim_ticks 861538205000 # Number of ticks simulated final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3097767 # Simulator instruction rate (inst/s) -host_op_rate 3455787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1727895925 # Simulator tick rate (ticks/s) -host_mem_usage 212936 # Number of bytes of host memory used -host_seconds 498.61 # Real time elapsed on the host +host_inst_rate 3009474 # Simulator instruction rate (inst/s) +host_op_rate 3357290 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1678647401 # Simulator tick rate (ticks/s) +host_mem_usage 216676 # Number of bytes of host memory used +host_seconds 513.23 # Real time elapsed on the host sim_insts 1544563049 # Number of instructions simulated sim_ops 1723073862 # Number of ops (including micro ops) simulated system.physmem.bytes_read 7759650064 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 1723073862 # Nu system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498450 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941850 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 9736169e4..ce3f8d9d1 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index e00ec713c..515a2d834 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.431420 # Nu sim_ticks 2431419954000 # Number of ticks simulated final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1647360 # Simulator instruction rate (inst/s) -host_op_rate 1838469 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2603021191 # Simulator tick rate (ticks/s) -host_mem_usage 221840 # Number of bytes of host memory used -host_seconds 934.08 # Real time elapsed on the host +host_inst_rate 1665877 # Simulator instruction rate (inst/s) +host_op_rate 1859134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2632279795 # Simulator tick rate (ticks/s) +host_mem_usage 225588 # Number of bytes of host memory used +host_seconds 923.69 # Real time elapsed on the host sim_insts 1538759609 # Number of instructions simulated sim_ops 1717270343 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172766016 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 1717270343 # Nu system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498450 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941850 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index eef0e971d..b5f680e0c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 8c858c201..85e384123 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:58:01 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:41:00 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav @@ -23,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 88632152500 because target called exit() +122 123 124 Exiting @ tick 88752965000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 64cc4b80a..dd675185f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.088632 # Number of seconds simulated -sim_ticks 88632152500 # Number of ticks simulated -final_tick 88632152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.088753 # Number of seconds simulated +sim_ticks 88752965000 # Number of ticks simulated +final_tick 88752965000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134694 # Simulator instruction rate (inst/s) -host_op_rate 147478 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69281557 # Simulator tick rate (ticks/s) -host_mem_usage 227272 # Number of bytes of host memory used -host_seconds 1279.30 # Real time elapsed on the host -sim_insts 172315139 # Number of instructions simulated -sim_ops 188668622 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 244352 # Number of bytes read from this memory -system.physmem.bytes_inst_read 132032 # Number of instructions bytes read from this memory +host_inst_rate 137389 # Simulator instruction rate (inst/s) +host_op_rate 150427 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70763677 # Simulator tick rate (ticks/s) +host_mem_usage 230996 # Number of bytes of host memory used +host_seconds 1254.22 # Real time elapsed on the host +sim_insts 172315134 # Number of instructions simulated +sim_ops 188668617 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 245120 # Number of bytes read from this memory +system.physmem.bytes_inst_read 132800 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3818 # Number of read requests responded to by this memory +system.physmem.num_reads 3830 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2756923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1489663 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2756923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2761823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1496288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2761823 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,315 +63,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 177264306 # number of cpu cycles simulated +system.cpu.numCycles 177505931 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96525090 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 74749964 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6668938 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46796658 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44215963 # Number of BTB hits +system.cpu.BPredUnit.lookups 95571520 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 75157417 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6614903 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 45712904 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 43519744 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4389679 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114813 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 39966229 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 381133369 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96525090 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48605642 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80754991 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27412697 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 35762422 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 4405793 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 115592 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 39981641 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 379098511 # Number of instructions fetch has processed +system.cpu.fetch.Branches 95571520 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47925537 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80419547 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27360994 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36321255 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9389 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 9619 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 36758976 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1679336 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 177207232 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.350259 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.058598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36794328 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1674379 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 177448059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.339145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.059886 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 96615622 54.52% 54.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5430463 3.06% 57.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10300720 5.81% 63.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10325695 5.83% 69.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8756862 4.94% 74.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6889395 3.89% 78.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6237128 3.52% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8634116 4.87% 86.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24017231 13.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 97198391 54.78% 54.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5418485 3.05% 57.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10378909 5.85% 63.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10238278 5.77% 69.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8615978 4.86% 74.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6776678 3.82% 78.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6211591 3.50% 81.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8309244 4.68% 86.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24300505 13.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 177207232 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.544526 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.150085 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46183847 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 34297054 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74780894 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1386206 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20559231 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14846637 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 165269 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392589126 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 748420 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20559231 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52356007 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 443712 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29007637 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 69958724 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4881921 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 367191514 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 92621 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2515930 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 627979317 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1558602975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1541578337 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17024638 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298063528 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 329915789 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2303042 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2294526 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21773052 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 41898813 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 15562062 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3360389 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2124393 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 324040554 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2103109 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 248819756 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 576048 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 136002156 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 346792965 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 466892 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 177207232 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.404117 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.633607 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 177448059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.538413 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.135695 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46244696 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 34742594 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74394013 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1503955 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20562801 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14594283 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162509 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 391670680 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 678477 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20562801 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52453090 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 543058 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28975165 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69650922 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5263023 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 366605935 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 86833 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2872425 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 626371131 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1557311065 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1540047768 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17263297 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298063520 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 328307611 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2289898 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2280879 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 22663777 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 42181045 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 15903489 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4032649 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2834648 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 323955475 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2094173 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249134070 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 566766 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 135834494 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 345192034 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 457957 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 177448059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.403983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.631604 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 78492090 44.29% 44.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 28577659 16.13% 60.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26660356 15.04% 75.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 21359445 12.05% 87.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12490578 7.05% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5763951 3.25% 97.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3149996 1.78% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 544249 0.31% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 168908 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 78553048 44.27% 44.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 28575726 16.10% 60.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26790293 15.10% 75.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21442072 12.08% 87.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12420165 7.00% 94.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5896079 3.32% 97.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3065113 1.73% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 544695 0.31% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 160868 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 177207232 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 177448059 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 627952 27.03% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5535 0.24% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 48 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1223626 52.68% 79.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 465789 20.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 586662 26.53% 26.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5526 0.25% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 139 0.01% 26.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 26 0.00% 26.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1170221 52.93% 79.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 448459 20.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194916381 78.34% 78.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 997256 0.40% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33202 0.01% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 163976 0.07% 78.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 252533 0.10% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76462 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 463893 0.19% 79.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206151 0.08% 79.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71843 0.03% 79.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 37907135 15.23% 94.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13730603 5.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194883965 78.22% 78.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 995226 0.40% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33040 0.01% 78.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164177 0.07% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 253566 0.10% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76466 0.03% 78.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 466502 0.19% 79.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206303 0.08% 79.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71862 0.03% 79.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38048843 15.27% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13933800 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 248819756 # Type of FU issued -system.cpu.iq.rate 1.403665 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2322951 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009336 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 674003670 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 460004017 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 236904190 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3742073 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2153997 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1836768 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 249257876 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1884831 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1793335 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249134070 # Type of FU issued +system.cpu.iq.rate 1.403525 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2211033 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008875 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 674734020 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 459694658 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237377529 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3759978 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2202441 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1840495 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 249450810 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1894293 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1632018 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12046906 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20817 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12587 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2915006 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12329139 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16500 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13400 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3256434 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 150 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 152 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20559231 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11749 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 500 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 326199297 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1048998 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 41898813 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 15562062 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2080622 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 86 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 254 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12587 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4245338 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3938864 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8184202 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 241936044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36336721 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6883712 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20562801 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11850 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 518 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 326106294 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1027766 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 42181045 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 15903489 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2071684 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 91 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 257 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13400 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4154974 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3938016 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8092990 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242315384 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36530974 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6818686 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 55634 # number of nop insts executed -system.cpu.iew.exec_refs 49775211 # number of memory reference insts executed -system.cpu.iew.exec_branches 53836233 # Number of branches executed -system.cpu.iew.exec_stores 13438490 # Number of stores executed -system.cpu.iew.exec_rate 1.364832 # Inst execution rate -system.cpu.iew.wb_sent 239697329 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 238740958 # cumulative count of insts written-back -system.cpu.iew.wb_producers 143497606 # num instructions producing a value -system.cpu.iew.wb_consumers 250089451 # num instructions consuming a value +system.cpu.iew.exec_nop 56646 # number of nop insts executed +system.cpu.iew.exec_refs 50147755 # number of memory reference insts executed +system.cpu.iew.exec_branches 53661515 # Number of branches executed +system.cpu.iew.exec_stores 13616781 # Number of stores executed +system.cpu.iew.exec_rate 1.365111 # Inst execution rate +system.cpu.iew.wb_sent 240126243 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239218024 # cumulative count of insts written-back +system.cpu.iew.wb_producers 143974107 # num instructions producing a value +system.cpu.iew.wb_consumers 250982237 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.346808 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.573785 # average fanout of values written-back +system.cpu.iew.wb_rate 1.347662 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.573643 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 172329527 # The number of committed instructions -system.cpu.commit.commitCommittedOps 188683010 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 137516300 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1636217 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6533063 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 156648002 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.204503 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.917568 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 172329522 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188683005 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 137423310 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1636216 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6480810 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 156885259 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.202682 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.914186 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79778069 50.93% 50.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 37231664 23.77% 74.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15824405 10.10% 84.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8489087 5.42% 90.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4756905 3.04% 93.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1480671 0.95% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1767391 1.13% 95.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1258526 0.80% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6061284 3.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79822518 50.88% 50.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 37410215 23.85% 74.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15894720 10.13% 84.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8464339 5.40% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4786654 3.05% 93.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1458057 0.93% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1746360 1.11% 95.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1243896 0.79% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6058500 3.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 156648002 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172329527 # Number of instructions committed -system.cpu.commit.committedOps 188683010 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 156885259 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172329522 # Number of instructions committed +system.cpu.commit.committedOps 188683005 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498963 # Number of memory references committed -system.cpu.commit.loads 29851907 # Number of loads committed +system.cpu.commit.refs 42498961 # Number of memory references committed +system.cpu.commit.loads 29851906 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40284105 # Number of branches committed +system.cpu.commit.branches 40284104 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115913 # Number of committed integer instructions. +system.cpu.commit.int_insts 150115909 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6061284 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6058500 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 476780827 # The number of ROB reads -system.cpu.rob.rob_writes 673054212 # The number of ROB writes -system.cpu.timesIdled 1680 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 57074 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172315139 # Number of Instructions Simulated -system.cpu.committedOps 188668622 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172315139 # Number of Instructions Simulated -system.cpu.cpi 1.028722 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.028722 # CPI: Total CPI of All Threads -system.cpu.ipc 0.972080 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.972080 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1073592031 # number of integer regfile reads -system.cpu.int_regfile_writes 384645437 # number of integer regfile writes -system.cpu.fp_regfile_reads 2906196 # number of floating regfile reads -system.cpu.fp_regfile_writes 2487132 # number of floating regfile writes -system.cpu.misc_regfile_reads 464057527 # number of misc regfile reads -system.cpu.misc_regfile_writes 824880 # number of misc regfile writes +system.cpu.rob.rob_reads 476927873 # The number of ROB reads +system.cpu.rob.rob_writes 672877067 # The number of ROB writes +system.cpu.timesIdled 1694 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 57872 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172315134 # Number of Instructions Simulated +system.cpu.committedOps 188668617 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172315134 # Number of Instructions Simulated +system.cpu.cpi 1.030124 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.030124 # CPI: Total CPI of All Threads +system.cpu.ipc 0.970757 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.970757 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1076172941 # number of integer regfile reads +system.cpu.int_regfile_writes 384809064 # number of integer regfile writes +system.cpu.fp_regfile_reads 2908130 # number of floating regfile reads +system.cpu.fp_regfile_writes 2493684 # number of floating regfile writes +system.cpu.misc_regfile_reads 462718931 # number of misc regfile reads +system.cpu.misc_regfile_writes 824878 # number of misc regfile writes system.cpu.icache.replacements 2566 # number of replacements -system.cpu.icache.tagsinuse 1366.287383 # Cycle average of tags in use -system.cpu.icache.total_refs 36753975 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4308 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8531.563370 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 1372.206162 # Cycle average of tags in use +system.cpu.icache.total_refs 36789295 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4311 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8533.819299 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1366.287383 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.667133 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.667133 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36753975 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36753975 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36753975 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36753975 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36753975 # number of overall hits -system.cpu.icache.overall_hits::total 36753975 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5001 # number of ReadReq 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-system.cpu.icache.ReadReq_accesses::cpu.inst 36758976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36758976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36758976 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36758976 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36758976 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36758976 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000136 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000136 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000136 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21760.647870 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21760.647870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21760.647870 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1372.206162 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.670023 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.670023 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36789295 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36789295 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36789295 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36789295 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36789295 # number of overall hits +system.cpu.icache.overall_hits::total 36789295 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5033 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5033 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5033 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5033 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5033 # number of overall misses +system.cpu.icache.overall_misses::total 5033 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 109886500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 109886500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 109886500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 109886500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 109886500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 109886500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36794328 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36794328 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36794328 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36794328 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36794328 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36794328 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21833.200874 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21833.200874 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21833.200874 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,94 +381,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 692 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 692 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 692 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 692 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 692 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4309 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4309 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4309 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4309 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4309 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4309 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78064500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 78064500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78064500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 78064500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78064500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 78064500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 722 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 722 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 722 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 722 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 722 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 722 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4311 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4311 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4311 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4311 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4311 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4311 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 78475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 78475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78475000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 78475000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18116.616384 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18116.616384 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18116.616384 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18203.433078 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18203.433078 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18203.433078 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 55 # number of replacements -system.cpu.dcache.tagsinuse 1415.234721 # Cycle average of tags in use -system.cpu.dcache.total_refs 46401176 # Total number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1411.383328 # Cycle average of tags in use +system.cpu.dcache.total_refs 46835892 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 24893.334764 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25126.551502 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1415.234721 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345516 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345516 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 33991693 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 33991693 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356758 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356758 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 27891 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 27891 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 24829 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 24829 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46348451 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46348451 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46348451 # number of overall hits -system.cpu.dcache.overall_hits::total 46348451 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1783 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1783 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7529 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7529 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1411.383328 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.344576 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.344576 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34426629 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34426629 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356789 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356789 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 27646 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 27646 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 24828 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 24828 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46783418 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46783418 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46783418 # number of overall hits +system.cpu.dcache.overall_hits::total 46783418 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1806 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1806 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7498 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7498 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9312 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9312 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9312 # number of overall misses -system.cpu.dcache.overall_misses::total 9312 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58909500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58909500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 235574500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 235574500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9304 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9304 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9304 # number of overall misses +system.cpu.dcache.overall_misses::total 9304 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59300000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59300000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 235066000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 235066000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 294484000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 294484000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 294484000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 294484000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 33993476 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 33993476 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 294366000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 294366000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 294366000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 294366000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34428435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34428435 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27893 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 27893 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 24829 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 24829 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46357763 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46357763 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46357763 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46357763 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27648 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 27648 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 24828 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 24828 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46792722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46792722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46792722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46792722 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000052 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000609 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000606 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000201 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000201 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33039.540101 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31288.949396 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000199 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000199 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32834.994463 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31350.493465 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31624.140893 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31624.140893 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31638.650043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31638.650043 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,121 +479,116 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 20 # number of writebacks system.cpu.dcache.writebacks::total 20 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1009 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6438 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6438 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1032 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1032 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6408 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6408 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7447 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7447 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7447 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7447 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7440 # number of demand (read+write) MSHR hits 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demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4308 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6175 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4311 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1864 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6172 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.479573 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894057 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.990826 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.479573 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.950644 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34334.274421 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34270.211742 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34334.274421 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -602,56 +598,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 17 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 20 # 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-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 675 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2738 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 16 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3818 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2063 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3830 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3818 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64062500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21038500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85101000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33524500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33524500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64062500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54563000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 118625500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64062500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54563000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 118625500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.872093 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_misses::total 3830 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64436000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20976000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85412000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33589000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33589000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64436000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54565000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 119001000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64436000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54565000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 119001000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869509 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992661 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31053.078042 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.148148 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31041.203704 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31053.078042 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31090.028490 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31053.078042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31090.028490 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31053.493976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31167.904903 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31043.438078 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31053.493976 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31091.168091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31053.493976 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31091.168091 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 8e458b793..7c9dcfcb7 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 5d6608220..d09b5d511 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu sim_ticks 103106771000 # Number of ticks simulated final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3118510 # Simulator instruction rate (inst/s) -host_op_rate 3414466 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1865971013 # Simulator tick rate (ticks/s) -host_mem_usage 216012 # Number of bytes of host memory used -host_seconds 55.26 # Real time elapsed on the host +host_inst_rate 3116971 # Simulator instruction rate (inst/s) +host_op_rate 3412781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1865050079 # Simulator tick rate (ticks/s) +host_mem_usage 219792 # Number of bytes of host memory used +host_seconds 55.28 # Real time elapsed on the host sim_insts 172317417 # Number of instructions simulated sim_ops 188670900 # Number of ops (including micro ops) simulated system.physmem.bytes_read 869973902 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 188670900 # Nu system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3504894 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 31949383 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 32534025 # number of instructions that are conditional controls system.cpu.num_int_insts 150106226 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions system.cpu.num_int_register_reads 809396650 # number of times the integer registers were read diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index f90360da8..f911a437c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index f86e3b057..96e0b8441 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.232077 # Nu sim_ticks 232077154000 # Number of ticks simulated final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1867609 # Simulator instruction rate (inst/s) -host_op_rate 2045232 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2522247357 # Simulator tick rate (ticks/s) -host_mem_usage 224952 # Number of bytes of host memory used -host_seconds 92.01 # Real time elapsed on the host +host_inst_rate 1962361 # Simulator instruction rate (inst/s) +host_op_rate 2148995 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2650211347 # Simulator tick rate (ticks/s) +host_mem_usage 228700 # Number of bytes of host memory used +host_seconds 87.57 # Real time elapsed on the host sim_insts 171842491 # Number of instructions simulated sim_ops 188185929 # Number of ops (including micro ops) simulated system.physmem.bytes_read 220992 # Number of bytes read from this memory @@ -71,7 +71,7 @@ system.cpu.committedOps 188185929 # Nu system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3504894 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 31949383 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 32534025 # number of instructions that are conditional controls system.cpu.num_int_insts 150106226 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions system.cpu.num_int_register_reads 898652287 # number of times the integer registers were read diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index a8278f7b9..f60d68e94 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.411694 # Nu sim_ticks 2411694099500 # Number of ticks simulated final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1397437 # Simulator instruction rate (inst/s) -host_op_rate 1806505 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54757981393 # Simulator tick rate (ticks/s) -host_mem_usage 382236 # Number of bytes of host memory used -host_seconds 44.04 # Real time elapsed on the host +host_inst_rate 2022463 # Simulator instruction rate (inst/s) +host_op_rate 2614492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79249307765 # Simulator tick rate (ticks/s) +host_mem_usage 379912 # Number of bytes of host memory used +host_seconds 30.43 # Real time elapsed on the host sim_insts 61546998 # Number of instructions simulated sim_ops 79563488 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory @@ -264,7 +264,7 @@ system.cpu0.committedOps 44975797 # Nu system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses system.cpu0.num_func_calls 1311755 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls +system.cpu0.num_conditional_control_insts 4652122 # number of instructions that are conditional controls system.cpu0.num_int_insts 39858123 # number of integer instructions system.cpu0.num_fp_insts 4945 # number of float instructions system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read @@ -433,7 +433,7 @@ system.cpu1.committedOps 34587691 # Nu system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses system.cpu1.num_func_calls 758024 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3375080 # number of instructions that are conditional controls +system.cpu1.num_conditional_control_insts 3438794 # number of instructions that are conditional controls system.cpu1.num_int_insts 30998246 # number of integer instructions system.cpu1.num_fp_insts 5772 # number of float instructions system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 38cf5a959..86fb980a7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332317 # Nu sim_ticks 2332316587000 # Number of ticks simulated final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1602803 # Simulator instruction rate (inst/s) -host_op_rate 2069882 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63078962864 # Simulator tick rate (ticks/s) -host_mem_usage 382192 # Number of bytes of host memory used -host_seconds 36.97 # Real time elapsed on the host +host_inst_rate 1979884 # Simulator instruction rate (inst/s) +host_op_rate 2556849 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77919104565 # Simulator tick rate (ticks/s) +host_mem_usage 379864 # Number of bytes of host memory used +host_seconds 29.93 # Real time elapsed on the host sim_insts 59262876 # Number of instructions simulated sim_ops 76532931 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory @@ -189,7 +189,7 @@ system.cpu.committedOps 76532931 # Nu system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 1971944 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7572657 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 7793824 # number of instructions that are conditional controls system.cpu.num_int_insts 68161177 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 415456c85..a94cfdfbd 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.669611 # Nu sim_ticks 2669611225000 # Number of ticks simulated final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 656752 # Simulator instruction rate (inst/s) -host_op_rate 840171 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28603719755 # Simulator tick rate (ticks/s) -host_mem_usage 384032 # Number of bytes of host memory used -host_seconds 93.33 # Real time elapsed on the host +host_inst_rate 888599 # Simulator instruction rate (inst/s) +host_op_rate 1136769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38701401221 # Simulator tick rate (ticks/s) +host_mem_usage 381720 # Number of bytes of host memory used +host_seconds 68.98 # Real time elapsed on the host sim_insts 61295262 # Number of instructions simulated sim_ops 78413959 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory @@ -494,7 +494,7 @@ system.cpu0.committedOps 43969024 # Nu system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses system.cpu0.num_func_calls 977479 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4512711 # number of instructions that are conditional controls +system.cpu0.num_conditional_control_insts 4566516 # number of instructions that are conditional controls system.cpu0.num_int_insts 39881498 # number of integer instructions system.cpu0.num_fp_insts 4107 # number of float instructions system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read @@ -762,7 +762,7 @@ system.cpu1.committedOps 34444935 # Nu system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses system.cpu1.num_func_calls 1093852 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3362553 # number of instructions that are conditional controls +system.cpu1.num_conditional_control_insts 3529915 # number of instructions that are conditional controls system.cpu1.num_int_insts 31033253 # number of integer instructions system.cpu1.num_fp_insts 5714 # number of float instructions system.cpu1.num_int_register_reads 181157193 # number of times the integer registers were read diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index be18b1f6a..e62e718fc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.591442 # Nu sim_ticks 2591441692000 # Number of ticks simulated final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 652104 # Simulator instruction rate (inst/s) -host_op_rate 833155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28605499848 # Simulator tick rate (ticks/s) -host_mem_usage 382484 # Number of bytes of host memory used -host_seconds 90.59 # Real time elapsed on the host +host_inst_rate 886915 # Simulator instruction rate (inst/s) +host_op_rate 1133159 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38905818967 # Simulator tick rate (ticks/s) +host_mem_usage 380156 # Number of bytes of host memory used +host_seconds 66.61 # Real time elapsed on the host sim_insts 59075683 # Number of instructions simulated sim_ops 75477515 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory @@ -301,7 +301,7 @@ system.cpu.committedOps 75477515 # Nu system.cpu.num_int_alu_accesses 68255270 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 1975579 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7580611 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 7801778 # number of instructions that are conditional controls system.cpu.num_int_insts 68255270 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions system.cpu.num_int_register_reads 390835391 # number of times the integer registers were read diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status index 52e0ca5f6..48ab2f520 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status @@ -1 +1 @@ -build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing passed. +build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing FAILED! diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 5166f789f..762733a64 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 7 2012 20:12:09 -gem5 started Mar 7 2012 20:12:14 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:17:15 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 96a493c86..3a90ce183 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000010 # Nu sim_ticks 10389500 # Number of ticks simulated final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3665 # Simulator instruction rate (inst/s) -host_op_rate 4572 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8277068 # Simulator tick rate (ticks/s) -host_mem_usage 225396 # Number of bytes of host memory used -host_seconds 1.26 # Real time elapsed on the host +host_inst_rate 29724 # Simulator instruction rate (inst/s) +host_op_rate 37079 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67113828 # Simulator tick rate (ticks/s) +host_mem_usage 225376 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 25600 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index a46f1b25d..29d0ee1dd 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index e7e46b503..cdeb6fd62 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 19:57:12 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:17:15 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 6eeb02481..b762714e2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000010 # Nu sim_ticks 10389500 # Number of ticks simulated final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66059 # Simulator instruction rate (inst/s) -host_op_rate 82394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 149123755 # Simulator tick rate (ticks/s) -host_mem_usage 221320 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 31505 # Simulator instruction rate (inst/s) +host_op_rate 39300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71135954 # Simulator tick rate (ticks/s) +host_mem_usage 225060 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 25600 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 305feda00..1bb97fb57 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -154,7 +154,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index ee81f724d..708e8b4cb 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 8 2012 09:03:12 -gem5 started Mar 8 2012 09:06:54 -gem5 executing on u200540-lin +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:17:15 +gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index f9b36225f..047a13c77 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76819 # Simulator instruction rate (inst/s) -host_op_rate 95818 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47998674 # Simulator tick rate (ticks/s) -host_mem_usage 212240 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 25080 # Simulator instruction rate (inst/s) +host_op_rate 31285 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15673750 # Simulator tick rate (ticks/s) +host_mem_usage 214860 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22944 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index a2c85dbcd..85d2a6f4f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index ef47c4ce8..a7a548730 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:36:01 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:17:15 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 1e73e7e3d..b76299081 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 866385 # Simulator instruction rate (inst/s) -host_op_rate 1077395 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 538148768 # Simulator tick rate (ticks/s) -host_mem_usage 211284 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 24562 # Simulator instruction rate (inst/s) +host_op_rate 30640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15350765 # Simulator tick rate (ticks/s) +host_mem_usage 214764 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22944 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 1d87891a2..50ec8fd07 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 378a682d4..25b5aeda6 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:36:11 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:17:15 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index a93efeca8..4b008ff5c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 26361000 # Number of ticks simulated final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 456104 # Simulator instruction rate (inst/s) -host_op_rate 565540 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2619225899 # Simulator tick rate (ticks/s) -host_mem_usage 220184 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 29458 # Simulator instruction rate (inst/s) +host_op_rate 36586 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 169706423 # Simulator tick rate (ticks/s) +host_mem_usage 223936 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 4574 # Number of instructions simulated sim_ops 5682 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22400 # Number of bytes read from this memory |