summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2009-08-05 03:01:23 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-08-05 03:01:23 -0700
commit77dc6b33ee836e030a2e9c230b8ce67e0e39c322 (patch)
tree49916bb97c3096475d69d571810ece25a00a2e7f
parentc8b1a4583e7062d0bf20a5d1c91f799c3bd79270 (diff)
downloadgem5-77dc6b33ee836e030a2e9c230b8ce67e0e39c322.tar.xz
X86: Fix the overflow bit for rotate right with carry.
-rw-r--r--src/arch/x86/isa/microops/regop.isa6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index e3ad164eb..0bf3420b8 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -777,13 +777,15 @@ let {{
flag_code = '''
// If the shift amount is zero, no flags should be modified.
if (shiftAmt) {
+ int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
//Zero out any flags we might modify. This way we only have to
//worry about setting them.
ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
//Figure out what the OF bit should be.
- if ((ext & OFBit) && ((ccFlagBits & CFBit) ^
- bits(SrcReg1, dataSize * 8 - 1)))
+ if ((ext & OFBit) && (origCFBit ^
+ bits(SrcReg1, dataSize * 8 - 1))) {
ccFlagBits = ccFlagBits | OFBit;
+ }
//If some combination of the CF bits need to be set, set them.
if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));