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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-10-01 04:07:15 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-10-01 04:07:15 -0400 |
| commit | 7dd171ba965330164767c39a50e77a9a2ad568a4 (patch) | |
| tree | 55690c1b1efec8ca50690bdefb1d6942828cd765 | |
| parent | 02881a7bf3e5a5920d258d13ed0aed282f252f07 (diff) | |
| download | gem5-7dd171ba965330164767c39a50e77a9a2ad568a4.tar.xz | |
config: Fix 'learning gem5' configs after SMT push
This patch updates the 'learning gem5' example scripts to match the
recent push of the SMT patches.
| -rw-r--r-- | configs/learning_gem5/part1/simple.py | 6 | ||||
| -rw-r--r-- | configs/learning_gem5/part1/two_level.py | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py index 8e3fed658..1249a8464 100644 --- a/configs/learning_gem5/part1/simple.py +++ b/configs/learning_gem5/part1/simple.py @@ -70,9 +70,9 @@ system.cpu.createInterruptController() # For x86 only, make sure the interrupts are connected to the memory # Note: these are directly connected to the memory bus and are not cached if m5.defines.buildEnv['TARGET_ISA'] == "x86": - system.cpu.interrupts.pio = system.membus.master - system.cpu.interrupts.int_master = system.membus.slave - system.cpu.interrupts.int_slave = system.membus.master + system.cpu.interrupts[0].pio = system.membus.master + system.cpu.interrupts[0].int_master = system.membus.slave + system.cpu.interrupts[0].int_slave = system.membus.master # Create a DDR3 memory controller and connect it to the membus system.mem_ctrl = DDR3_1600_x64() diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py index edaeafe79..de012b30e 100644 --- a/configs/learning_gem5/part1/two_level.py +++ b/configs/learning_gem5/part1/two_level.py @@ -120,9 +120,9 @@ system.cpu.createInterruptController() # For x86 only, make sure the interrupts are connected to the memory # Note: these are directly connected to the memory bus and are not cached if m5.defines.buildEnv['TARGET_ISA'] == "x86": - system.cpu.interrupts.pio = system.membus.master - system.cpu.interrupts.int_master = system.membus.slave - system.cpu.interrupts.int_slave = system.membus.master + system.cpu.interrupts[0].pio = system.membus.master + system.cpu.interrupts[0].int_master = system.membus.slave + system.cpu.interrupts[0].int_slave = system.membus.master # Connect the system up to the membus system.system_port = system.membus.slave |