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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-09 11:07:53 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-16 09:26:43 +0000 |
| commit | 9c97d3fe691e0cf8da0dfb7fc2198bedd0529b2f (patch) | |
| tree | 3e3741df886ef4a5c70cdbe123fa22d564307302 | |
| parent | a30b0e39efaf14ba8b13cff1ada495d68a2ac01e (diff) | |
| download | gem5-9c97d3fe691e0cf8da0dfb7fc2198bedd0529b2f.tar.xz | |
arch-arm: Change ArmFault cast from reinterpret to static
Changing casting type in src/arch/arm/isa.cc
Change-Id: Ia19b30a1bf8b1b25df149b52613a3533eaced03a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8241
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/arch/arm/isa.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 5d34e188a..f6677323e 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1476,7 +1476,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", val, newVal); } else { - ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); + ArmFault *armFault = static_cast<ArmFault *>(fault.get()); // Set fault bit and FSR FSR fsr = armFault->getFsr(tc); @@ -1725,7 +1725,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", val, newVal); } else { - ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); + ArmFault *armFault = static_cast<ArmFault *>(fault.get()); // Set fault bit and FSR FSR fsr = armFault->getFsr(tc); |