Merge zizzer.eecs.umich.edu:/bk/newmem

into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : 81269f094834f43b4e908321bfce2e031b39d2a4

29 files changed, 170 insertions, 288 deletions

diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 304ee6c38..1754300d2 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -55,7 +55,7 @@
 #endif
 
 template <class Impl>
-AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(params)
+AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(this, params)
 {
     DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n");
 
@@ -124,17 +124,6 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(params)
         this->thread[i]->setFuncExeInst(0);
     }
 
-    // Sets CPU pointers. These must be set at this level because the CPU
-    // pointers are defined to be the highest level of CPU class.
-    this->fetch.setCPU(this);
-    this->decode.setCPU(this);
-    this->rename.setCPU(this);
-    this->iew.setCPU(this);
-    this->commit.setCPU(this);
-
-    this->rob.setCPU(this);
-    this->regFile.setCPU(this);
-
     lockAddr = 0;
     lockFlag = false;
 }
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index e2ad23954..fba618c14 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -136,7 +136,7 @@ class DefaultCommit
 
   public:
     /** Construct a DefaultCommit with the given parameters. */
-    DefaultCommit(Params *params);
+    DefaultCommit(O3CPU *_cpu, Params *params);
 
     /** Returns the name of the DefaultCommit. */
     std::string name() const;
@@ -144,9 +144,6 @@ class DefaultCommit
     /** Registers statistics. */
     void regStats();
 
-    /** Sets the CPU pointer. */
-    void setCPU(O3CPU *cpu_ptr);
-
     /** Sets the list of threads. */
     void setThreads(std::vector<Thread *> &threads);
 
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 65e36d99a..65625065d 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -71,8 +71,9 @@ DefaultCommit<Impl>::TrapEvent::description()
 }
 
 template <class Impl>
-DefaultCommit<Impl>::DefaultCommit(Params *params)
-    : squashCounter(0),
+DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params)
+    : cpu(_cpu),
+      squashCounter(0),
       iewToCommitDelay(params->iewToCommitDelay),
       commitToIEWDelay(params->commitToIEWDelay),
       renameToROBDelay(params->renameToROBDelay),
@@ -96,7 +97,7 @@ DefaultCommit<Impl>::DefaultCommit(Params *params)
     if (policy == "aggressive"){
         commitPolicy = Aggressive;
 
-//        DPRINTF(Commit,"Commit Policy set to Aggressive.");
+        DPRINTF(Commit,"Commit Policy set to Aggressive.");
     } else if (policy == "roundrobin"){
         commitPolicy = RoundRobin;
 
@@ -105,11 +106,11 @@ DefaultCommit<Impl>::DefaultCommit(Params *params)
             priority_list.push_back(tid);
         }
 
-//        DPRINTF(Commit,"Commit Policy set to Round Robin.");
+        DPRINTF(Commit,"Commit Policy set to Round Robin.");
     } else if (policy == "oldestready"){
         commitPolicy = OldestReady;
 
-//        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
+        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
     } else {
         assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
                "RoundRobin,OldestReady}");
@@ -227,20 +228,6 @@ DefaultCommit<Impl>::regStats()
 
 template <class Impl>
 void
-DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
-{
-    cpu = cpu_ptr;
-    DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
-
-    // Commit must broadcast the number of free entries it has at the start of
-    // the simulation, so it starts as active.
-    cpu->activateStage(O3CPU::CommitIdx);
-
-    trapLatency = cpu->cycles(trapLatency);
-}
-
-template <class Impl>
-void
 DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
 {
     thread = threads;
@@ -333,7 +320,12 @@ DefaultCommit<Impl>::initStage()
         toIEW->commitInfo[i].emptyROB = true;
     }
 
+    // Commit must broadcast the number of free entries it has at the
+    // start of the simulation, so it starts as active.
+    cpu->activateStage(O3CPU::CommitIdx);
+
     cpu->activityThisCycle();
+    trapLatency = cpu->cycles(trapLatency);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 354e3c490..2e6a43f9c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -148,7 +148,7 @@ FullO3CPU<Impl>::DeallocateContextEvent::description()
 }
 
 template <class Impl>
-FullO3CPU<Impl>::FullO3CPU(Params *params)
+FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
     : BaseO3CPU(params),
 #if FULL_SYSTEM
       itb(params->itb),
@@ -156,19 +156,21 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
 #endif
       tickEvent(this),
       removeInstsThisCycle(false),
-      fetch(params),
-      decode(params),
-      rename(params),
-      iew(params),
-      commit(params),
+      fetch(o3_cpu, params),
+      decode(o3_cpu, params),
+      rename(o3_cpu, params),
+      iew(o3_cpu, params),
+      commit(o3_cpu, params),
 
-      regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
+      regFile(o3_cpu, params->numPhysIntRegs,
+              params->numPhysFloatRegs),
 
       freeList(params->numberOfThreads,
                TheISA::NumIntRegs, params->numPhysIntRegs,
                TheISA::NumFloatRegs, params->numPhysFloatRegs),
 
-      rob(params->numROBEntries, params->squashWidth,
+      rob(o3_cpu,
+          params->numROBEntries, params->squashWidth,
           params->smtROBPolicy, params->smtROBThreshold,
           params->numberOfThreads),
 
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 0ab20ba2a..e71d05c8e 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -95,6 +95,7 @@ class FullO3CPU : public BaseO3CPU
     typedef typename Impl::CPUPol CPUPolicy;
     typedef typename Impl::Params Params;
     typedef typename Impl::DynInstPtr DynInstPtr;
+    typedef typename Impl::O3CPU O3CPU;
 
     typedef O3ThreadState<Impl> Thread;
 
@@ -256,7 +257,7 @@ class FullO3CPU : public BaseO3CPU
 
   public:
     /** Constructs a CPU with the given parameters. */
-    FullO3CPU(Params *params);
+    FullO3CPU(O3CPU *o3_cpu, Params *params);
     /** Destructor. */
     ~FullO3CPU();
 
diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index 4a845e670..3e82033ca 100644
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -86,7 +86,7 @@ class DefaultDecode
 
   public:
     /** DefaultDecode constructor. */
-    DefaultDecode(Params *params);
+    DefaultDecode(O3CPU *_cpu, Params *params);
 
     /** Returns the name of decode. */
     std::string name() const;
@@ -94,9 +94,6 @@ class DefaultDecode
     /** Registers statistics. */
     void regStats();
 
-    /** Sets CPU pointer. */
-    void setCPU(O3CPU *cpu_ptr);
-
     /** Sets the main backwards communication time buffer pointer. */
     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 93d02bfcd..314864f94 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -31,8 +31,9 @@
 #include "cpu/o3/decode.hh"
 
 template<class Impl>
-DefaultDecode<Impl>::DefaultDecode(Params *params)
-    : renameToDecodeDelay(params->renameToDecodeDelay),
+DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, Params *params)
+    : cpu(_cpu),
+      renameToDecodeDelay(params->renameToDecodeDelay),
       iewToDecodeDelay(params->iewToDecodeDelay),
       commitToDecodeDelay(params->commitToDecodeDelay),
       fetchToDecodeDelay(params->fetchToDecodeDelay),
@@ -112,14 +113,6 @@ DefaultDecode<Impl>::regStats()
 
 template<class Impl>
 void
-DefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr)
-{
-    cpu = cpu_ptr;
-    DPRINTF(Decode, "Setting CPU pointer.\n");
-}
-
-template<class Impl>
-void
 DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 {
     timeBuffer = tb_ptr;
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 811f4d2bc..241935416 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -160,7 +160,7 @@ class DefaultFetch
 
   public:
     /** DefaultFetch constructor. */
-    DefaultFetch(Params *params);
+    DefaultFetch(O3CPU *_cpu, Params *params);
 
     /** Returns the name of fetch. */
     std::string name() const;
@@ -171,9 +171,6 @@ class DefaultFetch
     /** Returns the icache port. */
     Port *getIcachePort() { return icachePort; }
 
-    /** Sets CPU pointer. */
-    void setCPU(O3CPU *cpu_ptr);
-
     /** Sets the main backwards communication time buffer pointer. */
     void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 85885906d..e16f97558 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -110,8 +110,9 @@ DefaultFetch<Impl>::IcachePort::recvRetry()
 }
 
 template<class Impl>
-DefaultFetch<Impl>::DefaultFetch(Params *params)
-    : branchPred(params),
+DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
+    : cpu(_cpu),
+      branchPred(params),
       predecoder(NULL),
       decodeToFetchDelay(params->decodeToFetchDelay),
       renameToFetchDelay(params->renameToFetchDelay),
@@ -163,6 +164,17 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
 
     // Get the size of an instruction.
     instSize = sizeof(TheISA::MachInst);
+
+    // Name is finally available, so create the port.
+    icachePort = new IcachePort(this);
+
+    icachePort->snoopRangeSent = false;
+
+#if USE_CHECKER
+    if (cpu->checker) {
+        cpu->checker->setIcachePort(icachePort);
+    }
+#endif
 }
 
 template <class Impl>
@@ -264,32 +276,6 @@ DefaultFetch<Impl>::regStats()
 
 template<class Impl>
 void
-DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
-{
-    cpu = cpu_ptr;
-    DPRINTF(Fetch, "Setting the CPU pointer.\n");
-
-    // Name is finally available, so create the port.
-    icachePort = new IcachePort(this);
-
-    icachePort->snoopRangeSent = false;
-
-#if USE_CHECKER
-    if (cpu->checker) {
-        cpu->checker->setIcachePort(icachePort);
-    }
-#endif
-
-    // Schedule fetch to get the correct PC from the CPU
-    // scheduleFetchStartupEvent(1);
-
-    // Fetch needs to start fetching instructions at the very beginning,
-    // so it must start up in active state.
-    switchToActive();
-}
-
-template<class Impl>
-void
 DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
 {
     timeBuffer = time_buffer;
@@ -342,6 +328,13 @@ DefaultFetch<Impl>::initStage()
         stalls[tid].iew = false;
         stalls[tid].commit = false;
     }
+
+    // Schedule fetch to get the correct PC from the CPU
+    // scheduleFetchStartupEvent(1);
+
+    // Fetch needs to start fetching instructions at the very beginning,
+    // so it must start up in active state.
+    switchToActive();
 }
 
 template<class Impl>
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index a400c9fa8..ce2991cfb 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -115,7 +115,7 @@ class DefaultIEW
 
   public:
     /** Constructs a DefaultIEW with the given parameters. */
-    DefaultIEW(Params *params);
+    DefaultIEW(O3CPU *_cpu, Params *params);
 
     /** Returns the name of the DefaultIEW stage. */
     std::string name() const;
@@ -129,9 +129,6 @@ class DefaultIEW
     /** Returns the dcache port. */
     Port *getDcachePort() { return ldstQueue.getDcachePort(); }
 
-    /** Sets CPU pointer for IEW, IQ, and LSQ. */
-    void setCPU(O3CPU *cpu_ptr);
-
     /** Sets main time buffer used for backwards communication. */
     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 
@@ -367,16 +364,6 @@ class DefaultIEW
     /** Scoreboard pointer. */
     Scoreboard* scoreboard;
 
-  public:
-    /** Instruction queue. */
-    IQ instQueue;
-
-    /** Load / store queue. */
-    LSQ ldstQueue;
-
-    /** Pointer to the functional unit pool. */
-    FUPool *fuPool;
-
   private:
     /** CPU pointer. */
     O3CPU *cpu;
@@ -398,6 +385,14 @@ class DefaultIEW
     void printAvailableInsts();
 
   public:
+    /** Instruction queue. */
+    IQ instQueue;
+
+    /** Load / store queue. */
+    LSQ ldstQueue;
+
+    /** Pointer to the functional unit pool. */
+    FUPool *fuPool;
     /** Records if the LSQ needs to be updated on the next cycle, so that
      * IEW knows if there will be activity on the next cycle.
      */
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index d2948a525..62e656e93 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -39,10 +39,11 @@
 #include "cpu/o3/iew.hh"
 
 template<class Impl>
-DefaultIEW<Impl>::DefaultIEW(Params *params)
+DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params)
     : issueToExecQueue(params->backComSize, params->forwardComSize),
-      instQueue(params),
-      ldstQueue(params),
+      cpu(_cpu),
+      instQueue(_cpu, this, params),
+      ldstQueue(_cpu, this, params),
       fuPool(params->fuPool),
       commitToIEWDelay(params->commitToIEWDelay),
       renameToIEWDelay(params->renameToIEWDelay),
@@ -64,9 +65,6 @@ DefaultIEW<Impl>::DefaultIEW(Params *params)
     // Instruction queue needs the queue between issue and execute.
     instQueue.setIssueToExecuteQueue(&issueToExecQueue);
 
-    instQueue.setIEW(this);
-    ldstQueue.setIEW(this);
-
     for (int i=0; i < numThreads; i++) {
         dispatchStatus[i] = Running;
         stalls[i].commit = false;
@@ -276,17 +274,6 @@ DefaultIEW<Impl>::initStage()
         toRename->iewInfo[tid].freeLSQEntries =
             ldstQueue.numFreeEntries(tid);
     }
-}
-
-template<class Impl>
-void
-DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
-{
-    cpu = cpu_ptr;
-    DPRINTF(IEW, "Setting CPU pointer.\n");
-
-    instQueue.setCPU(cpu_ptr);
-    ldstQueue.setCPU(cpu_ptr);
 
     cpu->activateStage(O3CPU::IEWIdx);
 }
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 3dd4dc658..9d7c457ca 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -110,7 +110,7 @@ class InstructionQueue
     };
 
     /** Constructs an IQ. */
-    InstructionQueue(Params *params);
+    InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params);
 
     /** Destructs the IQ. */
     ~InstructionQueue();
@@ -124,15 +124,9 @@ class InstructionQueue
     /** Resets all instruction queue state. */
     void resetState();
 
-    /** Sets CPU pointer. */
-    void setCPU(O3CPU *_cpu) { cpu = _cpu; }
-
     /** Sets active threads list. */
     void setActiveThreads(std::list<unsigned> *at_ptr);
 
-    /** Sets the IEW pointer. */
-    void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; }
-
     /** Sets the timer buffer between issue and execute. */
     void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
 
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 4d99fb520..10c3287f2 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -64,8 +64,11 @@ InstructionQueue<Impl>::FUCompletion::description()
 }
 
 template <class Impl>
-InstructionQueue<Impl>::InstructionQueue(Params *params)
-    : fuPool(params->fuPool),
+InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
+                                         Params *params)
+    : cpu(cpu_ptr),
+      iewStage(iew_ptr),
+      fuPool(params->fuPool),
       numEntries(params->numIQEntries),
       totalWidth(params->issueWidth),
       numPhysIntRegs(params->numPhysIntRegs),
@@ -122,11 +125,8 @@ InstructionQueue<Impl>::InstructionQueue(Params *params)
             maxEntries[i] = part_amt;
         }
 
-/*
         DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
                 "%i entries per thread.\n",part_amt);
-*/
-
     } else if (policy == "threshold") {
         iqPolicy = Threshold;
 
@@ -139,10 +139,8 @@ InstructionQueue<Impl>::InstructionQueue(Params *params)
             maxEntries[i] = thresholdIQ;
         }
 
-/*
         DPRINTF(IQ, "IQ sharing policy set to Threshold:"
                 "%i entries per thread.\n",thresholdIQ);
-*/
    } else {
        assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
               "Partitioned, Threshold}");
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 80f53a726..fd8f878a7 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -57,7 +57,7 @@ class LSQ {
     };
 
     /** Constructs an LSQ with the given parameters. */
-    LSQ(Params *params);
+    LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params);
 
     /** Returns the name of the LSQ. */
     std::string name() const;
@@ -74,10 +74,6 @@ class LSQ {
 
     /** Sets the pointer to the list of active threads. */
     void setActiveThreads(std::list<unsigned> *at_ptr);
-    /** Sets the CPU pointer. */
-    void setCPU(O3CPU *cpu_ptr);
-    /** Sets the IEW stage pointer. */
-    void setIEW(IEW *iew_ptr);
     /** Switches out the LSQ. */
     void switchOut();
     /** Takes over execution from another CPU's thread. */
@@ -283,6 +279,12 @@ class LSQ {
     template <class T>
     Fault write(RequestPtr req, T &data, int store_idx);
 
+    /** The CPU pointer. */
+    O3CPU *cpu;
+
+    /** The IEW stage pointer. */
+    IEW *iewStage;
+
     /** DcachePort class for this LSQ.  Handles doing the
      * communication with the cache/memory.
      */
@@ -295,7 +297,7 @@ class LSQ {
       public:
         /** Default constructor. */
         DcachePort(LSQ *_lsq)
-            : lsq(_lsq)
+            : Port(_lsq->name() + "-dport"), lsq(_lsq)
         { }
 
         bool snoopRangeSent;
@@ -341,12 +343,6 @@ class LSQ {
     /** The LSQ units for individual threads. */
     LSQUnit thread[Impl::MaxThreads];
 
-    /** The CPU pointer. */
-    O3CPU *cpu;
-
-    /** The IEW stage pointer. */
-    IEW *iewStage;
-
     /** List of Active Threads in System. */
     std::list<unsigned> *activeThreads;
 
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 02cc5784c..b4a6a02da 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -107,9 +107,11 @@ LSQ<Impl>::DcachePort::recvRetry()
 }
 
 template <class Impl>
-LSQ<Impl>::LSQ(Params *params)
-    : dcachePort(this), LQEntries(params->LQEntries),
-      SQEntries(params->SQEntries), numThreads(params->numberOfThreads),
+LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params)
+    : cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this),
+      LQEntries(params->LQEntries),
+      SQEntries(params->SQEntries),
+      numThreads(params->numberOfThreads),
       retryTid(-1)
 {
     dcachePort.snoopRangeSent = false;
@@ -129,20 +131,18 @@ LSQ<Impl>::LSQ(Params *params)
 
         maxLQEntries = LQEntries;
         maxSQEntries = SQEntries;
-/*
+
         DPRINTF(LSQ, "LSQ sharing policy set to Dynamic\n");
-*/
     } else if (policy == "partitioned") {
         lsqPolicy = Partitioned;
 
         //@todo:make work if part_amt doesnt divide evenly.
         maxLQEntries = LQEntries / numThreads;
         maxSQEntries = SQEntries / numThreads;
-/*
+
         DPRINTF(Fetch, "LSQ sharing policy set to Partitioned: "
                 "%i entries per LQ | %i entries per SQ",
                 maxLQEntries,maxSQEntries);
-*/
     } else if (policy == "threshold") {
         lsqPolicy = Threshold;
 
@@ -154,12 +154,10 @@ LSQ<Impl>::LSQ(Params *params)
         //amount of the LSQ
         maxLQEntries  = params->smtLSQThreshold;
         maxSQEntries  = params->smtLSQThreshold;
-/*
+
         DPRINTF(LSQ, "LSQ sharing policy set to Threshold: "
                 "%i entries per LQ | %i entries per SQ",
                 maxLQEntries,maxSQEntries);
-*/
-
     } else {
         assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
                     "Partitioned, Threshold}");
@@ -167,7 +165,8 @@ LSQ<Impl>::LSQ(Params *params)
 
     //Initialize LSQs
     for (int tid=0; tid < numThreads; tid++) {
-        thread[tid].init(params, this, maxLQEntries, maxSQEntries, tid);
+        thread[tid].init(cpu, iew_ptr, params, this,
+                         maxLQEntries, maxSQEntries, tid);
         thread[tid].setDcachePort(&dcachePort);
     }
 }
@@ -198,30 +197,6 @@ LSQ<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
     assert(activeThreads != 0);
 }
 
-template<class Impl>
-void
-LSQ<Impl>::setCPU(O3CPU *cpu_ptr)
-{
-    cpu = cpu_ptr;
-
-    dcachePort.setName(name());
-
-    for (int tid=0; tid < numThreads; tid++) {
-        thread[tid].setCPU(cpu_ptr);
-    }
-}
-
-template<class Impl>
-void
-LSQ<Impl>::setIEW(IEW *iew_ptr)
-{
-    iewStage = iew_ptr;
-
-    for (int tid=0; tid < numThreads; tid++) {
-        thread[tid].setIEW(iew_ptr);
-    }
-}
-
 template <class Impl>
 void
 LSQ<Impl>::switchOut()
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index ebfa75059..f24de20d9 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -73,8 +73,8 @@ class LSQUnit {
     LSQUnit();
 
     /** Initializes the LSQ unit with the specified number of entries. */
-    void init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
-              unsigned maxSQEntries, unsigned id);
+    void init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
+              unsigned maxLQEntries, unsigned maxSQEntries, unsigned id);
 
     /** Returns the name of the LSQ unit. */
     std::string name() const;
@@ -82,16 +82,8 @@ class LSQUnit {
     /** Registers statistics. */
     void regStats();
 
-    /** Sets the CPU pointer. */
-    void setCPU(O3CPU *cpu_ptr);
-
-    /** Sets the IEW stage pointer. */
-    void setIEW(IEW *iew_ptr)
-    { iewStage = iew_ptr; }
-
     /** Sets the pointer to the dcache port. */
-    void setDcachePort(Port *dcache_port)
-    { dcachePort = dcache_port; }
+    void setDcachePort(Port *dcache_port);
 
     /** Switches out LSQ unit. */
     void switchOut();
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index a47528e32..d558e2dfa 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -57,6 +57,11 @@ LSQUnit<Impl>::WritebackEvent::process()
     if (!lsqPtr->isSwitchedOut()) {
         lsqPtr->writeback(inst, pkt);
     }
+
+    if (pkt->senderState)
+        delete pkt->senderState;
+
+    delete pkt->req;
     delete pkt;
 }
 
@@ -80,10 +85,6 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
 
     if (isSwitchedOut() || inst->isSquashed()) {
         iewStage->decrWb(inst->seqNum);
-        delete state;
-        delete pkt->req;
-        delete pkt;
-        return;
     } else {
         if (!state->noWB) {
             writeback(inst, pkt);
@@ -109,10 +110,13 @@ LSQUnit<Impl>::LSQUnit()
 
 template<class Impl>
 void
-LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
-                    unsigned maxSQEntries, unsigned id)
+LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
+                    unsigned maxLQEntries, unsigned maxSQEntries, unsigned id)
 {
-//    DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
+    cpu = cpu_ptr;
+    iewStage = iew_ptr;
+
+    DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
 
     switchedOut = false;
 
@@ -141,19 +145,6 @@ LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
 }
 
 template<class Impl>
-void
-LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
-{
-    cpu = cpu_ptr;
-
-#if USE_CHECKER
-    if (cpu->checker) {
-        cpu->checker->setDcachePort(dcachePort);
-    }
-#endif
-}
-
-template<class Impl>
 std::string
 LSQUnit<Impl>::name() const
 {
@@ -211,6 +202,19 @@ LSQUnit<Impl>::regStats()
 
 template<class Impl>
 void
+LSQUnit<Impl>::setDcachePort(Port *dcache_port)
+{
+    dcachePort = dcache_port;
+
+#if USE_CHECKER
+    if (cpu->checker) {
+        cpu->checker->setDcachePort(dcachePort);
+    }
+#endif
+}
+
+template<class Impl>
+void
 LSQUnit<Impl>::clearLQ()
 {
     loadQueue.clear();
diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc
index 66741aee9..c6acc0bfb 100644
--- a/src/cpu/o3/mips/cpu_builder.cc
+++ b/src/cpu/o3/mips/cpu_builder.cc
@@ -51,6 +51,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
 Param<int> clock;
 Param<int> phase;
 Param<int> numThreads;
+Param<int> cpu_id;
 Param<int> activity;
 
 SimObjectVectorParam<Process *> workload;
@@ -149,6 +150,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
     INIT_PARAM(clock, "clock speed"),
     INIT_PARAM_DFLT(phase, "clock phase", 0),
     INIT_PARAM(numThreads, "number of HW thread contexts"),
+    INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM_DFLT(activity, "Initial activity count", 0),
 
     INIT_PARAM(workload, "Processes to run"),
@@ -275,9 +277,11 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     MipsSimpleParams *params = new MipsSimpleParams;
 
     params->clock = clock;
+    params->phase = phase;
 
     params->name = getInstanceName();
     params->numberOfThreads = actual_num_threads;
+    params->cpu_id = cpu_id;
     params->activity = activity;
 
     params->workload = workload;
diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh
index 317fd748e..d1135f048 100644
--- a/src/cpu/o3/mips/cpu_impl.hh
+++ b/src/cpu/o3/mips/cpu_impl.hh
@@ -47,7 +47,7 @@
 
 template <class Impl>
 MipsO3CPU<Impl>::MipsO3CPU(Params *params)
-    : FullO3CPU<Impl>(params)
+    : FullO3CPU<Impl>(this, params)
 {
     DPRINTF(O3CPU, "Creating MipsO3CPU object.\n");
 
@@ -95,6 +95,7 @@ MipsO3CPU<Impl>::MipsO3CPU(Params *params)
 
         // Give the thread the TC.
         this->thread[i]->tc = tc;
+        this->thread[i]->setCpuId(params->cpu_id);
 
         // Add the TC to the CPU's list of TC's.
         this->threadContexts.push_back(tc);
@@ -104,17 +105,6 @@ MipsO3CPU<Impl>::MipsO3CPU(Params *params)
         this->thread[i]->setFuncExeInst(0);
     }
 
-    // Sets CPU pointers. These must be set at this level because the CPU
-    // pointers are defined to be the highest level of CPU class.
-    this->fetch.setCPU(this);
-    this->decode.setCPU(this);
-    this->rename.setCPU(this);
-    this->iew.setCPU(this);
-    this->commit.setCPU(this);
-
-    this->rob.setCPU(this);
-    this->regFile.setCPU(this);
-
     lockAddr = 0;
     lockFlag = false;
 }
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index c4f8f3a9f..bbc69fc96 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -76,7 +76,7 @@ class PhysRegFile
      * Constructs a physical register file with the specified amount of
      * integer and floating point registers.
      */
-    PhysRegFile(unsigned _numPhysicalIntRegs,
+    PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
                 unsigned _numPhysicalFloatRegs);
 
     //Everything below should be pretty well identical to the normal
@@ -268,9 +268,6 @@ class PhysRegFile
     O3CPU *cpu;
 
   public:
-    /** Sets the CPU pointer. */
-    void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; }
-
     /** Number of physical integer registers. */
     unsigned numPhysicalIntRegs;
     /** Number of physical floating point registers. */
@@ -278,9 +275,9 @@ class PhysRegFile
 };
 
 template <class Impl>
-PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
+PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
                                unsigned _numPhysicalFloatRegs)
-    : numPhysicalIntRegs(_numPhysicalIntRegs),
+    : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs),
       numPhysicalFloatRegs(_numPhysicalFloatRegs)
 {
     intRegFile = new IntReg[numPhysicalIntRegs];
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index 6b4628f92..b2faffe43 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -107,7 +107,7 @@ class DefaultRename
 
   public:
     /** DefaultRename constructor. */
-    DefaultRename(Params *params);
+    DefaultRename(O3CPU *_cpu, Params *params);
 
     /** Returns the name of rename. */
     std::string name() const;
@@ -115,9 +115,6 @@ class DefaultRename
     /** Registers statistics. */
     void regStats();
 
-    /** Sets CPU pointer. */
-    void setCPU(O3CPU *cpu_ptr);
-
     /** Sets the main backwards communication time buffer pointer. */
     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index eb04ca733..c0d34116d 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -37,8 +37,9 @@
 #include "cpu/o3/rename.hh"
 
 template <class Impl>
-DefaultRename<Impl>::DefaultRename(Params *params)
-    : iewToRenameDelay(params->iewToRenameDelay),
+DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params)
+    : cpu(_cpu),
+      iewToRenameDelay(params->iewToRenameDelay),
       decodeToRenameDelay(params->decodeToRenameDelay),
       commitToRenameDelay(params->commitToRenameDelay),
       renameWidth(params->renameWidth),
@@ -166,14 +167,6 @@ DefaultRename<Impl>::regStats()
 
 template <class Impl>
 void
-DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr)
-{
-    cpu = cpu_ptr;
-    DPRINTF(Rename, "Setting CPU pointer.\n");
-}
-
-template <class Impl>
-void
 DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 {
     timeBuffer = tb_ptr;
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh
index 7cd5a5143..00329abb0 100644
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -82,17 +82,12 @@ class ROB
      *  @param _smtROBThreshold Max Resources(by %) a thread can have in the ROB.
      *  @param _numThreads      The number of active threads.
      */
-    ROB(unsigned _numEntries, unsigned _squashWidth, std::string smtROBPolicy,
-        unsigned _smtROBThreshold, unsigned _numThreads);
+    ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
+        std::string smtROBPolicy, unsigned _smtROBThreshold,
+        unsigned _numThreads);
 
     std::string name() const;
 
-    /** Function to set the CPU pointer, necessary due to which object the ROB
-     *  is created within.
-     *  @param cpu_ptr Pointer to the implementation specific full CPU object.
-     */
-    void setCPU(O3CPU *cpu_ptr);
-
     /** Sets pointer to the list of active threads.
      *  @param at_ptr Pointer to the list of active threads.
      */
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 975aba379..7ff3aa274 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -35,10 +35,11 @@
 #include <list>
 
 template <class Impl>
-ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
+ROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
                std::string _smtROBPolicy, unsigned _smtROBThreshold,
                unsigned _numThreads)
-    : numEntries(_numEntries),
+    : cpu(_cpu),
+      numEntries(_numEntries),
       squashWidth(_squashWidth),
       numInstsInROB(0),
       numThreads(_numThreads)
@@ -66,7 +67,7 @@ ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
 
     } else if (policy == "partitioned") {
         robPolicy = Partitioned;
-//	DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
+        DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
 
         //@todo:make work if part_amt doesnt divide evenly.
         int part_amt = numEntries / numThreads;
@@ -78,7 +79,7 @@ ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
 
     } else if (policy == "threshold") {
         robPolicy = Threshold;
-//	DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
+        DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
 
         int threshold =  _smtROBThreshold;;
 
@@ -90,20 +91,6 @@ ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
         assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
                     "Partitioned, Threshold}");
     }
-}
-
-template <class Impl>
-std::string
-ROB<Impl>::name() const
-{
-    return cpu->name() + ".rob";
-}
-
-template <class Impl>
-void
-ROB<Impl>::setCPU(O3CPU *cpu_ptr)
-{
-    cpu = cpu_ptr;
 
     // Set the per-thread iterators to the end of the instruction list.
     for (int i=0; i < numThreads;i++) {
@@ -117,6 +104,13 @@ ROB<Impl>::setCPU(O3CPU *cpu_ptr)
 }
 
 template <class Impl>
+std::string
+ROB<Impl>::name() const
+{
+    return cpu->name() + ".rob";
+}
+
+template <class Impl>
 void
 ROB<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 {
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index a425a8a56..50d980f55 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -55,7 +55,7 @@
 #endif
 
 template <class Impl>
-SparcO3CPU<Impl>::SparcO3CPU(Params *params) : FullO3CPU<Impl>(params)
+SparcO3CPU<Impl>::SparcO3CPU(Params *params) : FullO3CPU<Impl>(this, params)
 {
     DPRINTF(O3CPU, "Creating SparcO3CPU object.\n");
 
@@ -113,6 +113,7 @@ SparcO3CPU<Impl>::SparcO3CPU(Params *params) : FullO3CPU<Impl>(params)
 #endif
         // Give the thread the TC.
         this->thread[i]->tc = tc;
+        this->thread[i]->setCpuId(params->cpu_id);
 
         // Add the TC to the CPU's list of TC's.
         this->threadContexts.push_back(tc);
@@ -122,17 +123,6 @@ SparcO3CPU<Impl>::SparcO3CPU(Params *params) : FullO3CPU<Impl>(params)
         this->thread[i]->setFuncExeInst(0);
     }
 
-    // Sets CPU pointers. These must be set at this level because the CPU
-    // pointers are defined to be the highest level of CPU class.
-    this->fetch.setCPU(this);
-    this->decode.setCPU(this);
-    this->rename.setCPU(this);
-    this->iew.setCPU(this);
-    this->commit.setCPU(this);
-
-    this->rob.setCPU(this);
-    this->regFile.setCPU(this);
-
     lockAddr = 0;
     lockFlag = false;
 }
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 6e6ba2380..b0636ecc2 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -52,9 +52,19 @@ Bus::getPort(const std::string &if_name, int idx)
         } else
             fatal("Default port already set\n");
     }
+    int id;
+    if (if_name == "functional") {
+        if (!funcPort) {
+            id = maxId++;
+            funcPort = new BusPort(csprintf("%s-p%d-func", name(), id), this, id);
+            funcPortId = id;
+            interfaces[id] = funcPort;
+        }
+        return funcPort;
+    }
 
     // if_name ignored?  forced to be empty?
-    int id = maxId++;
+    id = maxId++;
     assert(maxId < std::numeric_limits<typeof(maxId)>::max());
     BusPort *bp = new BusPort(csprintf("%s-p%d", name(), id), this, id);
     interfaces[id] = bp;
@@ -64,10 +74,15 @@ Bus::getPort(const std::string &if_name, int idx)
 void
 Bus::deletePortRefs(Port *p)
 {
+
     BusPort *bp =  dynamic_cast<BusPort*>(p);
     if (bp == NULL)
         panic("Couldn't convert Port* to BusPort*\n");
+    // If this is our one functional port
+    if (funcPort == bp)
+        return;
     interfaces.erase(bp->getId());
+    delete bp;
 }
 
 /** Get the ranges of anyone other buses that we are connected to. */
@@ -520,7 +535,7 @@ Bus::recvStatusChange(Port::Status status, int id)
     m5::hash_map<short,BusPort*>::iterator intIter;
 
     for (intIter = interfaces.begin(); intIter != interfaces.end(); intIter++)
-        if (intIter->first != id)
+        if (intIter->first != id && intIter->first != funcPortId)
             intIter->second->sendStatusChange(Port::RangeChange);
 
     if (id != defaultId && defaultPort)
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 6706b6c77..0dd7547c5 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -63,6 +63,7 @@ class Bus : public MemObject
 
     Event * drainEvent;
 
+
     static const int defaultId = -3; //Make it unique from Broadcast
 
     struct DevMap {
@@ -249,6 +250,9 @@ class Bus : public MemObject
     /** Port that handles requests that don't match any of the interfaces.*/
     BusPort *defaultPort;
 
+    BusPort *funcPort;
+    int funcPortId;
+
     /** Has the user specified their own default responder? */
     bool responderSet;
 
@@ -266,7 +270,8 @@ class Bus : public MemObject
         bool responder_set)
         : MemObject(n), busId(bus_id), clock(_clock), width(_width),
           tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
-          maxId(0), defaultPort(NULL), responderSet(responder_set)
+          maxId(0), defaultPort(NULL), funcPort(NULL), funcPortId(-4),
+          responderSet(responder_set)
     {
         //Both the width and clock period must be positive
         if (width <= 0)
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index ec0ef1be4..0a528aa5d 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1183,7 +1183,8 @@ Cache<TagStore,Coherence>::deletePortRefs(Port *p)
 {
     if (cpuSidePort == p || memSidePort == p)
         panic("Can only delete functional ports\n");
-    // nothing else to do
+
+    delete p;
 }
 
 
diff --git a/src/mem/port.cc b/src/mem/port.cc
index e75e50e4d..e6ea773f2 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -51,7 +51,6 @@ Port::removeConn()
 {
     if (peer->getOwner())
         peer->getOwner()->deletePortRefs(peer);
-    delete peer;
     peer = NULL;
 }