diff options
| author | Derek Hower <drh5@cs.wisc.edu> | 2009-08-05 14:23:32 -0500 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2009-08-05 14:23:32 -0500 |
| commit | dff7c9eaa0795dc23b32608dc1e26026a5292d30 (patch) | |
| tree | f5335c8359d19535c6832238dd51d528ba6c1086 | |
| parent | 60d4a0f6d7328b251797b14c33fd6766b95bc1ea (diff) | |
| parent | 867269bc9650e0b5b2384daf0c09fba60aa7438c (diff) | |
| download | gem5-dff7c9eaa0795dc23b32608dc1e26026a5292d30.tar.xz | |
merge
53 files changed, 1663 insertions, 1560 deletions
diff --git a/src/mem/gems_common/Map.hh b/src/mem/gems_common/Map.hh index 5128a0fee..6e581d375 100644 --- a/src/mem/gems_common/Map.hh +++ b/src/mem/gems_common/Map.hh @@ -93,6 +93,8 @@ bool Map<KEY_TYPE, VALUE_TYPE>::exist(const KEY_TYPE& key) const template <class KEY_TYPE, class VALUE_TYPE> VALUE_TYPE& Map<KEY_TYPE, VALUE_TYPE>::lookup(const KEY_TYPE& key) const { + if (!exist(key)) + cerr << *this << " is looking for " << key << endl; assert(exist(key)); return m_map[key]; } diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 16a158f0d..915a0eb99 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -1,5 +1,8 @@ -machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY_ISSUE_LATENCY { +machine(L1Cache, "MI Example L1 Cache") +: int cache_response_latency, + int issue_latency +{ // NETWORK BUFFERS MessageBuffer requestFromCache, network="To", virtual_network="0", ordered="true"; @@ -188,8 +191,8 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY // ACTIONS action(a_issueRequest, "a", desc="Issue a request") { - enqueue(requestNetwork_out, RequestMsg, latency="ISSUE_LATENCY") { - out_msg.Address := address; + enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -198,7 +201,7 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY } action(b_issuePUT, "b", desc="Issue a PUT request") { - enqueue(requestNetwork_out, RequestMsg, latency="ISSUE_LATENCY") { + enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:PUTX; out_msg.Requestor := machineID; @@ -211,7 +214,7 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY action(e_sendData, "e", desc="Send data from cache to requestor") { peek(forwardRequestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="CACHE_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -224,7 +227,7 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") { peek(forwardRequestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="CACHE_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm index fa8903d47..9af1940f7 100644 --- a/src/mem/protocol/MI_example-dir.sm +++ b/src/mem/protocol/MI_example-dir.sm @@ -1,5 +1,9 @@ -machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_DIRECTORY_LATENCY LATENCY_MEMORY_LATENCY { +machine(Directory, "Directory protocol") +: int directory_latency, + int dma_select_low_bit, + int dma_select_num_bits +{ MessageBuffer forwardFromDir, network="To", virtual_network="2", ordered="false"; MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false"; @@ -65,9 +69,9 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D // TBE entries for DMA requests structure(TBE, desc="TBE entries for outstanding DMA requests") { + Address PhysicalAddress, desc="physical address"; State TBEState, desc="Transient State"; DataBlock DataBlk, desc="Data to be written (DMA write only)"; - int Offset, desc="..."; int Len, desc="..."; } @@ -180,7 +184,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { + enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:WB_ACK; out_msg.Requestor := in_msg.Requestor; @@ -192,7 +196,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D action(l_sendWriteBackAck, "la", desc="Send writeback ack to requestor") { peek(memQueue_in, MemoryMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="TO_MEM_CTRL_LATENCY") { + enqueue(forwardNetwork_out, RequestMsg, latency="1") { out_msg.Address := address; out_msg.Type := CoherenceRequestType:WB_ACK; out_msg.Requestor := in_msg.OriginalRequestorMachId; @@ -204,7 +208,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { + enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:WB_NACK; out_msg.Requestor := in_msg.Requestor; @@ -218,29 +222,9 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D directory[address].Owner.clear(); } -// action(d_sendData, "d", desc="Send data to requestor") { -// peek(requestQueue_in, RequestMsg) { -// enqueue(responseNetwork_out, ResponseMsg, latency="MEMORY_LATENCY") { -// out_msg.Address := address; -// -// if (in_msg.Type == CoherenceRequestType:GETS && directory[address].Sharers.count() == 0) { -// // out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE_CLEAN; -// out_msg.Type := CoherenceResponseType:DATA; -// } else { -// out_msg.Type := CoherenceResponseType:DATA; -// } -// -// out_msg.Sender := machineID; -// out_msg.Destination.add(in_msg.Requestor); -// out_msg.DataBlk := directory[in_msg.Address].DataBlk; -// out_msg.MessageSize := MessageSizeType:Response_Data; -// } -// } -// } - action(d_sendData, "d", desc="Send data to requestor") { peek(memQueue_in, MemoryMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="TO_MEM_CTRL_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency="1") { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -251,26 +235,15 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D } } -// action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") { -// peek(dmaRequestQueue_in, DMARequestMsg) { -// enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") { -// out_msg.PhysicalAddress := address; -// out_msg.Type := DMAResponseType:DATA; -// out_msg.DataBlk := directory[in_msg.PhysicalAddress].DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be -// out_msg.Destination.add(map_Address_to_DMA(address)); -// out_msg.MessageSize := MessageSizeType:Response_Data; -// } -// } -// } - action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") { peek(memQueue_in, MemoryMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { out_msg.PhysicalAddress := address; out_msg.LineAddress := address; out_msg.Type := DMAResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be - out_msg.Destination.add(map_Address_to_DMA(address)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA, + dma_select_low_bit, dma_select_num_bits)); out_msg.MessageSize := MessageSizeType:Response_Data; } } @@ -280,23 +253,25 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") { peek(requestQueue_in, RequestMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { out_msg.PhysicalAddress := address; out_msg.LineAddress := address; out_msg.Type := DMAResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be - out_msg.Destination.add(map_Address_to_DMA(address)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA, + dma_select_low_bit, dma_select_num_bits)); out_msg.MessageSize := MessageSizeType:Response_Data; } } } action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") { + enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") { out_msg.PhysicalAddress := address; out_msg.LineAddress := address; out_msg.Type := DMAResponseType:ACK; - out_msg.Destination.add(map_Address_to_DMA(address)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA, + dma_select_low_bit, dma_select_num_bits)); out_msg.MessageSize := MessageSizeType:Writeback_Control; } } @@ -318,7 +293,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D APPEND_TRANSITION_COMMENT(directory[in_msg.Address].Owner); APPEND_TRANSITION_COMMENT("Req: "); APPEND_TRANSITION_COMMENT(in_msg.Requestor); - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { + enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -330,7 +305,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { + enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := machineID; @@ -359,14 +334,14 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D } action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") { - directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, TBEs[address].Offset, TBEs[address].Len); + directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len); } action(v_allocateTBE, "v", desc="Allocate TBE") { peek(dmaRequestQueue_in, DMARequestMsg) { TBEs.allocate(address); TBEs[address].DataBlk := in_msg.DataBlk; - TBEs[address].Offset := in_msg.Offset; + TBEs[address].PhysicalAddress := in_msg.PhysicalAddress; TBEs[address].Len := in_msg.Len; } } @@ -389,7 +364,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") { peek(requestQueue_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") { + enqueue(memQueue_out, MemoryMsg, latency="1") { out_msg.Address := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -403,7 +378,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") { + enqueue(memQueue_out, MemoryMsg, latency="1") { out_msg.Address := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; @@ -414,29 +389,15 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D } } } -// action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") { -// peek(dmaRequestQueue_in, DMARequestMsg) { -// enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") { -// out_msg.Address := address; -// out_msg.Type := MemoryRequestType:MEMORY_WB; -// out_msg.OriginalRequestorMachId := machineID; -// out_msg.DataBlk := in_msg.DataBlk; -// out_msg.MessageSize := in_msg.MessageSize; - -// DEBUG_EXPR(out_msg); -// } -// } -// } - action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") { peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") { + enqueue(memQueue_out, MemoryMsg, latency="1") { out_msg.Address := address; out_msg.Type := MemoryRequestType:MEMORY_WB; //out_msg.OriginalRequestorMachId := machineID; //out_msg.DataBlk := in_msg.DataBlk; - out_msg.DataBlk.copyPartial(in_msg.DataBlk, in_msg.Offset, in_msg.Len); + out_msg.DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.PhysicalAddress), in_msg.Len); out_msg.MessageSize := in_msg.MessageSize; //out_msg.Prefetch := in_msg.Prefetch; @@ -447,12 +408,12 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") { peek(requestQueue_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") { + enqueue(memQueue_out, MemoryMsg, latency="1") { out_msg.Address := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.OriginalRequestorMachId := in_msg.Requestor; //out_msg.DataBlk := in_msg.DataBlk; - out_msg.DataBlk.copyPartial(TBEs[address].DataBlk, TBEs[address].Offset, TBEs[address].Len); + out_msg.DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len); out_msg.MessageSize := in_msg.MessageSize; //out_msg.Prefetch := in_msg.Prefetch; @@ -465,7 +426,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") { peek(requestQueue_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") { + enqueue(memQueue_out, MemoryMsg, latency="1") { out_msg.Address := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.OriginalRequestorMachId := in_msg.Requestor; diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm index d5de18552..e883288df 100644 --- a/src/mem/protocol/MI_example-dma.sm +++ b/src/mem/protocol/MI_example-dma.sm @@ -1,5 +1,7 @@ -machine(DMA, "DMA Controller") { +machine(DMA, "DMA Controller") +: int request_latency +{ MessageBuffer responseFromDir, network="From", virtual_network="4", ordered="true", no_vector="true"; MessageBuffer reqToDirectory, network="To", virtual_network="5", ordered="false", no_vector="true"; @@ -35,12 +37,12 @@ machine(DMA, "DMA Controller") { out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="..."); - in_port(dmaRequestQueue_in, DMARequestMsg, mandatoryQueue, desc="...") { + in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { if (dmaRequestQueue_in.isReady()) { - peek(dmaRequestQueue_in, DMARequestMsg) { - if (in_msg.Type == DMARequestType:READ ) { + peek(dmaRequestQueue_in, SequencerMsg) { + if (in_msg.Type == SequencerRequestType:LD ) { trigger(Event:ReadRequest, in_msg.LineAddress); - } else if (in_msg.Type == DMARequestType:WRITE) { + } else if (in_msg.Type == SequencerRequestType:ST) { trigger(Event:WriteRequest, in_msg.LineAddress); } else { error("Invalid request type"); @@ -64,9 +66,9 @@ machine(DMA, "DMA Controller") { } action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { - peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(reqToDirectory_out, DMARequestMsg) { - out_msg.PhysicalAddress := address; + peek(dmaRequestQueue_in, SequencerMsg) { + enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { + out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:READ; out_msg.DataBlk := in_msg.DataBlk; @@ -78,9 +80,9 @@ machine(DMA, "DMA Controller") { } action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { - peek(dmaRequestQueue_in, DMARequestMsg) { - enqueue(reqToDirectory_out, DMARequestMsg) { - out_msg.PhysicalAddress := address; + peek(dmaRequestQueue_in, SequencerMsg) { + enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { + out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:WRITE; out_msg.DataBlk := in_msg.DataBlk; diff --git a/src/mem/protocol/MI_example-msg.sm b/src/mem/protocol/MI_example-msg.sm index 8c0afed2e..d4d557200 100644 --- a/src/mem/protocol/MI_example-msg.sm +++ b/src/mem/protocol/MI_example-msg.sm @@ -107,7 +107,6 @@ structure(DMARequestMsg, desc="...", interface="NetworkMessage") { Address LineAddress, desc="Line address for this request"; NetDest Destination, desc="Destination"; DataBlock DataBlk, desc="DataBlk attached to this request"; - int Offset, desc="The offset into the datablock"; int Len, desc="The length of the request"; MessageSizeType MessageSize, desc="size category of the message"; } diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index a65ade10f..28800b2bd 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -32,7 +32,11 @@ * */ -machine(L1Cache, "Directory protocol") { +machine(L1Cache, "Directory protocol") + : int request_latency, + int l2_select_low_bit, + int l2_select_num_bits +{ // NODE L1 CACHE // From this node's L1 cache TO the network @@ -125,7 +129,7 @@ machine(L1Cache, "Directory protocol") { external_type(CacheMemory) { bool cacheAvail(Address); Address cacheProbe(Address); - void allocate(Address); + void allocate(Address, Entry); void deallocate(Address); Entry lookup(Address); void changePermission(Address, AccessPermission); @@ -141,11 +145,11 @@ machine(L1Cache, "Directory protocol") { MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true"; - Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i"; + Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg["sequencer"])'; TBETable TBEs, template_hack="<L1Cache_TBE>"; - CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"', abstract_chip_ptr="true"; - CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"', abstract_chip_ptr="true"; + CacheMemory L1IcacheMemory, factory='RubySystem::getCache(m_cfg["icache"])'; + CacheMemory L1DcacheMemory, factory='RubySystem::getCache(m_cfg["dcache"])'; TimerTable useTimerTable; Entry getCacheEntry(Address addr), return_by_ref="yes" { @@ -305,7 +309,7 @@ machine(L1Cache, "Directory protocol") { assert(in_msg.Destination.isElement(machineID)); DEBUG_EXPR("MRM_DEBUG: L1 received"); DEBUG_EXPR(in_msg.Type); - if (in_msg.Type == CoherenceRequestType:GETX) { +if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_READ || in_msg.Type == CoherenceRequestType:DMA_WRITE) { if (in_msg.Requestor == machineID && in_msg.RequestorMachine == MachineType:L1Cache) { trigger(Event:Own_GETX, in_msg.Address); } else { @@ -357,40 +361,40 @@ machine(L1Cache, "Directory protocol") { // ** INSTRUCTION ACCESS *** // Check to see if it is in the OTHER L1 - if (L1DcacheMemory.isTagPresent(in_msg.Address)) { + if (L1DcacheMemory.isTagPresent(in_msg.LineAddress)) { // The block is in the wrong L1, put the request on the queue to the shared L2 - trigger(Event:L1_Replacement, in_msg.Address); + trigger(Event:L1_Replacement, in_msg.LineAddress); } - if (L1IcacheMemory.isTagPresent(in_msg.Address)) { + if (L1IcacheMemory.isTagPresent(in_msg.LineAddress)) { // The tag matches for the L1, so the L1 asks the L2 for it. - trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address); + trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress); } else { - if (L1IcacheMemory.cacheAvail(in_msg.Address)) { + if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it - trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address); + trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress); } else { // No room in the L1, so we need to make room in the L1 - trigger(Event:L1_Replacement, L1IcacheMemory.cacheProbe(in_msg.Address)); + trigger(Event:L1_Replacement, L1IcacheMemory.cacheProbe(in_msg.LineAddress)); } } } else { // *** DATA ACCESS *** // Check to see if it is in the OTHER L1 - if (L1IcacheMemory.isTagPresent(in_msg.Address)) { + if (L1IcacheMemory.isTagPresent(in_msg.LineAddress)) { // The block is in the wrong L1, put the request on the queue to the shared L2 - trigger(Event:L1_Replacement, in_msg.Address); + trigger(Event:L1_Replacement, in_msg.LineAddress); } - if (L1DcacheMemory.isTagPresent(in_msg.Address)) { + if (L1DcacheMemory.isTagPresent(in_msg.LineAddress)) { // The tag matches for the L1, so the L1 ask the L2 for it - trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address); + trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress); } else { - if (L1DcacheMemory.cacheAvail(in_msg.Address)) { + if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it - trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address); + trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress); } else { // No room in the L1, so we need to make room in the L1 - trigger(Event:L1_Replacement, L1DcacheMemory.cacheProbe(in_msg.Address)); + trigger(Event:L1_Replacement, L1DcacheMemory.cacheProbe(in_msg.LineAddress)); } } } @@ -403,11 +407,12 @@ machine(L1Cache, "Directory protocol") { action(a_issueGETS, "a", desc="Issue GETS") { peek(mandatoryQueue_in, CacheMsg) { - enqueue(requestNetwork_out, RequestMsg, latency="L1_REQUEST_LATENCY") { + enqueue(requestNetwork_out, RequestMsg, latency= request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.MessageSize := MessageSizeType:Request_Control; out_msg.AccessMode := in_msg.AccessMode; out_msg.Prefetch := in_msg.Prefetch; @@ -417,11 +422,12 @@ machine(L1Cache, "Directory protocol") { action(b_issueGETX, "b", desc="Issue GETX") { peek(mandatoryQueue_in, CacheMsg) { - enqueue(requestNetwork_out, RequestMsg, latency="L1_REQUEST_LATENCY") { + enqueue(requestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.MessageSize := MessageSizeType:Request_Control; out_msg.AccessMode := in_msg.AccessMode; out_msg.Prefetch := in_msg.Prefetch; @@ -430,34 +436,37 @@ machine(L1Cache, "Directory protocol") { } action(d_issuePUTX, "d", desc="Issue PUTX") { - // enqueue(writebackNetwork_out, RequestMsg, latency="L1_REQUEST_LATENCY") { - enqueue(requestNetwork_out, RequestMsg, latency="L1_REQUEST_LATENCY") { + // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) { + enqueue(requestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:PUTX; out_msg.Requestor := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.MessageSize := MessageSizeType:Writeback_Control; } } action(dd_issuePUTO, "\d", desc="Issue PUTO") { - // enqueue(writebackNetwork_out, RequestMsg, latency="L1_REQUEST_LATENCY") { - enqueue(requestNetwork_out, RequestMsg, latency="L1_REQUEST_LATENCY") { + // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) { + enqueue(requestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:PUTO; out_msg.Requestor := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.MessageSize := MessageSizeType:Writeback_Control; } } action(dd_issuePUTS, "\ds", desc="Issue PUTS") { - // enqueue(writebackNetwork_out, RequestMsg, latency="L1_REQUEST_LATENCY") { - enqueue(requestNetwork_out, RequestMsg, latency="L1_REQUEST_LATENCY") { + // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) { + enqueue(requestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:PUTS; out_msg.Requestor := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.MessageSize := MessageSizeType:Writeback_Control; } } @@ -465,11 +474,12 @@ machine(L1Cache, "Directory protocol") { action(e_sendData, "e", desc="Send data from cache to requestor") { peek(requestNetwork_in, RequestMsg) { if (in_msg.RequestorMachine == MachineType:L2Cache) { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(in_msg.Address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.DataBlk := getCacheEntry(address).DataBlk; // out_msg.Dirty := getCacheEntry(address).Dirty; out_msg.Dirty := false; @@ -480,7 +490,7 @@ machine(L1Cache, "Directory protocol") { DEBUG_EXPR(in_msg.Address); } else { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -497,11 +507,12 @@ machine(L1Cache, "Directory protocol") { } action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.DataBlk := getCacheEntry(address).DataBlk; out_msg.Dirty := getCacheEntry(address).Dirty; out_msg.Acks := 0; // irrelevant @@ -513,12 +524,13 @@ machine(L1Cache, "Directory protocol") { action(ee_sendDataExclusive, "\e", desc="Send data from cache to requestor, don't keep a shared copy") { peek(requestNetwork_in, RequestMsg) { if (in_msg.RequestorMachine == MachineType:L2Cache) { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(in_msg.Address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.DataBlk := getCacheEntry(address).DataBlk; out_msg.Dirty := getCacheEntry(address).Dirty; out_msg.Acks := in_msg.Acks; @@ -527,7 +539,7 @@ machine(L1Cache, "Directory protocol") { DEBUG_EXPR("Sending exclusive data to L2"); } else { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -546,7 +558,7 @@ machine(L1Cache, "Directory protocol") { action(f_sendAck, "f", desc="Send ack from cache to requestor") { peek(requestNetwork_in, RequestMsg) { if (in_msg.RequestorMachine == MachineType:L1Cache) { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -557,12 +569,13 @@ machine(L1Cache, "Directory protocol") { } } else { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(in_msg.Address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.Acks := 0 - 1; // -1 out_msg.MessageSize := MessageSizeType:Response_Control; } @@ -571,21 +584,23 @@ machine(L1Cache, "Directory protocol") { } action(g_sendUnblock, "g", desc="Send unblock to memory") { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.MessageSize := MessageSizeType:Unblock_Control; } } action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to memory") { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE; out_msg.Sender := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.MessageSize := MessageSizeType:Unblock_Control; } } @@ -627,7 +642,6 @@ machine(L1Cache, "Directory protocol") { action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") { peek(responseToL1Cache_in, ResponseMsg) { DEBUG_EXPR("MRM_DEBUG: L1 decrementNumberOfMessages"); - DEBUG_EXPR(id); DEBUG_EXPR(in_msg.Acks); TBEs[address].NumPendingMsgs := TBEs[address].NumPendingMsgs - in_msg.Acks; } @@ -660,7 +674,7 @@ machine(L1Cache, "Directory protocol") { action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") { peek(requestNetwork_in, RequestMsg) { if (in_msg.RequestorMachine == MachineType:L1Cache) { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -673,11 +687,12 @@ machine(L1Cache, "Directory protocol") { } } else { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address,machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.DataBlk := TBEs[address].DataBlk; // out_msg.Dirty := TBEs[address].Dirty; out_msg.Dirty := false; @@ -691,7 +706,7 @@ machine(L1Cache, "Directory protocol") { action(q_sendExclusiveDataFromTBEToCache, "qq", desc="Send data from TBE to cache") { peek(requestNetwork_in, RequestMsg) { if (in_msg.RequestorMachine == MachineType:L1Cache) { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -703,11 +718,12 @@ machine(L1Cache, "Directory protocol") { } } else { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address,machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.DataBlk := TBEs[address].DataBlk; out_msg.Dirty := TBEs[address].Dirty; out_msg.Acks := in_msg.Acks; @@ -720,11 +736,12 @@ machine(L1Cache, "Directory protocol") { // L2 will usually request data for a writeback action(qq_sendWBDataFromTBEToL2, "\q", desc="Send data from TBE to L2") { - enqueue(responseNetwork_out, ResponseMsg, latency="L1_REQUEST_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) { out_msg.Address := address; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; - out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID)); + out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, + l2_select_low_bit, l2_select_num_bits)); out_msg.Dirty := TBEs[address].Dirty; if (TBEs[address].Dirty) { out_msg.Type := CoherenceResponseType:WRITEBACK_DIRTY_DATA; @@ -770,13 +787,13 @@ machine(L1Cache, "Directory protocol") { action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") { if (L1DcacheMemory.isTagPresent(address) == false) { - L1DcacheMemory.allocate(address); + L1DcacheMemory.allocate(address, new Entry); } } action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") { if (L1IcacheMemory.isTagPresent(address) == false) { - L1IcacheMemory.allocate(address); + L1IcacheMemory.allocate(address, new Entry); } } @@ -784,7 +801,7 @@ machine(L1Cache, "Directory protocol") { action(uu_profileMiss, "\u", desc="Profile the demand miss") { peek(mandatoryQueue_in, CacheMsg) { - profile_miss(in_msg, id); + // profile_miss(in_msg); } } diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm index fa01f925c..68d3a2cd3 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -32,7 +32,10 @@ * */ -machine(L2Cache, "Token protocol") { +machine(L2Cache, "Token protocol") +: int response_latency, + int request_latency +{ // L2 BANK QUEUES // From local bank of L2 cache TO the network @@ -208,7 +211,7 @@ machine(L2Cache, "Token protocol") { external_type(CacheMemory) { bool cacheAvail(Address); Address cacheProbe(Address); - void allocate(Address); + void allocate(Address, Entry); void deallocate(Address); Entry lookup(Address); void changePermission(Address, AccessPermission); @@ -225,13 +228,15 @@ machine(L2Cache, "Token protocol") { TBETable L2_TBEs, template_hack="<L2Cache_TBE>"; - CacheMemory L2cacheMemory, template_hack="<L2Cache_Entry>", constructor_hack='L2_CACHE_NUM_SETS_BITS,L2_CACHE_ASSOC,MachineType_L2Cache,int_to_string(i)+"_L2"'; + CacheMemory L2cacheMemory, factory='RubySystem::getCache(m_cfg["cache"])'; PerfectCacheMemory localDirectory, template_hack="<L2Cache_DirEntry>"; Entry getL2CacheEntry(Address addr), return_by_ref="yes" { if (L2cacheMemory.isTagPresent(addr)) { return L2cacheMemory[addr]; + } else { + return L2cacheMemory[addr]; } } @@ -579,7 +584,7 @@ machine(L2Cache, "Token protocol") { in_port(requestNetwork_in, RequestMsg, GlobalRequestToL2Cache) { if (requestNetwork_in.isReady()) { peek(requestNetwork_in, RequestMsg) { - if (in_msg.Type == CoherenceRequestType:GETX) { + if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_READ || in_msg.Type == CoherenceRequestType:DMA_WRITE) { if (in_msg.Requestor == machineID) { trigger(Event:Own_GETX, in_msg.Address); } else { @@ -675,7 +680,7 @@ machine(L2Cache, "Token protocol") { action(a_issueGETS, "a", desc="issue local request globally") { peek(L1requestNetwork_in, RequestMsg) { - enqueue(globalRequestNetwork_out, RequestMsg, latency="L2_REQUEST_LATENCY") { + enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.RequestorMachine := MachineType:L2Cache; @@ -688,7 +693,7 @@ machine(L2Cache, "Token protocol") { action(a_issueGETX, "\a", desc="issue local request globally") { peek(L1requestNetwork_in, RequestMsg) { - enqueue(globalRequestNetwork_out, RequestMsg, latency="L2_REQUEST_LATENCY") { + enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.RequestorMachine := MachineType:L2Cache; @@ -700,7 +705,7 @@ machine(L2Cache, "Token protocol") { } action(b_issuePUTX, "b", desc="Issue PUTX") { - enqueue(globalRequestNetwork_out, RequestMsg, latency="L2_REQUEST_LATENCY") { + enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:PUTX; out_msg.RequestorMachine := MachineType:L2Cache; @@ -711,7 +716,7 @@ machine(L2Cache, "Token protocol") { } action(b_issuePUTO, "\b", desc="Issue PUTO") { - enqueue(globalRequestNetwork_out, RequestMsg, latency="L2_REQUEST_LATENCY") { + enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:PUTO; out_msg.Requestor := machineID; @@ -723,7 +728,7 @@ machine(L2Cache, "Token protocol") { /* PUTO, but local sharers exist */ action(b_issuePUTO_ls, "\bb", desc="Issue PUTO") { - enqueue(globalRequestNetwork_out, RequestMsg, latency="L2_REQUEST_LATENCY") { + enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:PUTO_SHARERS; out_msg.Requestor := machineID; @@ -734,7 +739,7 @@ machine(L2Cache, "Token protocol") { } action(c_sendDataFromTBEToL1GETS, "c", desc="Send data from TBE to L1 requestors in TBE") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -750,7 +755,7 @@ machine(L2Cache, "Token protocol") { } action(c_sendDataFromTBEToL1GETX, "\c", desc="Send data from TBE to L1 requestors in TBE") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -766,7 +771,7 @@ machine(L2Cache, "Token protocol") { } action(c_sendExclusiveDataFromTBEToL1GETS, "\cc", desc="Send data from TBE to L1 requestors in TBE") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -779,7 +784,7 @@ machine(L2Cache, "Token protocol") { } action(c_sendDataFromTBEToFwdGETX, "cc", desc="Send data from TBE to external GETX") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -793,7 +798,7 @@ machine(L2Cache, "Token protocol") { } action(c_sendDataFromTBEToFwdGETS, "ccc", desc="Send data from TBE to external GETX") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -810,7 +815,7 @@ machine(L2Cache, "Token protocol") { } action(c_sendExclusiveDataFromTBEToFwdGETS, "\ccc", desc="Send data from TBE to external GETX") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -827,7 +832,7 @@ machine(L2Cache, "Token protocol") { action(d_sendDataToL1GETS, "d", desc="Send data directly to L1 requestor") { peek(L1requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -845,7 +850,7 @@ machine(L2Cache, "Token protocol") { action(d_sendDataToL1GETX, "\d", desc="Send data and a token from TBE to L1 requestor") { peek(L1requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -863,7 +868,7 @@ machine(L2Cache, "Token protocol") { action(dd_sendDataToFwdGETX, "dd", desc="send data") { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -882,7 +887,7 @@ machine(L2Cache, "Token protocol") { action(dd_sendDataToFwdGETS, "\dd", desc="send data") { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -900,7 +905,7 @@ machine(L2Cache, "Token protocol") { action(dd_sendExclusiveDataToFwdGETS, "\d\d", desc="send data") { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -913,7 +918,7 @@ machine(L2Cache, "Token protocol") { } action(e_sendAck, "e", desc="Send ack with the tokens we've collected thus far.") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -927,7 +932,7 @@ machine(L2Cache, "Token protocol") { action(e_sendAckToL1Requestor, "\e", desc="Send ack with the tokens we've collected thus far.") { peek(L1requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -940,7 +945,7 @@ machine(L2Cache, "Token protocol") { } action(e_sendAckToL1RequestorFromTBE, "eee", desc="Send ack with the tokens we've collected thus far.") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -955,14 +960,13 @@ machine(L2Cache, "Token protocol") { L2_TBEs[address].NumIntPendingAcks := countLocalSharers(address); DEBUG_EXPR(address); DEBUG_EXPR(getLocalSharers(address)); - DEBUG_EXPR(id); DEBUG_EXPR(L2_TBEs[address].NumIntPendingAcks); if (isLocalOwnerValid(address)) { L2_TBEs[address].NumIntPendingAcks := L2_TBEs[address].NumIntPendingAcks + 1; DEBUG_EXPR(getLocalOwner(address)); } - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := machineID; @@ -982,7 +986,7 @@ machine(L2Cache, "Token protocol") { L2_TBEs[address].NumIntPendingAcks := countLocalSharers(address); if (countLocalSharers(address) > 0) { - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := machineID; @@ -1013,7 +1017,7 @@ machine(L2Cache, "Token protocol") { L2_TBEs[address].NumIntPendingAcks := countLocalSharers(address); } - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := in_msg.Requestor; @@ -1038,7 +1042,7 @@ machine(L2Cache, "Token protocol") { L2_TBEs[address].NumIntPendingAcks := countLocalSharers(address); } } - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := L2_TBEs[address].L1_GetX_ID; @@ -1051,7 +1055,7 @@ machine(L2Cache, "Token protocol") { action(f_sendUnblock, "f", desc="Send unblock to global directory") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -1063,7 +1067,7 @@ machine(L2Cache, "Token protocol") { action(f_sendExclusiveUnblock, "\f", desc="Send unblock to global directory") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -1140,7 +1144,7 @@ machine(L2Cache, "Token protocol") { action(j_forwardGlobalRequestToLocalOwner, "j", desc="Forward external request to local owner") { peek(requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := in_msg.Address; out_msg.Type := in_msg.Type; out_msg.Requestor := machineID; @@ -1156,7 +1160,7 @@ machine(L2Cache, "Token protocol") { action(k_forwardLocalGETSToLocalSharer, "k", desc="Forward local request to local sharer/owner") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := in_msg.Address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := in_msg.Requestor; @@ -1169,7 +1173,7 @@ machine(L2Cache, "Token protocol") { } action(k_forwardLocalGETXToLocalOwner, "\k", desc="Forward local request to local owner") { - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := L2_TBEs[address].L1_GetX_ID; @@ -1183,7 +1187,7 @@ machine(L2Cache, "Token protocol") { // same as previous except that it assumes to TBE is present to get number of acks action(kk_forwardLocalGETXToLocalExclusive, "kk", desc="Forward local request to local owner") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := in_msg.Address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := in_msg.Requestor; @@ -1197,7 +1201,7 @@ machine(L2Cache, "Token protocol") { action(kk_forwardLocalGETSToLocalOwner, "\kk", desc="Forward local request to local owner") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := in_msg.Address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := in_msg.Requestor; @@ -1211,7 +1215,7 @@ machine(L2Cache, "Token protocol") { action(l_writebackAckNeedData, "l", desc="Send writeback ack to L1 requesting data") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := in_msg.Address; // out_msg.Type := CoherenceResponseType:WRITEBACK_SEND_DATA; out_msg.Type := CoherenceRequestType:WB_ACK_DATA; @@ -1225,7 +1229,7 @@ machine(L2Cache, "Token protocol") { action(l_writebackAckDropData, "\l", desc="Send writeback ack to L1 indicating to drop data") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := in_msg.Address; // out_msg.Type := CoherenceResponseType:WRITEBACK_ACK; out_msg.Type := CoherenceRequestType:WB_ACK; @@ -1239,7 +1243,7 @@ machine(L2Cache, "Token protocol") { action(ll_writebackNack, "\ll", desc="Send writeback nack to L1") { peek(L1requestNetwork_in, RequestMsg) { - enqueue( localRequestNetwork_out, RequestMsg, latency="L2_RESPONSE_LATENCY" ) { + enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) { out_msg.Address := in_msg.Address; out_msg.Type := CoherenceRequestType:WB_NACK; out_msg.Requestor := machineID; @@ -1305,7 +1309,7 @@ machine(L2Cache, "Token protocol") { action( qq_sendDataFromTBEToMemory, "qq", desc="Send data from TBE to directory") { - enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) { out_msg.Address := address; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L2Cache; @@ -1372,7 +1376,7 @@ machine(L2Cache, "Token protocol") { } action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") { - L2cacheMemory.allocate(address); + L2cacheMemory.allocate(address, new Entry); } action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") { @@ -1389,7 +1393,7 @@ machine(L2Cache, "Token protocol") { action(uu_profileMiss, "\u", desc="Profile the demand miss") { peek(L1requestNetwork_in, RequestMsg) { // AccessModeType not implemented - profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, machineIDToNodeID(in_msg.Requestor)); + // profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, machineIDToNodeID(in_msg.Requestor)); } } diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm index a016836c2..edd67707e 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -31,13 +31,15 @@ * $Id$ */ -machine(Directory, "Directory protocol") { +machine(Directory, "Directory protocol") +: int directory_latency +{ // ** IN QUEUES ** MessageBuffer foo1, network="From", virtual_network="0", ordered="false"; // a mod-L2 bank -> this Dir MessageBuffer requestToDir, network="From", virtual_network="1", ordered="false"; // a mod-L2 bank -> this Dir MessageBuffer responseToDir, network="From", virtual_network="2", ordered="false"; // a mod-L2 bank -> this Dir - + MessageBuffer goo1, network="To", virtual_network="0", ordered="false"; MessageBuffer forwardFromDir, network="To", virtual_network="1", ordered="false"; MessageBuffer responseFromDir, network="To", virtual_network="2", ordered="false"; // Dir -> mod-L2 bank @@ -56,11 +58,16 @@ machine(Directory, "Directory protocol") { OO, desc="Blocked, was in owned"; MO, desc="Blocked, going to owner or maybe modified"; MM, desc="Blocked, going to modified"; + MM_DMA, desc="Blocked, going to I"; MI, desc="Blocked on a writeback"; MIS, desc="Blocked on a writeback, but don't remove from sharers when received"; OS, desc="Blocked on a writeback"; OSS, desc="Blocked on a writeback, but don't remove from sharers when received"; + + XI_M, desc="In a stable state, going to I, waiting for the memory controller"; + XI_U, desc="In a stable state, going to I, waiting for an unblock"; + OI_D, desc="In O, going to I, waiting for data"; } // Events @@ -75,6 +82,11 @@ machine(Directory, "Directory protocol") { Exclusive_Unblock, desc="The processor become the exclusive owner (E or M) of the line"; Clean_Writeback, desc="The final message as part of a PutX/PutS, no data"; Dirty_Writeback, desc="The final message as part of a PutX/PutS, contains data"; + Memory_Data, desc="Fetched data from memory arrives"; + Memory_Ack, desc="Writeback Ack from memory arrives"; + DMA_READ, desc="DMA Read"; + DMA_WRITE, desc="DMA Write"; + Data, desc="Data to directory"; } // TYPES @@ -88,15 +100,36 @@ machine(Directory, "Directory protocol") { int WaitingUnblocks, desc="Number of acks we're waiting for"; } + structure(TBE, desc="...") { + Address address, desc="Address for this entry"; + int Len, desc="Length of request"; + DataBlock DataBlk, desc="DataBlk"; + MachineID Requestor, desc="original requestor"; + } + external_type(DirectoryMemory) { Entry lookup(Address); bool isPresent(Address); } + external_type(TBETable) { + TBE lookup(Address); + void allocate(Address); + void deallocate(Address); + bool isPresent(Address); + } + + // to simulate detailed DRAM + external_type(MemoryControl, inport="yes", outport="yes") { + + } + // ** OBJECTS ** - DirectoryMemory directory, constructor_hack="i"; + DirectoryMemory directory, factory='RubySystem::getDirectory(m_cfg["directory_name"])'; + MemoryControl memBuffer, factory='RubySystem::getMemoryControl(m_cfg["memory_controller_name"])'; + TBETable TBEs, template_hack="<Directory_TBE>"; State getState(Address addr) { return directory[addr].DirectoryState; @@ -164,6 +197,7 @@ machine(Directory, "Directory protocol") { out_port(responseNetwork_out, ResponseMsg, responseFromDir); // out_port(requestQueue_out, ResponseMsg, requestFromDir); // For recycling requests out_port(goo1_out, ResponseMsg, goo1); + out_port(memQueue_out, MemoryMsg, memBuffer); // ** IN_PORTS ** @@ -188,6 +222,8 @@ machine(Directory, "Directory protocol") { trigger(Event:Dirty_Writeback, in_msg.Address); } else if (in_msg.Type == CoherenceResponseType:WRITEBACK_CLEAN_ACK) { trigger(Event:Clean_Writeback, in_msg.Address); + } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) { + trigger(Event:Data, in_msg.Address); } else { error("Invalid message"); } @@ -208,7 +244,27 @@ machine(Directory, "Directory protocol") { trigger(Event:PUTO, in_msg.Address); } else if (in_msg.Type == CoherenceRequestType:PUTO_SHARERS) { trigger(Event:PUTO_SHARERS, in_msg.Address); + } else if (in_msg.Type == CoherenceRequestType:DMA_READ) { + trigger(Event:DMA_READ, in_msg.Address); + } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) { + trigger(Event:DMA_WRITE, in_msg.Address); + } else { + error("Invalid message"); + } + } + } + } + + // off-chip memory request/response is done + in_port(memQueue_in, MemoryMsg, memBuffer) { + if (memQueue_in.isReady()) { + peek(memQueue_in, MemoryMsg) { + if (in_msg.Type == MemoryRequestType:MEMORY_READ) { + trigger(Event:Memory_Data, in_msg.Address); + } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) { + trigger(Event:Memory_Ack, in_msg.Address); } else { + DEBUG_EXPR(in_msg.Type); error("Invalid message"); } } @@ -219,7 +275,7 @@ machine(Directory, "Directory protocol") { action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { + enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:WB_ACK; out_msg.Requestor := in_msg.Requestor; @@ -231,7 +287,7 @@ machine(Directory, "Directory protocol") { action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { + enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:WB_NACK; out_msg.Requestor := in_msg.Requestor; @@ -254,26 +310,21 @@ machine(Directory, "Directory protocol") { directory[address].Sharers.clear(); } - action(d_sendData, "d", desc="Send data to requestor") { - peek(requestQueue_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="MEMORY_LATENCY") { - // enqueue(responseNetwork_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") { + action(d_sendDataMsg, "d", desc="Send data to requestor") { + peek(memQueue_in, MemoryMsg) { + enqueue(responseNetwork_out, ResponseMsg, latency="1") { out_msg.Address := address; - - if (in_msg.Type == CoherenceRequestType:GETS && directory[address].Sharers.count() == 0) { - out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; - } else { - out_msg.Type := CoherenceResponseType:DATA; - } - out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:Directory; - out_msg.Destination.add(in_msg.Requestor); - out_msg.DataBlk := directory[in_msg.Address].DataBlk; + out_msg.Destination.add(in_msg.OriginalRequestorMachId); + //out_msg.DataBlk := directory[in_msg.Address].DataBlk; + out_msg.DataBlk := in_msg.DataBlk; out_msg.Dirty := false; // By definition, the block is now clean - out_msg.Acks := directory[address].Sharers.count(); - if (directory[address].Sharers.isElement(in_msg.Requestor)) { - out_msg.Acks := out_msg.Acks - 1; + out_msg.Acks := in_msg.Acks; + if (in_msg.ReadX) { + out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; + } else { + out_msg.Type := CoherenceResponseType:DATA; } out_msg.MessageSize := MessageSizeType:Response_Data; } @@ -289,7 +340,7 @@ machine(Directory, "Directory protocol") { action(f_forwardRequest, "f", desc="Forward request to owner") { peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { + enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; @@ -303,11 +354,27 @@ machine(Directory, "Directory protocol") { } } + action(f_forwardRequestDirIsRequestor, "\f", desc="Forward request to owner") { + peek(requestQueue_in, RequestMsg) { + enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { + out_msg.Address := address; + out_msg.Type := in_msg.Type; + out_msg.Requestor := machineID; + out_msg.Destination.addNetDest(directory[in_msg.Address].Owner); + out_msg.Acks := directory[address].Sharers.count(); + if (directory[address].Sharers.isElement(in_msg.Requestor)) { + out_msg.Acks := out_msg.Acks - 1; + } + out_msg.MessageSize := MessageSizeType:Forwarded_Control; + } + } + } + action(g_sendInvalidations, "g", desc="Send invalidations to sharers, not including the requester") { peek(requestQueue_in, RequestMsg) { if ((directory[in_msg.Address].Sharers.count() > 1) || ((directory[in_msg.Address].Sharers.count() > 0) && (directory[in_msg.Address].Sharers.isElement(in_msg.Requestor) == false))) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { + enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := in_msg.Requestor; @@ -338,7 +405,7 @@ machine(Directory, "Directory protocol") { } } - action(ll_checkDataInMemory, "\l", desc="Check PUTX/PUTO data is same as in the memory") { + action(ll_checkDataInMemory, "\ld", desc="Check PUTX/PUTO data is same as in the memory") { peek(unblockNetwork_in, ResponseMsg) { assert(in_msg.Dirty == false); assert(in_msg.MessageSize == MessageSizeType:Writeback_Control); @@ -366,6 +433,70 @@ machine(Directory, "Directory protocol") { assert(directory[address].WaitingUnblocks >= 0); } + action(q_popMemQueue, "q", desc="Pop off-chip request queue") { + memQueue_in.dequeue(); + } + + action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") { + peek(requestQueue_in, RequestMsg) { + enqueue(memQueue_out, MemoryMsg, latency="1") { + out_msg.Address := address; + out_msg.Type := MemoryRequestType:MEMORY_READ; + out_msg.Sender := machineID; + out_msg.OriginalRequestorMachId := in_msg.Requestor; + out_msg.DataBlk := directory[in_msg.Address].DataBlk; + out_msg.MessageSize := in_msg.MessageSize; + //out_msg.Prefetch := false; + // These are not used by memory but are passed back here with the read data: + out_msg.ReadX := (in_msg.Type == CoherenceRequestType:GETS && directory[address].Sharers.count() == 0); + out_msg.Acks := directory[address].Sharers.count(); + if (directory[address].Sharers.isElement(in_msg.Requestor)) { + out_msg.Acks := out_msg.Acks - 1; + } + DEBUG_EXPR(out_msg); + } + } + } + + action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") { + peek(unblockNetwork_in, ResponseMsg) { + enqueue(memQueue_out, MemoryMsg, latency="1") { + out_msg.Address := address; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + if (TBEs.isPresent(address)) { + out_msg.OriginalRequestorMachId := TBEs[address].Requestor; + } + out_msg.DataBlk := in_msg.DataBlk; + out_msg.MessageSize := in_msg.MessageSize; + //out_msg.Prefetch := false; + // Not used: + out_msg.ReadX := false; + out_msg.Acks := directory[address].Sharers.count(); // for dma requests + DEBUG_EXPR(out_msg); + } + } + } + + action(qw_queueMemoryWBRequest2, "/qw", desc="Queue off-chip writeback request") { + peek(requestQueue_in, RequestMsg) { + enqueue(memQueue_out, MemoryMsg, latency="1") { + out_msg.Address := address; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.OriginalRequestorMachId := in_msg.Requestor; + out_msg.DataBlk := in_msg.DataBlk; + out_msg.MessageSize := in_msg.MessageSize; + //out_msg.Prefetch := false; + // Not used: + out_msg.ReadX := false; + out_msg.Acks := directory[address].Sharers.count(); // for dma requests + DEBUG_EXPR(out_msg); + } + } + } + + // action(z_stall, "z", desc="Cannot be handled right now.") { // Special name recognized as do nothing case // } @@ -374,26 +505,106 @@ machine(Directory, "Directory protocol") { requestQueue_in.recycle(); } + action(a_sendDMAAck, "\a", desc="Send DMA Ack that write completed, along with Inv Ack count") { + peek(memQueue_in, MemoryMsg) { + enqueue(responseNetwork_out, ResponseMsg, latency="1") { + out_msg.Address := address; + out_msg.Sender := machineID; + out_msg.SenderMachine := MachineType:Directory; + out_msg.Destination.add(in_msg.OriginalRequestorMachId); + out_msg.DataBlk := in_msg.DataBlk; + out_msg.Acks := in_msg.Acks; + out_msg.Type := CoherenceResponseType:DMA_ACK; + out_msg.MessageSize := MessageSizeType:Writeback_Control; + } + } + } + + action(l_writeDMADataToMemory, "\l", desc="Write data from a DMA_WRITE to memory") { + peek(requestQueue_in, RequestMsg) { + directory[address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len); + } + } + + action(l_writeDMADataToMemoryFromTBE, "\ll", desc="Write data from a DMA_WRITE to memory") { + directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(address), TBEs[address].Len); + } + + action(v_allocateTBE, "v", desc="Allocate TBE entry") { + peek (requestQueue_in, RequestMsg) { + TBEs.allocate(address); + TBEs[address].Len := in_msg.Len; + TBEs[address].DataBlk := in_msg.DataBlk; + TBEs[address].Requestor := in_msg.Requestor; + } + } + + action(w_deallocateTBE, "w", desc="Deallocate TBE entry") { + TBEs.deallocate(address); + } + + + // TRANSITIONS transition(I, GETX, MM) { - d_sendData; + qf_queueMemoryFetchRequest; + i_popIncomingRequestQueue; + } + + transition(I, DMA_READ, XI_M) { + qf_queueMemoryFetchRequest; i_popIncomingRequestQueue; } + transition(I, DMA_WRITE, XI_M) { + qw_queueMemoryWBRequest2; + l_writeDMADataToMemory; + i_popIncomingRequestQueue; + } + + transition(XI_M, Memory_Data, XI_U) { + d_sendDataMsg; // ack count may be zero + q_popMemQueue; + } + + transition(XI_M, Memory_Ack, XI_U) { + a_sendDMAAck; // ack count may be zero + q_popMemQueue; + } + + transition(XI_U, Exclusive_Unblock, I) { + cc_clearSharers; + c_clearOwner; + j_popIncomingUnblockQueue; + } + transition(S, GETX, MM) { - d_sendData; + qf_queueMemoryFetchRequest; g_sendInvalidations; i_popIncomingRequestQueue; } + transition(S, DMA_READ, XI_M) { + qf_queueMemoryFetchRequest; + g_sendInvalidations; // the DMA will collect the invalidations then send an Unblock Exclusive + i_popIncomingRequestQueue; + } + + transition(S, DMA_WRITE, XI_M) { + qw_queueMemoryWBRequest2; + l_writeDMADataToMemory; + g_sendInvalidations; // the DMA will collect invalidations + i_popIncomingRequestQueue; + } + transition(I, GETS, IS) { - d_sendData; + qf_queueMemoryFetchRequest; i_popIncomingRequestQueue; } transition({S, SS}, GETS, SS) { - d_sendData; + qf_queueMemoryFetchRequest; n_incrementOutstanding; i_popIncomingRequestQueue; } @@ -414,6 +625,27 @@ machine(Directory, "Directory protocol") { i_popIncomingRequestQueue; } + transition(O, DMA_READ, XI_U) { + f_forwardRequest; // this will cause the data to go to DMA directly + g_sendInvalidations; // this will cause acks to be sent to the DMA + i_popIncomingRequestQueue; + } + + transition({O,M}, DMA_WRITE, OI_D) { + f_forwardRequestDirIsRequestor; // need the modified data before we can proceed + g_sendInvalidations; // these go to the DMA Controller + v_allocateTBE; + i_popIncomingRequestQueue; + } + + transition(OI_D, Data, XI_M) { + qw_queueMemoryWBRequest; + l_writeDataToMemory; + l_writeDMADataToMemoryFromTBE; + w_deallocateTBE; + j_popIncomingUnblockQueue; + } + transition({O, OO}, GETS, OO) { f_forwardRequest; n_incrementOutstanding; @@ -425,6 +657,12 @@ machine(Directory, "Directory protocol") { i_popIncomingRequestQueue; } + // no exclusive unblock will show up to the directory + transition(M, DMA_READ, XI_U) { + f_forwardRequest; // this will cause the data to go to DMA directly + i_popIncomingRequestQueue; + } + transition(M, GETS, MO) { f_forwardRequest; i_popIncomingRequestQueue; @@ -457,7 +695,7 @@ machine(Directory, "Directory protocol") { } - transition({MM, MO, MI, MIS, OS, OSS}, {GETS, GETX, PUTO, PUTO_SHARERS, PUTX}) { + transition({MM, MO, MI, MIS, OS, OSS}, {GETS, GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ}) { zz_recycleRequest; } @@ -472,7 +710,7 @@ machine(Directory, "Directory protocol") { j_popIncomingUnblockQueue; } - transition({IS, SS, OO}, {GETX, PUTO, PUTO_SHARERS, PUTX}) { + transition({IS, SS, OO}, {GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ}) { zz_recycleRequest; } @@ -519,12 +757,14 @@ machine(Directory, "Directory protocol") { c_clearOwner; cc_clearSharers; l_writeDataToMemory; + qw_queueMemoryWBRequest; j_popIncomingUnblockQueue; } transition(MIS, Dirty_Writeback, S) { c_moveOwnerToSharer; l_writeDataToMemory; + qw_queueMemoryWBRequest; j_popIncomingUnblockQueue; } @@ -536,12 +776,14 @@ machine(Directory, "Directory protocol") { transition(OS, Dirty_Writeback, S) { c_clearOwner; l_writeDataToMemory; + qw_queueMemoryWBRequest; j_popIncomingUnblockQueue; } transition(OSS, Dirty_Writeback, S) { c_moveOwnerToSharer; l_writeDataToMemory; + qw_queueMemoryWBRequest; j_popIncomingUnblockQueue; } @@ -570,4 +812,15 @@ machine(Directory, "Directory protocol") { transition({OS, OSS}, Unblock, O) { j_popIncomingUnblockQueue; } + + transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS}, Memory_Data) { + d_sendDataMsg; + q_popMemQueue; + } + + transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS}, Memory_Ack) { + //a_sendAck; + q_popMemQueue; + } + } diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm new file mode 100644 index 000000000..74246c730 --- /dev/null +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -0,0 +1,267 @@ + +machine(DMA, "DMA Controller") +: int request_latency, + int response_latency +{ + + MessageBuffer goo1, network="From", virtual_network="0", ordered="false"; + MessageBuffer goo2, network="From", virtual_network="1", ordered="false"; + MessageBuffer responseFromDir, network="From", virtual_network="2", ordered="false"; + + MessageBuffer foo1, network="To", virtual_network="0", ordered="false"; + MessageBuffer reqToDir, network="To", virtual_network="1", ordered="false"; + MessageBuffer respToDir, network="To", virtual_network="2", ordered="false"; + + enumeration(State, desc="DMA states", default="DMA_State_READY") { + READY, desc="Ready to accept a new request"; + BUSY_RD, desc="Busy: currently processing a request"; + BUSY_WR, desc="Busy: currently processing a request"; + } + + enumeration(Event, desc="DMA events") { + ReadRequest, desc="A new read request"; + WriteRequest, desc="A new write request"; + Data, desc="Data from a DMA memory read"; + DMA_Ack, desc="DMA write to memory completed"; + Inv_Ack, desc="Invalidation Ack from a sharer"; + All_Acks, desc="All acks received"; + } + + structure(TBE, desc="...") { + Address address, desc="Physical address"; + int NumAcks, default="0", desc="Number of Acks pending"; + DataBlock DataBlk, desc="Data"; + } + + external_type(DMASequencer) { + void ackCallback(); + void dataCallback(DataBlock); + } + + external_type(TBETable) { + TBE lookup(Address); + void allocate(Address); + void deallocate(Address); + bool isPresent(Address); + } + + MessageBuffer mandatoryQueue, ordered="false"; + MessageBuffer triggerQueue, ordered="true"; + DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])'; + TBETable TBEs, template_hack="<DMA_TBE>"; + State cur_state; + + State getState(Address addr) { + return cur_state; + } + void setState(Address addr, State state) { + cur_state := state; + } + + out_port(reqToDirectory_out, RequestMsg, reqToDir, desc="..."); + out_port(respToDirectory_out, ResponseMsg, respToDir, desc="..."); + out_port(foo1_out, ResponseMsg, foo1, desc="..."); + out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="..."); + + in_port(goo1_in, RequestMsg, goo1) { + if (goo1_in.isReady()) { + peek(goo1_in, RequestMsg) { + assert(false); + } + } + } + + in_port(goo2_in, RequestMsg, goo2) { + if (goo2_in.isReady()) { + peek(goo2_in, RequestMsg) { + assert(false); + } + } + } + + in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { + if (dmaRequestQueue_in.isReady()) { + peek(dmaRequestQueue_in, SequencerMsg) { + if (in_msg.Type == SequencerRequestType:LD ) { + trigger(Event:ReadRequest, in_msg.PhysicalAddress); + } else if (in_msg.Type == SequencerRequestType:ST) { + trigger(Event:WriteRequest, in_msg.PhysicalAddress); + } else { + error("Invalid request type"); + } + } + } + } + + in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") { + if (dmaResponseQueue_in.isReady()) { + peek( dmaResponseQueue_in, ResponseMsg) { + if (in_msg.Type == CoherenceResponseType:DMA_ACK) { + trigger(Event:DMA_Ack, in_msg.Address); + } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) { + trigger(Event:Data, in_msg.Address); + } else if (in_msg.Type == CoherenceResponseType:ACK) { + trigger(Event:Inv_Ack, in_msg.Address); + } else { + error("Invalid response type"); + } + } + } + } + + // Trigger Queue + in_port(triggerQueue_in, TriggerMsg, triggerQueue) { + if (triggerQueue_in.isReady()) { + peek(triggerQueue_in, TriggerMsg) { + if (in_msg.Type == TriggerType:ALL_ACKS) { + trigger(Event:All_Acks, in_msg.Address); + } else { + error("Unexpected message"); + } + } + } + } + + action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { + peek(dmaRequestQueue_in, SequencerMsg) { + enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceRequestType:DMA_READ; + out_msg.DataBlk := in_msg.DataBlk; + out_msg.Len := in_msg.Len; + out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Requestor := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Control; + } + } + } + + action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { + peek(dmaRequestQueue_in, SequencerMsg) { + enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceRequestType:DMA_WRITE; + out_msg.DataBlk := in_msg.DataBlk; + out_msg.Len := in_msg.Len; + out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Requestor := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Control; + } + } + } + + action(a_ackCallback, "a", desc="Notify dma controller that write request completed") { + dma_sequencer.ackCallback(); + } + + action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") { + if (TBEs[address].NumAcks == 0) { + enqueue(triggerQueue_out, TriggerMsg) { + out_msg.Address := address; + out_msg.Type := TriggerType:ALL_ACKS; + } + } + } + + action(u_updateAckCount, "u", desc="Update ack count") { + peek(dmaResponseQueue_in, ResponseMsg) { + TBEs[address].NumAcks := TBEs[address].NumAcks - in_msg.Acks; + } + } + + action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") { + enqueue(respToDirectory_out, ResponseMsg, latency=response_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE; + out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.MessageSize := MessageSizeType:Writeback_Control; + } + } + + action(p_popRequestQueue, "p", desc="Pop request queue") { + dmaRequestQueue_in.dequeue(); + } + + action(p_popResponseQueue, "\p", desc="Pop request queue") { + dmaResponseQueue_in.dequeue(); + } + + action(p_popTriggerQueue, "pp", desc="Pop trigger queue") { + triggerQueue_in.dequeue(); + } + + action(t_updateTBEData, "t", desc="Update TBE Data") { + peek(dmaResponseQueue_in, ResponseMsg) { + TBEs[address].DataBlk := in_msg.DataBlk; + } + } + + action(d_dataCallbackFromTBE, "/d", desc="data callback with data from TBE") { + dma_sequencer.dataCallback(TBEs[address].DataBlk); + } + + action(v_allocateTBE, "v", desc="Allocate TBE entry") { + TBEs.allocate(address); + } + + action(w_deallocateTBE, "w", desc="Deallocate TBE entry") { + TBEs.deallocate(address); + } + + action(z_stall, "z", desc="dma is busy..stall") { + // do nothing + } + + + + transition(READY, ReadRequest, BUSY_RD) { + s_sendReadRequest; + v_allocateTBE; + p_popRequestQueue; + } + + transition(BUSY_RD, Inv_Ack) { + u_updateAckCount; + o_checkForCompletion; + p_popResponseQueue; + } + + transition(BUSY_RD, Data) { + t_updateTBEData; + u_updateAckCount; + o_checkForCompletion; + p_popResponseQueue; + } + + transition(BUSY_RD, All_Acks, READY) { + d_dataCallbackFromTBE; + u_sendExclusiveUnblockToDir; + w_deallocateTBE; + p_popTriggerQueue; + } + + transition(READY, WriteRequest, BUSY_WR) { + s_sendWriteRequest; + v_allocateTBE; + p_popRequestQueue; + } + + transition(BUSY_WR, Inv_Ack) { + u_updateAckCount; + o_checkForCompletion; + p_popResponseQueue; + } + + transition(BUSY_WR, DMA_Ack) { + u_updateAckCount; // actually increases + o_checkForCompletion; + p_popResponseQueue; + } + + transition(BUSY_WR, All_Acks, READY) { + a_ackCallback; + u_sendExclusiveUnblockToDir; + w_deallocateTBE; + p_popTriggerQueue; + } +} diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm b/src/mem/protocol/MOESI_CMP_directory-msg.sm index 08b4abec3..edbff0c96 100644 --- a/src/mem/protocol/MOESI_CMP_directory-msg.sm +++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm @@ -44,6 +44,9 @@ enumeration(CoherenceRequestType, desc="...") { WB_ACK_DATA, desc="Writeback ack"; WB_NACK, desc="Writeback neg. ack"; INV, desc="Invalidation"; + + DMA_READ, desc="DMA Read"; + DMA_WRITE, desc="DMA Write"; } // CoherenceResponseType @@ -56,6 +59,8 @@ enumeration(CoherenceResponseType, desc="...") { WRITEBACK_CLEAN_DATA, desc="Clean writeback (contains data)"; WRITEBACK_CLEAN_ACK, desc="Clean writeback (contains no data)"; WRITEBACK_DIRTY_DATA, desc="Dirty writeback (contains data)"; + + DMA_ACK, desc="Ack that a DMA write completed"; } // TriggerType @@ -72,10 +77,12 @@ structure(TriggerMsg, desc="...", interface="Message") { // RequestMsg (and also forwarded requests) structure(RequestMsg, desc="...", interface="NetworkMessage") { Address Address, desc="Physical address for this request"; + int Len, desc="Length of Request"; CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)"; MachineID Requestor, desc="Node who initiated the request"; MachineType RequestorMachine, desc="type of component"; NetDest Destination, desc="Multicast destination mask"; + DataBlock DataBlk, desc="data for the cache line (DMA WRITE request)"; int Acks, desc="How many acks to expect"; MessageSizeType MessageSize, desc="size category of the message"; AccessModeType AccessMode, desc="user/supervisor access type"; @@ -95,32 +102,4 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") { MessageSizeType MessageSize, desc="size category of the message"; } -GenericRequestType convertToGenericType(CoherenceRequestType type) { - if(type == CoherenceRequestType:PUTX) { - return GenericRequestType:PUTX; - } else if(type == CoherenceRequestType:GETS) { - return GenericRequestType:GETS; - } else if(type == CoherenceRequestType:GETX) { - return GenericRequestType:GETX; - } else if(type == CoherenceRequestType:PUTS) { - return GenericRequestType:PUTS; - } else if(type == CoherenceRequestType:PUTX) { - return GenericRequestType:PUTS; - } else if(type == CoherenceRequestType:PUTO) { - return GenericRequestType:PUTO; - } else if(type == CoherenceRequestType:PUTO_SHARERS) { - return GenericRequestType:PUTO; - } else if(type == CoherenceRequestType:INV) { - return GenericRequestType:INV; - } else if(type == CoherenceRequestType:WB_ACK) { - return GenericRequestType:WB_ACK; - } else if(type == CoherenceRequestType:WB_ACK_DATA) { - return GenericRequestType:WB_ACK; - } else if(type == CoherenceRequestType:WB_NACK) { - return GenericRequestType:NACK; - } else { - DEBUG_EXPR(type); - error("invalid CoherenceRequestType"); - } -} diff --git a/src/mem/protocol/MOESI_CMP_directory.slicc b/src/mem/protocol/MOESI_CMP_directory.slicc index c552d7157..f288aa4b0 100644 --- a/src/mem/protocol/MOESI_CMP_directory.slicc +++ b/src/mem/protocol/MOESI_CMP_directory.slicc @@ -1,5 +1,6 @@ MOESI_CMP_directory-msg.sm MOESI_CMP_directory-L2cache.sm MOESI_CMP_directory-L1cache.sm +MOESI_CMP_directory-dma.sm MOESI_CMP_directory-dir.sm standard_CMP-protocol.sm diff --git a/src/mem/protocol/MOESI_CMP_directory_m-dir.sm b/src/mem/protocol/MOESI_CMP_directory_m-dir.sm deleted file mode 100644 index 3a4d875c1..000000000 --- a/src/mem/protocol/MOESI_CMP_directory_m-dir.sm +++ /dev/null @@ -1,652 +0,0 @@ - -/* - * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * $Id$ - */ - -machine(Directory, "Directory protocol") { - - // ** IN QUEUES ** - MessageBuffer foo1, network="From", virtual_network="0", ordered="false"; // a mod-L2 bank -> this Dir - MessageBuffer requestToDir, network="From", virtual_network="1", ordered="false"; // a mod-L2 bank -> this Dir - MessageBuffer responseToDir, network="From", virtual_network="2", ordered="false"; // a mod-L2 bank -> this Dir - - MessageBuffer goo1, network="To", virtual_network="0", ordered="false"; - MessageBuffer forwardFromDir, network="To", virtual_network="1", ordered="false"; - MessageBuffer responseFromDir, network="To", virtual_network="2", ordered="false"; // Dir -> mod-L2 bank - - - // STATES - enumeration(State, desc="Directory states", default="Directory_State_I") { - // Base states - I, desc="Invalid"; - S, desc="Shared"; - O, desc="Owner"; - M, desc="Modified"; - - IS, desc="Blocked, was in idle"; - SS, desc="Blocked, was in shared"; - OO, desc="Blocked, was in owned"; - MO, desc="Blocked, going to owner or maybe modified"; - MM, desc="Blocked, going to modified"; - - MI, desc="Blocked on a writeback"; - MIS, desc="Blocked on a writeback, but don't remove from sharers when received"; - OS, desc="Blocked on a writeback"; - OSS, desc="Blocked on a writeback, but don't remove from sharers when received"; - } - - // Events - enumeration(Event, desc="Directory events") { - GETX, desc="A GETX arrives"; - GETS, desc="A GETS arrives"; - PUTX, desc="A PUTX arrives"; - PUTO, desc="A PUTO arrives"; - PUTO_SHARERS, desc="A PUTO arrives, but don't remove from sharers list"; - Unblock, desc="An unblock message arrives"; - Last_Unblock, desc="An unblock message arrives, we're not waiting for any additional unblocks"; - Exclusive_Unblock, desc="The processor become the exclusive owner (E or M) of the line"; - Clean_Writeback, desc="The final message as part of a PutX/PutS, no data"; - Dirty_Writeback, desc="The final message as part of a PutX/PutS, contains data"; - Memory_Data, desc="Fetched data from memory arrives"; - Memory_Ack, desc="Writeback Ack from memory arrives"; - } - - // TYPES - - // DirectoryEntry - structure(Entry, desc="...") { - State DirectoryState, desc="Directory state"; - DataBlock DataBlk, desc="data for the block"; - NetDest Sharers, desc="Sharers for this block"; - NetDest Owner, desc="Owner of this block"; - int WaitingUnblocks, desc="Number of acks we're waiting for"; - } - - external_type(DirectoryMemory) { - Entry lookup(Address); - bool isPresent(Address); - } - - // to simulate detailed DRAM - external_type(MemoryControl, inport="yes", outport="yes") { - - } - - - // ** OBJECTS ** - - DirectoryMemory directory, constructor_hack="i"; - MemoryControl memBuffer, constructor_hack="i"; - - State getState(Address addr) { - return directory[addr].DirectoryState; - } - - void setState(Address addr, State state) { - if (directory.isPresent(addr)) { - - if (state == State:I) { - assert(directory[addr].Owner.count() == 0); - assert(directory[addr].Sharers.count() == 0); - } - - if (state == State:S) { - assert(directory[addr].Owner.count() == 0); - } - - if (state == State:O) { - assert(directory[addr].Owner.count() == 1); - assert(directory[addr].Sharers.isSuperset(directory[addr].Owner) == false); - } - - if (state == State:M) { - assert(directory[addr].Owner.count() == 1); - assert(directory[addr].Sharers.count() == 0); - } - - if ((state != State:SS) && (state != State:OO)) { - assert(directory[addr].WaitingUnblocks == 0); - } - - if ( (directory[addr].DirectoryState != State:I) && (state == State:I) ) { - directory[addr].DirectoryState := state; - // disable coherence checker - // sequencer.checkCoherence(addr); - } - else { - directory[addr].DirectoryState := state; - } - } - } - - // if no sharers, then directory can be considered both a sharer and exclusive w.r.t. coherence checking - bool isBlockShared(Address addr) { - if (directory.isPresent(addr)) { - if (directory[addr].DirectoryState == State:I) { - return true; - } - } - return false; - } - - bool isBlockExclusive(Address addr) { - if (directory.isPresent(addr)) { - if (directory[addr].DirectoryState == State:I) { - return true; - } - } - return false; - } - - - // ** OUT_PORTS ** - out_port(forwardNetwork_out, RequestMsg, forwardFromDir); - out_port(responseNetwork_out, ResponseMsg, responseFromDir); -// out_port(requestQueue_out, ResponseMsg, requestFromDir); // For recycling requests - out_port(goo1_out, ResponseMsg, goo1); - out_port(memQueue_out, MemoryMsg, memBuffer); - - // ** IN_PORTS ** - - in_port(foo1_in, ResponseMsg, foo1) { - - } - - // in_port(unblockNetwork_in, ResponseMsg, unblockToDir) { - // if (unblockNetwork_in.isReady()) { - in_port(unblockNetwork_in, ResponseMsg, responseToDir) { - if (unblockNetwork_in.isReady()) { - peek(unblockNetwork_in, ResponseMsg) { - if (in_msg.Type == CoherenceResponseType:UNBLOCK) { - if (directory[in_msg.Address].WaitingUnblocks == 1) { - trigger(Event:Last_Unblock, in_msg.Address); - } else { - trigger(Event:Unblock, in_msg.Address); - } - } else if (in_msg.Type == CoherenceResponseType:UNBLOCK_EXCLUSIVE) { - trigger(Event:Exclusive_Unblock, in_msg.Address); - } else if (in_msg.Type == CoherenceResponseType:WRITEBACK_DIRTY_DATA) { - trigger(Event:Dirty_Writeback, in_msg.Address); - } else if (in_msg.Type == CoherenceResponseType:WRITEBACK_CLEAN_ACK) { - trigger(Event:Clean_Writeback, in_msg.Address); - } else { - error("Invalid message"); - } - } - } - } - - in_port(requestQueue_in, RequestMsg, requestToDir) { - if (requestQueue_in.isReady()) { - peek(requestQueue_in, RequestMsg) { - if (in_msg.Type == CoherenceRequestType:GETS) { - trigger(Event:GETS, in_msg.Address); - } else if (in_msg.Type == CoherenceRequestType:GETX) { - trigger(Event:GETX, in_msg.Address); - } else if (in_msg.Type == CoherenceRequestType:PUTX) { - trigger(Event:PUTX, in_msg.Address); - } else if (in_msg.Type == CoherenceRequestType:PUTO) { - trigger(Event:PUTO, in_msg.Address); - } else if (in_msg.Type == CoherenceRequestType:PUTO_SHARERS) { - trigger(Event:PUTO_SHARERS, in_msg.Address); - } else { - error("Invalid message"); - } - } - } - } - - // off-chip memory request/response is done - in_port(memQueue_in, MemoryMsg, memBuffer) { - if (memQueue_in.isReady()) { - peek(memQueue_in, MemoryMsg) { - if (in_msg.Type == MemoryRequestType:MEMORY_READ) { - trigger(Event:Memory_Data, in_msg.Address); - } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) { - trigger(Event:Memory_Ack, in_msg.Address); - } else { - DEBUG_EXPR(in_msg.Type); - error("Invalid message"); - } - } - } - } - - // Actions - - action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") { - peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { - out_msg.Address := address; - out_msg.Type := CoherenceRequestType:WB_ACK; - out_msg.Requestor := in_msg.Requestor; - out_msg.Destination.add(in_msg.Requestor); - out_msg.MessageSize := MessageSizeType:Writeback_Control; - } - } - } - - action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") { - peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { - out_msg.Address := address; - out_msg.Type := CoherenceRequestType:WB_NACK; - out_msg.Requestor := in_msg.Requestor; - out_msg.Destination.add(in_msg.Requestor); - out_msg.MessageSize := MessageSizeType:Writeback_Control; - } - } - } - - action(c_clearOwner, "c", desc="Clear the owner field") { - directory[address].Owner.clear(); - } - - action(c_moveOwnerToSharer, "cc", desc="Move owner to sharers") { - directory[address].Sharers.addNetDest(directory[address].Owner); - directory[address].Owner.clear(); - } - - action(cc_clearSharers, "\c", desc="Clear the sharers field") { - directory[address].Sharers.clear(); - } - - action(d_sendDataMsg, "d", desc="Send data to requestor") { - peek(memQueue_in, MemoryMsg) { - enqueue(responseNetwork_out, ResponseMsg, latency="1") { - out_msg.Address := address; - out_msg.Sender := machineID; - out_msg.SenderMachine := MachineType:Directory; - out_msg.Destination.add(in_msg.OriginalRequestorMachId); - //out_msg.DataBlk := directory[in_msg.Address].DataBlk; - out_msg.DataBlk := in_msg.DataBlk; - out_msg.Dirty := false; // By definition, the block is now clean - out_msg.Acks := in_msg.Acks; - if (in_msg.ReadX) { - out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; - } else { - out_msg.Type := CoherenceResponseType:DATA; - } - out_msg.MessageSize := MessageSizeType:Response_Data; - } - } - } - - action(e_ownerIsUnblocker, "e", desc="The owner is now the unblocker") { - peek(unblockNetwork_in, ResponseMsg) { - directory[address].Owner.clear(); - directory[address].Owner.add(in_msg.Sender); - } - } - - action(f_forwardRequest, "f", desc="Forward request to owner") { - peek(requestQueue_in, RequestMsg) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { - out_msg.Address := address; - out_msg.Type := in_msg.Type; - out_msg.Requestor := in_msg.Requestor; - out_msg.Destination.addNetDest(directory[in_msg.Address].Owner); - out_msg.Acks := directory[address].Sharers.count(); - if (directory[address].Sharers.isElement(in_msg.Requestor)) { - out_msg.Acks := out_msg.Acks - 1; - } - out_msg.MessageSize := MessageSizeType:Forwarded_Control; - } - } - } - - action(g_sendInvalidations, "g", desc="Send invalidations to sharers, not including the requester") { - peek(requestQueue_in, RequestMsg) { - if ((directory[in_msg.Address].Sharers.count() > 1) || - ((directory[in_msg.Address].Sharers.count() > 0) && (directory[in_msg.Address].Sharers.isElement(in_msg.Requestor) == false))) { - enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") { - out_msg.Address := address; - out_msg.Type := CoherenceRequestType:INV; - out_msg.Requestor := in_msg.Requestor; - // out_msg.Destination := directory[in_msg.Address].Sharers; - out_msg.Destination.addNetDest(directory[in_msg.Address].Sharers); - out_msg.Destination.remove(in_msg.Requestor); - out_msg.MessageSize := MessageSizeType:Invalidate_Control; - } - } - } - } - - action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") { - requestQueue_in.dequeue(); - } - - action(j_popIncomingUnblockQueue, "j", desc="Pop incoming unblock queue") { - unblockNetwork_in.dequeue(); - } - - action(l_writeDataToMemory, "l", desc="Write PUTX/PUTO data to memory") { - peek(unblockNetwork_in, ResponseMsg) { - assert(in_msg.Dirty); - assert(in_msg.MessageSize == MessageSizeType:Writeback_Data); - directory[in_msg.Address].DataBlk := in_msg.DataBlk; - DEBUG_EXPR(in_msg.Address); - DEBUG_EXPR(in_msg.DataBlk); - } - } - - action(ll_checkDataInMemory, "\l", desc="Check PUTX/PUTO data is same as in the memory") { - peek(unblockNetwork_in, ResponseMsg) { - assert(in_msg.Dirty == false); - assert(in_msg.MessageSize == MessageSizeType:Writeback_Control); - - // NOTE: The following check would not be valid in a real - // implementation. We include the data in the "dataless" - // message so we can assert the clean data matches the datablock - // in memory - assert(directory[in_msg.Address].DataBlk == in_msg.DataBlk); - } - } - - action(m_addUnlockerToSharers, "m", desc="Add the unlocker to the sharer list") { - peek(unblockNetwork_in, ResponseMsg) { - directory[address].Sharers.add(in_msg.Sender); - } - } - - action(n_incrementOutstanding, "n", desc="Increment outstanding requests") { - directory[address].WaitingUnblocks := directory[address].WaitingUnblocks + 1; - } - - action(o_decrementOutstanding, "o", desc="Decrement outstanding requests") { - directory[address].WaitingUnblocks := directory[address].WaitingUnblocks - 1; - assert(directory[address].WaitingUnblocks >= 0); - } - - action(q_popMemQueue, "q", desc="Pop off-chip request queue") { - memQueue_in.dequeue(); - } - - action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") { - peek(requestQueue_in, RequestMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { - out_msg.Address := address; - out_msg.Type := MemoryRequestType:MEMORY_READ; - out_msg.Sender := machineID; - out_msg.OriginalRequestorMachId := in_msg.Requestor; - out_msg.DataBlk := directory[in_msg.Address].DataBlk; - out_msg.MessageSize := in_msg.MessageSize; - //out_msg.Prefetch := false; - // These are not used by memory but are passed back here with the read data: - out_msg.ReadX := (in_msg.Type == CoherenceRequestType:GETS && directory[address].Sharers.count() == 0); - out_msg.Acks := directory[address].Sharers.count(); - if (directory[address].Sharers.isElement(in_msg.Requestor)) { - out_msg.Acks := out_msg.Acks - 1; - } - DEBUG_EXPR(out_msg); - } - } - } - - action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") { - peek(unblockNetwork_in, ResponseMsg) { - enqueue(memQueue_out, MemoryMsg, latency="1") { - out_msg.Address := address; - out_msg.Type := MemoryRequestType:MEMORY_WB; - out_msg.Sender := machineID; - //out_msg.OriginalRequestorMachId := in_msg.Requestor; - out_msg.DataBlk := in_msg.DataBlk; - out_msg.MessageSize := in_msg.MessageSize; - //out_msg.Prefetch := false; - // Not used: - out_msg.ReadX := false; - out_msg.Acks := 0; - DEBUG_EXPR(out_msg); - } - } - } - - - // action(z_stall, "z", desc="Cannot be handled right now.") { - // Special name recognized as do nothing case - // } - - action(zz_recycleRequest, "\z", desc="Recycle the request queue") { - requestQueue_in.recycle(); - } - - // TRANSITIONS - - transition(I, GETX, MM) { - qf_queueMemoryFetchRequest; - i_popIncomingRequestQueue; - } - - transition(S, GETX, MM) { - qf_queueMemoryFetchRequest; - g_sendInvalidations; - i_popIncomingRequestQueue; - } - - transition(I, GETS, IS) { - qf_queueMemoryFetchRequest; - i_popIncomingRequestQueue; - } - - transition({S, SS}, GETS, SS) { - qf_queueMemoryFetchRequest; - n_incrementOutstanding; - i_popIncomingRequestQueue; - } - - transition({I, S}, PUTO) { - b_sendWriteBackNack; - i_popIncomingRequestQueue; - } - - transition({I, S, O}, PUTX) { - b_sendWriteBackNack; - i_popIncomingRequestQueue; - } - - transition(O, GETX, MM) { - f_forwardRequest; - g_sendInvalidations; - i_popIncomingRequestQueue; - } - - transition({O, OO}, GETS, OO) { - f_forwardRequest; - n_incrementOutstanding; - i_popIncomingRequestQueue; - } - - transition(M, GETX, MM) { - f_forwardRequest; - i_popIncomingRequestQueue; - } - - transition(M, GETS, MO) { - f_forwardRequest; - i_popIncomingRequestQueue; - } - - transition(M, PUTX, MI) { - a_sendWriteBackAck; - i_popIncomingRequestQueue; - } - - // happens if M->O transition happens on-chip - transition(M, PUTO, MI) { - a_sendWriteBackAck; - i_popIncomingRequestQueue; - } - - transition(M, PUTO_SHARERS, MIS) { - a_sendWriteBackAck; - i_popIncomingRequestQueue; - } - - transition(O, PUTO, OS) { - a_sendWriteBackAck; - i_popIncomingRequestQueue; - } - - transition(O, PUTO_SHARERS, OSS) { - a_sendWriteBackAck; - i_popIncomingRequestQueue; - } - - - transition({MM, MO, MI, MIS, OS, OSS}, {GETS, GETX, PUTO, PUTO_SHARERS, PUTX}) { - zz_recycleRequest; - } - - transition({MM, MO}, Exclusive_Unblock, M) { - cc_clearSharers; - e_ownerIsUnblocker; - j_popIncomingUnblockQueue; - } - - transition(MO, Unblock, O) { - m_addUnlockerToSharers; - j_popIncomingUnblockQueue; - } - - transition({IS, SS, OO}, {GETX, PUTO, PUTO_SHARERS, PUTX}) { - zz_recycleRequest; - } - - transition(IS, GETS) { - zz_recycleRequest; - } - - transition(IS, Unblock, S) { - m_addUnlockerToSharers; - j_popIncomingUnblockQueue; - } - - transition(IS, Exclusive_Unblock, M) { - cc_clearSharers; - e_ownerIsUnblocker; - j_popIncomingUnblockQueue; - } - - transition(SS, Unblock) { - m_addUnlockerToSharers; - o_decrementOutstanding; - j_popIncomingUnblockQueue; - } - - transition(SS, Last_Unblock, S) { - m_addUnlockerToSharers; - o_decrementOutstanding; - j_popIncomingUnblockQueue; - } - - transition(OO, Unblock) { - m_addUnlockerToSharers; - o_decrementOutstanding; - j_popIncomingUnblockQueue; - } - - transition(OO, Last_Unblock, O) { - m_addUnlockerToSharers; - o_decrementOutstanding; - j_popIncomingUnblockQueue; - } - - transition(MI, Dirty_Writeback, I) { - c_clearOwner; - cc_clearSharers; - l_writeDataToMemory; - qw_queueMemoryWBRequest; - j_popIncomingUnblockQueue; - } - - transition(MIS, Dirty_Writeback, S) { - c_moveOwnerToSharer; - l_writeDataToMemory; - qw_queueMemoryWBRequest; - j_popIncomingUnblockQueue; - } - - transition(MIS, Clean_Writeback, S) { - c_moveOwnerToSharer; - j_popIncomingUnblockQueue; - } - - transition(OS, Dirty_Writeback, S) { - c_clearOwner; - l_writeDataToMemory; - qw_queueMemoryWBRequest; - j_popIncomingUnblockQueue; - } - - transition(OSS, Dirty_Writeback, S) { - c_moveOwnerToSharer; - l_writeDataToMemory; - qw_queueMemoryWBRequest; - j_popIncomingUnblockQueue; - } - - transition(OSS, Clean_Writeback, S) { - c_moveOwnerToSharer; - j_popIncomingUnblockQueue; - } - - transition(MI, Clean_Writeback, I) { - c_clearOwner; - cc_clearSharers; - ll_checkDataInMemory; - j_popIncomingUnblockQueue; - } - - transition(OS, Clean_Writeback, S) { - c_clearOwner; - ll_checkDataInMemory; - j_popIncomingUnblockQueue; - } - - transition({MI, MIS}, Unblock, M) { - j_popIncomingUnblockQueue; - } - - transition({OS, OSS}, Unblock, O) { - j_popIncomingUnblockQueue; - } - - transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS}, Memory_Data) { - d_sendDataMsg; - q_popMemQueue; - } - - transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS}, Memory_Ack) { - //a_sendAck; - q_popMemQueue; - } - -} diff --git a/src/mem/protocol/MOESI_CMP_directory_m.slicc b/src/mem/protocol/MOESI_CMP_directory_m.slicc deleted file mode 100644 index 3abe8603a..000000000 --- a/src/mem/protocol/MOESI_CMP_directory_m.slicc +++ /dev/null @@ -1,5 +0,0 @@ -MOESI_CMP_directory-msg.sm -MOESI_CMP_directory-L2cache.sm -MOESI_CMP_directory-L1cache.sm -MOESI_CMP_directory_m-dir.sm -standard_CMP-protocol.sm diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/protocol/RubySlicc_ComponentMapping.sm index 022bb6862..559e54a8c 100644 --- a/src/mem/protocol/RubySlicc_ComponentMapping.sm +++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm @@ -30,14 +30,11 @@ // Mapping functions // NodeID map_address_to_node(Address addr); +MachineID mapAddressToRange(Address addr, MachineType type, int low, int high); MachineID map_Address_to_DMA(Address addr); MachineID map_Address_to_Directory(Address addr); NodeID map_Address_to_DirectoryNode(Address addr); -MachineID map_Address_to_CentralArbiterNode(Address addr); -NodeID oldmap_L1RubyNode_to_L2Cache(Address addr, NodeID L1RubyNode); -MachineID map_L1CacheMachId_to_L2Cache(Address addr, MachineID L1CacheMachId); -MachineID map_L2ChipId_to_L2Cache(Address addr, NodeID L2ChipId); -// MachineID map_L1RubyNode_to_Arb(NodeID L1RubyNode); + MachineID getL1MachineID(NodeID L1RubyNode); NodeID getChipID(MachineID L2machID); diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index a8b58b96c..412fd0de0 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -39,7 +39,10 @@ external_type(string, primitive="yes"); external_type(uint64, primitive="yes"); external_type(Time, primitive="yes", default="0"); external_type(Address); - +external_type(DataBlock, desc="..."){ + void clear(); + void copyPartial(DataBlock, int, int); +} // Declarations of external types that are common to all protocols @@ -131,12 +134,12 @@ enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") { IO, desc="I/O"; REPLACEMENT, desc="Replacement"; COMMIT, desc="Commit version"; - LD_XACT, desc="Transactional Load"; - LDX_XACT, desc="Transactional Load-Intend-To-Modify"; - ST_XACT, desc="Transactional Store"; - BEGIN_XACT, desc="Begin Transaction"; - COMMIT_XACT, desc="Commit Transaction"; - ABORT_XACT, desc="Abort Transaction"; + NULL, desc="Invalid request type"; +} + +enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") { + LD, desc="Load"; + ST, desc="Store"; NULL, desc="Invalid request type"; } @@ -167,7 +170,9 @@ enumeration(GenericRequestType, desc="...", default="GenericRequestType_NULL") { ST_XACT, desc="Transactional Store"; BEGIN_XACT, desc="Begin Transaction"; COMMIT_XACT, desc="Commit Transaction"; - ABORT_XACT, desc="Abort Transaction"; + ABORT_XACT, desc="Abort Transaction"; + DMA_READ, desc="DMA READ"; + DMA_WRITE, desc="DMA WRITE"; NULL, desc="null request type"; } @@ -232,6 +237,18 @@ structure(CacheMsg, desc="...", interface="Message") { PrefetchBit Prefetch, desc="Is this a prefetch request"; } +// CacheMsg +structure(SequencerMsg, desc="...", interface="Message") { + Address LineAddress, desc="Line address for this request"; + Address PhysicalAddress, desc="Physical address for this request"; + SequencerRequestType Type, desc="Type of request (LD, ST, etc)"; + Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; + AccessModeType AccessMode, desc="user/supervisor access type"; + DataBlock DataBlk, desc="Data"; + int Len, desc="size in bytes of access"; + PrefetchBit Prefetch, desc="Is this a prefetch request"; +} + // MaskPredictorType enumeration(MaskPredictorType, "MaskPredictorType_Undefined", desc="...") { Undefined, desc="Undefined"; diff --git a/src/mem/protocol/RubySlicc_Profiler.sm b/src/mem/protocol/RubySlicc_Profiler.sm index 7a7fbdae1..d360af160 100644 --- a/src/mem/protocol/RubySlicc_Profiler.sm +++ b/src/mem/protocol/RubySlicc_Profiler.sm @@ -34,7 +34,7 @@ void profileCacheCLBsize(int size, int numStaleI); void profileMemoryCLBsize(int size, int numStaleI); // used by 2level exclusive cache protocols -void profile_miss(CacheMsg msg, NodeID id); +void profile_miss(CacheMsg msg); // used by non-fast path protocols void profile_L1Cache_miss(CacheMsg msg, NodeID l1cacheID); diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index aa5648a9e..9679b7b6f 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -29,11 +29,6 @@ // External Types -external_type(DataBlock, desc="..."){ - void clear(); - void copyPartial(DataBlock, int, int); -} - external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes"); external_type(OutPort, primitive="yes"); diff --git a/src/mem/protocol/RubySlicc_Util.sm b/src/mem/protocol/RubySlicc_Util.sm index 7f7ebf5ed..b37725402 100644 --- a/src/mem/protocol/RubySlicc_Util.sm +++ b/src/mem/protocol/RubySlicc_Util.sm @@ -57,5 +57,5 @@ int N_tokens(); bool distributedPersistentEnabled(); Address setOffset(Address addr, int offset); Address makeLineAddress(Address addr); - +int addressOffset(Address addr); diff --git a/src/mem/protocol/SConscript b/src/mem/protocol/SConscript index 9630c685a..293346f13 100644 --- a/src/mem/protocol/SConscript +++ b/src/mem/protocol/SConscript @@ -61,7 +61,7 @@ def slicc_generator(target, source, env, for_signature): if not isdir(hdir): os.mkdir(hdir) - do_html = "no_html" + do_html = "html" cmdline = [ slicc_bin, pdir, hdir, protocol, do_html ] cmdline += [ str(s) for s in source[2:] ] cmdline = ' '.join(cmdline) diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb index d43e384e5..2b416e647 100644 --- a/src/mem/ruby/config/MI_example-homogeneous.rb +++ b/src/mem/ruby/config/MI_example-homogeneous.rb @@ -8,20 +8,27 @@ require "cfg.rb" +RubySystem.reset + # default values num_cores = 2 -L1_CACHE_SIZE_KB = 32 -L1_CACHE_ASSOC = 8 -L1_CACHE_LATENCY = 1 +l1_cache_size_kb = 32 +l1_cache_assoc = 8 +l1_cache_latency = 1 num_memories = 2 memory_size_mb = 1024 -NUM_DMA = 1 +num_dma = 1 +protocol = "MI_example" # check for overrides + for i in 0..$*.size-1 do - if $*[i] == "-p" + if $*[i] == "-c" + protocol = $*[i+1] + i = i+1 + elsif $*[i] == "-p" num_cores = $*[i+1].to_i i = i+1 elsif $*[i] == "-m" @@ -36,13 +43,17 @@ end net_ports = Array.new iface_ports = Array.new +assert(protocol == "MI_example", __FILE__ + " cannot be used with protocol " + protocol) + +require protocol+".rb" + num_cores.times { |n| - cache = SetAssociativeCache.new("l1u_"+n.to_s, L1_CACHE_SIZE_KB, L1_CACHE_LATENCY, L1_CACHE_ASSOC, "PSEUDO_LRU") + cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_kb, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU") sequencer = Sequencer.new("Sequencer_"+n.to_s, cache, cache) iface_ports << sequencer net_ports << MI_example_CacheController.new("L1CacheController_"+n.to_s, "L1Cache", - [cache], + cache, sequencer) } num_memories.times { |n| @@ -52,10 +63,10 @@ num_memories.times { |n| "Directory", directory, memory_control) } -NUM_DMA.times { |n| +num_dma.times { |n| dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s) iface_ports << dma_sequencer - net_ports << DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer) + net_ports << MI_example_DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer) } topology = CrossbarTopology.new("theTopology", net_ports) diff --git a/src/mem/ruby/config/MI_example.rb b/src/mem/ruby/config/MI_example.rb new file mode 100644 index 000000000..187dc7a68 --- /dev/null +++ b/src/mem/ruby/config/MI_example.rb @@ -0,0 +1,39 @@ + +require "util.rb" + +class MI_example_CacheController < L1CacheController + attr :cache + def initialize(obj_name, mach_type, cache, sequencer) + super(obj_name, mach_type, [cache], sequencer) + @cache = cache + end + def argv() + vec = super() + vec += " cache " + @cache.obj_name + vec += " issue_latency "+issue_latency.to_s + vec += " cache_response_latency "+cache_response_latency.to_s + end + +end + +class MI_example_DirectoryController < DirectoryController + def initialize(obj_name, mach_type, directory, memory_control) + super(obj_name, mach_type, directory, memory_control) + end + def argv() + vec = super() + vec += " directory_latency "+directory_latency.to_s + vec += " dma_select_low_bit "+log_int(RubySystem.block_size_bytes).to_s + vec += " dma_select_num_bits "+log_int(NetPort.totalOfType("DMA")).to_s + end +end + +class MI_example_DMAController < DMAController + def initialize(obj_name, mach_type, dma_sequencer) + super(obj_name, mach_type, dma_sequencer) + end + def argv() + vec = super + vec += " request_latency "+request_latency.to_s + end +end diff --git a/src/mem/ruby/config/MOESI_CMP_directory.rb b/src/mem/ruby/config/MOESI_CMP_directory.rb new file mode 100644 index 000000000..1e8a82fab --- /dev/null +++ b/src/mem/ruby/config/MOESI_CMP_directory.rb @@ -0,0 +1,69 @@ + +require "cfg.rb" +require "util.rb" + + +class MOESI_CMP_directory_L1CacheController < L1CacheController + attr :icache, :dcache + attr :num_l2_controllers + def initialize(obj_name, mach_type, icache, dcache, sequencer, num_l2_controllers) + super(obj_name, mach_type, [icache, dcache], sequencer) + @icache = icache + @dcache = dcache + @num_l2_controllers = num_l2_controllers + end + def argv() + num_select_bits = log_int(num_l2_controllers) + num_block_bits = log_int(RubySystem.block_size_bytes) + + l2_select_low_bit = num_block_bits + + vec = super() + vec += " icache " + @icache.obj_name + vec += " dcache " + @dcache.obj_name + vec += " request_latency "+request_latency().to_s + vec += " l2_select_low_bit " + l2_select_low_bit.to_s + vec += " l2_select_num_bits " + num_select_bits.to_s + return vec + end +end + +class MOESI_CMP_directory_L2CacheController < CacheController + attr :cache + def initialize(obj_name, mach_type, cache) + super(obj_name, mach_type, [cache]) + @cache = cache + end + def argv() + vec = super() + vec += " cache " + @cache.obj_name + vec += " request_latency "+request_latency().to_s + vec += " response_latency "+response_latency().to_s + return vec + end +end + + +class MOESI_CMP_directory_DirectoryController < DirectoryController + def initialize(obj_name, mach_type, directory, memory_control) + super(obj_name, mach_type, directory, memory_control) + end + def argv() + vec = super() + vec += " directory_latency "+directory_latency.to_s + return vec + end + +end + +class MOESI_CMP_directory_DMAController < DMAController + def initialize(obj_name, mach_type, dma_sequencer) + super(obj_name, mach_type, dma_sequencer) + end + def argv() + vec = super + vec += " request_latency "+request_latency.to_s + vec += " response_latency "+response_latency.to_s + return vec + end +end diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb new file mode 100644 index 000000000..8a202d450 --- /dev/null +++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb @@ -0,0 +1,100 @@ +#!/usr/bin/ruby +# +# Creates a homogeneous CMP system with a single unified cache per +# core and a crossbar network. Uses the default parameters listed +# below, which can be overridden using command line args. +# + +require "cfg.rb" + +RubySystem.reset + +# default values + +num_cores = 2 +l1_icache_size_kb = 32 +l1_icache_assoc = 8 +l1_icache_latency = 1 +l1_dcache_size_kb = 32 +l1_dcache_assoc = 8 +l1_dcache_latency = 1 +l2_cache_size_kb = 2048 # total size (sum of all banks) +l2_cache_assoc = 16 +l2_cache_latency = 12 +num_l2_banks = num_cores +num_memories = 1 +memory_size_mb = 1024 +num_dma = 1 + +protocol = "MOESI_CMP_directory" + +# check for overrides + +for i in 0..$*.size-1 do + if $*[i] == "-c" or $*[i] == "--protocol" + i += 1 + protocol = $*[i] + elsif $*[i] == "-m" + num_memories = $*[i+1].to_i + i = i+1 + elsif $*[i] == "-p" + num_cores = $*[i+1].to_i + i = i+1 + elsif $*[i] == "-s" + memory_size_mb = $*[i+1].to_i + i = i + 1 + end +end + +net_ports = Array.new +iface_ports = Array.new + +assert(protocol == "MOESI_CMP_directory", __FILE__+" cannot be used with protocol "+protocol); + +require protocol+".rb" + +num_cores.times { |n| + icache = SetAssociativeCache.new("l1i_"+n.to_s, l1_icache_size_kb, l1_icache_latency, l1_icache_assoc, "PSEUDO_LRU") + dcache = SetAssociativeCache.new("l1d_"+n.to_s, l1_dcache_size_kb, l1_dcache_latency, l1_dcache_assoc, "PSEUDO_LRU") + sequencer = Sequencer.new("Sequencer_"+n.to_s, icache, dcache) + iface_ports << sequencer + if protocol == "MOESI_CMP_directory" + net_ports << MOESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s, + "L1Cache", + icache, dcache, + sequencer, + num_l2_banks) + end +} +num_l2_banks.times { |n| + cache = SetAssociativeCache.new("l2u_"+n.to_s, l2_cache_size_kb/num_l2_banks, l2_cache_latency, l2_cache_assoc, "PSEUDO_LRU") + if protocol == "MOESI_CMP_directory" + net_ports << MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s, + "L2Cache", + cache) + end +} +num_memories.times { |n| + directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories) + memory_control = MemoryControl.new("MemoryControl_"+n.to_s) + if protocol == "MOESI_CMP_directory" + net_ports << MOESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s, + "Directory", + directory, + memory_control) + end +} +num_dma.times { |n| + dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s) + iface_ports << dma_sequencer + if protocol == "MOESI_CMP_directory" + net_ports << MOESI_CMP_directory_DMAController.new("DMAController_"+n.to_s, + "DMA", + dma_sequencer) + end +} + +topology = CrossbarTopology.new("theTopology", net_ports) +on_chip_net = Network.new("theNetwork", topology) + +RubySystem.init(iface_ports, on_chip_net) diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb index a43b5e125..ffc36dd67 100644 --- a/src/mem/ruby/config/cfg.rb +++ b/src/mem/ruby/config/cfg.rb @@ -150,6 +150,9 @@ class NetPort < LibRubyObject def cppClassName "NetPort" end + def self.totalOfType(mach_type) + return @@type_cnt[mach_type] + end end class MemoryVector < LibRubyObject @@ -190,6 +193,7 @@ end class RubySystem @@params = Hash.new + @@defaults = Hash.new @@network = nil def self.init(iface_ports, network) @@ -197,6 +201,14 @@ class RubySystem @@network = network end + def self.reset() + @@iface_ports = nil + @@network = nil + @@params.each { |param_name, param| + param = @@defaults[param_name] + } + end + def self.default_param(param_name, type, default) if default.is_a?(FalseClass) || default.is_a?(TrueClass) assert type.is_a?(Boolean), "default value of param \"#{param_name}\" must be either true or false" @@ -204,6 +216,7 @@ class RubySystem assert default.is_a?(type), "default value of param \"#{param_name}\" does not match type #{type}" end @@params[param_name] = default + @@defaults[param_name] = default method_name = (param_name.to_s).to_sym instance_eval <<-EOS def #{method_name.to_s} @@ -233,6 +246,7 @@ class RubySystem end } str += LibRubyObject.printConstructors + #puts str.gsub('%',' ').gsub('#','\n') return str end @@ -287,35 +301,33 @@ end class CacheController < NetPort - @@total_cache_controllers = 0 - attr :caches - attr :sequencer - def initialize(obj_name, mach_type, caches, sequencer) + @@total_cache_controllers = Hash.new + + def initialize(obj_name, mach_type, caches) super(obj_name, mach_type) - @caches = caches - @caches.each { |cache| + caches.each { |cache| cache.controller = self } - @sequencer = sequencer - @sequencer.controller = self - - @version = @@total_cache_controllers - @@total_cache_controllers += 1 - @sequencer.version = @version - buffer_size() + if !@@total_cache_controllers.has_key?(mach_type) + @@total_cache_controllers[mach_type] = 0 + end + @version = @@total_cache_controllers[mach_type] + @@total_cache_controllers[mach_type] += 1 + + # call inhereted parameters + transitions_per_cycle + buffer_size + number_of_TBEs + recycle_latency end def argv() vec = "version "+@version.to_s - @caches.each { |cache| - vec += " cache " + cache.obj_name - } - vec += " sequencer "+@sequencer.obj_name vec += " transitions_per_cycle "+@params[:transitions_per_cycle].to_s vec += " buffer_size "+@params[:buffer_size].to_s vec += " number_of_TBEs "+@params[:number_of_TBEs].to_s - + vec += " recycle_latency "+@params[:recycle_latency].to_s end def cppClassName() @@ -323,6 +335,23 @@ class CacheController < NetPort end end +class L1CacheController < CacheController + attr :sequencer + + def initialize(obj_name, mach_type, caches, sequencer) + super(obj_name, mach_type, caches) + + @sequencer = sequencer + @sequencer.controller = self + @sequencer.version = @version + end + + def argv() + vec = super() + vec += " sequencer "+@sequencer.obj_name + end +end + class DirectoryController < NetPort @@total_directory_controllers = 0 attr :directory @@ -364,7 +393,7 @@ class DMAController < NetPort end def argv() - "version "+@version.to_s+" dma_sequencer "+@dma_sequencer.obj_name+" transitions_per_cycle "+@params[:transitions_per_cycle].to_s + " buffer_size "+@params[:buffer_size].to_s + " number_of_TBEs "+@params[:number_of_TBEs].to_s + "version "+@version.to_s+" dma_sequencer "+@dma_sequencer.obj_name+" transitions_per_cycle "+@params[:transitions_per_cycle].to_s + " buffer_size "+@params[:buffer_size].to_s + " number_of_TBEs "+@params[:number_of_TBEs].to_s + " recycle_latency "+@params[:recycle_latency].to_s end def cppClassName() @@ -606,7 +635,7 @@ class Network < LibRubyObject end def printTopology() - topology.printFile + topology().printFile end def cppClassName() "SimpleNetwork" @@ -686,31 +715,6 @@ class Profiler < LibRubyObject end -class MI_example_CacheController < CacheController - def initialize(obj_name, mach_type, caches, sequencer) - super(obj_name, mach_type, caches, sequencer) - end - def argv() - vec = super() - vec += " issue_latency "+issue_latency.to_s - vec += " cache_response_latency "+cache_response_latency.to_s - end - -end - -class MI_example_DirectoryController < DirectoryController - def initialize(obj_name, mach_type, directory, memory_control) - super(obj_name, mach_type, directory, memory_control) - end - def argv() - vec = super() - vec += " to_mem_ctrl_latency "+to_mem_ctrl_latency.to_s - vec += " directory_latency "+directory_latency.to_s - vec += " memory_latency "+memory_latency.to_s - end - -end - #added by SS class GarnetNetwork < Network def initialize(name, topo) diff --git a/src/mem/ruby/config/defaults.rb b/src/mem/ruby/config/defaults.rb index e54b148e0..4723df505 100644 --- a/src/mem/ruby/config/defaults.rb +++ b/src/mem/ruby/config/defaults.rb @@ -106,19 +106,6 @@ class Profiler < LibRubyObject end #added by SS -class MI_example_CacheController < CacheController - default_param :issue_latency, Integer, 2 - default_param :cache_response_latency, Integer, 12 -end - -class MI_example_DirectoryController < DirectoryController - default_param :to_mem_ctrl_latency, Integer, 1 - default_param :directory_latency, Integer, 6 - default_param :memory_latency, Integer, 158 -end - - -#added by SS class MemoryControl < LibRubyObject default_param :mem_bus_cycle_multiplier, Integer, 10 @@ -141,6 +128,43 @@ class MemoryControl < LibRubyObject end +###### Protocols ####### + +## MI_example protocol + +class MI_example_CacheController < L1CacheController + default_param :issue_latency, Integer, 2 + default_param :cache_response_latency, Integer, 12 +end + +class MI_example_DirectoryController < DirectoryController + default_param :directory_latency, Integer, 6 +end + +class MI_example_DMAController < DMAController + default_param :request_latency, Integer, 6 +end + +## MOESI_CMP_directory protocol + +class MOESI_CMP_directory_L1CacheController < L1CacheController + default_param :request_latency, Integer, 2 +end + +class MOESI_CMP_directory_L2CacheController < CacheController + default_param :request_latency, Integer, 2 + default_param :response_latency, Integer, 2 +end + +class MOESI_CMP_directory_DirectoryController < DirectoryController + default_param :directory_latency, Integer, 6 +end + +class MOESI_CMP_directory_DMAController < DMAController + default_param :request_latency, Integer, 6 + default_param :response_latency, Integer, 6 +end + class RubySystem # Random seed used by the simulation. If set to "rand", the seed diff --git a/src/mem/ruby/config/util.rb b/src/mem/ruby/config/util.rb new file mode 100644 index 000000000..a6aa8f6ab --- /dev/null +++ b/src/mem/ruby/config/util.rb @@ -0,0 +1,10 @@ + +def log_int(n) + assert(n.is_a?(Fixnum), "log_int takes a number for an argument") + counter = 0 + while n >= 2 do + counter += 1 + n = n >> 1 + end + return counter +end diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh index cd3cdbe48..96405c8dd 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh @@ -85,6 +85,16 @@ MachineID map_Address_to_DMA(const Address & addr) return dma; } +inline +MachineID mapAddressToRange(const Address & addr, MachineType type, int low_bit, int num_bits) +{ + MachineID mach = {type, 0}; + if (num_bits == 0) + return mach; + mach.num = addr.bitSelect(low_bit, low_bit+num_bits-1); + return mach; +} + extern inline NodeID machineIDToNodeID(MachineID machID) { return machID.num; diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh index e4e20c99a..0ea5df08b 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh @@ -173,4 +173,9 @@ extern inline Address makeLineAddress(Address addr) return result; } +extern inline int addressOffset(Address addr) +{ + return addr.getOffset(); +} + #endif //SLICC_UTIL_H diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc index d29dba602..8af892007 100644 --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -4,9 +4,8 @@ #include "mem/ruby/slicc_interface/AbstractController.hh" /* SLICC generated types */ -#include "mem/protocol/DMARequestMsg.hh" -#include "mem/protocol/DMARequestType.hh" -#include "mem/protocol/DMAResponseMsg.hh" +#include "mem/protocol/SequencerMsg.hh" +#include "mem/protocol/SequencerRequestType.hh" #include "mem/ruby/system/System.hh" DMASequencer::DMASequencer(const string & name) @@ -66,20 +65,16 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request) active_request.bytes_issued = 0; active_request.id = makeUniqueRequestID(); - DMARequestMsg msg; + SequencerMsg msg; msg.getPhysicalAddress() = Address(paddr); msg.getLineAddress() = line_address(msg.getPhysicalAddress()); - msg.getType() = write ? DMARequestType_WRITE : DMARequestType_READ; - msg.getOffset() = paddr & m_data_block_mask; - msg.getLen() = (msg.getOffset() + len) <= RubySystem::getBlockSizeBytes() ? + msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; + int offset = paddr & m_data_block_mask; + msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? len : - RubySystem::getBlockSizeBytes() - msg.getOffset(); - if (write) { - msg.getType() = DMARequestType_WRITE; - msg.getDataBlk().setData(data, msg.getOffset(), msg.getLen()); - } else { - msg.getType() = DMARequestType_READ; - } + RubySystem::getBlockSizeBytes() - offset; + if (write) + msg.getDataBlk().setData(data, offset, msg.getLen()); m_mandatory_q_ptr->enqueue(msg); active_request.bytes_issued += msg.getLen(); @@ -96,14 +91,13 @@ void DMASequencer::issueNext() return; } - DMARequestMsg msg; + SequencerMsg msg; msg.getPhysicalAddress() = Address(active_request.start_paddr + active_request.bytes_completed); assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0); msg.getLineAddress() = line_address(msg.getPhysicalAddress()); - msg.getOffset() = 0; - msg.getType() = (active_request.write ? DMARequestType_WRITE : - DMARequestType_READ); + msg.getType() = (active_request.write ? SequencerRequestType_ST : + SequencerRequestType_LD); msg.getLen() = (active_request.len - active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? active_request.len - active_request.bytes_completed : @@ -111,9 +105,9 @@ void DMASequencer::issueNext() if (active_request.write) { msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], 0, msg.getLen()); - msg.getType() = DMARequestType_WRITE; + msg.getType() = SequencerRequestType_ST; } else { - msg.getType() = DMARequestType_READ; + msg.getType() = SequencerRequestType_LD; } m_mandatory_q_ptr->enqueue(msg); active_request.bytes_issued += msg.getLen(); diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc index b279d21af..c87be94a2 100644 --- a/src/mem/ruby/system/DirectoryMemory.cc +++ b/src/mem/ruby/system/DirectoryMemory.cc @@ -58,12 +58,14 @@ void DirectoryMemory::init(const vector<string> & argv) if ( (*it) == "version" ) m_version = atoi( (*(++it)).c_str() ); else if ( (*it) == "size_mb" ) { - m_size_bytes = atoi((*(++it)).c_str()) * (1<<20); + m_size_bytes = atoi((*(++it)).c_str()) * static_cast<uint64>(1<<20); m_size_bits = log_int(m_size_bytes); } else if ( (*it) == "controller" ) { m_controller = RubySystem::getController((*(++it))); - } else + } else { + cerr << "DirectoryMemory: Unkown config parameter: " << (*it) << endl; assert(0); + } } assert(m_controller != NULL); diff --git a/src/mem/ruby/system/DirectoryMemory.hh b/src/mem/ruby/system/DirectoryMemory.hh index 6445ecc62..39de679ed 100644 --- a/src/mem/ruby/system/DirectoryMemory.hh +++ b/src/mem/ruby/system/DirectoryMemory.hh @@ -59,7 +59,7 @@ public: int mapAddressToLocalIdx(PhysAddress address); static int mapAddressToDirectoryVersion(PhysAddress address); - int getSize() { return m_size_bytes; } + uint64 getSize() { return m_size_bytes; } // Public Methods void printConfig(ostream& out) const; @@ -84,8 +84,8 @@ private: // Data Members (m_ prefix) Directory_Entry **m_entries; // int m_size; // # of memory module blocks this directory is responsible for - uint32 m_size_bytes; - uint32 m_size_bits; + uint64 m_size_bytes; + uint64 m_size_bits; int m_num_entries; int m_version; diff --git a/src/mem/ruby/system/PerfectCacheMemory.hh b/src/mem/ruby/system/PerfectCacheMemory.hh index 90c9273e5..6561d028b 100644 --- a/src/mem/ruby/system/PerfectCacheMemory.hh +++ b/src/mem/ruby/system/PerfectCacheMemory.hh @@ -43,7 +43,6 @@ #include "mem/gems_common/Map.hh" #include "mem/protocol/AccessPermission.hh" #include "mem/ruby/common/Address.hh" -#include "mem/ruby/slicc_interface/AbstractChip.hh" template<class ENTRY> class PerfectCacheLineState { @@ -54,11 +53,18 @@ public: }; template<class ENTRY> +extern inline +ostream& operator<<(ostream& out, const PerfectCacheLineState<ENTRY>& obj) +{ + return out; +} + +template<class ENTRY> class PerfectCacheMemory { public: // Constructors - PerfectCacheMemory(AbstractChip* chip_ptr); + PerfectCacheMemory(); // Destructor //~PerfectCacheMemory(); @@ -106,7 +112,6 @@ private: // Data Members (m_prefix) Map<Address, PerfectCacheLineState<ENTRY> > m_map; - AbstractChip* m_chip_ptr; }; // Output operator declaration @@ -129,9 +134,8 @@ ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj) template<class ENTRY> extern inline -PerfectCacheMemory<ENTRY>::PerfectCacheMemory(AbstractChip* chip_ptr) +PerfectCacheMemory<ENTRY>::PerfectCacheMemory() { - m_chip_ptr = chip_ptr; } // STATIC METHODS diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh index dbf4dbc78..38ef09177 100644 --- a/src/mem/ruby/system/System.hh +++ b/src/mem/ruby/system/System.hh @@ -104,6 +104,9 @@ public: static RubyPort* getPortOnly(const string & name) { assert(m_ports.count(name) == 1); return m_ports[name]; } static RubyPort* getPort(const string & name, void (*hit_callback)(int64_t)) { + if (m_ports.count(name) != 1){ + cerr << "Port " << name << " has " << m_ports.count(name) << " instances" << endl; + } assert(m_ports.count(name) == 1); m_ports[name]->registerHitCallback(hit_callback); return m_ports[name]; } static Network* getNetwork() { assert(m_network_ptr != NULL); return m_network_ptr; } static Topology* getTopology(const string & name) { assert(m_topologies.count(name) == 1); return m_topologies[name]; } diff --git a/src/mem/ruby/system/TimerTable.cc b/src/mem/ruby/system/TimerTable.cc index edc2de230..5d496da04 100644 --- a/src/mem/ruby/system/TimerTable.cc +++ b/src/mem/ruby/system/TimerTable.cc @@ -35,11 +35,9 @@ #include "mem/ruby/system/TimerTable.hh" #include "mem/ruby/eventqueue/RubyEventQueue.hh" -TimerTable::TimerTable(Chip* chip_ptr) +TimerTable::TimerTable() { - assert(chip_ptr != NULL); m_consumer_ptr = NULL; - m_chip_ptr = chip_ptr; m_next_valid = false; m_next_address = Address(0); m_next_time = 0; diff --git a/src/mem/ruby/system/TimerTable.hh b/src/mem/ruby/system/TimerTable.hh index 9912036f3..eda84069d 100644 --- a/src/mem/ruby/system/TimerTable.hh +++ b/src/mem/ruby/system/TimerTable.hh @@ -43,13 +43,12 @@ #include "mem/gems_common/Map.hh" #include "mem/ruby/common/Address.hh" class Consumer; -class Chip; class TimerTable { public: // Constructors - TimerTable(Chip* chip_ptr); + TimerTable(); // Destructor //~TimerTable(); @@ -77,7 +76,6 @@ private: // Data Members (m_prefix) Map<Address, Time> m_map; - Chip* m_chip_ptr; mutable bool m_next_valid; mutable Time m_next_time; // Only valid if m_next_valid is true mutable Address m_next_address; // Only valid if m_next_valid is true diff --git a/src/mem/slicc/ast/AST.hh b/src/mem/slicc/ast/AST.hh index 53f9a6c33..33c9b84ed 100644 --- a/src/mem/slicc/ast/AST.hh +++ b/src/mem/slicc/ast/AST.hh @@ -50,28 +50,28 @@ public: // Constructors AST(Map<string, string> pairs) { m_pairs = pairs; }; AST() {}; - + // Destructor virtual ~AST() {}; - + // Public Methods virtual void print(ostream& out) const = 0; void error(string err_msg) const { m_location.error(err_msg); }; string embedError(string err_msg) const { return m_location.embedError(err_msg); }; void warning(string err_msg) const { m_location.warning(err_msg); }; - + const Location& getLocation() const { return m_location; }; - + const Map<string, string>& getPairs() const { return m_pairs; }; Map<string, string>& getPairs() { return m_pairs; }; - + private: // Private Methods - + // Private copy constructor and assignment operator // AST(const AST& obj); // AST& operator=(const AST& obj); - + // Data Members (m_ prefix) Location m_location; Map<string, string> m_pairs; diff --git a/src/mem/slicc/ast/ActionDeclAST.cc b/src/mem/slicc/ast/ActionDeclAST.cc index 2734722d1..e46412ff7 100644 --- a/src/mem/slicc/ast/ActionDeclAST.cc +++ b/src/mem/slicc/ast/ActionDeclAST.cc @@ -36,8 +36,10 @@ * */ + #include "mem/slicc/ast/ActionDeclAST.hh" #include "mem/slicc/symbols/Action.hh" +#include "mem/slicc/ast/StatementListAST.hh" ActionDeclAST::ActionDeclAST(string* ident_ptr, PairListAST* pairs_ptr, diff --git a/src/mem/slicc/ast/ActionDeclAST.hh b/src/mem/slicc/ast/ActionDeclAST.hh index 53d938ca8..4970ee254 100644 --- a/src/mem/slicc/ast/ActionDeclAST.hh +++ b/src/mem/slicc/ast/ActionDeclAST.hh @@ -41,7 +41,8 @@ #include "mem/slicc/slicc_global.hh" #include "mem/slicc/ast/DeclAST.hh" -#include "mem/slicc/ast/StatementListAST.hh" + +class StatementListAST; class ActionDeclAST : public DeclAST { public: diff --git a/src/mem/slicc/ast/EnqueueStatementAST.cc b/src/mem/slicc/ast/EnqueueStatementAST.cc index 8be0378c9..a422d8a28 100644 --- a/src/mem/slicc/ast/EnqueueStatementAST.cc +++ b/src/mem/slicc/ast/EnqueueStatementAST.cc @@ -77,7 +77,14 @@ void EnqueueStatementAST::generate(string& code, Type* return_type_ptr) const code += ".enqueue(out_msg"; if (getPairs().exist("latency")) { - code += ", m_LATENCY_" + getPairs().lookup("latency"); + bool is_number = true; + string val = getPairs().lookup("latency"); + for (int i=0; i<val.size(); i++) + if (!isdigit(val[i])) is_number = false; + if (is_number) + code += ", " + getPairs().lookup("latency"); + else + code += ", m_" + getPairs().lookup("latency"); } code += ");\n"; diff --git a/src/mem/slicc/ast/FormalParamAST.cc b/src/mem/slicc/ast/FormalParamAST.cc index 4ca2c8978..529811f25 100644 --- a/src/mem/slicc/ast/FormalParamAST.cc +++ b/src/mem/slicc/ast/FormalParamAST.cc @@ -38,6 +38,7 @@ #include "mem/slicc/ast/FormalParamAST.hh" #include "mem/slicc/ast/StatementAST.hh" +#include "mem/slicc/ast/TypeAST.hh" #include "mem/slicc/symbols/SymbolTable.hh" FormalParamAST::~FormalParamAST() @@ -46,6 +47,16 @@ FormalParamAST::~FormalParamAST() delete m_type_ast_ptr; } +string FormalParamAST::getTypeName() const +{ + return m_type_ast_ptr->toString(); +} + +Type* FormalParamAST::getType() const +{ + return m_type_ast_ptr->lookupType(); +} + Type* FormalParamAST::generate(string& code) const { string param = "param_" + *m_ident_ptr; diff --git a/src/mem/slicc/ast/FormalParamAST.hh b/src/mem/slicc/ast/FormalParamAST.hh index 63d66cc03..ca27948b7 100644 --- a/src/mem/slicc/ast/FormalParamAST.hh +++ b/src/mem/slicc/ast/FormalParamAST.hh @@ -40,7 +40,9 @@ #define FORMALPARAMAST_H #include "mem/slicc/slicc_global.hh" -#include "mem/slicc/ast/TypeAST.hh" +#include "mem/slicc/ast/AST.hh" + +class TypeAST; class FormalParamAST : public AST { @@ -55,6 +57,8 @@ public: Type* generate(string& code) const; void print(ostream& out) const { out << "[FormalParamAST: " << *m_ident_ptr << "]"; } string getName() const { return *m_ident_ptr; } + string getTypeName() const; + Type* getType() const; private: // Private Methods diff --git a/src/mem/slicc/ast/FuncDeclAST.cc b/src/mem/slicc/ast/FuncDeclAST.cc index 7fb0e6346..2a0905f06 100644 --- a/src/mem/slicc/ast/FuncDeclAST.cc +++ b/src/mem/slicc/ast/FuncDeclAST.cc @@ -37,6 +37,7 @@ */ #include "mem/slicc/ast/FuncDeclAST.hh" +#include "mem/slicc/ast/FormalParamAST.hh" #include "mem/slicc/symbols/SymbolTable.hh" #include "mem/slicc/main.hh" diff --git a/src/mem/slicc/ast/FuncDeclAST.hh b/src/mem/slicc/ast/FuncDeclAST.hh index d60694303..205e71a85 100644 --- a/src/mem/slicc/ast/FuncDeclAST.hh +++ b/src/mem/slicc/ast/FuncDeclAST.hh @@ -43,7 +43,8 @@ #include "mem/slicc/ast/DeclAST.hh" #include "mem/slicc/ast/TypeFieldAST.hh" #include "mem/slicc/ast/TypeAST.hh" -#include "mem/slicc/ast/FormalParamAST.hh" + +class FormalParamsAST; class FuncDeclAST : public DeclAST { public: diff --git a/src/mem/slicc/ast/MachineAST.cc b/src/mem/slicc/ast/MachineAST.cc index 2096db591..ae8026458 100644 --- a/src/mem/slicc/ast/MachineAST.cc +++ b/src/mem/slicc/ast/MachineAST.cc @@ -37,21 +37,20 @@ */ #include "mem/slicc/ast/MachineAST.hh" +#include "mem/slicc/ast/FormalParamAST.hh" #include "mem/slicc/symbols/SymbolTable.hh" MachineAST::MachineAST(string* ident_ptr, PairListAST* pairs_ptr, - Vector<TypeFieldAST*>* config_params_ptr, - std::vector<std::string*>* latency_vector, + Vector<FormalParamAST*>* config_parameters, DeclListAST* decl_list_ptr) : DeclAST(pairs_ptr) { m_ident_ptr = ident_ptr; m_pairs_ptr = pairs_ptr; - m_config_params_ptr = config_params_ptr; + m_config_parameters = config_parameters; m_decl_list_ptr = decl_list_ptr; - m_latency_vector = latency_vector; } MachineAST::~MachineAST() @@ -69,7 +68,7 @@ void MachineAST::generate() g_sym_table.pushFrame(); // Create a new machine - machine_ptr = new StateMachine(*m_ident_ptr, getLocation(), getPairs(), m_latency_vector); + machine_ptr = new StateMachine(*m_ident_ptr, getLocation(), getPairs(), m_config_parameters); g_sym_table.newCurrentMachine(machine_ptr); // Generate code for all the internal decls diff --git a/src/mem/slicc/ast/MachineAST.hh b/src/mem/slicc/ast/MachineAST.hh index 8f83e4cfe..5d1bc2a1c 100644 --- a/src/mem/slicc/ast/MachineAST.hh +++ b/src/mem/slicc/ast/MachineAST.hh @@ -45,13 +45,14 @@ #include "mem/slicc/ast/TypeFieldAST.hh" #include "mem/slicc/symbols/StateMachine.hh" +class FormalParamAST; + class MachineAST : public DeclAST { public: // Constructors MachineAST(string* ident_ptr, PairListAST* pairs_ptr, - Vector<TypeFieldAST*>* config_params_ptr, - std::vector<std::string*>* latency_vector, + Vector<FormalParamAST*>* config_parameters, DeclListAST* decl_list_ptr); // Destructor @@ -69,10 +70,9 @@ private: MachineAST& operator=(const MachineAST& obj); // Data Members (m_ prefix) - std::vector<std::string*>* m_latency_vector; + Vector<FormalParamAST*>* m_config_parameters; string* m_ident_ptr; DeclListAST* m_decl_list_ptr; - Vector<TypeFieldAST*>* m_config_params_ptr; PairListAST* m_pairs_ptr; }; diff --git a/src/mem/slicc/parser/parser.py b/src/mem/slicc/parser/parser.py index c042ba2c1..7fecfd273 100644 --- a/src/mem/slicc/parser/parser.py +++ b/src/mem/slicc/parser/parser.py @@ -76,7 +76,7 @@ tokens = [ 'EQ', 'NE', 'LT', 'GT', 'LE', 'GE', 'NOT', 'AND', 'OR', 'PLUS', 'DASH', 'STAR', 'SLASH', 'DOUBLE_COLON', 'SEMICOLON', - 'ASSIGN', 'DOT', 'LATENCY', + 'ASSIGN', 'DOT', 'IDENT', 'LIT_BOOL', 'FLOATNUMBER', 'NUMBER', 'STRING' ] tokens += reserved.values() @@ -197,19 +197,8 @@ def p_decl(p): | d_func_def""" p[0] = p[1] -def p_latency(p): - """latency : LATENCY""" - pass - -def p_latencies(p): - """latencies : latency latencies - | empty""" - return [] - def p_d_machine(p): - """d_machine : MACHINE '(' ident pair_l ')' '{' decl_l '}' - | MACHINE '(' ident pair_l ')' ':' type_members '{' decl_l '}' - | MACHINE '(' ident pair_l ')' ':' latencies '{' decl_l '}'""" + """d_machine : MACHINE '(' ident pair_l ')' ':' param_l '{' decl_l '}'""" if len(p) == 9: decl_l = p[7] @@ -549,10 +538,11 @@ def scan(filenames): for filename in filenames: lex.lexer.lineno = 1 try: + print "parsing ",filename results = yacc.parse(file(filename, 'r').read()) except (TokenError, ParseError), e: sys.exit("%s: %s:%d" % (e, filename, e.token.lineno)) - + for result in results: result.add(hh, cc) diff --git a/src/mem/slicc/parser/parser.yy b/src/mem/slicc/parser/parser.yy index fa5a3b355..c8cef3b21 100644 --- a/src/mem/slicc/parser/parser.yy +++ b/src/mem/slicc/parser/parser.yy @@ -111,8 +111,6 @@ extern "C" int yylex(); %type <expr_ptr> expr literal enumeration %type <expr_vector_ptr> expr_list -%type <stdstring_vector_ptr> myrule - %type <pair_ptr> pair %type <pair_list_ptr> pair_list pairs @@ -148,9 +146,7 @@ decls: decl decls { $2->insertAtTop($1); $$ = $2; } | { $$ = new Vector<DeclAST*>; } ; -decl: MACHINE_DECL '(' ident pair_list ')' ':' myrule '{' decl_list '}' { $$ = new MachineAST($3, $4, NULL, $7, $9); } -// | MACHINE_DECL '(' ident pair_list ')' ':' type_members '{' decl_list '}' { $$ = new MachineAST($3, $4, $7, string_vector, $9); } - | MACHINE_DECL '(' ident pair_list ')' '{' decl_list '}' { $$ = new MachineAST($3, $4, NULL, new vector<string*>(), $7); } +decl: MACHINE_DECL '(' ident pair_list ')' ':' formal_param_list '{' decl_list '}' { $$ = new MachineAST($3, $4, $7, $9); } | ACTION_DECL '(' ident pair_list ')' statement_list { $$ = new ActionDeclAST($3, $4, $6); } | IN_PORT_DECL '(' ident ',' type ',' var pair_list ')' statement_list { $$ = new InPortDeclAST($3, $5, $7, $8, $10); } | OUT_PORT_DECL '(' ident ',' type ',' var pair_list ')' SEMICOLON { $$ = new OutPortDeclAST($3, $5, $7, $8); } @@ -336,10 +332,6 @@ var: ident { $$ = new VarExprAST($1); } field: ident { $$ = $1; } ; -myrule: myrule IDENT { $1->push_back($2); } - | IDENT { $$ = new vector<string*>(1, $1); } - ; - %% extern FILE *yyin; diff --git a/src/mem/slicc/symbols/StateMachine.cc b/src/mem/slicc/symbols/StateMachine.cc index 4a9ee3714..7bc84ffe0 100644 --- a/src/mem/slicc/symbols/StateMachine.cc +++ b/src/mem/slicc/symbols/StateMachine.cc @@ -43,14 +43,25 @@ #include "mem/slicc/symbols/SymbolTable.hh" #include "mem/gems_common/util.hh" #include "mem/gems_common/Vector.hh" +#include "mem/slicc/ast/FormalParamAST.hh" #include <set> -StateMachine::StateMachine(string ident, const Location& location, const Map<string, string>& pairs, std::vector<std::string*>* latency_vector) +StateMachine::StateMachine(string ident, const Location& location, const Map<string, string>& pairs, Vector<FormalParamAST*>* config_parameters) : Symbol(ident, location, pairs) { m_table_built = false; - m_latency_vector = *latency_vector; + m_config_parameters = config_parameters; + + for (int i=0; i< m_config_parameters->size(); i++) { + Var* var = new Var(m_config_parameters->ref(i)->getName(), + location, + m_config_parameters->ref(i)->getType(), + "m_"+m_config_parameters->ref(i)->getName(), + Map<string, string>(), + this); + g_sym_table.registerSym(m_config_parameters->ref(i)->getName(), var); + } } StateMachine::~StateMachine() @@ -284,9 +295,8 @@ void StateMachine::printControllerH(ostream& out, string component) out << "private:" << endl; //added by SS // found_to_mem = 0; - std::vector<std::string*>::const_iterator it; - for(it=m_latency_vector.begin();it!=m_latency_vector.end();it++){ - out << " int m_" << (*it)->c_str() << ";" << endl; + for(int i=0;i<m_config_parameters->size();i++){ + out << " int m_" << m_config_parameters->ref(i)->getName() << ";" << endl; } if (strncmp(component.c_str(), "L1Cache", 7) == 0) { out << " bool servicing_atomic;" << endl; @@ -429,41 +439,22 @@ void StateMachine::printControllerC(ostream& out, string component) out << " else if (argv[i] == \"number_of_TBEs\") " << endl; out << " m_number_of_TBEs = atoi(argv[i+1].c_str());" << endl; - if (m_latency_vector.size()) { - out << " else { " << endl; - std::vector<std::string*>::const_iterator it; - for(it=m_latency_vector.begin();it!=m_latency_vector.end();it++) { - string str = (*it)->c_str(); - str.erase(0,8); -//convert to lowercase - size_t i; - char* strc = (char*) malloc (str.length()+1); - strc[str.length()]=0; - for(i=0; i < str.length(); i++) { - strc[i] = str.at(i); - strc[i] = tolower(strc[i]); - } - str = strc; - delete strc; - out << " if (argv[i] == \"" << str << "\"){" << endl; - if (str == "to_mem_ctrl_latency") - out << " m_" << (*it)->c_str() << "=" << "atoi(argv[i+1].c_str())+(random() % 5);" << endl; + if (m_config_parameters->size()) { + for(int i= 0 ; i < m_config_parameters->size(); i++) { + out << " else if (argv[i] == \"" << m_config_parameters->ref(i)->getName() << "\")" << endl; + if (m_config_parameters->ref(i)->getTypeName() == "int") + out << " m_" << m_config_parameters->ref(i)->getName() << "=" << "atoi(argv[i+1].c_str());" << endl; else - out << " m_" << (*it)->c_str() << "=" << "atoi(argv[i+1].c_str());" << endl; -// out << " printf (\"SET m_" << it->c_str() << "= %i \\n \", m_" << it->c_str() << ");" << endl; - out << " }" << endl; + assert(0); // only int parameters are supported right now + // if (str == "to_mem_ctrl_latency") + // out << " m_" << (*it)->c_str() << "=" << "atoi(argv[i+1].c_str())+(random() % 5);" << endl; } - out << " }" << endl; } out << " }" << endl; - out << " m_net_ptr = net_ptr;" << endl; out << " m_machineID.type = MachineType_" << component << ";" << endl; out << " m_machineID.num = m_version;" << endl; -// out << " printf (\"I set m_LATENCY_ISSUE_LATENCY to %i \\n \", m_LATENCY_ISSUE_LATENCY);" << endl; -// out << " printf (\"I set m_LATENCY_CACHE_RESPONSE_LATENCY to %i \\n \", m_LATENCY_CACHE_RESPONSE_LATENCY);" << endl; - // make configuration array out << " for (size_t i=0; i < argv.size(); i+=2) {" << endl; out << " if (argv[i] != \"version\") " << endl; @@ -724,25 +715,7 @@ void StateMachine::printControllerC(ostream& out, string component) string c_code_string = action.lookupPair("c_code"); -/* - size_t found = c_code_string.find("RubyConfig::get"); - - if (found!=string::npos){ //found --> replace it with local access - //if it is related to latency --> replace it - std::vector<std::string*>::const_iterator it; - for(it=m_latency_vector.begin();it!=m_latency_vector.end();it++){ - string str = (*it)->c_str(); - str.erase(0,8); - size_t fd = c_code_string.find(str, found); - if (fd!=string::npos && (fd == found+15)){ - string rstr = "m_"; - rstr += (*it)->c_str(); - c_code_string.replace(found,15+str.size()+2,rstr); - break; - } - } - } -*/ + // add here: if (strncmp(component.c_str(), "L1Cache", 7) == 0) { if (c_code_string.find("writeCallback") != string::npos) { diff --git a/src/mem/slicc/symbols/StateMachine.hh b/src/mem/slicc/symbols/StateMachine.hh index 101e38547..f5f3ab073 100644 --- a/src/mem/slicc/symbols/StateMachine.hh +++ b/src/mem/slicc/symbols/StateMachine.hh @@ -49,11 +49,12 @@ class State; class Action; class Var; class Func; +class FormalParamAST; class StateMachine : public Symbol { public: // Constructors - StateMachine(string ident, const Location& location, const Map<string, string>& pairs, std::vector<std::string*>* latency_vector); + StateMachine(string ident, const Location& location, const Map<string, string>& pairs, Vector<FormalParamAST*>* config_parameters); // Destructor ~StateMachine(); @@ -94,7 +95,7 @@ public: void print(ostream& out) const { out << "[StateMachine: " << toString() << "]" << endl; } private: - std::vector<std::string*> m_latency_vector; + Vector<FormalParamAST*>* m_config_parameters; // Private Methods void checkForDuplicate(const Symbol& sym) const; diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index f8b15caeb..824e957e9 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -15,17 +15,19 @@ DMA_Controller config: DMAController_0 buffer_size: 32 dma_sequencer: DMASequencer_0 number_of_TBEs: 256 + recycle_latency: 10 + request_latency: 6 transitions_per_cycle: 32 Directory_Controller config: DirectoryController_0 version: 0 buffer_size: 32 directory_latency: 6 directory_name: DirectoryMemory_0 + dma_select_low_bit: 6 + dma_select_num_bits: 0 memory_controller_name: MemoryControl_0 - memory_latency: 1 number_of_TBEs: 256 recycle_latency: 10 - to_mem_ctrl_latency: 1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_0 version: 0 @@ -34,6 +36,7 @@ L1Cache_Controller config: L1CacheController_0 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_0 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_1 @@ -43,6 +46,7 @@ L1Cache_Controller config: L1CacheController_1 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_2 @@ -52,6 +56,7 @@ L1Cache_Controller config: L1CacheController_2 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_2 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_3 @@ -61,6 +66,7 @@ L1Cache_Controller config: L1CacheController_3 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_3 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_4 @@ -70,6 +76,7 @@ L1Cache_Controller config: L1CacheController_4 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_4 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_5 @@ -79,6 +86,7 @@ L1Cache_Controller config: L1CacheController_5 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_5 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_6 @@ -88,6 +96,7 @@ L1Cache_Controller config: L1CacheController_6 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_6 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_7 @@ -97,6 +106,7 @@ L1Cache_Controller config: L1CacheController_7 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_7 transitions_per_cycle: 32 Cache config: l1u_0 @@ -376,34 +386,34 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/29/2009 15:40:36 +Real time: Aug/05/2009 14:05:27 Profiler Stats -------------- -Elapsed_time_in_seconds: 1279 -Elapsed_time_in_minutes: 21.3167 -Elapsed_time_in_hours: 0.355278 -Elapsed_time_in_days: 0.0148032 +Elapsed_time_in_seconds: 1657 +Elapsed_time_in_minutes: 27.6167 +Elapsed_time_in_hours: 0.460278 +Elapsed_time_in_days: 0.0191782 -Virtual_time_in_seconds: 1279.21 -Virtual_time_in_minutes: 21.3202 -Virtual_time_in_hours: 0.355336 -Virtual_time_in_days: 0.0148057 +Virtual_time_in_seconds: 1574.85 +Virtual_time_in_minutes: 26.2475 +Virtual_time_in_hours: 0.437458 +Virtual_time_in_days: 0.0182274 -Ruby_current_time: 31814465 +Ruby_current_time: 31871403 Ruby_start_time: 1 -Ruby_cycles: 31814464 +Ruby_cycles: 31871402 -mbytes_resident: 150.707 -mbytes_total: 1502.61 -resident_ratio: 0.100302 +mbytes_resident: 150.73 +mbytes_total: 1502.58 +resident_ratio: 0.10032 Total_misses: 0 total_misses: 0 [ 0 0 0 0 0 0 0 0 ] user_misses: 0 [ 0 0 0 0 0 0 0 0 ] supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ] -ruby_cycles_executed: 254515720 [ 31814465 31814465 31814465 31814465 31814465 31814465 31814465 31814465 ] +ruby_cycles_executed: 254971224 [ 31871403 31871403 31871403 31871403 31871403 31871403 31871403 31871403 ] transactions_started: 0 [ 0 0 0 0 0 0 0 0 ] transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ] @@ -412,40 +422,40 @@ misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ] Memory control MemoryControl_0: - memory_total_requests: 1388468 - memory_reads: 694293 - memory_writes: 694043 - memory_refreshes: 66280 - memory_total_request_delays: 426683648 - memory_delays_per_request: 307.305 - memory_delays_in_input_queue: 87635910 - memory_delays_behind_head_of_bank_queue: 258531255 - memory_delays_stalled_at_head_of_bank_queue: 80516483 - memory_stalls_for_bank_busy: 12165032 + memory_total_requests: 1389969 + memory_reads: 695049 + memory_writes: 694795 + memory_refreshes: 66399 + memory_total_request_delays: 426018769 + memory_delays_per_request: 306.495 + memory_delays_in_input_queue: 90894877 + memory_delays_behind_head_of_bank_queue: 255108229 + memory_delays_stalled_at_head_of_bank_queue: 80015663 + memory_stalls_for_bank_busy: 12108953 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 24715948 - memory_stalls_for_arbitration: 15631815 - memory_stalls_for_bus: 20544794 + memory_stalls_for_anti_starvation: 24487499 + memory_stalls_for_arbitration: 15539710 + memory_stalls_for_bus: 20434932 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 6014461 - memory_stalls_for_read_read_turnaround: 1444433 - accesses_per_bank: 43313 43907 44020 43692 43588 43833 44012 43419 43405 43526 43433 43395 43597 43293 43128 43416 43269 43509 43139 43194 43419 43535 43304 43225 43160 43143 43188 43018 42886 43118 43257 43127 + memory_stalls_for_read_write_turnaround: 6003845 + memory_stalls_for_read_read_turnaround: 1440724 + accesses_per_bank: 43357 44015 43781 43810 43753 43615 43533 43621 43760 43473 43392 43592 43408 43516 43431 43583 43408 43238 43387 43265 43461 43404 43268 43371 43341 43146 43143 43177 43023 43329 42971 43397 Busy Controller Counts: -L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:1 L1Cache-6:0 L1Cache-7:0 +L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:2 Directory-0:0 DMA-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 748260 average: 11.8029 | standard deviation: 3.40671 | 0 1091 2889 5609 9615 15772 23675 33311 44184 55041 64248 70323 72503 72248 68934 64870 143947 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 749091 average: 11.7606 | standard deviation: 3.43055 | 0 1195 3094 5987 10211 16213 24379 33889 44818 55183 63828 70245 72985 71727 68120 64568 142649 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 20559 count: 748171 average: 3866.31 | standard deviation: 2352.95 | 21417 1969 3723 6729 8868 8455 7676 8627 10203 11965 13796 13743 11900 13009 16352 17532 16234 15941 17304 16977 16916 18538 19194 16531 16082 17521 18191 15886 15702 16749 15616 14095 14916 15648 13793 11856 12863 13378 11663 10762 11443 11095 9691 9387 10128 9009 7817 8024 8496 7458 6302 6700 6887 5633 5066 5555 5357 4326 4220 4651 4016 3318 3403 3600 3054 2613 2796 2637 2141 2011 2128 1973 1548 1420 1531 1276 1047 1080 1093 914 741 749 732 584 493 515 525 388 363 345 325 251 268 277 202 190 183 189 147 117 143 119 90 93 91 82 60 58 58 49 51 48 39 28 34 36 30 17 16 21 24 23 12 17 16 9 12 16 12 13 7 4 7 8 7 8 5 7 5 8 4 4 6 5 3 3 2 1 4 1 2 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 128 max: 20559 count: 486192 average: 3864.95 | standard deviation: 2353.73 | 13998 1281 2484 4424 5714 5472 5029 5648 6631 7775 8926 8800 7735 8448 10496 11466 10602 10387 11224 11076 10939 12065 12497 10830 10391 11396 11931 10259 10262 10939 10169 9130 9608 10113 8955 7714 8408 8711 7593 6973 7459 7162 6232 6134 6554 5848 5110 5134 5495 4860 4083 4319 4432 3674 3259 3647 3406 2774 2755 3099 2579 2160 2269 2367 1984 1705 1833 1725 1372 1293 1349 1289 1004 902 970 862 693 720 732 613 484 488 462 374 341 336 349 246 226 213 205 156 178 186 130 122 119 126 100 72 94 79 57 64 63 57 37 38 35 33 35 27 23 19 22 28 17 7 10 14 16 16 10 7 11 6 8 9 3 6 5 4 4 4 4 4 2 6 3 5 4 3 2 5 3 3 1 1 2 1 2 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 128 max: 19863 count: 261979 average: 3868.82 | standard deviation: 2351.5 | 7419 688 1239 2305 3154 2983 2647 2979 3572 4190 4870 4943 4165 4561 5856 6066 5632 5554 6080 5901 5977 6473 6697 5701 5691 6125 6260 5627 5440 5810 5447 4965 5308 5535 4838 4142 4455 4667 4070 3789 3984 3933 3459 3253 3574 3161 2707 2890 3001 2598 2219 2381 2455 1959 1807 1908 1951 1552 1465 1552 1437 1158 1134 1233 1070 908 963 912 769 718 779 684 544 518 561 414 354 360 361 301 257 261 270 210 152 179 176 142 137 132 120 95 90 91 72 68 64 63 47 45 49 40 33 29 28 25 23 20 23 16 16 21 16 9 12 8 13 10 6 7 8 7 2 10 5 3 4 7 9 7 2 0 3 4 3 4 3 1 2 3 0 1 4 0 0 0 1 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 21143 count: 748999 average: 3853.8 | standard deviation: 2347.14 | 21685 2046 3724 6754 8786 8411 7788 8757 10178 12006 13478 13800 12395 13185 16353 16995 16436 16328 17286 17295 16892 18651 19670 16684 16291 17758 18049 16416 15965 16404 15524 14164 14431 15506 13589 12027 13053 13566 11578 10619 11289 11140 9536 9219 10023 9112 7727 7948 8409 7483 6331 6838 6701 5601 5153 5461 5371 4328 4243 4405 4068 3507 3548 3405 3002 2597 2725 2712 2106 1961 2002 1909 1487 1417 1536 1278 1012 1084 1058 904 709 736 738 545 501 536 472 397 337 357 316 252 267 271 202 195 179 183 140 124 136 106 74 91 89 65 54 61 55 60 60 45 33 31 24 39 28 23 30 31 14 20 14 16 22 12 6 10 21 6 9 8 6 4 6 11 7 9 5 2 4 2 3 6 3 2 0 2 2 2 1 1 2 1 1 4 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 128 max: 21143 count: 486326 average: 3852.66 | standard deviation: 2347.25 | 14072 1327 2443 4342 5729 5496 5083 5762 6663 7790 8820 8935 8050 8477 10578 11081 10605 10643 11287 11230 10992 12105 12745 10874 10606 11424 11647 10600 10427 10676 10079 9205 9306 10079 8868 7739 8487 8814 7465 6849 7339 7219 6182 6042 6453 5924 4980 5095 5515 4905 4170 4487 4307 3622 3327 3554 3511 2838 2751 2831 2713 2289 2261 2177 1939 1693 1757 1749 1388 1246 1314 1278 984 907 995 845 687 693 691 577 445 486 462 351 310 350 295 258 213 235 213 163 184 180 128 131 111 118 88 90 95 65 46 53 54 46 30 38 30 35 44 29 22 17 15 25 18 17 25 20 8 13 11 12 16 6 5 5 12 4 6 5 1 2 5 6 4 5 4 2 3 2 1 4 2 1 0 2 1 0 0 0 1 1 1 2 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 128 max: 21029 count: 262673 average: 3855.92 | standard deviation: 2346.94 | 7613 719 1281 2412 3057 2915 2705 2995 3515 4216 4658 4865 4345 4708 5775 5914 5831 5685 5999 6065 5900 6546 6925 5810 5685 6334 6402 5816 5538 5728 5445 4959 5125 5427 4721 4288 4566 4752 4113 3770 3950 3921 3354 3177 3570 3188 2747 2853 2894 2578 2161 2351 2394 1979 1826 1907 1860 1490 1492 1574 1355 1218 1287 1228 1063 904 968 963 718 715 688 631 503 510 541 433 325 391 367 327 264 250 276 194 191 186 177 139 124 122 103 89 83 91 74 64 68 65 52 34 41 41 28 38 35 19 24 23 25 25 16 16 11 14 9 14 10 6 5 11 6 7 3 4 6 6 1 5 9 2 3 3 5 2 1 5 3 4 1 0 1 0 2 2 1 1 0 0 1 2 1 1 1 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -459,11 +469,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 18 count: 1496498 average: 0.0019285 | standard deviation: 0.169351 | 1496294 0 2 0 3 0 1 0 1 0 29 0 28 0 42 0 61 0 37 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 1496498 average: 0.0019285 | standard deviation: 0.169351 | 1496294 0 2 0 3 0 1 0 1 0 29 0 28 0 42 0 61 0 37 ] +Total_delay_cycles: [binsize: 1 max: 34 count: 1498140 average: 0.00218137 | standard deviation: 0.184029 | 1497918 0 1 0 2 0 3 0 5 0 13 0 27 0 56 0 72 0 40 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 34 count: 1498140 average: 0.00218137 | standard deviation: 0.184029 | 1497918 0 1 0 2 0 3 0 5 0 13 0 27 0 56 0 72 0 40 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 748171 average: 0 | standard deviation: 0 | 748171 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 18 count: 748327 average: 0.0038566 | standard deviation: 0.239469 | 748123 0 2 0 3 0 1 0 1 0 29 0 28 0 42 0 61 0 37 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 748999 average: 0 | standard deviation: 0 | 748999 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 34 count: 749141 average: 0.00436233 | standard deviation: 0.260226 | 748919 0 1 0 2 0 3 0 5 0 13 0 27 0 56 0 72 0 40 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -471,9 +481,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 1496498 average: 0.0019285 Resource Usage -------------- page_size: 4096 -user_time: 1279 -system_time: 0 -page_reclaims: 39805 +user_time: 1568 +system_time: 6 +page_reclaims: 39818 page_faults: 0 swaps: 0 block_inputs: 0 @@ -484,110 +494,110 @@ Network Stats switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.0183757 - links_utilized_percent_switch_0_link_0: 0.0073498 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.0294016 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.0183566 + links_utilized_percent_switch_0_link_0: 0.00734197 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.0293713 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 93520 748160 [ 0 93520 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 93544 748352 [ 0 0 93544 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 93523 748184 [ 93523 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 86916 695328 [ 86916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 6640 53120 [ 0 6640 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 93592 748736 [ 0 93592 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 93607 748856 [ 0 0 93607 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 93601 748808 [ 93601 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 86982 695856 [ 86982 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 6638 53104 [ 0 6638 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0183711 - links_utilized_percent_switch_1_link_0: 0.00734831 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.0293939 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.0183583 + links_utilized_percent_switch_1_link_0: 0.0073431 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.0293735 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 93502 748016 [ 0 93502 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 93524 748192 [ 0 0 93524 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 93506 748048 [ 93506 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Data: 86741 693928 [ 86741 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 6783 54264 [ 0 6783 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 93606 748848 [ 0 93606 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 93622 748976 [ 0 0 93622 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 93610 748880 [ 93610 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Data: 86850 694800 [ 86850 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 6775 54200 [ 0 6775 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.0183707 - links_utilized_percent_switch_2_link_0: 0.00734752 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.0293939 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.0183623 + links_utilized_percent_switch_2_link_0: 0.00734448 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.0293801 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 93497 747976 [ 0 93497 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 93509 748072 [ 0 0 93509 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 93510 748080 [ 93510 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 86829 694632 [ 86829 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 6691 53528 [ 0 6691 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 93626 749008 [ 0 93626 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 93632 749056 [ 93632 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 86768 694144 [ 86768 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 6877 55016 [ 0 6877 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.0183818 - links_utilized_percent_switch_3_link_0: 0.00735177 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.0294118 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.0183636 + links_utilized_percent_switch_3_link_0: 0.00734471 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.0293825 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 93545 748360 [ 0 93545 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 93558 748464 [ 93558 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Data: 86852 694816 [ 86852 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 6734 53872 [ 0 6734 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 93633 749064 [ 0 93633 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 93636 749088 [ 0 0 93636 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 93645 749160 [ 93645 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Data: 86943 695544 [ 86943 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 6704 53632 [ 0 6704 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.0183835 - links_utilized_percent_switch_4_link_0: 0.00735287 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.0294141 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.0183624 + links_utilized_percent_switch_4_link_0: 0.00734432 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.0293806 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 93560 748480 [ 0 93560 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 93582 748656 [ 0 0 93582 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 93567 748536 [ 93567 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Data: 86798 694384 [ 86798 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 6794 54352 [ 0 6794 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 93622 748976 [ 0 93622 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 93631 749048 [ 93631 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Data: 86839 694712 [ 86839 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 6810 54480 [ 0 6810 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.0183813 - links_utilized_percent_switch_5_link_0: 0.00735204 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.0294105 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.0183663 + links_utilized_percent_switch_5_link_0: 0.00734561 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.029387 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 93552 748416 [ 0 93552 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 93561 748488 [ 93561 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Data: 86705 693640 [ 86705 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 6870 54960 [ 0 6870 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 93632 749056 [ 0 93632 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 93660 749280 [ 0 0 93660 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 93647 749176 [ 93647 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Data: 87074 696592 [ 87074 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 6600 52800 [ 0 6600 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.0183704 - links_utilized_percent_switch_6_link_0: 0.00734764 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.0293932 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.0183699 + links_utilized_percent_switch_6_link_0: 0.00734765 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.0293922 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 93494 747952 [ 0 93494 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 93502 748016 [ 93502 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Data: 86898 695184 [ 86898 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 6626 53008 [ 0 6626 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 93657 749256 [ 0 93657 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 93687 749496 [ 0 0 93687 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 93662 749296 [ 93662 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Data: 86788 694304 [ 86788 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 6904 55232 [ 0 6904 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.0183714 - links_utilized_percent_switch_7_link_0: 0.00734792 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.0293948 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.018364 + links_utilized_percent_switch_7_link_0: 0.00734538 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.0293826 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 93501 748008 [ 0 93501 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 93509 748072 [ 93509 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Data: 86787 694296 [ 86787 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 6740 53920 [ 0 6740 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 93631 749048 [ 0 93631 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 93655 749240 [ 0 0 93655 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 93635 749080 [ 93635 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Data: 87012 696096 [ 87012 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 6646 53168 [ 0 6646 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.141705 - links_utilized_percent_switch_8_link_0: 0.0566866 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.226724 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.141605 + links_utilized_percent_switch_8_link_0: 0.0566464 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.226565 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 748236 5985888 [ 748236 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Data: 694526 5556208 [ 694526 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 694293 5554344 [ 0 694293 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 748327 5986616 [ 0 0 748327 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 749063 5992504 [ 749063 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Data: 695256 5562048 [ 695256 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 695045 5560360 [ 0 695045 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 749141 5993128 [ 0 0 749141 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 @@ -598,148 +608,148 @@ links_utilized_percent_switch_9: 0 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.0461938 - links_utilized_percent_switch_10_link_0: 0.0293992 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.0293932 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.0293901 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.0294071 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.0294115 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.0294082 bw: 160000 base_latency: 1 +links_utilized_percent_switch_10: 0.0461614 + links_utilized_percent_switch_10_link_0: 0.0293679 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.0293724 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.0293779 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.0293788 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.0293773 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.0293825 bw: 160000 base_latency: 1 links_utilized_percent_switch_10_link_6: 0.0293906 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.0293917 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.226746 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.0293815 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 0.226585 bw: 160000 base_latency: 1 links_utilized_percent_switch_10_link_9: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 93520 748160 [ 0 93520 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Writeback_Control: 93544 748352 [ 0 0 93544 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 93502 748016 [ 0 93502 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Writeback_Control: 93524 748192 [ 0 0 93524 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 93497 747976 [ 0 93497 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Writeback_Control: 93509 748072 [ 0 0 93509 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 93545 748360 [ 0 93545 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 93560 748480 [ 0 93560 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Writeback_Control: 93582 748656 [ 0 0 93582 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 93552 748416 [ 0 93552 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 93494 747952 [ 0 93494 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 93501 748008 [ 0 93501 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 748236 5985888 [ 748236 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Data: 694526 5556208 [ 694526 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 93592 748736 [ 0 93592 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Control: 93607 748856 [ 0 0 93607 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 93606 748848 [ 0 93606 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Writeback_Control: 93622 748976 [ 0 0 93622 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 93626 749008 [ 0 93626 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 93633 749064 [ 0 93633 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Writeback_Control: 93636 749088 [ 0 0 93636 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 93622 748976 [ 0 93622 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 93632 749056 [ 0 93632 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Writeback_Control: 93660 749280 [ 0 0 93660 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 93657 749256 [ 0 93657 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Writeback_Control: 93687 749496 [ 0 0 93687 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 93631 749048 [ 0 93631 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Writeback_Control: 93655 749240 [ 0 0 93655 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Control: 749063 5992504 [ 749063 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Data: 695256 5562048 [ 695256 0 0 0 0 0 ] base_latency: 1 l1u_0 cache stats: - l1u_0_total_misses: 93523 - l1u_0_total_demand_misses: 93523 + l1u_0_total_misses: 93601 + l1u_0_total_demand_misses: 93601 l1u_0_total_prefetches: 0 l1u_0_total_sw_prefetches: 0 l1u_0_total_hw_prefetches: 0 l1u_0_misses_per_transaction: inf - l1u_0_request_type_LD: 64.8311% - l1u_0_request_type_ST: 35.1689% + l1u_0_request_type_LD: 64.9138% + l1u_0_request_type_ST: 35.0862% - l1u_0_access_mode_type_SupervisorMode: 93523 100% - l1u_0_request_size: [binsize: log2 max: 1 count: 93523 average: 1 | standard deviation: 0 | 0 93523 ] + l1u_0_access_mode_type_SupervisorMode: 93601 100% + l1u_0_request_size: [binsize: log2 max: 1 count: 93601 average: 1 | standard deviation: 0 | 0 93601 ] l1u_1 cache stats: - l1u_1_total_misses: 93506 - l1u_1_total_demand_misses: 93506 + l1u_1_total_misses: 93610 + l1u_1_total_demand_misses: 93610 l1u_1_total_prefetches: 0 l1u_1_total_sw_prefetches: 0 l1u_1_total_hw_prefetches: 0 l1u_1_misses_per_transaction: inf - l1u_1_request_type_LD: 64.8162% - l1u_1_request_type_ST: 35.1838% + l1u_1_request_type_LD: 64.9364% + l1u_1_request_type_ST: 35.0636% - l1u_1_access_mode_type_SupervisorMode: 93506 100% - l1u_1_request_size: [binsize: log2 max: 1 count: 93506 average: 1 | standard deviation: 0 | 0 93506 ] + l1u_1_access_mode_type_SupervisorMode: 93610 100% + l1u_1_request_size: [binsize: log2 max: 1 count: 93610 average: 1 | standard deviation: 0 | 0 93610 ] l1u_2 cache stats: - l1u_2_total_misses: 93510 - l1u_2_total_demand_misses: 93510 + l1u_2_total_misses: 93632 + l1u_2_total_demand_misses: 93632 l1u_2_total_prefetches: 0 l1u_2_total_sw_prefetches: 0 l1u_2_total_hw_prefetches: 0 l1u_2_misses_per_transaction: inf - l1u_2_request_type_LD: 64.931% - l1u_2_request_type_ST: 35.069% + l1u_2_request_type_LD: 65.0301% + l1u_2_request_type_ST: 34.9699% - l1u_2_access_mode_type_SupervisorMode: 93510 100% - l1u_2_request_size: [binsize: log2 max: 1 count: 93510 average: 1 | standard deviation: 0 | 0 93510 ] + l1u_2_access_mode_type_SupervisorMode: 93632 100% + l1u_2_request_size: [binsize: log2 max: 1 count: 93632 average: 1 | standard deviation: 0 | 0 93632 ] l1u_3 cache stats: - l1u_3_total_misses: 93558 - l1u_3_total_demand_misses: 93558 + l1u_3_total_misses: 93645 + l1u_3_total_demand_misses: 93645 l1u_3_total_prefetches: 0 l1u_3_total_sw_prefetches: 0 l1u_3_total_hw_prefetches: 0 l1u_3_misses_per_transaction: inf - l1u_3_request_type_LD: 64.9693% - l1u_3_request_type_ST: 35.0307% + l1u_3_request_type_LD: 64.768% + l1u_3_request_type_ST: 35.232% - l1u_3_access_mode_type_SupervisorMode: 93558 100% - l1u_3_request_size: [binsize: log2 max: 1 count: 93558 average: 1 | standard deviation: 0 | 0 93558 ] + l1u_3_access_mode_type_SupervisorMode: 93645 100% + l1u_3_request_size: [binsize: log2 max: 1 count: 93645 average: 1 | standard deviation: 0 | 0 93645 ] l1u_4 cache stats: - l1u_4_total_misses: 93567 - l1u_4_total_demand_misses: 93567 + l1u_4_total_misses: 93631 + l1u_4_total_demand_misses: 93631 l1u_4_total_prefetches: 0 l1u_4_total_sw_prefetches: 0 l1u_4_total_hw_prefetches: 0 l1u_4_misses_per_transaction: inf - l1u_4_request_type_LD: 65.2474% - l1u_4_request_type_ST: 34.7526% + l1u_4_request_type_LD: 65.1579% + l1u_4_request_type_ST: 34.8421% - l1u_4_access_mode_type_SupervisorMode: 93567 100% - l1u_4_request_size: [binsize: log2 max: 1 count: 93567 average: 1 | standard deviation: 0 | 0 93567 ] + l1u_4_access_mode_type_SupervisorMode: 93631 100% + l1u_4_request_size: [binsize: log2 max: 1 count: 93631 average: 1 | standard deviation: 0 | 0 93631 ] l1u_5 cache stats: - l1u_5_total_misses: 93561 - l1u_5_total_demand_misses: 93561 + l1u_5_total_misses: 93647 + l1u_5_total_demand_misses: 93647 l1u_5_total_prefetches: 0 l1u_5_total_sw_prefetches: 0 l1u_5_total_hw_prefetches: 0 l1u_5_misses_per_transaction: inf - l1u_5_request_type_LD: 65.0004% - l1u_5_request_type_ST: 34.9996% + l1u_5_request_type_LD: 64.9086% + l1u_5_request_type_ST: 35.0914% - l1u_5_access_mode_type_SupervisorMode: 93561 100% - l1u_5_request_size: [binsize: log2 max: 1 count: 93561 average: 1 | standard deviation: 0 | 0 93561 ] + l1u_5_access_mode_type_SupervisorMode: 93647 100% + l1u_5_request_size: [binsize: log2 max: 1 count: 93647 average: 1 | standard deviation: 0 | 0 93647 ] l1u_6 cache stats: - l1u_6_total_misses: 93502 - l1u_6_total_demand_misses: 93502 + l1u_6_total_misses: 93662 + l1u_6_total_demand_misses: 93662 l1u_6_total_prefetches: 0 l1u_6_total_sw_prefetches: 0 l1u_6_total_hw_prefetches: 0 l1u_6_misses_per_transaction: inf - l1u_6_request_type_LD: 64.9569% - l1u_6_request_type_ST: 35.0431% + l1u_6_request_type_LD: 64.8353% + l1u_6_request_type_ST: 35.1647% - l1u_6_access_mode_type_SupervisorMode: 93502 100% - l1u_6_request_size: [binsize: log2 max: 1 count: 93502 average: 1 | standard deviation: 0 | 0 93502 ] + l1u_6_access_mode_type_SupervisorMode: 93662 100% + l1u_6_request_size: [binsize: log2 max: 1 count: 93662 average: 1 | standard deviation: 0 | 0 93662 ] l1u_7 cache stats: - l1u_7_total_misses: 93509 - l1u_7_total_demand_misses: 93509 + l1u_7_total_misses: 93635 + l1u_7_total_demand_misses: 93635 l1u_7_total_prefetches: 0 l1u_7_total_sw_prefetches: 0 l1u_7_total_hw_prefetches: 0 l1u_7_misses_per_transaction: inf - l1u_7_request_type_LD: 65.1189% - l1u_7_request_type_ST: 34.8811% + l1u_7_request_type_LD: 64.8881% + l1u_7_request_type_ST: 35.1119% - l1u_7_access_mode_type_SupervisorMode: 93509 100% - l1u_7_request_size: [binsize: log2 max: 1 count: 93509 average: 1 | standard deviation: 0 | 0 93509 ] + l1u_7_access_mode_type_SupervisorMode: 93635 100% + l1u_7_request_size: [binsize: log2 max: 1 count: 93635 average: 1 | standard deviation: 0 | 0 93635 ] --- DMA 0 --- - Event Counts - @@ -758,24 +768,24 @@ BUSY_WR Ack 0 <-- --- Directory 0 --- - Event Counts - -GETX 7422269 +GETX 7426933 GETS 0 -PUTX 694113 -PUTX_NotOwner 412 +PUTX 694863 +PUTX_NotOwner 393 DMA_READ 0 DMA_WRITE 0 -Memory_Data 694293 -Memory_Ack 694037 +Memory_Data 695045 +Memory_Ack 694794 - Transitions - -I GETX 694355 +I GETX 695106 I PUTX_NotOwner 0 <-- I DMA_READ 0 <-- I DMA_WRITE 0 <-- -M GETX 53878 -M PUTX 694113 -M PUTX_NotOwner 412 +M GETX 53954 +M PUTX 694863 +M PUTX_NotOwner 393 M DMA_READ 0 <-- M DMA_WRITE 0 <-- @@ -787,21 +797,21 @@ M_DWR PUTX 0 <-- M_DWRI Memory_Ack 0 <-- -IM GETX 3217688 +IM GETX 3188108 IM GETS 0 <-- IM PUTX 0 <-- IM PUTX_NotOwner 0 <-- IM DMA_READ 0 <-- IM DMA_WRITE 0 <-- -IM Memory_Data 694293 +IM Memory_Data 695045 -MI GETX 3456348 +MI GETX 3489765 MI GETS 0 <-- MI PUTX 0 <-- MI PUTX_NotOwner 0 <-- MI DMA_READ 0 <-- MI DMA_WRITE 0 <-- -MI Memory_Ack 694037 +MI Memory_Ack 694794 ID GETX 0 <-- ID GETS 0 <-- @@ -821,289 +831,289 @@ ID_W Memory_Ack 0 <-- --- L1Cache 0 --- - Event Counts - -Load 60632 +Load 60760 Ifetch 0 -Store 32891 -Data 93520 -Fwd_GETX 6640 +Store 32841 +Data 93592 +Fwd_GETX 6638 Inv 0 -Replacement 93491 -Writeback_Ack 86841 -Writeback_Nack 63 +Replacement 93569 +Writeback_Ack 86918 +Writeback_Nack 51 - Transitions - -I Load 60632 +I Load 60760 I Ifetch 0 <-- -I Store 32891 +I Store 32841 I Inv 0 <-- -I Replacement 6575 +I Replacement 6587 -II Writeback_Nack 63 +II Writeback_Nack 51 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6577 +M Fwd_GETX 6587 M Inv 0 <-- -M Replacement 86916 +M Replacement 86982 -MI Fwd_GETX 63 +MI Fwd_GETX 51 MI Inv 0 <-- -MI Writeback_Ack 86841 +MI Writeback_Ack 86918 -IS Data 60630 +IS Data 60754 -IM Data 32890 +IM Data 32838 --- L1Cache 1 --- - Event Counts - -Load 60607 +Load 60787 Ifetch 0 -Store 32899 -Data 93502 -Fwd_GETX 6783 +Store 32823 +Data 93606 +Fwd_GETX 6775 Inv 0 -Replacement 93474 -Writeback_Ack 86692 -Writeback_Nack 49 +Replacement 93578 +Writeback_Ack 86801 +Writeback_Nack 46 - Transitions - -I Load 60607 +I Load 60787 I Ifetch 0 <-- -I Store 32899 +I Store 32823 I Inv 0 <-- -I Replacement 6733 +I Replacement 6728 -II Writeback_Nack 49 +II Writeback_Nack 46 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6734 +M Fwd_GETX 6729 M Inv 0 <-- -M Replacement 86741 +M Replacement 86850 -MI Fwd_GETX 49 +MI Fwd_GETX 46 MI Inv 0 <-- -MI Writeback_Ack 86692 +MI Writeback_Ack 86801 -IS Data 60604 +IS Data 60784 -IM Data 32898 +IM Data 32822 --- L1Cache 2 --- - Event Counts - -Load 60717 +Load 60889 Ifetch 0 -Store 32793 -Data 93497 -Fwd_GETX 6691 +Store 32743 +Data 93626 +Fwd_GETX 6877 Inv 0 -Replacement 93478 -Writeback_Ack 86777 -Writeback_Nack 41 +Replacement 93600 +Writeback_Ack 86717 +Writeback_Nack 43 - Transitions - -I Load 60717 +I Load 60889 I Ifetch 0 <-- -I Store 32793 +I Store 32743 I Inv 0 <-- -I Replacement 6649 +I Replacement 6832 -II Writeback_Nack 41 +II Writeback_Nack 43 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6650 +M Fwd_GETX 6834 M Inv 0 <-- -M Replacement 86829 +M Replacement 86768 -MI Fwd_GETX 41 +MI Fwd_GETX 43 MI Inv 0 <-- -MI Writeback_Ack 86777 +MI Writeback_Ack 86717 -IS Data 60709 +IS Data 60884 -IM Data 32788 +IM Data 32742 --- L1Cache 3 --- - Event Counts - -Load 60784 +Load 60652 Ifetch 0 -Store 32774 -Data 93545 -Fwd_GETX 6734 +Store 32993 +Data 93633 +Fwd_GETX 6704 Inv 0 -Replacement 93526 -Writeback_Ack 86775 -Writeback_Nack 60 +Replacement 93613 +Writeback_Ack 86899 +Writeback_Nack 33 - Transitions - -I Load 60784 +I Load 60652 I Ifetch 0 <-- -I Store 32774 +I Store 32993 I Inv 0 <-- -I Replacement 6674 +I Replacement 6670 -II Writeback_Nack 60 +II Writeback_Nack 33 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6674 +M Fwd_GETX 6671 M Inv 0 <-- -M Replacement 86852 +M Replacement 86943 -MI Fwd_GETX 60 +MI Fwd_GETX 33 MI Inv 0 <-- -MI Writeback_Ack 86775 +MI Writeback_Ack 86899 -IS Data 60776 +IS Data 60644 -IM Data 32769 +IM Data 32989 --- L1Cache 4 --- - Event Counts - -Load 61050 +Load 61008 Ifetch 0 -Store 32517 -Data 93560 -Fwd_GETX 6794 +Store 32623 +Data 93622 +Fwd_GETX 6810 Inv 0 -Replacement 93535 -Writeback_Ack 86735 -Writeback_Nack 53 +Replacement 93599 +Writeback_Ack 86779 +Writeback_Nack 48 - Transitions - -I Load 61050 +I Load 61008 I Ifetch 0 <-- -I Store 32517 +I Store 32623 I Inv 0 <-- -I Replacement 6737 +I Replacement 6760 -II Writeback_Nack 53 +II Writeback_Nack 48 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6741 +M Fwd_GETX 6762 M Inv 0 <-- -M Replacement 86798 +M Replacement 86839 -MI Fwd_GETX 53 +MI Fwd_GETX 48 MI Inv 0 <-- -MI Writeback_Ack 86735 +MI Writeback_Ack 86779 -IS Data 61047 +IS Data 61004 -IM Data 32513 +IM Data 32618 --- L1Cache 5 --- - Event Counts - -Load 60815 +Load 60785 Ifetch 0 -Store 32746 -Data 93552 -Fwd_GETX 6870 +Store 32862 +Data 93632 +Fwd_GETX 6600 Inv 0 -Replacement 93529 -Writeback_Ack 86654 -Writeback_Nack 45 +Replacement 93615 +Writeback_Ack 87003 +Writeback_Nack 57 - Transitions - -I Load 60815 +I Load 60785 I Ifetch 0 <-- -I Store 32746 +I Store 32862 I Inv 0 <-- -I Replacement 6824 +I Replacement 6541 -II Writeback_Nack 45 +II Writeback_Nack 57 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6825 +M Fwd_GETX 6543 M Inv 0 <-- -M Replacement 86705 +M Replacement 87074 -MI Fwd_GETX 45 +MI Fwd_GETX 57 MI Inv 0 <-- -MI Writeback_Ack 86654 +MI Writeback_Ack 87003 -IS Data 60809 +IS Data 60776 -IM Data 32743 +IM Data 32856 --- L1Cache 6 --- - Event Counts - -Load 60736 +Load 60726 Ifetch 0 -Store 32766 -Data 93494 -Fwd_GETX 6626 +Store 32936 +Data 93657 +Fwd_GETX 6904 Inv 0 -Replacement 93470 -Writeback_Ack 86837 -Writeback_Nack 52 +Replacement 93630 +Writeback_Ack 86721 +Writeback_Nack 62 - Transitions - -I Load 60736 +I Load 60726 I Ifetch 0 <-- -I Store 32766 +I Store 32936 I Inv 0 <-- -I Replacement 6572 +I Replacement 6842 -II Writeback_Nack 52 +II Writeback_Nack 62 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6574 +M Fwd_GETX 6842 M Inv 0 <-- -M Replacement 86898 +M Replacement 86788 -MI Fwd_GETX 52 +MI Fwd_GETX 62 MI Inv 0 <-- -MI Writeback_Ack 86837 +MI Writeback_Ack 86721 -IS Data 60730 +IS Data 60724 -IM Data 32764 +IM Data 32933 --- L1Cache 7 --- - Event Counts - -Load 60892 +Load 60758 Ifetch 0 -Store 32617 -Data 93501 -Fwd_GETX 6740 +Store 32877 +Data 93631 +Fwd_GETX 6646 Inv 0 -Replacement 93477 -Writeback_Ack 86726 -Writeback_Nack 49 +Replacement 93603 +Writeback_Ack 86956 +Writeback_Nack 53 - Transitions - -I Load 60892 +I Load 60758 I Ifetch 0 <-- -I Store 32617 +I Store 32877 I Inv 0 <-- -I Replacement 6690 +I Replacement 6591 -II Writeback_Nack 49 +II Writeback_Nack 53 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6691 +M Fwd_GETX 6593 M Inv 0 <-- -M Replacement 86787 +M Replacement 87012 -MI Fwd_GETX 49 +MI Fwd_GETX 53 MI Inv 0 <-- -MI Writeback_Ack 86726 +MI Writeback_Ack 86956 -IS Data 60887 +IS Data 60756 -IM Data 32614 +IM Data 32875 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr index bab30a994..dd896132a 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -1,76 +1,76 @@ ["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "8", "-m", "1", "-s", "1024"] print config: 1 -system.cpu1: completed 10000 read accesses @3663630 -system.cpu2: completed 10000 read accesses @3663638 -system.cpu5: completed 10000 read accesses @3680002 -system.cpu7: completed 10000 read accesses @3691164 -system.cpu3: completed 10000 read accesses @3698130 -system.cpu4: completed 10000 read accesses @3701748 -system.cpu6: completed 10000 read accesses @3704092 -system.cpu0: completed 10000 read accesses @3742302 -system.cpu2: completed 20000 read accesses @6788966 -system.cpu7: completed 20000 read accesses @6816416 -system.cpu5: completed 20000 read accesses @6822351 -system.cpu4: completed 20000 read accesses @6824056 -system.cpu1: completed 20000 read accesses @6825604 -system.cpu3: completed 20000 read accesses @6829578 -system.cpu6: completed 20000 read accesses @6857232 -system.cpu0: completed 20000 read accesses @6872452 -system.cpu5: completed 30000 read accesses @9928492 -system.cpu2: completed 30000 read accesses @9933192 -system.cpu7: completed 30000 read accesses @9950074 -system.cpu4: completed 30000 read accesses @9965775 -system.cpu6: completed 30000 read accesses @9978835 -system.cpu0: completed 30000 read accesses @9993926 -system.cpu1: completed 30000 read accesses @9994767 -system.cpu3: completed 30000 read accesses @9996366 -system.cpu5: completed 40000 read accesses @13012070 -system.cpu2: completed 40000 read accesses @13044972 -system.cpu7: completed 40000 read accesses @13077010 -system.cpu4: completed 40000 read accesses @13081178 -system.cpu1: completed 40000 read accesses @13100740 -system.cpu0: completed 40000 read accesses @13111135 -system.cpu6: completed 40000 read accesses @13147706 -system.cpu3: completed 40000 read accesses @13153176 -system.cpu5: completed 50000 read accesses @16120762 -system.cpu2: completed 50000 read accesses @16176586 -system.cpu7: completed 50000 read accesses @16213417 -system.cpu4: completed 50000 read accesses @16219872 -system.cpu6: completed 50000 read accesses @16231538 -system.cpu1: completed 50000 read accesses @16246976 -system.cpu3: completed 50000 read accesses @16276612 -system.cpu0: completed 50000 read accesses @16293234 -system.cpu5: completed 60000 read accesses @19263804 -system.cpu4: completed 60000 read accesses @19313220 -system.cpu2: completed 60000 read accesses @19330470 -system.cpu7: completed 60000 read accesses @19340197 -system.cpu6: completed 60000 read accesses @19399766 -system.cpu0: completed 60000 read accesses @19424570 -system.cpu1: completed 60000 read accesses @19425712 -system.cpu3: completed 60000 read accesses @19444952 -system.cpu5: completed 70000 read accesses @22408750 -system.cpu4: completed 70000 read accesses @22449746 -system.cpu7: completed 70000 read accesses @22451736 -system.cpu2: completed 70000 read accesses @22461052 -system.cpu0: completed 70000 read accesses @22554296 -system.cpu1: completed 70000 read accesses @22555310 -system.cpu3: completed 70000 read accesses @22588935 -system.cpu6: completed 70000 read accesses @22602456 -system.cpu5: completed 80000 read accesses @25540598 -system.cpu4: completed 80000 read accesses @25577430 -system.cpu7: completed 80000 read accesses @25617532 -system.cpu1: completed 80000 read accesses @25644879 -system.cpu2: completed 80000 read accesses @25660256 -system.cpu0: completed 80000 read accesses @25710799 -system.cpu3: completed 80000 read accesses @25716714 -system.cpu6: completed 80000 read accesses @25776606 -system.cpu5: completed 90000 read accesses @28693458 -system.cpu4: completed 90000 read accesses @28705416 -system.cpu7: completed 90000 read accesses @28729734 -system.cpu1: completed 90000 read accesses @28778532 -system.cpu2: completed 90000 read accesses @28801770 -system.cpu0: completed 90000 read accesses @28857559 -system.cpu6: completed 90000 read accesses @28885159 -system.cpu3: completed 90000 read accesses @28894168 -system.cpu7: completed 100000 read accesses @31814464 +system.cpu4: completed 10000 read accesses @3654068 +system.cpu1: completed 10000 read accesses @3658672 +system.cpu6: completed 10000 read accesses @3667702 +system.cpu0: completed 10000 read accesses @3693712 +system.cpu2: completed 10000 read accesses @3695692 +system.cpu7: completed 10000 read accesses @3702934 +system.cpu3: completed 10000 read accesses @3713843 +system.cpu5: completed 10000 read accesses @3747976 +system.cpu4: completed 20000 read accesses @6783252 +system.cpu6: completed 20000 read accesses @6788574 +system.cpu1: completed 20000 read accesses @6811444 +system.cpu2: completed 20000 read accesses @6811575 +system.cpu7: completed 20000 read accesses @6823208 +system.cpu3: completed 20000 read accesses @6833412 +system.cpu0: completed 20000 read accesses @6842332 +system.cpu5: completed 20000 read accesses @6892128 +system.cpu4: completed 30000 read accesses @9900552 +system.cpu6: completed 30000 read accesses @9919466 +system.cpu7: completed 30000 read accesses @9934195 +system.cpu3: completed 30000 read accesses @9940524 +system.cpu2: completed 30000 read accesses @9940526 +system.cpu0: completed 30000 read accesses @9949032 +system.cpu1: completed 30000 read accesses @10008962 +system.cpu5: completed 30000 read accesses @10013847 +system.cpu0: completed 40000 read accesses @12997824 +system.cpu3: completed 40000 read accesses @13026659 +system.cpu4: completed 40000 read accesses @13029141 +system.cpu6: completed 40000 read accesses @13053052 +system.cpu7: completed 40000 read accesses @13057445 +system.cpu2: completed 40000 read accesses @13075320 +system.cpu5: completed 40000 read accesses @13152513 +system.cpu1: completed 40000 read accesses @13163064 +system.cpu3: completed 50000 read accesses @16170822 +system.cpu0: completed 50000 read accesses @16183660 +system.cpu4: completed 50000 read accesses @16197183 +system.cpu6: completed 50000 read accesses @16212971 +system.cpu7: completed 50000 read accesses @16214970 +system.cpu5: completed 50000 read accesses @16230286 +system.cpu2: completed 50000 read accesses @16247930 +system.cpu1: completed 50000 read accesses @16329114 +system.cpu3: completed 60000 read accesses @19272882 +system.cpu7: completed 60000 read accesses @19345830 +system.cpu4: completed 60000 read accesses @19346068 +system.cpu6: completed 60000 read accesses @19382538 +system.cpu0: completed 60000 read accesses @19393516 +system.cpu2: completed 60000 read accesses @19397285 +system.cpu5: completed 60000 read accesses @19426724 +system.cpu1: completed 60000 read accesses @19469424 +system.cpu3: completed 70000 read accesses @22377862 +system.cpu4: completed 70000 read accesses @22461180 +system.cpu2: completed 70000 read accesses @22521889 +system.cpu6: completed 70000 read accesses @22522406 +system.cpu5: completed 70000 read accesses @22529566 +system.cpu7: completed 70000 read accesses @22543033 +system.cpu0: completed 70000 read accesses @22547582 +system.cpu1: completed 70000 read accesses @22584856 +system.cpu3: completed 80000 read accesses @25551111 +system.cpu4: completed 80000 read accesses @25606550 +system.cpu6: completed 80000 read accesses @25616752 +system.cpu2: completed 80000 read accesses @25647434 +system.cpu5: completed 80000 read accesses @25665443 +system.cpu0: completed 80000 read accesses @25669616 +system.cpu1: completed 80000 read accesses @25693304 +system.cpu7: completed 80000 read accesses @25704210 +system.cpu3: completed 90000 read accesses @28724260 +system.cpu6: completed 90000 read accesses @28724466 +system.cpu5: completed 90000 read accesses @28743404 +system.cpu4: completed 90000 read accesses @28745769 +system.cpu2: completed 90000 read accesses @28803478 +system.cpu0: completed 90000 read accesses @28806136 +system.cpu1: completed 90000 read accesses @28823872 +system.cpu7: completed 90000 read accesses @28858910 +system.cpu3: completed 100000 read accesses @31871402 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout index 511812c26..17519e7a0 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 29 2009 15:19:07 -M5 revision a6e8795b73de+ 6384+ default tip -M5 started Jul 29 2009 15:19:16 +M5 compiled Aug 5 2009 13:36:56 +M5 revision 26abdfe2d980+ 6439+ default tip +M5 started Aug 5 2009 13:37:49 M5 executing on clover-02.cs.wisc.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 31814464 because maximum number of loads reached +Exiting @ tick 31871402 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 53437462a..2c9df6517 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 1538672 # Number of bytes of host memory used -host_seconds 1279.29 # Real time elapsed on the host -host_tick_rate 24869 # Simulator tick rate (ticks/s) +host_mem_usage 1538648 # Number of bytes of host memory used +host_seconds 1657.04 # Real time elapsed on the host +host_tick_rate 19234 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 31814464 # Number of ticks simulated +sim_ticks 31871402 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99342 # number of read accesses completed -system.cpu0.num_writes 53699 # number of write accesses completed +system.cpu0.num_reads 99819 # number of read accesses completed +system.cpu0.num_writes 53816 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99812 # number of read accesses completed -system.cpu1.num_writes 53757 # number of write accesses completed +system.cpu1.num_reads 99606 # number of read accesses completed +system.cpu1.num_writes 53868 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99597 # number of read accesses completed -system.cpu2.num_writes 53671 # number of write accesses completed +system.cpu2.num_reads 99741 # number of read accesses completed +system.cpu2.num_writes 53973 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99365 # number of read accesses completed -system.cpu3.num_writes 53444 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 53819 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99713 # number of read accesses completed -system.cpu4.num_writes 54044 # number of write accesses completed +system.cpu4.num_reads 99858 # number of read accesses completed +system.cpu4.num_writes 53805 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99943 # number of read accesses completed -system.cpu5.num_writes 53789 # number of write accesses completed +system.cpu5.num_reads 99895 # number of read accesses completed +system.cpu5.num_writes 53573 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99307 # number of read accesses completed -system.cpu6.num_writes 53603 # number of write accesses completed +system.cpu6.num_reads 99989 # number of read accesses completed +system.cpu6.num_writes 53856 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 100000 # number of read accesses completed -system.cpu7.num_writes 53881 # number of write accesses completed +system.cpu7.num_reads 99668 # number of read accesses completed +system.cpu7.num_writes 53858 # number of write accesses completed ---------- End Simulation Statistics ---------- |