Merge zizzer.eecs.umich.edu:/bk/newmem

into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace

--HG--
extra : convert_revision : 61eca737296a5ce839d3b97f047b4fda062cb899

12 files changed, 68 insertions, 49 deletions

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index ac30afde9..5bd572d38 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -231,14 +231,6 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
         return hintp;
       case MISCREG_HTBA:
         return htba;
-      case MISCREG_HVER:
-        // XXX set to match Legion
-        return ULL(0x3e) << 48 |
-               ULL(0x23) << 32 |
-               ULL(0x20) << 24 |
-                   //MaxGL << 16 | XXX For some reason legion doesn't set GL
-                   MaxTL << 8  |
-           (NWindows -1) << 0;
       case MISCREG_STRAND_STS_REG:
         return strandStatusReg;
       case MISCREG_HSTICK_CMPR:
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 439f38457..48e97a531 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -195,6 +195,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
             panic("No support for setting spec_en bit\n");
         setRegNoEffect(miscReg, bits(val,0,0));
         if (!bits(val,0,0)) {
+            DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
             // Time to go to sleep
             tc->suspend();
             if (tc->getKernelStats())
@@ -235,7 +236,13 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
       case MISCREG_HTBA:
         return readRegNoEffect(miscReg) & ULL(~0x7FFF);
       case MISCREG_HVER:
-        return NWindows | MaxTL << 8 | MaxGL << 16;
+        // XXX set to match Legion
+        return ULL(0x3e) << 48 |
+               ULL(0x23) << 32 |
+               ULL(0x20) << 24 |
+                   //MaxGL << 16 | XXX For some reason legion doesn't set GL
+                   MaxTL << 8  |
+           (NWindows -1) << 0;
 
       case MISCREG_STRAND_STS_REG:
         System *sys;
@@ -301,7 +308,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
         tc->getCpuPtr()->instCount();
     assert(ticks >= 0 && "stick compare missed interrupt cycle");
 
-    if (ticks == 0) {
+    if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
         DPRINTF(Timer, "STick compare cycle reached at %#x\n",
                 (stick_cmpr & mask(63)));
         if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
@@ -318,11 +325,15 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
     // we're actually at the correct cycle or we need to wait a little while
     // more
     int ticks;
+    if ( tc->status() == ThreadContext::Halted ||
+         tc->status() == ThreadContext::Unallocated)
+       return;
+
     ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
         tc->getCpuPtr()->instCount();
     assert(ticks >= 0 && "hstick compare missed interrupt cycle");
 
-    if (ticks == 0) {
+    if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
         DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
                 (stick_cmpr & mask(63)));
         if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
diff --git a/src/base/cprintf.hh b/src/base/cprintf.hh
index 7f8e33367..cff73a228 100644
--- a/src/base/cprintf.hh
+++ b/src/base/cprintf.hh
@@ -143,20 +143,20 @@ ccprintf(std::ostream &stream, const std::string &format,
 inline void
 ccprintf(std::ostream &stream, const std::string &format, CPRINTF_DECLARATION)
 {
-    ccprintf(stream, format, VARARGS_ALLARGS);
+    ccprintf(stream, format.c_str(), VARARGS_ALLARGS);
 }
 
 inline void
 cprintf(const std::string &format, CPRINTF_DECLARATION)
 {
-    ccprintf(std::cout, format, VARARGS_ALLARGS);
+    ccprintf(std::cout, format.c_str(), VARARGS_ALLARGS);
 }
 
 inline std::string
 csprintf(const std::string &format, CPRINTF_DECLARATION)
 {
     std::stringstream stream;
-    ccprintf(stream, format, VARARGS_ALLARGS);
+    ccprintf(stream, format.c_str(), VARARGS_ALLARGS);
     return stream.str();
 }
 
diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 66c5955d7..a018c4837 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -251,6 +251,7 @@ VectorPrint::operator()(std::ostream &stream) const
     ScalarPrint print;
     print.name = name;
     print.desc = desc;
+    print.compat = compat;
     print.precision = precision;
     print.descriptions = descriptions;
     print.flags = flags;
diff --git a/src/base/trace.cc b/src/base/trace.cc
index 2dde1f688..0a7e6e833 100644
--- a/src/base/trace.cc
+++ b/src/base/trace.cc
@@ -192,22 +192,20 @@ dumpStatus()
 
 
 // add a set of functions that can easily be invoked from gdb
-extern "C" {
-    void
-    setTraceFlag(const char *string)
-    {
-        Trace::changeFlag(string, true);
-    }
+void
+setTraceFlag(const char *string)
+{
+    Trace::changeFlag(string, true);
+}
 
-    void
-    clearTraceFlag(const char *string)
-    {
-        Trace::changeFlag(string, false);
-    }
+void
+clearTraceFlag(const char *string)
+{
+    Trace::changeFlag(string, false);
+}
 
-    void
-    dumpTraceStatus()
-    {
-        Trace::dumpStatus();
-    }
-/* extern "C" */ }
+void
+dumpTraceStatus()
+{
+    Trace::dumpStatus();
+}
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index cb17d98d3..a36db1963 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -116,6 +116,7 @@ baseFlags = [
     'ISP',
     'IdeCtrl',
     'IdeDisk',
+    'Iob',
     'Interrupt',
     'LLSC',
     'LSQ',
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 8b3e9a11e..607cf1066 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -369,7 +369,7 @@ MemTest::tick()
         //This means we assume CPU does write forwarding to reads that alias something
         //in the cpu store buffer.
         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
-            delete result;
+            delete [] result;
             delete req;
             return;
         }
diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index 7ab8bfcb8..438218df2 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -138,14 +138,12 @@ BreakPCEvent::process(ThreadContext *tc)
 }
 
 #if FULL_SYSTEM
-extern "C"
 void
 sched_break_pc_sys(System *sys, Addr addr)
 {
     new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
 }
 
-extern "C"
 void
 sched_break_pc(Addr addr)
 {
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index f6c109127..9feb09851 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -301,7 +301,7 @@ BaseSimpleCPU::post_interrupt(int int_num, int index)
     BaseCPU::post_interrupt(int_num, index);
 
     if (thread->status() == ThreadContext::Suspended) {
-                DPRINTF(IPI,"Suspended Processor awoke\n");
+                DPRINTF(Quiesce,"Suspended Processor awoke\n");
         thread->activate();
     }
 }
diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc
index 6bd40b631..e686e51f7 100644
--- a/src/dev/sparc/iob.cc
+++ b/src/dev/sparc/iob.cc
@@ -192,6 +192,8 @@ Iob::writeIob(PacketPtr pkt)
             data = pkt->get<uint64_t>();
             intMan[index].cpu = bits(data,12,8);
             intMan[index].vector = bits(data,5,0);
+            DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index,
+                    intMan[index].cpu, intMan[index].vector);
             return;
         }
 
@@ -201,11 +203,14 @@ Iob::writeIob(PacketPtr pkt)
             intCtl[index].mask = bits(data,2,2);
             if (bits(data,1,1))
                 intCtl[index].pend = false;
+            DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index,
+                    intCtl[index].pend, bits(data,2,2));
             return;
         }
 
         if (accessAddr == JIntVecAddr) {
             jIntVec = bits(pkt->get<uint64_t>(), 5,0);
+            DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec);
             return;
         }
 
@@ -237,11 +242,15 @@ Iob::writeJBus(PacketPtr pkt)
             index = (accessAddr - JIntBusyAddr) >> 3;
             data = pkt->get<uint64_t>();
             jIntBusy[index].busy = bits(data,5,5);
+            DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index,
+                    jIntBusy[index].busy);
             return;
         }
         if (accessAddr == JIntABusyAddr) {
             data = pkt->get<uint64_t>();
             jIntBusy[cpuid].busy = bits(data,5,5);
+            DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid,
+                    jIntBusy[cpuid].busy);
             return;
         };
 
@@ -256,6 +265,8 @@ Iob::receiveDeviceInterrupt(DeviceId devid)
         return;
     intCtl[devid].mask = true;
     intCtl[devid].pend = true;
+    DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n",
+            devid, intMan[devid].cpu, intMan[devid].vector);
     ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
 }
 
@@ -269,6 +280,8 @@ Iob::generateIpi(Type type, int cpu_id, int vector)
 
     switch (type) {
       case 0: // interrupt
+        DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d vec %d\n",
+                cpu_id, vector);
         ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
         break;
       case 1: // reset
@@ -279,9 +292,11 @@ Iob::generateIpi(Type type, int cpu_id, int vector)
         sys->threadContexts[cpu_id]->activate();
         break;
       case 2: // idle -- this means stop executing and don't wake on interrupts
+        DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id);
         sys->threadContexts[cpu_id]->halt();
         break;
       case 3: // resume
+        DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id);
         sys->threadContexts[cpu_id]->activate();
         break;
       default:
@@ -297,6 +312,9 @@ Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
     if (jIntBusy[cpu_id].busy)
         return false;
 
+    DPRINTF(Iob, "Receiving jBus interrupt: %d for cpu %d vec %d\n",
+            source, cpu_id, jIntVec);
+
     jIntBusy[cpu_id].busy = true;
     jIntBusy[cpu_id].source = source;
     jBusData0[cpu_id] = d0;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 056f6033f..5c6ab0950 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -570,8 +570,10 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
         }
     }
     while (!writebacks.empty()) {
-        missQueue->doWriteback(writebacks.front());
+        PacketPtr wbPkt = writebacks.front();
+        missQueue->doWriteback(wbPkt);
         writebacks.pop_front();
+        delete wbPkt;
     }
 
     DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(),
@@ -581,12 +583,7 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
         // Hit
         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
         // clear dirty bit if write through
-        if (pkt->needsResponse())
-            respond(pkt, curTick+lat);
-        if (pkt->cmd == MemCmd::Writeback) {
-            //Signal that you can kill the pkt/req
-            pkt->flags |= SATISFIED;
-        }
+        respond(pkt, curTick+lat);
         return true;
     }
 
@@ -604,14 +601,14 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
     if (pkt->flags & SATISFIED) {
         // happens when a store conditional fails because it missed
         // the cache completely
-        if (pkt->needsResponse())
-            respond(pkt, curTick+lat);
+        respond(pkt, curTick+lat);
     } else {
         missQueue->handleMiss(pkt, size, curTick + hitLatency);
     }
 
-    if (pkt->cmd == MemCmd::Writeback) {
+    if (!pkt->needsResponse()) {
         //Need to clean up the packet on a writeback miss, but leave the request
+        //for the next level.
         delete pkt;
     }
 
@@ -721,8 +718,10 @@ Cache<TagStore,Coherence>::handleResponse(PacketPtr &pkt)
             blk = handleFill(blk, (MSHR*)pkt->senderState,
                                    new_state, writebacks, pkt);
             while (!writebacks.empty()) {
-                    missQueue->doWriteback(writebacks.front());
-                    writebacks.pop_front();
+                PacketPtr wbPkt = writebacks.front();
+                missQueue->doWriteback(wbPkt);
+                writebacks.pop_front();
+                delete wbPkt;
             }
         }
         missQueue->handleResponse(pkt, curTick + hitLatency);
@@ -1040,8 +1039,10 @@ return 0;
             // There was a cache hit.
             // Handle writebacks if needed
             while (!writebacks.empty()){
-                memSidePort->sendAtomic(writebacks.front());
+                PacketPtr wbPkt = writebacks.front();
+                memSidePort->sendAtomic(wbPkt);
                 writebacks.pop_front();
+                delete wbPkt;
             }
 
             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index bcd0d3df3..65e115256 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -222,7 +222,6 @@ EventQueue::dump()
     cprintf("============================================================\n");
 }
 
-extern "C"
 void
 dumpMainQueue()
 {