tests: Move ISA-independent tests to the NULL ISA

This patch simply takes a first step to use the NULL ISA build for
tests that do not make use of a CPU. Most of the Ruby tests could go
the same way, but to avoid duplicating a lot of compilation targets
that will have to wait until Ruby is built as a library and linked in
independently.

--HG--
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/null/none/memtest/simerr
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/null/none/memtest/simout
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simerr
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt

11 files changed, 3 insertions, 1 deletions

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
index 1f567a1b9..1f567a1b9 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
index 014cde607..014cde607 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/null/none/memtest/simout
index 077a1416b..077a1416b 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simout
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index 6f84c5ba1..6f84c5ba1 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr
index cfdf73ce9..cfdf73ce9 100755
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr
diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
index d1faa751a..d1faa751a 100755
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
index 4e4b75a44..4e4b75a44 100644
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simerr
index e69de29bb..e69de29bb 100755
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simerr
diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
index 727a89c99..727a89c99 100755
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
index 14b3c1d80..14b3c1d80 100644
--- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
diff --git a/tests/run.py b/tests/run.py
index bc76717c0..461813559 100644
--- a/tests/run.py
+++ b/tests/run.py
@@ -192,8 +192,10 @@ def initCPUs(sys):
     def initCPU(cpu):
         # We might actually have a MemTest object or something similar
         # here that just pretends to be a CPU.
-        if isinstance(cpu, BaseCPU):
+        try:
             cpu.createThreads()
+        except:
+            pass
 
     # The CPU attribute doesn't exist in some cases, e.g. the Ruby
     # testers.