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authorGabe Black <gblack@eecs.umich.edu>2007-12-01 23:06:52 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-12-01 23:06:52 -0800
commit67fee0102648eb597c8c2a368da5f37f4b13b78b (patch)
tree270ebdc88cf148df97c0dba8cf3eb4ae98d81137
parent988c6f227afbd2048df2eeae55aed29a1addcab7 (diff)
downloadgem5-67fee0102648eb597c8c2a368da5f37f4b13b78b.tar.xz
X86: Fix a copy paste error in the bts microcode.
--HG-- extra : convert_revision : c4ac007d35ac13211f9816f1104c84f2b447ddba
-rw-r--r--src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
index 883ec4411..babd4a385 100644
--- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
+++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
@@ -128,7 +128,7 @@ def macroop BTC_P_I {
ldst t1, seg, [1, t2, t7]
sexti t0, t1, imm, flags=(CF,)
xor t1, t1, t3
- st t1, seg, [scale, index, t2], disp
+ st t1, seg, [1, t2, t7], disp
};
def macroop BTC_R_R {
@@ -159,7 +159,7 @@ def macroop BTC_P_R {
ldst t1, seg, [1, t2, t7]
sext t0, t1, reg, flags=(CF,)
xor t1, t1, t3
- st t1, seg, [scale, index, t2], disp
+ st t1, seg, [1, t2, t7], disp
};
def macroop BTR_R_I {
@@ -193,7 +193,7 @@ def macroop BTR_P_I {
ldst t1, seg, [1, t2, t7]
sexti t0, t1, imm, flags=(CF,)
and t1, t1, t3
- st t1, seg, [scale, index, t2], disp
+ st t1, seg, [1, t2, t7], disp
};
def macroop BTR_R_R {
@@ -224,7 +224,7 @@ def macroop BTR_P_R {
ldst t1, seg, [1, t2, t7]
sext t0, t1, reg, flags=(CF,)
and t1, t1, t3
- st t1, seg, [scale, index, t2], disp
+ st t1, seg, [1, t2, t7], disp
};
def macroop BTS_R_I {
@@ -258,7 +258,7 @@ def macroop BTS_P_I {
ldst t1, seg, [1, t2, t7]
sexti t0, t1, imm, flags=(CF,)
or t1, t1, t3
- st t1, seg, [scale, index, t2], disp
+ st t1, seg, [1, t2, t7], disp
};
def macroop BTS_R_R {
@@ -289,6 +289,6 @@ def macroop BTS_P_R {
ldst t1, seg, [1, t2, t7]
sext t0, t1, reg, flags=(CF,)
or t1, t1, t3
- st t1, seg, [scale, index, t2], disp
+ st t1, seg, [1, t2, t7], disp
};
'''