o3: Fix issue with LLSC ordering and speculation

This patch unlocks the cpu-local monitor when the CPU sees a snoop to a locked
address. Previously we relied on the cache to handle the locking for us, however
some users on the gem5 mailing list reported a case where the cpu speculatively
executes a ll operation after a pending sc operation in the pipeline and that
makes the cache monitor valid. This should handle that case by invaliding the
local monitor.

7 files changed, 126 insertions, 1 deletions

diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 24d028b54..e62ed1654 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -47,12 +59,34 @@
 
 #include "arch/alpha/registers.hh"
 #include "base/misc.hh"
+#include "mem/packet.hh"
 #include "mem/request.hh"
 
 namespace AlphaISA {
 
 template <class XC>
 inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+    // If we see a snoop come into the CPU and we currently have an LLSC
+    // operation pending we need to clear the lock flag if it is to the same
+    // cache line.
+
+    if (!xc->readMiscReg(MISCREG_LOCKFLAG))
+        return;
+
+    Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
+    Addr snoop_addr = pkt->getAddr();
+
+    assert((cacheBlockMask & snoop_addr) == snoop_addr);
+
+    if (locked_addr == snoop_addr)
+        xc->setMiscReg(MISCREG_LOCKFLAG, false);
+}
+
+
+template <class XC>
+inline void
 handleLockedRead(XC *xc, Request *req)
 {
     xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh
index f95542bb0..37973ff98 100644
--- a/src/arch/arm/locked_mem.hh
+++ b/src/arch/arm/locked_mem.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * Copyright (c) 2007-2008 The Florida State University
  * All rights reserved.
@@ -41,12 +53,29 @@
  */
 
 #include "arch/arm/miscregs.hh"
+#include "mem/packet.hh"
 #include "mem/request.hh"
 
 namespace ArmISA
 {
 template <class XC>
 inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+    if (!xc->readMiscReg(MISCREG_LOCKFLAG))
+        return;
+
+    Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
+    Addr snoop_addr = pkt->getAddr();
+
+    assert((cacheBlockMask & snoop_addr) == snoop_addr);
+
+    if (locked_addr == snoop_addr)
+        xc->setMiscReg(MISCREG_LOCKFLAG, false);
+}
+
+template <class XC>
+inline void
 handleLockedRead(XC *xc, Request *req)
 {
     xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 60df8252a..b4003fea9 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006-2007 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -41,10 +53,27 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "debug/LLSC.hh"
+#include "mem/packet.hh"
 #include "mem/request.hh"
 
 namespace MipsISA
 {
+template <class XC>
+inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+    if (!xc->readMiscReg(MISCREG_LLFLAG))
+        return;
+
+    Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
+    Addr snoop_addr = pkt->getAddr();
+
+    assert((cacheBlockMask & snoop_addr) == snoop_addr);
+
+    if (locked_addr == snoop_addr)
+        xc->setMiscReg(MISCREG_LLFLAG, false);
+}
+
 
 template <class XC>
 inline void
diff --git a/src/arch/power/locked_mem.hh b/src/arch/power/locked_mem.hh
index 6141b9ef2..f3d042d5c 100644
--- a/src/arch/power/locked_mem.hh
+++ b/src/arch/power/locked_mem.hh
@@ -41,6 +41,7 @@
  * ISA-specific helper functions for locked memory accesses.
  */
 
+#include "mem/packet.hh"
 #include "mem/request.hh"
 
 namespace PowerISA
@@ -48,6 +49,12 @@ namespace PowerISA
 
 template <class XC>
 inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+}
+
+template <class XC>
+inline void
 handleLockedRead(XC *xc, Request *req)
 {
 }
diff --git a/src/arch/sparc/locked_mem.hh b/src/arch/sparc/locked_mem.hh
index 556fbbdd9..8277ef487 100644
--- a/src/arch/sparc/locked_mem.hh
+++ b/src/arch/sparc/locked_mem.hh
@@ -37,12 +37,19 @@
  * ISA-specific helper functions for locked memory accesses.
  */
 
+#include "mem/packet.hh"
 #include "mem/request.hh"
 
 namespace SparcISA
 {
 template <class XC>
 inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+}
+
+template <class XC>
+inline void
 handleLockedRead(XC *xc, Request *req)
 {
 }
diff --git a/src/arch/x86/locked_mem.hh b/src/arch/x86/locked_mem.hh
index 496486997..c2a8395aa 100644
--- a/src/arch/x86/locked_mem.hh
+++ b/src/arch/x86/locked_mem.hh
@@ -37,12 +37,19 @@
  * ISA-specific helper functions for locked memory accesses.
  */
 
+#include "mem/packet.hh"
 #include "mem/request.hh"
 
 namespace X86ISA
 {
     template <class XC>
     inline void
+    handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+    {
+    }
+
+    template <class XC>
+    inline void
     handleLockedRead(XC *xc, Request *req)
     {
     }
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 8e12e990b..799759557 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2011 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -435,6 +435,18 @@ LSQUnit<Impl>::checkSnoop(PacketPtr pkt)
         cacheBlockMask = ~(bs - 1);
     }
 
+    // Unlock the cpu-local monitor when the CPU sees a snoop to a locked
+    // address. The CPU can speculatively execute a LL operation after a pending
+    // SC operation in the pipeline and that can make the cache monitor the CPU
+    // is connected to valid while it really shouldn't be.
+    for (int x = 0; x < cpu->numActiveThreads(); x++) {
+        ThreadContext *tc = cpu->getContext(x);
+        bool no_squash = cpu->thread[x]->noSquashFromTC;
+        cpu->thread[x]->noSquashFromTC = true;
+        TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
+        cpu->thread[x]->noSquashFromTC = no_squash;
+    }
+
     // If this is the only load in the LSQ we don't care
     if (load_idx == loadTail)
         return;