3 memory system fixes:

1. Update packet's flags properly when a snoop happens
2. Don't allow accesses to read a block's data if the block has outstanding MSHRs.  This avoids a RAW hazard in MP systems that the memory system was not detecting properly earlier (a write required a block to upgrade, and while the upgrade was outstanding, a read came along and read old data).
3. Update MSHR's request upon a response being handled.  If the MSHR has more targets than it can respond to in one cycle, then its request must be properly updated to the new head of the targets list.

src/mem/bus.cc:
    Update packet's flags properly upon snoop.
src/mem/cache/cache_impl.hh:
    Be sure to not allow accesses to a block with outstanding MSHRs.
src/mem/cache/miss/miss_queue.cc:
    Update MSHR's request upon a response being handled.

--HG--
extra : convert_revision : 76a9abc610ca3f1904f075ad21637148a41982d6

3 files changed, 11 insertions, 1 deletions

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index bd721dd68..401dc0186 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -159,8 +159,12 @@ Bus::recvTiming(PacketPtr pkt)
     }
 
     short dest = pkt->getDest();
+
+    // Make sure to clear the snoop commit flag so it doesn't think an
+    // access has been handled twice.
     if (dest == Packet::Broadcast) {
         port = findPort(pkt->getAddr(), pkt->getSrc());
+        pkt->flags &= ~SNOOP_COMMIT;
         if (timingSnoop(pkt, port ? port : interfaces[pkt->getSrc()])) {
             bool success;
 
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 10c244b8e..08e226343 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -545,8 +545,13 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
         //We are determining prefetches on access stream, call prefetcher
         prefetcher->handleMiss(pkt, curTick);
     }
+
+    Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
+
     if (!pkt->req->isUncacheable()) {
-        blk = handleAccess(pkt, lat, writebacks);
+        if (!missQueue->findMSHR(blk_addr)) {
+            blk = handleAccess(pkt, lat, writebacks);
+        }
     } else {
         size = pkt->getSize();
     }
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 1d3e22326..38c5ffa71 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -604,6 +604,7 @@ MissQueue::handleResponse(PacketPtr &pkt, Tick time)
             Packet::Command cmd = mshr->getTarget()->cmd;
             mshr->pkt->setDest(Packet::Broadcast);
             mshr->pkt->result = Packet::Unknown;
+            mshr->pkt->req = mshr->getTarget()->req;
             mq.markPending(mshr, cmd);
             mshr->order = order++;
             cache->setMasterRequest(Request_MSHR, time);