diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-18 22:32:21 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-18 22:32:21 -0400 |
| commit | 796fa429fef8b038278c4a020374149d8b5ef8eb (patch) | |
| tree | 878553b3b7fb002db8df2065cb0a38ea694aa528 | |
| parent | 381c4f6720d477bdf6d90dd2c09a54cd30b9ddd9 (diff) | |
| download | gem5-796fa429fef8b038278c4a020374149d8b5ef8eb.tar.xz | |
Change Packet parameters on Port methods from references to pointers.
--HG--
extra : convert_revision : 7193e70304d4cbe1e4cbe16ce0d8527b2754d066
38 files changed, 528 insertions, 528 deletions
diff --git a/cpu/simple/atomic.cc b/cpu/simple/atomic.cc index 35a69cd4a..c09f16ada 100644 --- a/cpu/simple/atomic.cc +++ b/cpu/simple/atomic.cc @@ -78,21 +78,21 @@ AtomicSimpleCPU::init() } bool -AtomicSimpleCPU::CpuPort::recvTiming(Packet &pkt) +AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt) { panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); return true; } Tick -AtomicSimpleCPU::CpuPort::recvAtomic(Packet &pkt) +AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt) { panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); return curTick; } void -AtomicSimpleCPU::CpuPort::recvFunctional(Packet &pkt) +AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt) { panic("AtomicSimpleCPU doesn't expect recvFunctional callback!"); } @@ -263,7 +263,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) data_read_pkt->addr = data_read_req->getPaddr(); data_read_pkt->size = sizeof(T); - dcache_complete = dcachePort.sendAtomic(*data_read_pkt); + dcache_complete = dcachePort.sendAtomic(data_read_pkt); dcache_access = true; assert(data_read_pkt->result == Success); @@ -345,7 +345,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) data_write_pkt->addr = data_write_req->getPaddr(); data_write_pkt->size = sizeof(T); - dcache_complete = dcachePort.sendAtomic(*data_write_pkt); + dcache_complete = dcachePort.sendAtomic(data_write_pkt); dcache_access = true; assert(data_write_pkt->result == Success); @@ -430,7 +430,7 @@ AtomicSimpleCPU::tick() Fault fault = setupFetchPacket(ifetch_pkt); if (fault == NoFault) { - Tick icache_complete = icachePort.sendAtomic(*ifetch_pkt); + Tick icache_complete = icachePort.sendAtomic(ifetch_pkt); // ifetch_req is initialized to read the instruction directly // into the CPU object's inst field. diff --git a/cpu/simple/atomic.hh b/cpu/simple/atomic.hh index 348308c46..d0ba085f0 100644 --- a/cpu/simple/atomic.hh +++ b/cpu/simple/atomic.hh @@ -90,11 +90,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU protected: - virtual bool recvTiming(Packet &pkt); + virtual bool recvTiming(Packet *pkt); - virtual Tick recvAtomic(Packet &pkt); + virtual Tick recvAtomic(Packet *pkt); - virtual void recvFunctional(Packet &pkt); + virtual void recvFunctional(Packet *pkt); virtual void recvStatusChange(Status status); diff --git a/cpu/simple/timing.cc b/cpu/simple/timing.cc index a511c3dbb..80d3380a5 100644 --- a/cpu/simple/timing.cc +++ b/cpu/simple/timing.cc @@ -60,14 +60,14 @@ TimingSimpleCPU::init() } Tick -TimingSimpleCPU::CpuPort::recvAtomic(Packet &pkt) +TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) { panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); return curTick; } void -TimingSimpleCPU::CpuPort::recvFunctional(Packet &pkt) +TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) { panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); } @@ -192,7 +192,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) data_read_pkt->size = sizeof(T); data_read_pkt->dest = Packet::Broadcast; - if (!dcachePort.sendTiming(*data_read_pkt)) { + if (!dcachePort.sendTiming(data_read_pkt)) { _status = DcacheRetry; dcache_pkt = data_read_pkt; } else { @@ -274,7 +274,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) data_write_pkt->addr = data_write_req->getPaddr(); data_write_pkt->dest = Packet::Broadcast; - if (!dcachePort.sendTiming(*data_write_pkt)) { + if (!dcachePort.sendTiming(data_write_pkt)) { _status = DcacheRetry; dcache_pkt = data_write_pkt; } else { @@ -354,7 +354,7 @@ TimingSimpleCPU::fetch() Fault fault = setupFetchPacket(ifetch_pkt); if (fault == NoFault) { - if (!icachePort.sendTiming(*ifetch_pkt)) { + if (!icachePort.sendTiming(ifetch_pkt)) { // Need to wait for retry _status = IcacheRetry; } else { @@ -406,7 +406,7 @@ TimingSimpleCPU::completeIfetch() bool -TimingSimpleCPU::IcachePort::recvTiming(Packet &pkt) +TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) { cpu->completeIfetch(); return true; @@ -442,9 +442,9 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt) bool -TimingSimpleCPU::DcachePort::recvTiming(Packet &pkt) +TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) { - cpu->completeDataAccess(&pkt); + cpu->completeDataAccess(pkt); return true; } diff --git a/cpu/simple/timing.hh b/cpu/simple/timing.hh index e1b564c69..83be025d9 100644 --- a/cpu/simple/timing.hh +++ b/cpu/simple/timing.hh @@ -77,9 +77,9 @@ class TimingSimpleCPU : public BaseSimpleCPU protected: - virtual Tick recvAtomic(Packet &pkt); + virtual Tick recvAtomic(Packet *pkt); - virtual void recvFunctional(Packet &pkt); + virtual void recvFunctional(Packet *pkt); virtual void recvStatusChange(Status status); @@ -98,7 +98,7 @@ class TimingSimpleCPU : public BaseSimpleCPU protected: - virtual bool recvTiming(Packet &pkt); + virtual bool recvTiming(Packet *pkt); virtual Packet *recvRetry(); }; @@ -113,7 +113,7 @@ class TimingSimpleCPU : public BaseSimpleCPU protected: - virtual bool recvTiming(Packet &pkt); + virtual bool recvTiming(Packet *pkt); virtual Packet *recvRetry(); }; diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 8cae10d2a..f24c09844 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -87,7 +87,7 @@ AlphaConsole::startup() } Tick -AlphaConsole::read(Packet &pkt) +AlphaConsole::read(Packet *pkt) { /** XXX Do we want to push the addr munging to a bus brige or something? So @@ -95,109 +95,109 @@ AlphaConsole::read(Packet &pkt) * machine dependent address swizzle is required? */ - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - pkt.time += pioDelay; - Addr daddr = pkt.addr - pioAddr; + pkt->time += pioDelay; + Addr daddr = pkt->addr - pioAddr; - pkt.allocate(); + pkt->allocate(); - switch (pkt.size) + switch (pkt->size) { case sizeof(uint32_t): switch (daddr) { case offsetof(AlphaAccess, last_offset): - pkt.set(alphaAccess->last_offset); + pkt->set(alphaAccess->last_offset); break; case offsetof(AlphaAccess, version): - pkt.set(alphaAccess->version); + pkt->set(alphaAccess->version); break; case offsetof(AlphaAccess, numCPUs): - pkt.set(alphaAccess->numCPUs); + pkt->set(alphaAccess->numCPUs); break; case offsetof(AlphaAccess, intrClockFrequency): - pkt.set(alphaAccess->intrClockFrequency); + pkt->set(alphaAccess->intrClockFrequency); break; default: /* Old console code read in everyting as a 32bit int * we now break that for better error checking. */ - pkt.result = BadAddress; + pkt->result = BadAddress; } DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, - pkt.get<uint32_t>()); + pkt->get<uint32_t>()); break; case sizeof(uint64_t): switch (daddr) { case offsetof(AlphaAccess, inputChar): - pkt.set(console->console_in()); + pkt->set(console->console_in()); break; case offsetof(AlphaAccess, cpuClock): - pkt.set(alphaAccess->cpuClock); + pkt->set(alphaAccess->cpuClock); break; case offsetof(AlphaAccess, mem_size): - pkt.set(alphaAccess->mem_size); + pkt->set(alphaAccess->mem_size); break; case offsetof(AlphaAccess, kernStart): - pkt.set(alphaAccess->kernStart); + pkt->set(alphaAccess->kernStart); break; case offsetof(AlphaAccess, kernEnd): - pkt.set(alphaAccess->kernEnd); + pkt->set(alphaAccess->kernEnd); break; case offsetof(AlphaAccess, entryPoint): - pkt.set(alphaAccess->entryPoint); + pkt->set(alphaAccess->entryPoint); break; case offsetof(AlphaAccess, diskUnit): - pkt.set(alphaAccess->diskUnit); + pkt->set(alphaAccess->diskUnit); break; case offsetof(AlphaAccess, diskCount): - pkt.set(alphaAccess->diskCount); + pkt->set(alphaAccess->diskCount); break; case offsetof(AlphaAccess, diskPAddr): - pkt.set(alphaAccess->diskPAddr); + pkt->set(alphaAccess->diskPAddr); break; case offsetof(AlphaAccess, diskBlock): - pkt.set(alphaAccess->diskBlock); + pkt->set(alphaAccess->diskBlock); break; case offsetof(AlphaAccess, diskOperation): - pkt.set(alphaAccess->diskOperation); + pkt->set(alphaAccess->diskOperation); break; case offsetof(AlphaAccess, outputChar): - pkt.set(alphaAccess->outputChar); + pkt->set(alphaAccess->outputChar); break; default: int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / sizeof(alphaAccess->cpuStack[0]); if (cpunum >= 0 && cpunum < 64) - pkt.set(alphaAccess->cpuStack[cpunum]); + pkt->set(alphaAccess->cpuStack[cpunum]); else panic("Unknown 64bit access, %#x\n", daddr); } DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, - pkt.get<uint64_t>()); + pkt->get<uint64_t>()); break; default: - pkt.result = BadAddress; + pkt->result = BadAddress; } - if (pkt.result == Unknown) pkt.result = Success; + if (pkt->result == Unknown) pkt->result = Success; return pioDelay; } Tick -AlphaConsole::write(Packet &pkt) +AlphaConsole::write(Packet *pkt) { - pkt.time += pioDelay; + pkt->time += pioDelay; - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); - Addr daddr = pkt.addr - pioAddr; + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + Addr daddr = pkt->addr - pioAddr; - uint64_t val = pkt.get<uint64_t>(); - assert(pkt.size == sizeof(uint64_t)); + uint64_t val = pkt->get<uint64_t>(); + assert(pkt->size == sizeof(uint64_t)); switch (daddr) { case offsetof(AlphaAccess, diskUnit): @@ -240,7 +240,7 @@ AlphaConsole::write(Packet &pkt) panic("Unknown 64bit access, %#x\n", daddr); } - pkt.result = Success; + pkt->result = Success; return pioDelay; } diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh index 05aec5ec1..34d21e15c 100644 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@ -116,8 +116,8 @@ class AlphaConsole : public BasicPioDevice /** * memory mapped reads and writes */ - virtual Tick read(Packet &pkt); - virtual Tick write(Packet &pkt); + virtual Tick read(Packet *pkt); + virtual Tick write(Packet *pkt); /** * standard serialization routines for checkpointing diff --git a/dev/baddev.cc b/dev/baddev.cc index dcabdbe0a..66fbd8a86 100644 --- a/dev/baddev.cc +++ b/dev/baddev.cc @@ -51,13 +51,13 @@ BadDevice::BadDevice(Params *p) } Tick -BadDevice::read(Packet &pkt) +BadDevice::read(Packet *pkt) { panic("Device %s not imlpmented\n", devname); } Tick -BadDevice::write(Packet &pkt) +BadDevice::write(Packet *pkt) { panic("Device %s not imlpmented\n", devname); } diff --git a/dev/baddev.hh b/dev/baddev.hh index 4cf0d6ba4..35ae0382a 100644 --- a/dev/baddev.hh +++ b/dev/baddev.hh @@ -65,8 +65,8 @@ class BadDevice : public BasicPioDevice */ BadDevice(Params *p); - virtual Tick read(Packet &pkt); - virtual Tick write(Packet &pkt); + virtual Tick read(Packet *pkt); + virtual Tick write(Packet *pkt); }; #endif // __DEV_BADDEV_HH__ diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index abdbe5d0a..cedd5c53e 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -423,39 +423,39 @@ IdeController::writeConfig(int offset, const uint32_t data) } Tick -IdeController::read(Packet &pkt) +IdeController::read(Packet *pkt) { Addr offset; IdeChannel channel; IdeRegType reg_type; int disk; - pkt.time += pioDelay; - pkt.allocate(); - if (pkt.size != 1 && pkt.size != 2 && pkt.size !=4) - panic("Bad IDE read size: %d\n", pkt.size); + pkt->time += pioDelay; + pkt->allocate(); + if (pkt->size != 1 && pkt->size != 2 && pkt->size !=4) + panic("Bad IDE read size: %d\n", pkt->size); - parseAddr(pkt.addr, offset, channel, reg_type); + parseAddr(pkt->addr, offset, channel, reg_type); if (!io_enabled) { - pkt.result = Success; + pkt->result = Success; return pioDelay; } switch (reg_type) { case BMI_BLOCK: - switch (pkt.size) { + switch (pkt->size) { case sizeof(uint8_t): - pkt.set(bmi_regs.data[offset]); + pkt->set(bmi_regs.data[offset]); break; case sizeof(uint16_t): - pkt.set(*(uint16_t*)&bmi_regs.data[offset]); + pkt->set(*(uint16_t*)&bmi_regs.data[offset]); break; case sizeof(uint32_t): - pkt.set(*(uint32_t*)&bmi_regs.data[offset]); + pkt->set(*(uint32_t*)&bmi_regs.data[offset]); break; default: - panic("IDE read of BMI reg invalid size: %#x\n", pkt.size); + panic("IDE read of BMI reg invalid size: %#x\n", pkt->size); } break; @@ -464,53 +464,53 @@ IdeController::read(Packet &pkt) disk = getDisk(channel); if (disks[disk] == NULL) { - pkt.set<uint8_t>(0); + pkt->set<uint8_t>(0); break; } switch (offset) { case DATA_OFFSET: - switch (pkt.size) { + switch (pkt->size) { case sizeof(uint16_t): - disks[disk]->read(offset, reg_type, pkt.getPtr<uint8_t>()); + disks[disk]->read(offset, reg_type, pkt->getPtr<uint8_t>()); break; case sizeof(uint32_t): - disks[disk]->read(offset, reg_type, pkt.getPtr<uint8_t>()); + disks[disk]->read(offset, reg_type, pkt->getPtr<uint8_t>()); disks[disk]->read(offset, reg_type, - pkt.getPtr<uint8_t>() + sizeof(uint16_t)); + pkt->getPtr<uint8_t>() + sizeof(uint16_t)); break; default: - panic("IDE read of data reg invalid size: %#x\n", pkt.size); + panic("IDE read of data reg invalid size: %#x\n", pkt->size); } break; default: - if (pkt.size == sizeof(uint8_t)) { - disks[disk]->read(offset, reg_type, pkt.getPtr<uint8_t>()); + if (pkt->size == sizeof(uint8_t)) { + disks[disk]->read(offset, reg_type, pkt->getPtr<uint8_t>()); } else - panic("IDE read of command reg of invalid size: %#x\n", pkt.size); + panic("IDE read of command reg of invalid size: %#x\n", pkt->size); } break; default: panic("IDE controller read of unknown register block type!\n"); } - if (pkt.size == 1) + if (pkt->size == 1) DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n", - offset, pkt.size, (uint32_t)pkt.get<uint8_t>()); - else if (pkt.size == 2) + offset, pkt->size, (uint32_t)pkt->get<uint8_t>()); + else if (pkt->size == 2) DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n", - offset, pkt.size, pkt.get<uint16_t>()); + offset, pkt->size, pkt->get<uint16_t>()); else DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n", - offset, pkt.size, pkt.get<uint32_t>()); + offset, pkt->size, pkt->get<uint32_t>()); - pkt.result = Success; + pkt->result = Success; return pioDelay; } Tick -IdeController::write(Packet &pkt) +IdeController::write(Packet *pkt) { Addr offset; IdeChannel channel; @@ -518,12 +518,12 @@ IdeController::write(Packet &pkt) int disk; uint8_t oldVal, newVal; - pkt.time += pioDelay; + pkt->time += pioDelay; - parseAddr(pkt.addr, offset, channel, reg_type); + parseAddr(pkt->addr, offset, channel, reg_type); if (!io_enabled) { - pkt.result = Success; + pkt->result = Success; DPRINTF(IdeCtrl, "io not enabled\n"); return pioDelay; } @@ -531,7 +531,7 @@ IdeController::write(Packet &pkt) switch (reg_type) { case BMI_BLOCK: if (!bm_enabled) { - pkt.result = Success; + pkt->result = Success; return pioDelay; } @@ -539,14 +539,14 @@ IdeController::write(Packet &pkt) // Bus master IDE command register case BMIC1: case BMIC0: - if (pkt.size != sizeof(uint8_t)) - panic("Invalid BMIC write size: %x\n", pkt.size); + if (pkt->size != sizeof(uint8_t)) + panic("Invalid BMIC write size: %x\n", pkt->size); // select the current disk based on DEV bit disk = getDisk(channel); oldVal = bmi_regs.chan[channel].bmic; - newVal = pkt.get<uint8_t>(); + newVal = pkt->get<uint8_t>(); // if a DMA transfer is in progress, R/W control cannot change if (oldVal & SSBM) { @@ -595,11 +595,11 @@ IdeController::write(Packet &pkt) // Bus master IDE status register case BMIS0: case BMIS1: - if (pkt.size != sizeof(uint8_t)) - panic("Invalid BMIS write size: %x\n", pkt.size); + if (pkt->size != sizeof(uint8_t)) + panic("Invalid BMIS write size: %x\n", pkt->size); oldVal = bmi_regs.chan[channel].bmis; - newVal = pkt.get<uint8_t>(); + newVal = pkt->get<uint8_t>(); // the BMIDEA bit is RO newVal |= (oldVal & BMIDEA); @@ -622,28 +622,28 @@ IdeController::write(Packet &pkt) case BMIDTP0: case BMIDTP1: { - if (pkt.size != sizeof(uint32_t)) - panic("Invalid BMIDTP write size: %x\n", pkt.size); + if (pkt->size != sizeof(uint32_t)) + panic("Invalid BMIDTP write size: %x\n", pkt->size); - bmi_regs.chan[channel].bmidtp = htole(pkt.get<uint32_t>() & ~0x3); + bmi_regs.chan[channel].bmidtp = htole(pkt->get<uint32_t>() & ~0x3); } break; default: - if (pkt.size != sizeof(uint8_t) && - pkt.size != sizeof(uint16_t) && - pkt.size != sizeof(uint32_t)) + if (pkt->size != sizeof(uint8_t) && + pkt->size != sizeof(uint16_t) && + pkt->size != sizeof(uint32_t)) panic("IDE controller write of invalid write size: %x\n", - pkt.size); + pkt->size); // do a default copy of data into the registers - memcpy(&bmi_regs.data[offset], pkt.getPtr<uint8_t>(), pkt.size); + memcpy(&bmi_regs.data[offset], pkt->getPtr<uint8_t>(), pkt->size); } break; case COMMAND_BLOCK: if (offset == IDE_SELECT_OFFSET) { uint8_t *devBit = &dev[channel]; - *devBit = (letoh(pkt.get<uint8_t>()) & IDE_SELECT_DEV_BIT) ? 1 : 0; + *devBit = (letoh(pkt->get<uint8_t>()) & IDE_SELECT_DEV_BIT) ? 1 : 0; } // fall-through ok! case CONTROL_BLOCK: @@ -654,43 +654,43 @@ IdeController::write(Packet &pkt) switch (offset) { case DATA_OFFSET: - switch (pkt.size) { + switch (pkt->size) { case sizeof(uint16_t): - disks[disk]->write(offset, reg_type, pkt.getPtr<uint8_t>()); + disks[disk]->write(offset, reg_type, pkt->getPtr<uint8_t>()); break; case sizeof(uint32_t): - disks[disk]->write(offset, reg_type, pkt.getPtr<uint8_t>()); - disks[disk]->write(offset, reg_type, pkt.getPtr<uint8_t>() + + disks[disk]->write(offset, reg_type, pkt->getPtr<uint8_t>()); + disks[disk]->write(offset, reg_type, pkt->getPtr<uint8_t>() + sizeof(uint16_t)); break; default: - panic("IDE write of data reg invalid size: %#x\n", pkt.size); + panic("IDE write of data reg invalid size: %#x\n", pkt->size); } break; default: - if (pkt.size == sizeof(uint8_t)) { - disks[disk]->write(offset, reg_type, pkt.getPtr<uint8_t>()); + if (pkt->size == sizeof(uint8_t)) { + disks[disk]->write(offset, reg_type, pkt->getPtr<uint8_t>()); } else - panic("IDE write of command reg of invalid size: %#x\n", pkt.size); + panic("IDE write of command reg of invalid size: %#x\n", pkt->size); } break; default: panic("IDE controller write of unknown register block type!\n"); } - if (pkt.size == 1) + if (pkt->size == 1) DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n", - offset, pkt.size, (uint32_t)pkt.get<uint8_t>()); - else if (pkt.size == 2) + offset, pkt->size, (uint32_t)pkt->get<uint8_t>()); + else if (pkt->size == 2) DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n", - offset, pkt.size, pkt.get<uint16_t>()); + offset, pkt->size, pkt->get<uint16_t>()); else DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n", - offset, pkt.size, pkt.get<uint32_t>()); + offset, pkt->size, pkt->get<uint32_t>()); - pkt.result = Success; + pkt->result = Success; return pioDelay; } diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh index a074f4f97..dda2cbb66 100644 --- a/dev/ide_ctrl.hh +++ b/dev/ide_ctrl.hh @@ -215,14 +215,14 @@ class IdeController : public PciDev * @param pkt Packet describing what is to be read * @return The amount of time to complete this request */ - virtual Tick read(Packet &pkt); + virtual Tick read(Packet *pkt); /** * Write a done field for a given target. * @param pkt Packet describing what is to be written * @return The amount of time to complete this request */ - virtual Tick write(Packet &pkt); + virtual Tick write(Packet *pkt); /** * Serialize this object to the given output stream. diff --git a/dev/io_device.cc b/dev/io_device.cc index aa411d132..634b11b7e 100644 --- a/dev/io_device.cc +++ b/dev/io_device.cc @@ -36,13 +36,13 @@ PioPort::PioPort(PioDevice *dev, Platform *p) Tick -PioPort::recvAtomic(Packet &pkt) +PioPort::recvAtomic(Packet *pkt) { return device->recvAtomic(pkt); } void -PioPort::recvFunctional(Packet &pkt) +PioPort::recvFunctional(Packet *pkt) { device->recvAtomic(pkt); } @@ -70,15 +70,15 @@ PioPort::SendEvent::process() if (port->Port::sendTiming(packet) == Success) return; - port->transmitList.push_back(&packet); + port->transmitList.push_back(packet); } bool -PioPort::recvTiming(Packet &pkt) +PioPort::recvTiming(Packet *pkt) { device->recvAtomic(pkt); - sendTiming(pkt, pkt.time-pkt.req->getTime()); + sendTiming(pkt, pkt->time - pkt->req->getTime()); return Success; } @@ -110,17 +110,17 @@ DmaPort::DmaPort(DmaDevice *dev, Platform *p) { } bool -DmaPort::recvTiming(Packet &pkt) +DmaPort::recvTiming(Packet *pkt) { - if (pkt.senderState) { + if (pkt->senderState) { DmaReqState *state; - state = (DmaReqState*)pkt.senderState; - state->completionEvent->schedule(pkt.time - pkt.req->getTime()); - delete pkt.req; - delete &pkt; + state = (DmaReqState*)pkt->senderState; + state->completionEvent->schedule(pkt->time - pkt->req->getTime()); + delete pkt->req; + delete pkt; } else { - delete pkt.req; - delete &pkt; + delete pkt->req; + delete pkt; } return Success; @@ -136,7 +136,7 @@ DmaPort::SendEvent::process() if (port->Port::sendTiming(packet) == Success) return; - port->transmitList.push_back(&packet); + port->transmitList.push_back(packet); } Packet * @@ -209,7 +209,7 @@ DmaPort::sendDma(Packet *pkt) if (sendTiming(pkt) == Failure) transmitList.push_back(&packet); } else if (state == Atomic) {*/ - sendAtomic(*pkt); + sendAtomic(pkt); if (pkt->senderState) { DmaReqState *state = (DmaReqState*)pkt->senderState; state->completionEvent->schedule(curTick + (pkt->time - pkt->req->getTime()) +1); @@ -222,7 +222,7 @@ DmaPort::sendDma(Packet *pkt) /* } else if (state == Functional) { sendFunctional(pkt); // Is this correct??? - completionEvent->schedule(pkt.req->responseTime - pkt.req->requestTime); + completionEvent->schedule(pkt->req->responseTime - pkt->req->requestTime); completionEvent == NULL; } else panic("Unknown memory command state."); diff --git a/dev/io_device.hh b/dev/io_device.hh index e492ccf0b..8b23422dd 100644 --- a/dev/io_device.hh +++ b/dev/io_device.hh @@ -68,11 +68,11 @@ class PioPort : public Port /** The current status of the peer(bus) that we are connected to. */ Status peerStatus; - virtual bool recvTiming(Packet &pkt); + virtual bool recvTiming(Packet *pkt); - virtual Tick recvAtomic(Packet &pkt); + virtual Tick recvAtomic(Packet *pkt); - virtual void recvFunctional(Packet &pkt) ; + virtual void recvFunctional(Packet *pkt) ; virtual void recvStatusChange(Status status) { peerStatus = status; } @@ -87,9 +87,9 @@ class PioPort : public Port class SendEvent : public Event { PioPort *port; - Packet packet; + Packet *packet; - SendEvent(PioPort *p, Packet &pkt, Tick t) + SendEvent(PioPort *p, Packet *pkt, Tick t) : Event(&mainEventQueue), packet(pkt) { schedule(curTick + t); } @@ -102,7 +102,7 @@ class PioPort : public Port }; /** Schedule a sendTiming() event to be called in the future. */ - void sendTiming(Packet &pkt, Tick time) + void sendTiming(Packet *pkt, Tick time) { new PioPort::SendEvent(this, pkt, time); } /** This function pops the last element off the transmit list and sends it.*/ @@ -137,10 +137,10 @@ class DmaPort : public Port /** Number of outstanding packets the dma port has. */ int pendingCount; - virtual bool recvTiming(Packet &pkt); - virtual Tick recvAtomic(Packet &pkt) + virtual bool recvTiming(Packet *pkt); + virtual Tick recvAtomic(Packet *pkt) { panic("dma port shouldn't be used for pio access."); } - virtual void recvFunctional(Packet &pkt) + virtual void recvFunctional(Packet *pkt) { panic("dma port shouldn't be used for pio access."); } virtual void recvStatusChange(Status status) @@ -154,9 +154,9 @@ class DmaPort : public Port class SendEvent : public Event { DmaPort *port; - Packet packet; + Packet *packet; - SendEvent(PioPort *p, Packet &pkt, Tick t) + SendEvent(PioPort *p, Packet *pkt, Tick t) : Event(&mainEventQueue), packet(pkt) { schedule(curTick + t); } @@ -206,22 +206,22 @@ class PioDevice : public MemObject /** As far as the devices are concerned they only accept atomic transactions * which are converted to either a write or a read. */ - Tick recvAtomic(Packet &pkt) - { return pkt.cmd == Read ? this->read(pkt) : this->write(pkt); } + Tick recvAtomic(Packet *pkt) + { return pkt->cmd == Read ? this->read(pkt) : this->write(pkt); } /** Pure virtual function that the device must implement. Called when a read * command is recieved by the port. * @param pkt Packet describing this request * @return number of ticks it took to complete */ - virtual Tick read(Packet &pkt) = 0; + virtual Tick read(Packet *pkt) = 0; /** Pure virtual function that the device must implement. Called when a * write command is recieved by the port. * @param pkt Packet describing this request * @return number of ticks it took to complete */ - virtual Tick write(Packet &pkt) = 0; + virtual Tick write(Packet *pkt) = 0; public: /** Params struct which is extended through each device based on the diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc index 2f392a41a..9717226b7 100644 --- a/dev/isa_fake.cc +++ b/dev/isa_fake.cc @@ -49,40 +49,40 @@ IsaFake::IsaFake(Params *p) } Tick -IsaFake::read(Packet &pkt) +IsaFake::read(Packet *pkt) { - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - pkt.time += pioDelay; + pkt->time += pioDelay; - DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size); + DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->addr, pkt->size); - switch (pkt.size) { - pkt.set(0xFFFFFFFFFFFFFFFFULL); + switch (pkt->size) { + pkt->set(0xFFFFFFFFFFFFFFFFULL); break; case sizeof(uint32_t): - pkt.set((uint32_t)0xFFFFFFFF); + pkt->set((uint32_t)0xFFFFFFFF); break; case sizeof(uint16_t): - pkt.set((uint16_t)0xFFFF); + pkt->set((uint16_t)0xFFFF); break; case sizeof(uint8_t): - pkt.set((uint8_t)0xFF); + pkt->set((uint8_t)0xFF); break; default: panic("invalid access size(?) for PCI configspace!\n"); } - pkt.result = Success; + pkt->result = Success; return pioDelay; } Tick -IsaFake::write(Packet &pkt) +IsaFake::write(Packet *pkt) { - pkt.time += pioDelay; - DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size); - pkt.result = Success; + pkt->time += pioDelay; + DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->addr, pkt->size); + pkt->result = Success; return pioDelay; } diff --git a/dev/isa_fake.hh b/dev/isa_fake.hh index 29050833d..65d44f6a5 100644 --- a/dev/isa_fake.hh +++ b/dev/isa_fake.hh @@ -65,14 +65,14 @@ class IsaFake : public BasicPioDevice * @param req The memory request. * @param data Where to put the data. */ - virtual Tick read(Packet &pkt); + virtual Tick read(Packet *pkt); /** * All writes are simply ignored. * @param req The memory request. * @param data the data to not write. */ - virtual Tick write(Packet &pkt); + virtual Tick write(Packet *pkt); }; #endif // __TSUNAMI_FAKE_HH__ diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 82b14388c..5e27db58d 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -488,17 +488,17 @@ NSGigE::writeConfig(int offset, const uint16_t data) * spec sheet */ Tick -NSGigE::read(Packet &pkt) +NSGigE::read(Packet *pkt) { assert(ioEnable); - pkt.time += pioDelay; - pkt.allocate(); + pkt->time += pioDelay; + pkt->allocate(); //The mask is to give you only the offset into the device register file - Addr daddr = pkt.addr & 0xfff; + Addr daddr = pkt->addr & 0xfff; DPRINTF(EthernetPIO, "read da=%#x pa=%#x size=%d\n", - daddr, pkt.addr, pkt.size); + daddr, pkt->addr, pkt->size); // there are some reserved registers, you can see ns_gige_reg.h and @@ -506,26 +506,26 @@ NSGigE::read(Packet &pkt) if (daddr > LAST && daddr <= RESERVED) { panic("Accessing reserved register"); } else if (daddr > RESERVED && daddr <= 0x3FC) { - if (pkt.size == sizeof(uint8_t)) - readConfig(daddr & 0xff, pkt.getPtr<uint8_t>()); - if (pkt.size == sizeof(uint16_t)) - readConfig(daddr & 0xff, pkt.getPtr<uint16_t>()); - if (pkt.size == sizeof(uint32_t)) - readConfig(daddr & 0xff, pkt.getPtr<uint32_t>()); - pkt.result = Success; + if (pkt->size == sizeof(uint8_t)) + readConfig(daddr & 0xff, pkt->getPtr<uint8_t>()); + if (pkt->size == sizeof(uint16_t)) + readConfig(daddr & 0xff, pkt->getPtr<uint16_t>()); + if (pkt->size == sizeof(uint32_t)) + readConfig(daddr & 0xff, pkt->getPtr<uint32_t>()); + pkt->result = Success; return pioDelay; } else if (daddr >= MIB_START && daddr <= MIB_END) { // don't implement all the MIB's. hopefully the kernel // doesn't actually DEPEND upon their values // MIB are just hardware stats keepers - pkt.set<uint32_t>(0); - pkt.result = Success; + pkt->set<uint32_t>(0); + pkt->result = Success; return pioDelay; } else if (daddr > 0x3FC) panic("Something is messed up!\n"); - assert(pkt.size == sizeof(uint32_t)); - uint32_t ® = *pkt.getPtr<uint32_t>(); + assert(pkt->size == sizeof(uint32_t)); + uint32_t ® = *pkt->getPtr<uint32_t>(); uint16_t rfaddr; switch (daddr) { @@ -715,37 +715,37 @@ NSGigE::read(Packet &pkt) DPRINTF(EthernetPIO, "read from %#x: data=%d data=%#x\n", daddr, reg, reg); - pkt.result = Success; + pkt->result = Success; return pioDelay; } Tick -NSGigE::write(Packet &pkt) +NSGigE::write(Packet *pkt) { assert(ioEnable); - Addr daddr = pkt.addr & 0xfff; + Addr daddr = pkt->addr & 0xfff; DPRINTF(EthernetPIO, "write da=%#x pa=%#x size=%d\n", - daddr, pkt.addr, pkt.size); + daddr, pkt->addr, pkt->size); - pkt.time += pioDelay; + pkt->time += pioDelay; if (daddr > LAST && daddr <= RESERVED) { panic("Accessing reserved register"); } else if (daddr > RESERVED && daddr <= 0x3FC) { - if (pkt.size == sizeof(uint8_t)) - writeConfig(daddr & 0xff, pkt.get<uint8_t>()); - if (pkt.size == sizeof(uint16_t)) - writeConfig(daddr & 0xff, pkt.get<uint16_t>()); - if (pkt.size == sizeof(uint32_t)) - writeConfig(daddr & 0xff, pkt.get<uint32_t>()); - pkt.result = Success; + if (pkt->size == sizeof(uint8_t)) + writeConfig(daddr & 0xff, pkt->get<uint8_t>()); + if (pkt->size == sizeof(uint16_t)) + writeConfig(daddr & 0xff, pkt->get<uint16_t>()); + if (pkt->size == sizeof(uint32_t)) + writeConfig(daddr & 0xff, pkt->get<uint32_t>()); + pkt->result = Success; return pioDelay; } else if (daddr > 0x3FC) panic("Something is messed up!\n"); - if (pkt.size == sizeof(uint32_t)) { - uint32_t reg = pkt.get<uint32_t>(); + if (pkt->size == sizeof(uint32_t)) { + uint32_t reg = pkt->get<uint32_t>(); uint16_t rfaddr; DPRINTF(EthernetPIO, "write data=%d data=%#x\n", reg, reg); @@ -1131,7 +1131,7 @@ NSGigE::write(Packet &pkt) } else { panic("Invalid Request Size"); } - pkt.result = Success; + pkt->result = Success; return pioDelay; } diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index 7bb422287..51520fd00 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -375,8 +375,8 @@ class NSGigE : public PciDev virtual void writeConfig(int offset, const uint16_t data); - virtual Tick read(Packet &pkt); - virtual Tick write(Packet &pkt); + virtual Tick read(Packet *pkt); + virtual Tick write(Packet *pkt); bool cpuIntrPending() const; void cpuIntrAck() { cpuIntrClear(); } diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index a8c742b07..f278a67cf 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -89,58 +89,58 @@ PciConfigAll::startup() } Tick -PciConfigAll::read(Packet &pkt) +PciConfigAll::read(Packet *pkt) { - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - Addr daddr = pkt.addr - pioAddr; + Addr daddr = pkt->addr - pioAddr; int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; int reg = daddr & 0xFF; - pkt.time += pioDelay; - pkt.allocate(); + pkt->time += pioDelay; + pkt->allocate(); - DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt.addr, daddr, - pkt.size); + DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt->addr, daddr, + pkt->size); - switch (pkt.size) { + switch (pkt->size) { case sizeof(uint32_t): if (devices[device][func] == NULL) - pkt.set<uint32_t>(0xFFFFFFFF); + pkt->set<uint32_t>(0xFFFFFFFF); else - devices[device][func]->readConfig(reg, pkt.getPtr<uint32_t>()); + devices[device][func]->readConfig(reg, pkt->getPtr<uint32_t>()); break; case sizeof(uint16_t): if (devices[device][func] == NULL) - pkt.set<uint16_t>(0xFFFF); + pkt->set<uint16_t>(0xFFFF); else - devices[device][func]->readConfig(reg, pkt.getPtr<uint16_t>()); + devices[device][func]->readConfig(reg, pkt->getPtr<uint16_t>()); break; case sizeof(uint8_t): if (devices[device][func] == NULL) - pkt.set<uint8_t>(0xFF); + pkt->set<uint8_t>(0xFF); else - devices[device][func]->readConfig(reg, pkt.getPtr<uint8_t>()); + devices[device][func]->readConfig(reg, pkt->getPtr<uint8_t>()); break; default: panic("invalid access size(?) for PCI configspace!\n"); } - pkt.result = Success; + pkt->result = Success; return pioDelay; } Tick -PciConfigAll::write(Packet &pkt) +PciConfigAll::write(Packet *pkt) { - pkt.time += pioDelay; + pkt->time += pioDelay; - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); - assert(pkt.size == sizeof(uint8_t) || pkt.size == sizeof(uint16_t) || - pkt.size == sizeof(uint32_t)); - Addr daddr = pkt.addr - pioAddr; + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + assert(pkt->size == sizeof(uint8_t) || pkt->size == sizeof(uint16_t) || + pkt->size == sizeof(uint32_t)); + Addr daddr = pkt->addr - pioAddr; int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; @@ -150,22 +150,22 @@ PciConfigAll::write(Packet &pkt) panic("Attempting to write to config space on non-existant device\n"); DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n", - pkt.addr, pkt.size, pkt.get<uint32_t>()); + pkt->addr, pkt->size, pkt->get<uint32_t>()); - switch (pkt.size) { + switch (pkt->size) { case sizeof(uint8_t): - devices[device][func]->writeConfig(reg, pkt.get<uint8_t>()); + devices[device][func]->writeConfig(reg, pkt->get<uint8_t>()); break; case sizeof(uint16_t): - devices[device][func]->writeConfig(reg, pkt.get<uint16_t>()); + devices[device][func]->writeConfig(reg, pkt->get<uint16_t>()); break; case sizeof(uint32_t): - devices[device][func]->writeConfig(reg, pkt.get<uint32_t>()); + devices[device][func]->writeConfig(reg, pkt->get<uint32_t>()); break; default: panic("invalid pci config write size\n"); } - pkt.result = Success; + pkt->result = Success; return pioDelay; } diff --git a/dev/pciconfigall.hh b/dev/pciconfigall.hh index 2393b445e..df4eae448 100644 --- a/dev/pciconfigall.hh +++ b/dev/pciconfigall.hh @@ -92,7 +92,7 @@ class PciConfigAll : public BasicPioDevice * @param pkt Contains the address of the field to read. * @return Amount of time to do the read */ - virtual Tick read(Packet &pkt); + virtual Tick read(Packet *pkt); /** * Write to PCI config spcae. If the device does not exit the simulator @@ -103,7 +103,7 @@ class PciConfigAll : public BasicPioDevice * @return The fault condition of the access. */ - virtual Tick write(Packet &pkt); + virtual Tick write(Packet *pkt); /** * Start up function to check if more than one person is using an interrupt line diff --git a/dev/sinic.cc b/dev/sinic.cc index f621c1b44..df7e4d167 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -312,51 +312,51 @@ Device::prepareWrite(int cpu, int index) * I/O read of device register */ Tick -Device::read(Packet &pkt) +Device::read(Packet *pkt) { assert(config.command & PCI_CMD_MSE); - assert(pkt.addr >= BARAddrs[0] && pkt.size < BARSize[0]); + assert(pkt->addr >= BARAddrs[0] && pkt->size < BARSize[0]); - int cpu = pkt.req->getCpuNum(); - Addr daddr = pkt.addr - BARAddrs[0]; + int cpu = pkt->req->getCpuNum(); + Addr daddr = pkt->addr - BARAddrs[0]; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; - pkt.time += pioDelay; - pkt.allocate(); + pkt->time += pioDelay; + pkt->allocate(); if (!regValid(raddr)) panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d", - cpu, index, daddr, pkt.addr, pkt.size); + cpu, index, daddr, pkt->addr, pkt->size); const Regs::Info &info = regInfo(raddr); if (!info.read) panic("read %s (write only): " "cpu=%d vnic=%d da=%#x pa=%#x size=%d", - info.name, cpu, index, daddr, pkt.addr, pkt.size); + info.name, cpu, index, daddr, pkt->addr, pkt->size); panic("read %s (invalid size): " "cpu=%d vnic=%d da=%#x pa=%#x size=%d", - info.name, cpu, index, daddr, pkt.addr, pkt.size); + info.name, cpu, index, daddr, pkt->addr, pkt->size); prepareRead(cpu, index); uint64_t value = 0; - if (pkt.size == 4) { + if (pkt->size == 4) { uint32_t reg = regData32(raddr); - pkt.set(reg); + pkt->set(reg); value = reg; } - if (pkt.size == 8) { + if (pkt->size == 8) { uint64_t reg = regData64(raddr); - pkt.set(reg); + pkt->set(reg); value = reg; } DPRINTF(EthernetPIO, "read %s: cpu=%d vnic=%d da=%#x pa=%#x size=%d val=%#x\n", - info.name, cpu, index, daddr, pkt.addr, pkt.size, value); + info.name, cpu, index, daddr, pkt->addr, pkt->size, value); // reading the interrupt status register has the side effect of // clearing it @@ -400,57 +400,57 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result) * I/O write of device register */ Tick -Device::write(Packet &pkt) +Device::write(Packet *pkt) { assert(config.command & PCI_CMD_MSE); - assert(pkt.addr >= BARAddrs[0] && pkt.size < BARSize[0]); + assert(pkt->addr >= BARAddrs[0] && pkt->size < BARSize[0]); - int cpu = pkt.req->getCpuNum(); - Addr daddr = pkt.addr - BARAddrs[0]; + int cpu = pkt->req->getCpuNum(); + Addr daddr = pkt->addr - BARAddrs[0]; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; - pkt.time += pioDelay; + pkt->time += pioDelay; if (!regValid(raddr)) panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d", - cpu, daddr, pkt.addr, pkt.size); + cpu, daddr, pkt->addr, pkt->size); const Regs::Info &info = regInfo(raddr); if (!info.write) panic("write %s (read only): " "cpu=%d vnic=%d da=%#x pa=%#x size=%d", - info.name, cpu, index, daddr, pkt.addr, pkt.size); + info.name, cpu, index, daddr, pkt->addr, pkt->size); - if (pkt.size != info.size) + if (pkt->size != info.size) panic("write %s (invalid size): " "cpu=%d vnic=%d da=%#x pa=%#x size=%d", - info.name, cpu, index, daddr, pkt.addr, pkt.size); + info.name, cpu, index, daddr, pkt->addr, pkt->size); VirtualReg &vnic = virtualRegs[index]; DPRINTF(EthernetPIO, "write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x size=%d\n", - info.name, index, cpu, info.size == 4 ? pkt.get<uint32_t>() : - pkt.get<uint64_t>(), daddr, pkt.addr, pkt.size); + info.name, index, cpu, info.size == 4 ? pkt->get<uint32_t>() : + pkt->get<uint64_t>(), daddr, pkt->addr, pkt->size); prepareWrite(cpu, index); switch (raddr) { case Regs::Config: - changeConfig(pkt.get<uint32_t>()); + changeConfig(pkt->get<uint32_t>()); break; case Regs::Command: - command(pkt.get<uint32_t>()); + command(pkt->get<uint32_t>()); break; case Regs::IntrStatus: - devIntrClear(regs.IntrStatus & pkt.get<uint32_t>()); + devIntrClear(regs.IntrStatus & pkt->get<uint32_t>()); break; case Regs::IntrMask: - devIntrChangeMask(pkt.get<uint32_t>()); + devIntrChangeMask(pkt->get<uint32_t>()); break; case Regs::RxData: @@ -460,9 +460,9 @@ Device::write(Packet &pkt) vnic.rxUnique = rxUnique++; vnic.RxDone = Regs::RxDone_Busy; - vnic.RxData = pkt.get<uint64_t>(); + vnic.RxData = pkt->get<uint64_t>(); - if (Regs::get_RxData_Vaddr(pkt.get<uint64_t>())) { + if (Regs::get_RxData_Vaddr(pkt->get<uint64_t>())) { panic("vtophys not implemented in newmem"); /* Addr vaddr = Regs::get_RxData_Addr(reg64); Addr paddr = vtophys(req->xc, vaddr); @@ -498,7 +498,7 @@ Device::write(Packet &pkt) vnic.txUnique = txUnique++; vnic.TxDone = Regs::TxDone_Busy; - if (Regs::get_TxData_Vaddr(pkt.get<uint64_t>())) { + if (Regs::get_TxData_Vaddr(pkt->get<uint64_t>())) { panic("vtophys won't work here in newmem.\n"); /*Addr vaddr = Regs::get_TxData_Addr(reg64); Addr paddr = vtophys(req->xc, vaddr); diff --git a/dev/sinic.hh b/dev/sinic.hh index a786c3e44..1bb4c77e0 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -262,8 +262,8 @@ class Device : public Base * Memory Interface */ public: - virtual Tick read(Packet &pkt); - virtual Tick write(Packet &pkt); + virtual Tick read(Packet *pkt); + virtual Tick write(Packet *pkt); void prepareIO(int cpu, int index); void prepareRead(int cpu, int index); diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 7b9032f6e..7206a61bb 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -69,76 +69,76 @@ TsunamiCChip::TsunamiCChip(Params *p) } Tick -TsunamiCChip::read(Packet &pkt) +TsunamiCChip::read(Packet *pkt) { - DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size); + DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->addr, pkt->size); - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - pkt.time += pioDelay; - Addr regnum = (pkt.addr - pioAddr) >> 6; - Addr daddr = (pkt.addr - pioAddr); + pkt->time += pioDelay; + Addr regnum = (pkt->addr - pioAddr) >> 6; + Addr daddr = (pkt->addr - pioAddr); - pkt.allocate(); - switch (pkt.size) { + pkt->allocate(); + switch (pkt->size) { case sizeof(uint64_t): if (daddr & TSDEV_CC_BDIMS) { - pkt.set(dim[(daddr >> 4) & 0x3F]); + pkt->set(dim[(daddr >> 4) & 0x3F]); break; } if (daddr & TSDEV_CC_BDIRS) { - pkt.set(dir[(daddr >> 4) & 0x3F]); + pkt->set(dir[(daddr >> 4) & 0x3F]); break; } switch(regnum) { case TSDEV_CC_CSR: - pkt.set(0x0); + pkt->set(0x0); break; case TSDEV_CC_MTR: panic("TSDEV_CC_MTR not implemeted\n"); break; case TSDEV_CC_MISC: - pkt.set((ipint << 8) & 0xF | (itint << 4) & 0xF | - (pkt.req->getCpuNum() & 0x3)); + pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF | + (pkt->req->getCpuNum() & 0x3)); break; case TSDEV_CC_AAR0: case TSDEV_CC_AAR1: case TSDEV_CC_AAR2: case TSDEV_CC_AAR3: - pkt.set(0); + pkt->set(0); break; case TSDEV_CC_DIM0: - pkt.set(dim[0]); + pkt->set(dim[0]); break; case TSDEV_CC_DIM1: - pkt.set(dim[1]); + pkt->set(dim[1]); break; case TSDEV_CC_DIM2: - pkt.set(dim[2]); + pkt->set(dim[2]); break; case TSDEV_CC_DIM3: - pkt.set(dim[3]); + pkt->set(dim[3]); break; case TSDEV_CC_DIR0: - pkt.set(dir[0]); + pkt->set(dir[0]); break; case TSDEV_CC_DIR1: - pkt.set(dir[1]); + pkt->set(dir[1]); break; case TSDEV_CC_DIR2: - pkt.set(dir[2]); + pkt->set(dir[2]); break; case TSDEV_CC_DIR3: - pkt.set(dir[3]); + pkt->set(dir[3]); break; case TSDEV_CC_DRIR: - pkt.set(drir); + pkt->set(drir); break; case TSDEV_CC_PRBEN: panic("TSDEV_CC_PRBEN not implemented\n"); @@ -156,10 +156,10 @@ TsunamiCChip::read(Packet &pkt) panic("TSDEV_CC_MPRx not implemented\n"); break; case TSDEV_CC_IPIR: - pkt.set(ipint); + pkt->set(ipint); break; case TSDEV_CC_ITIR: - pkt.set(itint); + pkt->set(itint); break; default: panic("default in cchip read reached, accessing 0x%x\n"); @@ -173,26 +173,26 @@ TsunamiCChip::read(Packet &pkt) panic("invalid access size(?) for tsunami register!\n"); } DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", - regnum, pkt.size, pkt.get<uint64_t>()); + regnum, pkt->size, pkt->get<uint64_t>()); - pkt.result = Success; + pkt->result = Success; return pioDelay; } Tick -TsunamiCChip::write(Packet &pkt) +TsunamiCChip::write(Packet *pkt) { - pkt.time += pioDelay; + pkt->time += pioDelay; - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); - Addr daddr = pkt.addr - pioAddr; - Addr regnum = (pkt.addr - pioAddr) >> 6 ; + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + Addr daddr = pkt->addr - pioAddr; + Addr regnum = (pkt->addr - pioAddr) >> 6 ; - assert(pkt.size == sizeof(uint64_t)); + assert(pkt->size == sizeof(uint64_t)); - DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt.addr, pkt.get<uint64_t>()); + DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->addr, pkt->get<uint64_t>()); bool supportedWrite = false; @@ -207,7 +207,7 @@ TsunamiCChip::write(Packet &pkt) olddim = dim[number]; olddir = dir[number]; - dim[number] = pkt.get<uint64_t>(); + dim[number] = pkt->get<uint64_t>(); dir[number] = dim[number] & drir; for(int x = 0; x < Tsunami::Max_CPUs; x++) { @@ -244,7 +244,7 @@ TsunamiCChip::write(Packet &pkt) panic("TSDEV_CC_MTR write not implemented\n"); case TSDEV_CC_MISC: uint64_t ipreq; - ipreq = (pkt.get<uint64_t>() >> 12) & 0xF; + ipreq = (pkt->get<uint64_t>() >> 12) & 0xF; //If it is bit 12-15, this is an IPI post if (ipreq) { reqIPI(ipreq); @@ -253,7 +253,7 @@ TsunamiCChip::write(Packet &pkt) //If it is bit 8-11, this is an IPI clear uint64_t ipintr; - ipintr = (pkt.get<uint64_t>() >> 8) & 0xF; + ipintr = (pkt->get<uint64_t>() >> 8) & 0xF; if (ipintr) { clearIPI(ipintr); supportedWrite = true; @@ -261,14 +261,14 @@ TsunamiCChip::write(Packet &pkt) //If it is the 4-7th bit, clear the RTC interrupt uint64_t itintr; - itintr = (pkt.get<uint64_t>() >> 4) & 0xF; + itintr = (pkt->get<uint64_t>() >> 4) & 0xF; if (itintr) { clearITI(itintr); supportedWrite = true; } // ignore NXMs - if (pkt.get<uint64_t>() & 0x10000000) + if (pkt->get<uint64_t>() & 0x10000000) supportedWrite = true; if(!supportedWrite) @@ -300,7 +300,7 @@ TsunamiCChip::write(Packet &pkt) olddim = dim[number]; olddir = dir[number]; - dim[number] = pkt.get<uint64_t>(); + dim[number] = pkt->get<uint64_t>(); dir[number] = dim[number] & drir; for(int x = 0; x < 64; x++) { @@ -350,19 +350,19 @@ TsunamiCChip::write(Packet &pkt) case TSDEV_CC_MPR3: panic("TSDEV_CC_MPRx write not implemented\n"); case TSDEV_CC_IPIR: - clearIPI(pkt.get<uint64_t>()); + clearIPI(pkt->get<uint64_t>()); break; case TSDEV_CC_ITIR: - clearITI(pkt.get<uint64_t>()); + clearITI(pkt->get<uint64_t>()); break; case TSDEV_CC_IPIQ: - reqIPI(pkt.get<uint64_t>()); + reqIPI(pkt->get<uint64_t>()); break; default: panic("default in cchip read reached, accessing 0x%x\n"); } // swtich(regnum) } // not BIG_TSUNAMI write - pkt.result = Success; + pkt->result = Success; return pioDelay; } diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh index 6cd6cf13f..3dde0131e 100644 --- a/dev/tsunami_cchip.hh +++ b/dev/tsunami_cchip.hh @@ -92,9 +92,9 @@ class TsunamiCChip : public BasicPioDevice */ TsunamiCChip(Params *p); - virtual Tick read(Packet &pkt); + virtual Tick read(Packet *pkt); - virtual Tick write(Packet &pkt); + virtual Tick write(Packet *pkt); /** * post an RTC interrupt to the CPU diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index 0efcc1028..dd9feae99 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -436,89 +436,89 @@ TsunamiIO::frequency() const } Tick -TsunamiIO::read(Packet &pkt) +TsunamiIO::read(Packet *pkt) { - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - pkt.time += pioDelay; - Addr daddr = pkt.addr - pioAddr; + pkt->time += pioDelay; + Addr daddr = pkt->addr - pioAddr; - DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt.addr, - pkt.size, daddr); + DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->addr, + pkt->size, daddr); - pkt.allocate(); + pkt->allocate(); - if (pkt.size == sizeof(uint8_t)) { + if (pkt->size == sizeof(uint8_t)) { switch(daddr) { // PIC1 mask read case TSDEV_PIC1_MASK: - pkt.set(~mask1); + pkt->set(~mask1); break; case TSDEV_PIC2_MASK: - pkt.set(~mask2); + pkt->set(~mask2); break; case TSDEV_PIC1_ISR: // !!! If this is modified 64bit case needs to be too // Pal code has to do a 64 bit physical read because there is // no load physical byte instruction - pkt.set(picr); + pkt->set(picr); break; case TSDEV_PIC2_ISR: // PIC2 not implemnted... just return 0 - pkt.set(0x00); + pkt->set(0x00); break; case TSDEV_TMR0_DATA: - pitimer.counter0.read(pkt.getPtr<uint8_t>()); + pitimer.counter0.read(pkt->getPtr<uint8_t>()); break; case TSDEV_TMR1_DATA: - pitimer.counter1.read(pkt.getPtr<uint8_t>()); + pitimer.counter1.read(pkt->getPtr<uint8_t>()); break; case TSDEV_TMR2_DATA: - pitimer.counter2.read(pkt.getPtr<uint8_t>()); + pitimer.counter2.read(pkt->getPtr<uint8_t>()); break; case TSDEV_RTC_DATA: - rtc.readData(pkt.getPtr<uint8_t>()); + rtc.readData(pkt->getPtr<uint8_t>()); break; case TSDEV_CTRL_PORTB: if (pitimer.counter2.outputHigh()) - pkt.set(PORTB_SPKR_HIGH); + pkt->set(PORTB_SPKR_HIGH); else - pkt.set(0x00); + pkt->set(0x00); break; default: - panic("I/O Read - va%#x size %d\n", pkt.addr, pkt.size); + panic("I/O Read - va%#x size %d\n", pkt->addr, pkt->size); } - } else if (pkt.size == sizeof(uint64_t)) { + } else if (pkt->size == sizeof(uint64_t)) { if (daddr == TSDEV_PIC1_ISR) - pkt.set<uint64_t>(picr); + pkt->set<uint64_t>(picr); else panic("I/O Read - invalid addr - va %#x size %d\n", - pkt.addr, pkt.size); + pkt->addr, pkt->size); } else { - panic("I/O Read - invalid size - va %#x size %d\n", pkt.addr, pkt.size); + panic("I/O Read - invalid size - va %#x size %d\n", pkt->addr, pkt->size); } - pkt.result = Success; + pkt->result = Success; return pioDelay; } Tick -TsunamiIO::write(Packet &pkt) +TsunamiIO::write(Packet *pkt) { - pkt.time += pioDelay; + pkt->time += pioDelay; - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); - Addr daddr = pkt.addr - pioAddr; + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + Addr daddr = pkt->addr - pioAddr; DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", - pkt.addr, pkt.size, pkt.addr & 0xfff, (uint32_t)pkt.get<uint8_t>()); + pkt->addr, pkt->size, pkt->addr & 0xfff, (uint32_t)pkt->get<uint8_t>()); - assert(pkt.size == sizeof(uint8_t)); + assert(pkt->size == sizeof(uint8_t)); switch(daddr) { case TSDEV_PIC1_MASK: - mask1 = ~(pkt.get<uint8_t>()); + mask1 = ~(pkt->get<uint8_t>()); if ((picr & mask1) && !picInterrupting) { picInterrupting = true; tsunami->cchip->postDRIR(55); @@ -531,38 +531,38 @@ TsunamiIO::write(Packet &pkt) } break; case TSDEV_PIC2_MASK: - mask2 = pkt.get<uint8_t>(); + mask2 = pkt->get<uint8_t>(); //PIC2 Not implemented to interrupt break; case TSDEV_PIC1_ACK: // clear the interrupt on the PIC - picr &= ~(1 << (pkt.get<uint8_t>() & 0xF)); + picr &= ~(1 << (pkt->get<uint8_t>() & 0xF)); if (!(picr & mask1)) tsunami->cchip->clearDRIR(55); break; case TSDEV_DMA1_MODE: - mode1 = pkt.get<uint8_t>(); + mode1 = pkt->get<uint8_t>(); break; case TSDEV_DMA2_MODE: - mode2 = pkt.get<uint8_t>(); + mode2 = pkt->get<uint8_t>(); break; case TSDEV_TMR0_DATA: - pitimer.counter0.write(pkt.get<uint8_t>()); + pitimer.counter0.write(pkt->get<uint8_t>()); break; case TSDEV_TMR1_DATA: - pitimer.counter1.write(pkt.get<uint8_t>()); + pitimer.counter1.write(pkt->get<uint8_t>()); break; case TSDEV_TMR2_DATA: - pitimer.counter2.write(pkt.get<uint8_t>()); + pitimer.counter2.write(pkt->get<uint8_t>()); break; case TSDEV_TMR_CTRL: - pitimer.writeControl(pkt.get<uint8_t>()); + pitimer.writeControl(pkt->get<uint8_t>()); break; case TSDEV_RTC_ADDR: - rtc.writeAddr(pkt.get<uint8_t>()); + rtc.writeAddr(pkt->get<uint8_t>()); break; case TSDEV_RTC_DATA: - rtc.writeData(pkt.get<uint8_t>()); + rtc.writeData(pkt->get<uint8_t>()); break; case TSDEV_KBD: case TSDEV_DMA1_CMND: @@ -577,10 +577,10 @@ TsunamiIO::write(Packet &pkt) case TSDEV_CTRL_PORTB: break; default: - panic("I/O Write - va%#x size %d data %#x\n", pkt.addr, pkt.size, pkt.get<uint8_t>()); + panic("I/O Write - va%#x size %d data %#x\n", pkt->addr, pkt->size, pkt->get<uint8_t>()); } - pkt.result = Success; + pkt->result = Success; return pioDelay; } diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh index c37f3aa16..4e4fb2036 100644 --- a/dev/tsunami_io.hh +++ b/dev/tsunami_io.hh @@ -318,8 +318,8 @@ class TsunamiIO : public BasicPioDevice */ TsunamiIO(Params *p); - virtual Tick read(Packet &pkt); - virtual Tick write(Packet &pkt); + virtual Tick read(Packet *pkt); + virtual Tick write(Packet *pkt); /** * Post an PIC interrupt to the CPU via the CChip diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index 1323a0548..999278e37 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -65,76 +65,76 @@ TsunamiPChip::TsunamiPChip(Params *p) } Tick -TsunamiPChip::read(Packet &pkt) +TsunamiPChip::read(Packet *pkt) { - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - pkt.time += pioDelay; - pkt.allocate(); - Addr daddr = (pkt.addr - pioAddr) >> 6;; - assert(pkt.size == sizeof(uint64_t)); + pkt->time += pioDelay; + pkt->allocate(); + Addr daddr = (pkt->addr - pioAddr) >> 6;; + assert(pkt->size == sizeof(uint64_t)); - DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size); + DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->addr, pkt->size); switch(daddr) { case TSDEV_PC_WSBA0: - pkt.set(wsba[0]); + pkt->set(wsba[0]); break; case TSDEV_PC_WSBA1: - pkt.set(wsba[1]); + pkt->set(wsba[1]); break; case TSDEV_PC_WSBA2: - pkt.set(wsba[2]); + pkt->set(wsba[2]); break; case TSDEV_PC_WSBA3: - pkt.set(wsba[3]); + pkt->set(wsba[3]); break; case TSDEV_PC_WSM0: - pkt.set(wsm[0]); + pkt->set(wsm[0]); break; case TSDEV_PC_WSM1: - pkt.set(wsm[1]); + pkt->set(wsm[1]); break; case TSDEV_PC_WSM2: - pkt.set(wsm[2]); + pkt->set(wsm[2]); break; case TSDEV_PC_WSM3: - pkt.set(wsm[3]); + pkt->set(wsm[3]); break; case TSDEV_PC_TBA0: - pkt.set(tba[0]); + pkt->set(tba[0]); break; case TSDEV_PC_TBA1: - pkt.set(tba[1]); + pkt->set(tba[1]); break; case TSDEV_PC_TBA2: - pkt.set(tba[2]); + pkt->set(tba[2]); break; case TSDEV_PC_TBA3: - pkt.set(tba[3]); + pkt->set(tba[3]); break; case TSDEV_PC_PCTL: - pkt.set(pctl); + pkt->set(pctl); break; case TSDEV_PC_PLAT: panic("PC_PLAT not implemented\n"); case TSDEV_PC_RES: panic("PC_RES not implemented\n"); case TSDEV_PC_PERROR: - pkt.set((uint64_t)0x00); + pkt->set((uint64_t)0x00); break; case TSDEV_PC_PERRMASK: - pkt.set((uint64_t)0x00); + pkt->set((uint64_t)0x00); break; case TSDEV_PC_PERRSET: panic("PC_PERRSET not implemented\n"); case TSDEV_PC_TLBIV: panic("PC_TLBIV not implemented\n"); case TSDEV_PC_TLBIA: - pkt.set((uint64_t)0x00); // shouldn't be readable, but linux + pkt->set((uint64_t)0x00); // shouldn't be readable, but linux break; case TSDEV_PC_PMONCTL: panic("PC_PMONCTL not implemented\n"); @@ -143,63 +143,63 @@ TsunamiPChip::read(Packet &pkt) default: panic("Default in PChip Read reached reading 0x%x\n", daddr); } - pkt.result = Success; + pkt->result = Success; return pioDelay; } Tick -TsunamiPChip::write(Packet &pkt) +TsunamiPChip::write(Packet *pkt) { - pkt.time += pioDelay; + pkt->time += pioDelay; - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); - Addr daddr = (pkt.addr - pioAddr) >> 6; + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + Addr daddr = (pkt->addr - pioAddr) >> 6; - assert(pkt.size == sizeof(uint64_t)); + assert(pkt->size == sizeof(uint64_t)); - DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size); + DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->addr, pkt->size); switch(daddr) { case TSDEV_PC_WSBA0: - wsba[0] = pkt.get<uint64_t>(); + wsba[0] = pkt->get<uint64_t>(); break; case TSDEV_PC_WSBA1: - wsba[1] = pkt.get<uint64_t>(); + wsba[1] = pkt->get<uint64_t>(); break; case TSDEV_PC_WSBA2: - wsba[2] = pkt.get<uint64_t>(); + wsba[2] = pkt->get<uint64_t>(); break; case TSDEV_PC_WSBA3: - wsba[3] = pkt.get<uint64_t>(); + wsba[3] = pkt->get<uint64_t>(); break; case TSDEV_PC_WSM0: - wsm[0] = pkt.get<uint64_t>(); + wsm[0] = pkt->get<uint64_t>(); break; case TSDEV_PC_WSM1: - wsm[1] = pkt.get<uint64_t>(); + wsm[1] = pkt->get<uint64_t>(); break; case TSDEV_PC_WSM2: - wsm[2] = pkt.get<uint64_t>(); + wsm[2] = pkt->get<uint64_t>(); break; case TSDEV_PC_WSM3: - wsm[3] = pkt.get<uint64_t>(); + wsm[3] = pkt->get<uint64_t>(); break; case TSDEV_PC_TBA0: - tba[0] = pkt.get<uint64_t>(); + tba[0] = pkt->get<uint64_t>(); break; case TSDEV_PC_TBA1: - tba[1] = pkt.get<uint64_t>(); + tba[1] = pkt->get<uint64_t>(); break; case TSDEV_PC_TBA2: - tba[2] = pkt.get<uint64_t>(); + tba[2] = pkt->get<uint64_t>(); break; case TSDEV_PC_TBA3: - tba[3] = pkt.get<uint64_t>(); + tba[3] = pkt->get<uint64_t>(); break; case TSDEV_PC_PCTL: - pctl = pkt.get<uint64_t>(); + pctl = pkt->get<uint64_t>(); break; case TSDEV_PC_PLAT: panic("PC_PLAT not implemented\n"); @@ -224,7 +224,7 @@ TsunamiPChip::write(Packet &pkt) } // uint64_t - pkt.result = Success; + pkt->result = Success; return pioDelay; } diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh index 2f3e8f078..bb84339c9 100644 --- a/dev/tsunami_pchip.hh +++ b/dev/tsunami_pchip.hh @@ -78,8 +78,8 @@ class TsunamiPChip : public BasicPioDevice */ Addr translatePciToDma(Addr busAddr); - virtual Tick read(Packet &pkt); - virtual Tick write(Packet &pkt); + virtual Tick read(Packet *pkt); + virtual Tick write(Packet *pkt); /** * Serialize this object to the given output stream. diff --git a/dev/uart8250.cc b/dev/uart8250.cc index 15752c735..a4b30cf25 100644 --- a/dev/uart8250.cc +++ b/dev/uart8250.cc @@ -108,15 +108,15 @@ Uart8250::Uart8250(Params *p) } Tick -Uart8250::read(Packet &pkt) +Uart8250::read(Packet *pkt) { - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); - assert(pkt.size == 1); + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + assert(pkt->size == 1); - pkt.time += pioDelay; - Addr daddr = pkt.addr - pioAddr; - pkt.allocate(); + pkt->time += pioDelay; + Addr daddr = pkt->addr - pioAddr; + pkt->allocate(); DPRINTF(Uart, " read register %#x\n", daddr); @@ -124,9 +124,9 @@ Uart8250::read(Packet &pkt) case 0x0: if (!(LCR & 0x80)) { // read byte if (cons->dataAvailable()) - cons->in(*pkt.getPtr<uint8_t>()); + cons->in(*pkt->getPtr<uint8_t>()); else { - pkt.set((uint8_t)0); + pkt->set((uint8_t)0); // A limited amount of these are ok. DPRINTF(Uart, "empty read of RX register\n"); } @@ -141,7 +141,7 @@ Uart8250::read(Packet &pkt) break; case 0x1: if (!(LCR & 0x80)) { // Intr Enable Register(IER) - pkt.set(IER); + pkt->set(IER); } else { // DLM divisor latch MSB ; } @@ -150,17 +150,17 @@ Uart8250::read(Packet &pkt) DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status); if (status & RX_INT) /* Rx data interrupt has a higher priority */ - pkt.set(IIR_RXID); + pkt->set(IIR_RXID); else if (status & TX_INT) - pkt.set(IIR_TXID); + pkt->set(IIR_TXID); else - pkt.set(IIR_NOPEND); + pkt->set(IIR_NOPEND); //Tx interrupts are cleared on IIR reads status &= ~TX_INT; break; case 0x3: // Line Control Register (LCR) - pkt.set(LCR); + pkt->set(LCR); break; case 0x4: // Modem Control Register (MCR) break; @@ -171,13 +171,13 @@ Uart8250::read(Packet &pkt) if (cons->dataAvailable()) lsr = UART_LSR_DR; lsr |= UART_LSR_TEMT | UART_LSR_THRE; - pkt.set(lsr); + pkt->set(lsr); break; case 0x6: // Modem Status Register (MSR) - pkt.set((uint8_t)0); + pkt->set((uint8_t)0); break; case 0x7: // Scratch Register (SCR) - pkt.set((uint8_t)0); // doesn't exist with at 8250. + pkt->set((uint8_t)0); // doesn't exist with at 8250. break; default: panic("Tried to access a UART port that doesn't exist\n"); @@ -186,27 +186,27 @@ Uart8250::read(Packet &pkt) /* uint32_t d32 = *data; DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32); */ - pkt.result = Success; + pkt->result = Success; return pioDelay; } Tick -Uart8250::write(Packet &pkt) +Uart8250::write(Packet *pkt) { - assert(pkt.result == Unknown); - assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize); - assert(pkt.size == 1); + assert(pkt->result == Unknown); + assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + assert(pkt->size == 1); - pkt.time += pioDelay; - Addr daddr = pkt.addr - pioAddr; + pkt->time += pioDelay; + Addr daddr = pkt->addr - pioAddr; - DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt.get<uint8_t>()); + DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt->get<uint8_t>()); switch (daddr) { case 0x0: if (!(LCR & 0x80)) { // write byte - cons->out(pkt.get<uint8_t>()); + cons->out(pkt->get<uint8_t>()); platform->clearConsoleInt(); status &= ~TX_INT; if (UART_IER_THRI & IER) @@ -217,7 +217,7 @@ Uart8250::write(Packet &pkt) break; case 0x1: if (!(LCR & 0x80)) { // Intr Enable Register(IER) - IER = pkt.get<uint8_t>(); + IER = pkt->get<uint8_t>(); if (UART_IER_THRI & IER) { DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n"); @@ -251,10 +251,10 @@ Uart8250::write(Packet &pkt) case 0x2: // FIFO Control Register (FCR) break; case 0x3: // Line Control Register (LCR) - LCR = pkt.get<uint8_t>(); + LCR = pkt->get<uint8_t>(); break; case 0x4: // Modem Control Register (MCR) - if (pkt.get<uint8_t>() == (UART_MCR_LOOP | 0x0A)) + if (pkt->get<uint8_t>() == (UART_MCR_LOOP | 0x0A)) MCR = 0x9A; break; case 0x7: // Scratch Register (SCR) @@ -264,7 +264,7 @@ Uart8250::write(Packet &pkt) panic("Tried to access a UART port that doesn't exist\n"); break; } - pkt.result = Success; + pkt->result = Success; return pioDelay; } diff --git a/dev/uart8250.hh b/dev/uart8250.hh index 19e4438bc..4b7c2f1e4 100644 --- a/dev/uart8250.hh +++ b/dev/uart8250.hh @@ -80,8 +80,8 @@ class Uart8250 : public Uart public: Uart8250(Params *p); - virtual Tick read(Packet &pkt); - virtual Tick write(Packet &pkt); + virtual Tick read(Packet *pkt); + virtual Tick write(Packet *pkt); virtual void addressRanges(AddrRangeList &range_list); diff --git a/mem/bridge.cc b/mem/bridge.cc index d358ef77b..c4b137869 100644 --- a/mem/bridge.cc +++ b/mem/bridge.cc @@ -48,7 +48,7 @@ Bridge::init() /** Function called by the port when the bus is recieving a Timing * transaction.*/ bool -Bridge::recvTiming(Packet &pkt, Side id) +Bridge::recvTiming(Packet *pkt, Side id) { if (blockedA && id == SideA) return false; @@ -59,10 +59,10 @@ Bridge::recvTiming(Packet &pkt, Side id) if (!sendEvent.scheduled()) sendEvent.schedule(curTick + delay); if (id == SideA) { - inboundA.push_back(std::make_pair<Packet*, Tick>(&pkt, curTick)); + inboundA.push_back(std::make_pair<Packet*, Tick>(pkt, curTick)); blockCheck(SideA); } else { - inboundB.push_back(std::make_pair<Packet*, Tick>(&pkt, curTick)); + inboundB.push_back(std::make_pair<Packet*, Tick>(pkt, curTick)); blockCheck(SideB); } } else { @@ -134,16 +134,16 @@ void Bridge::timerEvent() void -Bridge::BridgePort::sendPkt(Packet &pkt) +Bridge::BridgePort::sendPkt(Packet *pkt) { if (!sendTiming(pkt)) - outbound.push_back(std::make_pair<Packet*,Tick>(&pkt, curTick)); + outbound.push_back(std::make_pair<Packet*,Tick>(pkt, curTick)); } void Bridge::BridgePort::sendPkt(std::pair<Packet*, Tick> p) { - if (!sendTiming(*p.first)) + if (!sendTiming(p.first)) outbound.push_back(p); } @@ -163,9 +163,9 @@ Bridge::BridgePort::recvRetry() /** Function called by the port when the bus is recieving a Atomic * transaction.*/ Tick -Bridge::recvAtomic(Packet &pkt, Side id) +Bridge::recvAtomic(Packet *pkt, Side id) { - pkt.time += delay; + pkt->time += delay; if (id == SideA) return sideB->sendAtomic(pkt); @@ -176,33 +176,33 @@ Bridge::recvAtomic(Packet &pkt, Side id) /** Function called by the port when the bus is recieving a Functional * transaction.*/ void -Bridge::recvFunctional(Packet &pkt, Side id) +Bridge::recvFunctional(Packet *pkt, Side id) { - pkt.time += delay; + pkt->time += delay; std::list<std::pair<Packet*, Tick> >::iterator i; bool pktContinue = true; for(i = inboundA.begin(); i != inboundA.end(); ++i) { - if (pkt.intersect(i->first)) { - pktContinue &= fixPacket(pkt, *i->first); + if (pkt->intersect(i->first)) { + pktContinue &= fixPacket(pkt, i->first); } } for(i = inboundB.begin(); i != inboundB.end(); ++i) { - if (pkt.intersect(i->first)) { - pktContinue &= fixPacket(pkt, *i->first); + if (pkt->intersect(i->first)) { + pktContinue &= fixPacket(pkt, i->first); } } for(i = sideA->outbound.begin(); i != sideA->outbound.end(); ++i) { - if (pkt.intersect(i->first)) { - pktContinue &= fixPacket(pkt, *i->first); + if (pkt->intersect(i->first)) { + pktContinue &= fixPacket(pkt, i->first); } } for(i = sideB->outbound.begin(); i != sideB->outbound.end(); ++i) { - if (pkt.intersect(i->first)) { - pktContinue &= fixPacket(pkt, *i->first); + if (pkt->intersect(i->first)) { + pktContinue &= fixPacket(pkt, i->first); } } diff --git a/mem/bridge.hh b/mem/bridge.hh index 6bd4d81ab..5f19ded40 100644 --- a/mem/bridge.hh +++ b/mem/bridge.hh @@ -56,15 +56,15 @@ class Bridge : public MemObject protected: /** Function called by the port when the bus is recieving a Timing transaction.*/ - bool recvTiming(Packet &pkt, Side id); + bool recvTiming(Packet *pkt, Side id); /** Function called by the port when the bus is recieving a Atomic transaction.*/ - Tick recvAtomic(Packet &pkt, Side id); + Tick recvAtomic(Packet *pkt, Side id); /** Function called by the port when the bus is recieving a Functional transaction.*/ - void recvFunctional(Packet &pkt, Side id); + void recvFunctional(Packet *pkt, Side id); /** Function called by the port when the bus is recieving a status change.*/ void recvStatusChange(Port::Status status, Side id); @@ -104,12 +104,12 @@ class Bridge : public MemObject /** Data this is waiting to be transmitted. */ std::list<std::pair<Packet*, Tick> > outbound; - void sendPkt(Packet &pkt); + void sendPkt(Packet *pkt); void sendPkt(std::pair<Packet*, Tick> p); /** When reciving a timing request from the peer port, pass it to the bridge. */ - virtual bool recvTiming(Packet &pkt) + virtual bool recvTiming(Packet *pkt) { return bridge->recvTiming(pkt, side); } /** When reciving a retry request from the peer port, @@ -118,12 +118,12 @@ class Bridge : public MemObject /** When reciving a Atomic requestfrom the peer port, pass it to the bridge. */ - virtual Tick recvAtomic(Packet &pkt) + virtual Tick recvAtomic(Packet *pkt) { return bridge->recvAtomic(pkt, side); } /** When reciving a Functional request from the peer port, pass it to the bridge. */ - virtual void recvFunctional(Packet &pkt) + virtual void recvFunctional(Packet *pkt) { bridge->recvFunctional(pkt, side); } /** When reciving a status changefrom the peer port, diff --git a/mem/bus.cc b/mem/bus.cc index f84e38301..f7c2b874a 100644 --- a/mem/bus.cc +++ b/mem/bus.cc @@ -48,14 +48,14 @@ Bus::init() /** Function called by the port when the bus is recieving a Timing * transaction.*/ bool -Bus::recvTiming(Packet &pkt) +Bus::recvTiming(Packet *pkt) { Port *port; - if (pkt.dest == Packet::Broadcast) { - port = findPort(pkt.addr, pkt.src); + if (pkt->dest == Packet::Broadcast) { + port = findPort(pkt->addr, pkt->src); } else { - assert(pkt.dest > 0 && pkt.dest < interfaces.size()); - port = interfaces[pkt.dest]; + assert(pkt->dest > 0 && pkt->dest < interfaces.size()); + port = interfaces[pkt->dest]; } return port->sendTiming(pkt); } @@ -89,19 +89,19 @@ Bus::findPort(Addr addr, int id) /** Function called by the port when the bus is recieving a Atomic * transaction.*/ Tick -Bus::recvAtomic(Packet &pkt) +Bus::recvAtomic(Packet *pkt) { - assert(pkt.dest == Packet::Broadcast); - return findPort(pkt.addr, pkt.src)->sendAtomic(pkt); + assert(pkt->dest == Packet::Broadcast); + return findPort(pkt->addr, pkt->src)->sendAtomic(pkt); } /** Function called by the port when the bus is recieving a Functional * transaction.*/ void -Bus::recvFunctional(Packet &pkt) +Bus::recvFunctional(Packet *pkt) { - assert(pkt.dest == Packet::Broadcast); - findPort(pkt.addr, pkt.src)->sendFunctional(pkt); + assert(pkt->dest == Packet::Broadcast); + findPort(pkt->addr, pkt->src)->sendFunctional(pkt); } /** Function called by the port when the bus is recieving a status change.*/ diff --git a/mem/bus.hh b/mem/bus.hh index 40d274037..38573e514 100644 --- a/mem/bus.hh +++ b/mem/bus.hh @@ -57,15 +57,15 @@ class Bus : public MemObject /** Function called by the port when the bus is recieving a Timing transaction.*/ - bool recvTiming(Packet &pkt); + bool recvTiming(Packet *pkt); /** Function called by the port when the bus is recieving a Atomic transaction.*/ - Tick recvAtomic(Packet &pkt); + Tick recvAtomic(Packet *pkt); /** Function called by the port when the bus is recieving a Functional transaction.*/ - void recvFunctional(Packet &pkt); + void recvFunctional(Packet *pkt); /** Function called by the port when the bus is recieving a status change.*/ void recvStatusChange(Port::Status status, int id); @@ -108,18 +108,18 @@ class Bus : public MemObject /** When reciving a timing request from the peer port (at id), pass it to the bus. */ - virtual bool recvTiming(Packet &pkt) - { pkt.src = id; return bus->recvTiming(pkt); } + virtual bool recvTiming(Packet *pkt) + { pkt->src = id; return bus->recvTiming(pkt); } /** When reciving a Atomic requestfrom the peer port (at id), pass it to the bus. */ - virtual Tick recvAtomic(Packet &pkt) - { pkt.src = id; return bus->recvAtomic(pkt); } + virtual Tick recvAtomic(Packet *pkt) + { pkt->src = id; return bus->recvAtomic(pkt); } /** When reciving a Functional requestfrom the peer port (at id), pass it to the bus. */ - virtual void recvFunctional(Packet &pkt) - { pkt.src = id; bus->recvFunctional(pkt); } + virtual void recvFunctional(Packet *pkt) + { pkt->src = id; bus->recvFunctional(pkt); } /** When reciving a status changefrom the peer port (at id), pass it to the bus. */ diff --git a/mem/packet.cc b/mem/packet.cc index ecd2a7be1..a9be7ac51 100644 --- a/mem/packet.cc +++ b/mem/packet.cc @@ -90,5 +90,5 @@ Packet::reset() { -bool fixPacket(Packet &func, Packet &timing) +bool fixPacket(Packet *func, Packet *timing) { panic("Need to implement!"); } diff --git a/mem/packet.hh b/mem/packet.hh index ab961e304..e8a7b0c73 100644 --- a/mem/packet.hh +++ b/mem/packet.hh @@ -190,5 +190,5 @@ struct Packet bool intersect(Packet *p); }; -bool fixPacket(Packet &func, Packet &timing); +bool fixPacket(Packet *func, Packet *timing); #endif //__MEM_PACKET_HH diff --git a/mem/physical.cc b/mem/physical.cc index d0409995b..8de9c3203 100644 --- a/mem/physical.cc +++ b/mem/physical.cc @@ -50,7 +50,7 @@ using namespace std; using namespace TheISA; -PhysicalMemory::MemResponseEvent::MemResponseEvent(Packet &pkt, MemoryPort* _m) +PhysicalMemory::MemResponseEvent::MemResponseEvent(Packet *pkt, MemoryPort* _m) : Event(&mainEventQueue, CPU_Tick_Pri), pkt(pkt), memoryPort(_m) { @@ -123,11 +123,11 @@ PhysicalMemory::deviceBlockSize() } bool -PhysicalMemory::doTimingAccess (Packet &pkt, MemoryPort* memoryPort) +PhysicalMemory::doTimingAccess (Packet *pkt, MemoryPort* memoryPort) { doFunctionalAccess(pkt); - pkt.dest = pkt.src; + pkt->dest = pkt->src; MemResponseEvent* response = new MemResponseEvent(pkt, memoryPort); response->schedule(curTick + lat); @@ -135,32 +135,32 @@ PhysicalMemory::doTimingAccess (Packet &pkt, MemoryPort* memoryPort) } Tick -PhysicalMemory::doAtomicAccess(Packet &pkt) +PhysicalMemory::doAtomicAccess(Packet *pkt) { doFunctionalAccess(pkt); - pkt.time = curTick + lat; + pkt->time = curTick + lat; return curTick + lat; } void -PhysicalMemory::doFunctionalAccess(Packet &pkt) +PhysicalMemory::doFunctionalAccess(Packet *pkt) { - assert(pkt.addr + pkt.size < pmem_size); + assert(pkt->addr + pkt->size < pmem_size); - switch (pkt.cmd) { + switch (pkt->cmd) { case Read: - memcpy(pkt.getPtr<uint8_t>(), pmem_addr + pkt.addr - base_addr, - pkt.size); + memcpy(pkt->getPtr<uint8_t>(), pmem_addr + pkt->addr - base_addr, + pkt->size); break; case Write: - memcpy(pmem_addr + pkt.addr - base_addr, pkt.getPtr<uint8_t>(), - pkt.size); + memcpy(pmem_addr + pkt->addr - base_addr, pkt->getPtr<uint8_t>(), + pkt->size); break; default: panic("unimplemented"); } - pkt.result = Success; + pkt->result = Success; } Port * @@ -216,19 +216,19 @@ PhysicalMemory::MemoryPort::deviceBlockSize() } bool -PhysicalMemory::MemoryPort::recvTiming(Packet &pkt) +PhysicalMemory::MemoryPort::recvTiming(Packet *pkt) { return memory->doTimingAccess(pkt, this); } Tick -PhysicalMemory::MemoryPort::recvAtomic(Packet &pkt) +PhysicalMemory::MemoryPort::recvAtomic(Packet *pkt) { return memory->doAtomicAccess(pkt); } void -PhysicalMemory::MemoryPort::recvFunctional(Packet &pkt) +PhysicalMemory::MemoryPort::recvFunctional(Packet *pkt) { memory->doFunctionalAccess(pkt); } diff --git a/mem/physical.hh b/mem/physical.hh index f87683c45..1cf5444ab 100644 --- a/mem/physical.hh +++ b/mem/physical.hh @@ -55,11 +55,11 @@ class PhysicalMemory : public MemObject protected: - virtual bool recvTiming(Packet &pkt); + virtual bool recvTiming(Packet *pkt); - virtual Tick recvAtomic(Packet &pkt); + virtual Tick recvAtomic(Packet *pkt); - virtual void recvFunctional(Packet &pkt); + virtual void recvFunctional(Packet *pkt); virtual void recvStatusChange(Status status); @@ -74,10 +74,10 @@ class PhysicalMemory : public MemObject struct MemResponseEvent : public Event { - Packet &pkt; + Packet *pkt; MemoryPort *memoryPort; - MemResponseEvent(Packet &pkt, MemoryPort *memoryPort); + MemResponseEvent(Packet *pkt, MemoryPort *memoryPort); void process(); const char *description(); }; @@ -112,9 +112,9 @@ class PhysicalMemory : public MemObject // fast back-door memory access for vtophys(), remote gdb, etc. // uint64_t phys_read_qword(Addr addr) const; private: - bool doTimingAccess(Packet &pkt, MemoryPort *memoryPort); - Tick doAtomicAccess(Packet &pkt); - void doFunctionalAccess(Packet &pkt); + bool doTimingAccess(Packet *pkt, MemoryPort *memoryPort); + Tick doAtomicAccess(Packet *pkt); + void doFunctionalAccess(Packet *pkt); void recvStatusChange(Port::Status status); diff --git a/mem/port.cc b/mem/port.cc index 5b1f634d6..fb3103ed1 100644 --- a/mem/port.cc +++ b/mem/port.cc @@ -48,7 +48,7 @@ Port::blobHelper(Addr addr, uint8_t *p, int size, Command cmd) req.setPaddr(pkt.addr = gen.addr()); req.setSize(pkt.size = gen.size()); pkt.dataStatic(p); - sendFunctional(pkt); + sendFunctional(&pkt); p += gen.size(); } } diff --git a/mem/port.hh b/mem/port.hh index 2ab2806c9..1b1920c03 100644 --- a/mem/port.hh +++ b/mem/port.hh @@ -106,13 +106,13 @@ class Port * called by a peer port, never directly by any outside object. */ /** Called to recive a timing call from the peer port. */ - virtual bool recvTiming(Packet &pkt) = 0; + virtual bool recvTiming(Packet *pkt) = 0; /** Called to recive a atomic call from the peer port. */ - virtual Tick recvAtomic(Packet &pkt) = 0; + virtual Tick recvAtomic(Packet *pkt) = 0; /** Called to recive a functional call from the peer port. */ - virtual void recvFunctional(Packet &pkt) = 0; + virtual void recvFunctional(Packet *pkt) = 0; /** Called to recieve a status change from the peer port. */ virtual void recvStatusChange(Status status) = 0; @@ -150,13 +150,13 @@ class Port case a cache has a higher priority request come in while waiting for the bus to arbitrate. */ - bool sendTiming(Packet &pkt) { return peer->recvTiming(pkt); } + bool sendTiming(Packet *pkt) { return peer->recvTiming(pkt); } /** Function called by the associated device to send an atomic access, an access in which the data is moved and the state is updated in one cycle, without interleaving with other memory accesses. */ - Tick sendAtomic(Packet &pkt) + Tick sendAtomic(Packet *pkt) { return peer->recvAtomic(pkt); } /** Function called by the associated device to send a functional access, @@ -164,7 +164,7 @@ class Port memory system, without affecting the current state of any block or moving the block. */ - void sendFunctional(Packet &pkt) + void sendFunctional(Packet *pkt) { return peer->recvFunctional(pkt); } /** Called by the associated device to send a status change to the device @@ -224,9 +224,9 @@ class Port class FunctionalPort : public Port { public: - virtual bool recvTiming(Packet &pkt) { panic("FuncPort is UniDir"); } - virtual Tick recvAtomic(Packet &pkt) { panic("FuncPort is UniDir"); } - virtual void recvFunctional(Packet &pkt) { panic("FuncPort is UniDir"); } + virtual bool recvTiming(Packet *pkt) { panic("FuncPort is UniDir"); } + virtual Tick recvAtomic(Packet *pkt) { panic("FuncPort is UniDir"); } + virtual void recvFunctional(Packet *pkt) { panic("FuncPort is UniDir"); } virtual void recvStatusChange(Status status) {} template <typename T> |