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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-27 00:54:09 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-27 00:54:09 -0700 |
commit | 8ec235c7b189c3ae1bf13358774add595710cfd6 (patch) | |
tree | 99aa3e3421d29c28b060ce81457b7a1ddc01762c | |
parent | 1ad4de252852941fdde1838f007daeb34d1885c3 (diff) | |
download | gem5-8ec235c7b189c3ae1bf13358774add595710cfd6.tar.xz |
ARM: Make native trace print out what instruction caused an error.
-rw-r--r-- | src/arch/arm/nativetrace.cc | 15 | ||||
-rw-r--r-- | src/cpu/NativeTrace.py | 4 | ||||
-rw-r--r-- | src/cpu/nativetrace.cc | 2 | ||||
-rw-r--r-- | src/cpu/nativetrace.hh | 8 |
4 files changed, 22 insertions, 7 deletions
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc index 2dd0b8575..7301653f4 100644 --- a/src/arch/arm/nativetrace.cc +++ b/src/arch/arm/nativetrace.cc @@ -86,6 +86,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record) nState.update(this); mState.update(record->getThread()); + bool errorFound = false; // Regular int regs for (int i = 0; i < STATE_NUMVALS; i++) { if (nState.changed[i] || mState.changed[i]) { @@ -104,6 +105,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record) vergence, regNames[i], nState.newState[i], mState.oldState[i], mState.newState[i]); + errorFound = true; } else if (!mState.changed[i]) { DPRINTF(ExecRegDelta, "%s [%5s] "\ "Native: %#010x => %#010x "\ @@ -111,6 +113,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record) vergence, regNames[i], nState.oldState[i], nState.newState[i], mState.newState[i]); + errorFound = true; } else if (mState.oldState[i] != nState.oldState[i] || mState.newState[i] != nState.newState[i]) { DPRINTF(ExecRegDelta, "%s [%5s] "\ @@ -119,9 +122,21 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record) vergence, regNames[i], nState.oldState[i], nState.newState[i], mState.oldState[i], mState.newState[i]); + errorFound = true; } } } + if (errorFound) { + StaticInstPtr inst = record->getStaticInst(); + assert(inst); + bool ran = true; + if (inst->isMicroop()) { + ran = false; + inst = record->getMacroStaticInst(); + } + assert(inst); + record->traceInst(inst, ran); + } } } /* namespace Trace */ diff --git a/src/cpu/NativeTrace.py b/src/cpu/NativeTrace.py index 7fd240543..dba6de067 100644 --- a/src/cpu/NativeTrace.py +++ b/src/cpu/NativeTrace.py @@ -28,9 +28,9 @@ from m5.SimObject import SimObject from m5.params import * -from InstTracer import InstTracer +from ExeTracer import ExeTracer -class NativeTrace(InstTracer): +class NativeTrace(ExeTracer): abstract = True type = 'NativeTrace' cxx_class = 'Trace::NativeTrace' diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc index 47c58434f..8c17eb825 100644 --- a/src/cpu/nativetrace.cc +++ b/src/cpu/nativetrace.cc @@ -38,7 +38,7 @@ using namespace std; namespace Trace { NativeTrace::NativeTrace(const Params *p) - : InstTracer(p) + : ExeTracer(p) { if (ListenSocket::allDisabled()) fatal("All listeners are disabled!"); diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh index 34869f263..6ad6b0242 100644 --- a/src/cpu/nativetrace.hh +++ b/src/cpu/nativetrace.hh @@ -37,8 +37,8 @@ #include "base/socket.hh" #include "base/trace.hh" #include "base/types.hh" +#include "cpu/exetrace.hh" #include "cpu/static_inst.hh" -#include "sim/insttracer.hh" class ThreadContext; @@ -46,7 +46,7 @@ namespace Trace { class NativeTrace; -class NativeTraceRecord : public InstRecord +class NativeTraceRecord : public ExeTracerRecord { protected: NativeTrace * parent; @@ -56,7 +56,7 @@ class NativeTraceRecord : public InstRecord Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, Addr _pc, bool spec, const StaticInstPtr _macroStaticInst = NULL, MicroPC _upc = 0) - : InstRecord(_when, _thread, _staticInst, _pc, spec, + : ExeTracerRecord(_when, _thread, _staticInst, _pc, spec, _macroStaticInst, _upc), parent(_parent) { @@ -65,7 +65,7 @@ class NativeTraceRecord : public InstRecord void dump(); }; -class NativeTrace : public InstTracer +class NativeTrace : public ExeTracer { protected: int fd; |