Registers: Eliminate the ISA defined integer register file.

28 files changed, 27 insertions, 628 deletions

diff --git a/src/arch/alpha/intregfile.cc b/src/arch/alpha/intregfile.cc
index 8f692f856..de1c2a5d9 100644
--- a/src/arch/alpha/intregfile.cc
+++ b/src/arch/alpha/intregfile.cc
@@ -30,11 +30,7 @@
  *          Kevin Lim
  */
 
-#include <cstring>
-
-#include "arch/alpha/isa_traits.hh"
 #include "arch/alpha/intregfile.hh"
-#include "sim/serialize.hh"
 
 namespace AlphaISA {
 
@@ -52,23 +48,5 @@ const int reg_redir[NumIntRegs] = {
     /* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
 #endif
 
-void
-IntRegFile::clear()
-{
-    std::memset(regs, 0, sizeof(regs));
-}
-
-void
-IntRegFile::serialize(std::ostream &os)
-{
-    SERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void
-IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
 } // namespace AlphaISA
 
diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh
index 3aa7d92c4..2844b55d9 100644
--- a/src/arch/alpha/intregfile.hh
+++ b/src/arch/alpha/intregfile.hh
@@ -32,42 +32,13 @@
 #ifndef __ARCH_ALPHA_INTREGFILE_HH__
 #define __ARCH_ALPHA_INTREGFILE_HH__
 
-#include <iosfwd>
-#include <string>
-
-#include "arch/alpha/types.hh"
-
-class Checkpoint;
+#include "arch/alpha/isa_traits.hh"
 
 namespace AlphaISA {
 
 // redirected register map, really only used for the full system case.
 extern const int reg_redir[NumIntRegs];
 
-class IntRegFile
-{
-  protected:
-    IntReg regs[NumIntRegs];
-
-  public:
-    IntReg
-    readReg(int intReg)
-    {
-        return regs[intReg];
-    }
-
-    void
-    setReg(int intReg, const IntReg &val)
-    {
-        regs[intReg] = val;
-    }
-
-    void clear();
-
-    void serialize(std::ostream &os);
-    void unserialize(Checkpoint *cp, const std::string &section);
-};
-
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_INTREGFILE_HH__
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index df345278a..993c91387 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -41,7 +41,6 @@ namespace AlphaISA {
 void
 RegFile::serialize(EventManager *em, ostream &os)
 {
-    intRegFile.serialize(os);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
@@ -52,7 +51,6 @@ RegFile::serialize(EventManager *em, ostream &os)
 void
 RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
-    intRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
 #if FULL_SYSTEM
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 000bea259..113cf225c 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -89,9 +89,6 @@ class RegFile {
     setNextNPC(Addr val)
     { }
 
-  protected:
-    IntRegFile intRegFile;          // (signed) integer register file
-
   public:
 #if FULL_SYSTEM
     int intrflag;                   // interrupt flag
@@ -100,19 +97,6 @@ class RegFile {
     void
     clear()
     {
-        intRegFile.clear();
-    }
-
-    IntReg
-    readIntReg(int intReg)
-    {
-        return intRegFile.readReg(intReg);
-    }
-
-    void
-    setIntReg(int intReg, const IntReg &val)
-    {
-        intRegFile.setReg(intReg, val);
     }
 
     void serialize(EventManager *em, std::ostream &os);
diff --git a/src/arch/arm/regfile/int_regfile.hh b/src/arch/arm/regfile/int_regfile.hh
index b22129f33..1f2715a6b 100644
--- a/src/arch/arm/regfile/int_regfile.hh
+++ b/src/arch/arm/regfile/int_regfile.hh
@@ -43,11 +43,6 @@ class ThreadContext;
 
 namespace ArmISA
 {
-    static inline std::string getIntRegName(RegIndex)
-    {
-        return "";
-    }
-
     enum MiscIntRegNums {
         zero_reg = NumIntArchRegs,
         addr_reg,
@@ -77,42 +72,6 @@ namespace ArmISA
         r14_abt
     };
 
-    class IntRegFile
-    {
-      protected:
-        IntReg regs[NumIntRegs];
-
-      public:
-        IntReg readReg(int intReg)
-        {
-            DPRINTF(IntRegs, "Reading int reg %d as %#x.\n",
-                    intReg, regs[intReg]);
-            return regs[intReg];
-        }
-
-        void clear()
-        {
-            bzero(regs, sizeof(regs));
-        }
-
-        Fault setReg(int intReg, const IntReg &val)
-        {
-            DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", intReg, val);
-            regs[intReg] = val;
-            return NoFault;
-        }
-
-        void serialize(std::ostream &os)
-        {
-            SERIALIZE_ARRAY(regs, NumIntRegs);
-        }
-
-        void unserialize(Checkpoint *cp, const std::string &section)
-        {
-            UNSERIALIZE_ARRAY(regs, NumIntRegs);
-        }
-    };
-
 } // namespace ArmISA
 
 #endif
diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc
index 4ab3c771f..49ffb4f28 100644
--- a/src/arch/arm/regfile/regfile.cc
+++ b/src/arch/arm/regfile/regfile.cc
@@ -57,7 +57,6 @@ MiscRegFile::copyMiscRegs(ThreadContext *tc)
 void
 RegFile::serialize(EventManager *em, ostream &os)
 {
-    intRegFile.serialize(os);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
 }
@@ -65,7 +64,6 @@ RegFile::serialize(EventManager *em, ostream &os)
 void
 RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
-    intRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
 }
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
index 35830eabf..05f9197c3 100644
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -67,25 +67,10 @@ namespace ArmISA
 
     class RegFile
     {
-      protected:
-        IntRegFile intRegFile;		// (signed) integer register file
-
       public:
 
         void clear()
-        {
-            intRegFile.clear();
-        }
-
-        IntReg readIntReg(int intReg)
-        {
-            return intRegFile.readReg(intReg);
-        }
-
-        void setIntReg(int intReg, const IntReg &val)
-        {
-            intRegFile.setReg(intReg, val);
-        }
+        {}
       protected:
 
         Addr pc;			// program counter
@@ -95,14 +80,12 @@ namespace ArmISA
       public:
         Addr readPC()
         {
-            return intRegFile.readReg(PCReg);
-            //return pc;
+            return pc;
         }
 
         void setPC(Addr val)
         {
-            intRegFile.setReg(PCReg, val);
-            //pc = val;
+            pc = val;
         }
 
         Addr readNextPC()
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index dbbdf72b3..0b5f10611 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -35,7 +35,6 @@ Import('*')
 if env['TARGET_ISA'] == 'mips':
     Source('faults.cc')
     Source('isa.cc')
-    Source('regfile/int_regfile.cc')
     Source('regfile/misc_regfile.cc')
     Source('regfile/regfile.cc')
     Source('tlb.cc')
diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc
index 2fb53cd4c..760f7e028 100644
--- a/src/arch/mips/regfile.cc
+++ b/src/arch/mips/regfile.cc
@@ -48,7 +48,6 @@ using namespace MipsISA;
 
 void RegFile::clear()
 {
-    intRegFile.clear();
     miscRegFile.clear();
 }
 
@@ -56,20 +55,9 @@ void
 RegFile::reset(std::string core_name, ThreadID num_threads,
                unsigned num_vpes)
 {
-    bzero(&intRegFile, sizeof(intRegFile));
     miscRegFile.reset(core_name, num_threads, num_vpes);
 }
 
-IntReg RegFile::readIntReg(int intReg)
-{
-    return intRegFile.readReg(intReg);
-}
-
-Fault RegFile::setIntReg(int intReg, const IntReg &val)
-{
-    return intRegFile.setReg(intReg, val);
-}
-
 MiscReg
 RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid = 0)
 {
@@ -128,7 +116,6 @@ void RegFile::setNextNPC(Addr val)
 void
 RegFile::serialize(std::ostream &os)
 {
-    intRegFile.serialize(os);
     miscRegFile.serialize(os);
 
     SERIALIZE_SCALAR(pc);
@@ -140,7 +127,6 @@ RegFile::serialize(std::ostream &os)
 void
 RegFile::unserialize(Checkpoint *cp, const std::string &section)
 {
-    intRegFile.unserialize(cp, section);
     miscRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
diff --git a/src/arch/mips/regfile/int_regfile.cc b/src/arch/mips/regfile/int_regfile.cc
deleted file mode 100644
index 88de4be94..000000000
--- a/src/arch/mips/regfile/int_regfile.cc
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Korey Sewell
- *          Jaidev Patwardhan
- */
-
-#include "arch/mips/regfile/int_regfile.hh"
-#include "sim/serialize.hh"
-
-using namespace MipsISA;
-using namespace std;
-
-void
-IntRegFile::clear()
-{
-    bzero(&regs, sizeof(regs));
-    currShadowSet=0;
-}
-
-int
-IntRegFile::readShadowSet()
-{
-  return currShadowSet;
-}
-
-void
-IntRegFile::setShadowSet(int css)
-{
-    DPRINTF(MipsPRA, "Setting Shadow Set to :%d (%s)\n", css, currShadowSet);
-    currShadowSet = css;
-}
-
-IntReg
-IntRegFile::readReg(int intReg)
-{
-    if (intReg < NumIntArchRegs) {
-        // Regular GPR Read
-        DPRINTF(MipsPRA, "Reading Reg: %d, CurrShadowSet: %d\n", intReg,
-              currShadowSet);
-
-        return regs[intReg + NumIntArchRegs * currShadowSet];
-    } else {
-        unsigned special_reg_num = intReg - NumIntArchRegs;
-
-        // Read A Special Reg
-        return regs[TotalArchRegs + special_reg_num];
-    }
-}
-
-Fault
-IntRegFile::setReg(int intReg, const IntReg &val)
-{
-    if (intReg != ZeroReg) {
-        if (intReg < NumIntArchRegs) {
-          regs[intReg + NumIntArchRegs * currShadowSet] = val;
-        } else {
-          unsigned special_reg_num = intReg - NumIntArchRegs;
-
-          regs[TotalArchRegs + special_reg_num] = val;
-        }
-    }
-
-    return NoFault;
-}
-
-void
-IntRegFile::serialize(std::ostream &os)
-{
-    SERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void
-IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_ARRAY(regs, NumIntRegs);
-}
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index 3c7c8c64c..a2c5169aa 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -65,23 +65,6 @@ namespace MipsISA
     //TotalArchRegs = NumIntArchRegs * ShadowSets
     const int TotalArchRegs = NumIntArchRegs;
 
-    class IntRegFile
-    {
-      protected:
-        IntReg regs[NumIntRegs];
-        int currShadowSet;
-      public:
-        void clear();
-        int readShadowSet();
-        void setShadowSet(int css);
-        IntReg readReg(int intReg);
-        Fault setReg(int intReg, const IntReg &val);
-
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
-
-    };
-
 } // namespace MipsISA
 
 #endif
diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc
index eeec02ee4..a19962ff3 100644
--- a/src/arch/mips/regfile/regfile.cc
+++ b/src/arch/mips/regfile/regfile.cc
@@ -40,31 +40,16 @@ namespace MipsISA
 void
 RegFile::clear()
 {
-    intRegFile.clear();
 }
 
 void
 RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
                BaseCPU *_cpu)
 {
-    bzero(&intRegFile, sizeof(intRegFile));
-}
-
-IntReg
-RegFile::readIntReg(int intReg)
-{
-    return intRegFile.readReg(intReg);
-}
-
-Fault
-RegFile::setIntReg(int intReg, const IntReg &val)
-{
-    return intRegFile.setReg(intReg, val);
 }
 
 void
 RegFile::setShadowSet(int css){
-    intRegFile.setShadowSet(css);
 }
 
 
@@ -107,7 +92,6 @@ RegFile::setNextNPC(Addr val)
 void
 RegFile::serialize(EventManager *em, std::ostream &os)
 {
-    intRegFile.serialize(os);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
@@ -117,7 +101,6 @@ void
 RegFile::unserialize(EventManager *em, Checkpoint *cp,
     const std::string &section)
 {
-    intRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 105891bb9..061b4a07d 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -79,16 +79,11 @@ namespace MipsISA
                                         // used to implement branch delay slot
                                         // not real register
 
-        IntRegFile intRegFile;          // (signed) integer register file
-
       public:
         void clear();
         void reset(std::string core_name, ThreadID num_threads,
                    unsigned num_vpes, BaseCPU *_cpu);
 
-        IntReg readIntReg(int intReg);
-        Fault setIntReg(int intReg, const IntReg &val);
-
         void setShadowSet(int css);
 
       public:
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 2b10951d9..cfc03b718 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -34,7 +34,6 @@ Import('*')
 if env['TARGET_ISA'] == 'sparc':
     Source('asi.cc')
     Source('faults.cc')
-    Source('intregfile.cc')
     Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc
deleted file mode 100644
index 54c30d1cc..000000000
--- a/src/arch/sparc/intregfile.cc
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Ali Saidi
- */
-
-#include "arch/sparc/intregfile.hh"
-#include "base/trace.hh"
-#include "base/misc.hh"
-#include "sim/serialize.hh"
-
-#include <string.h>
-
-using namespace SparcISA;
-using namespace std;
-
-class Checkpoint;
-
-void IntRegFile::clear()
-{
-    memset(regs, 0, sizeof(IntReg) * NumIntRegs);
-}
-
-IntRegFile::IntRegFile()
-{
-    clear();
-}
-
-IntReg IntRegFile::readReg(int intReg)
-{
-    DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, regs[intReg]);
-    return regs[intReg];
-}
-
-void IntRegFile::setReg(int intReg, const IntReg &val)
-{
-    if(intReg)
-    {
-        DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val);
-        regs[intReg] = val;
-    }
-    return;
-}
-
-void IntRegFile::serialize(std::ostream &os)
-{
-    SERIALIZE_ARRAY(regs, NumIntRegs);
-    SERIALIZE_ARRAY(microRegs, NumMicroIntRegs);
-}
-
-void IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_ARRAY(regs, NumIntRegs);
-    UNSERIALIZE_ARRAY(microRegs, NumMicroIntRegs);
-}
diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/intregfile.hh
index f669f6b0d..0165fca10 100644
--- a/src/arch/sparc/intregfile.hh
+++ b/src/arch/sparc/intregfile.hh
@@ -32,39 +32,12 @@
 #ifndef __ARCH_SPARC_INTREGFILE_HH__
 #define __ARCH_SPARC_INTREGFILE_HH__
 
-#include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/types.hh"
-#include "base/bitfield.hh"
-
-#include <string>
-
-class Checkpoint;
+#include "arch/sparc/sparc_traits.hh"
 
 namespace SparcISA
 {
     const int NumIntArchRegs = 32;
     const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
-
-    class IntRegFile
-    {
-      protected:
-        IntReg microRegs[NumMicroIntRegs];
-        IntReg regs[NumIntRegs];
-
-      public:
-
-        void clear();
-
-        IntRegFile();
-
-        IntReg readReg(int intReg);
-
-        void setReg(int intReg, const IntReg &val);
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-    };
 }
 
 #endif
diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh
index 7775e858e..137e91fbd 100644
--- a/src/arch/sparc/predecoder.hh
+++ b/src/arch/sparc/predecoder.hh
@@ -32,6 +32,7 @@
 #define __ARCH_SPARC_PREDECODER_HH__
 
 #include "arch/sparc/types.hh"
+#include "base/bitfield.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 83a3dbcc2..e48bb07fe 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -68,25 +68,9 @@ void RegFile::setNextNPC(Addr val)
     nnpc = val;
 }
 
-void RegFile::clear()
-{
-    intRegFile.clear();
-}
-
-IntReg RegFile::readIntReg(int intReg)
-{
-    return intRegFile.readReg(intReg);
-}
-
-void RegFile::setIntReg(int intReg, const IntReg &val)
-{
-    intRegFile.setReg(intReg, val);
-}
-
 void
 RegFile::serialize(EventManager *em, ostream &os)
 {
-    intRegFile.serialize(os);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
     SERIALIZE_SCALAR(nnpc);
@@ -95,7 +79,6 @@ RegFile::serialize(EventManager *em, ostream &os)
 void
 RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
-    intRegFile.unserialize(cp, section);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
     UNSERIALIZE_SCALAR(nnpc);
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index c28a5274f..c3c53a414 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -61,16 +61,10 @@ namespace SparcISA
         Addr readNextNPC();
         void setNextNPC(Addr val);
 
-      protected:
-        IntRegFile intRegFile;          // integer register file
-
       public:
 
-        void clear();
-
-        IntReg readIntReg(int intReg);
-
-        void setIntReg(int intReg, const IntReg &val);
+        void clear()
+        {}
 
         void serialize(EventManager *em, std::ostream &os);
         void unserialize(EventManager *em, Checkpoint *cp,
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 157a703e2..f500089f3 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -94,7 +94,6 @@ if env['TARGET_ISA'] == 'x86':
     Source('insts/microop.cc')
     Source('insts/microregop.cc')
     Source('insts/static_inst.cc')
-    Source('intregfile.cc')
     Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
diff --git a/src/arch/x86/intregfile.cc b/src/arch/x86/intregfile.cc
deleted file mode 100644
index 58a37cb9e..000000000
--- a/src/arch/x86/intregfile.cc
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (c) 2003-2007 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-/*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
- * All rights reserved.
- *
- * Redistribution and use of this software in source and binary forms,
- * with or without modification, are permitted provided that the
- * following conditions are met:
- *
- * The software must be used only for Non-Commercial Use which means any
- * use which is NOT directed to receiving any direct monetary
- * compensation for, or commercial advantage from such use.  Illustrative
- * examples of non-commercial use are academic research, personal study,
- * teaching, education and corporate research & development.
- * Illustrative examples of commercial use are distributing products for
- * commercial advantage and providing services using the software for
- * commercial advantage.
- *
- * If you wish to use this software or functionality therein that may be
- * covered by patents for commercial use, please contact:
- *     Director of Intellectual Property Licensing
- *     Office of Strategy and Technology
- *     Hewlett-Packard Company
- *     1501 Page Mill Road
- *     Palo Alto, California  94304
- *
- * Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.  Redistributions
- * in binary form must reproduce the above copyright notice, this list of
- * conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.  Neither the name of
- * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.  No right of
- * sublicense is granted herewith.  Derivatives of the software and
- * output created using the software may be prepared, but only for
- * Non-Commercial Uses.  Derivatives of the software may be shared with
- * others provided: (i) the others agree to abide by the list of
- * conditions herein which includes the Non-Commercial Use restrictions;
- * and (ii) such Derivatives of the software include the above copyright
- * notice to acknowledge the contribution from this software where
- * applicable, this list of conditions and the disclaimer below.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/x86/intregfile.hh"
-#include "base/misc.hh"
-#include "base/trace.hh"
-#include "sim/serialize.hh"
-
-#include <string.h>
-
-using namespace X86ISA;
-using namespace std;
-
-class Checkpoint;
-
-int IntRegFile::flattenIndex(int reg)
-{
-    return reg;
-}
-
-void IntRegFile::clear()
-{
-    memset(regs, 0, sizeof(IntReg) * NumIntRegs);
-}
-
-IntReg IntRegFile::readReg(int intReg)
-{
-    DPRINTF(IntRegs, "Read int reg %d and got value %#x\n",
-            intReg, regs[intReg]);
-    return regs[intReg];
-}
-
-void IntRegFile::setReg(int intReg, const IntReg &val)
-{
-    DPRINTF(IntRegs, "Setting int reg %d to value %#x\n",
-            intReg, val);
-    regs[intReg] = val;
-}
-
-void IntRegFile::serialize(std::ostream &os)
-{
-    SERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    UNSERIALIZE_ARRAY(regs, NumIntRegs);
-}
diff --git a/src/arch/x86/intregfile.hh b/src/arch/x86/intregfile.hh
index 131245352..a0adcc7e6 100644
--- a/src/arch/x86/intregfile.hh
+++ b/src/arch/x86/intregfile.hh
@@ -89,41 +89,14 @@
 #define __ARCH_X86_INTREGFILE_HH__
 
 #include "arch/x86/intregs.hh"
-#include "arch/x86/types.hh"
 #include "arch/x86/x86_traits.hh"
 
-#include <string>
-
-class Checkpoint;
-
 namespace X86ISA
 {
-    class Regfile;
-
     const int NumIntArchRegs = NUM_INTREGS;
     const int NumIntRegs =
         NumIntArchRegs + NumMicroIntRegs +
         NumPseudoIntRegs + NumImplicitIntRegs;
-
-    class IntRegFile
-    {
-      protected:
-        IntReg regs[NumIntRegs];
-
-      public:
-
-        int flattenIndex(int reg);
-
-        void clear();
-
-        IntReg readReg(int intReg);
-
-        void setReg(int intReg, const IntReg &val);
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-    };
 }
 
 #endif //__ARCH_X86_INTREGFILE__
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 70680703c..54bc0999d 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -127,21 +127,6 @@ Addr RegFile::readNextNPC()
 void RegFile::setNextNPC(Addr val)
 { }
 
-void RegFile::clear()
-{
-    intRegFile.clear();
-}
-
-IntReg RegFile::readIntReg(int intReg)
-{
-    return intRegFile.readReg(intReg);
-}
-
-void RegFile::setIntReg(int intReg, const IntReg &val)
-{
-    intRegFile.setReg(intReg, val);
-}
-
 void
 X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
@@ -167,15 +152,3 @@ X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
     dest->setPC(src->readPC());
     dest->setNextPC(src->readNextPC());
 }
-
-void
-RegFile::serialize(EventManager *em, std::ostream &os)
-{
-    intRegFile.serialize(os);
-}
-
-void
-RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
-{
-    intRegFile.unserialize(cp, section);
-}
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index d1dbe3823..6f7e9120c 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -97,20 +97,17 @@ namespace X86ISA
         Addr readNextNPC();
         void setNextNPC(Addr val);
 
-      protected:
-        IntRegFile intRegFile; // integer register file
-
       public:
 
-        void clear();
-
-        IntReg readIntReg(int intReg);
+        void clear()
+        {}
 
-        void setIntReg(int intReg, const IntReg &val);
+        void serialize(EventManager *em, std::ostream &os)
+        {}
 
-        void serialize(EventManager *em, std::ostream &os);
         void unserialize(EventManager *em, Checkpoint *cp,
-            const std::string &section);
+                const std::string &section)
+        {}
     };
 
     void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 248e78314..36de86986 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -264,7 +264,7 @@ InOrderCPU::InOrderCPU(Params *params)
         squashSeqNum[tid] = MaxAddr;
         lastSquashCycle[tid] = 0;
 
-        intRegFile[tid].clear();
+        memset(intRegs[tid], 0, sizeof(intRegs[tid]));
         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
         isa[tid].clear();
 
@@ -886,7 +886,7 @@ InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid)
 uint64_t
 InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
 {
-    return intRegFile[tid].readReg(reg_idx);
+    return intRegs[tid][reg_idx];
 }
 
 FloatReg
@@ -904,7 +904,7 @@ InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
 void
 InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
 {
-    intRegFile[tid].setReg(reg_idx, val);
+    intRegs[tid][reg_idx] = val;
 }
 
 
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index f4cc72e9c..31010a01f 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -258,11 +258,11 @@ class InOrderCPU : public BaseCPU
     TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
 
     /** The Register File for the CPU */
-    TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
     union {
         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
     } floatRegs;
+    TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 
     /** ISA state */
     TheISA::ISA isa[ThePipeline::MaxThreads];
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 505222b37..d88e02ff1 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -71,7 +71,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
 
     quiesceEvent = new EndQuiesceEvent(tc);
 
-    regs.clear();
+    clearArchRegs();
 
     if (cpu->params()->profile) {
         profile = new FunctionProfile(system->kernelSymtab);
@@ -96,7 +96,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
     : ThreadState(_cpu, _thread_num, _process, _asid),
       cpu(_cpu), itb(_itb), dtb(_dtb)
 {
-    regs.clear();
+    clearArchRegs();
     tc = new ProxyThreadContext<SimpleThread>(this);
 }
 
@@ -193,6 +193,7 @@ SimpleThread::serialize(ostream &os)
     ThreadState::serialize(os);
     regs.serialize(cpu, os);
     SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
+    SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
     // thread_num and cpu_id are deterministic from the config
 }
 
@@ -203,6 +204,7 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
     ThreadState::unserialize(cp, section);
     regs.unserialize(cpu, cp, section);
     UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
+    UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
     // thread_num and cpu_id are deterministic from the config
 }
 
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 5e29fbb6d..97c02d7b8 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -36,6 +36,7 @@
 #include "arch/isa_traits.hh"
 #include "arch/regfile.hh"
 #include "arch/tlb.hh"
+#include "arch/types.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
 #include "cpu/thread_context.hh"
@@ -103,6 +104,7 @@ class SimpleThread : public ThreadState
         FloatReg f[TheISA::NumFloatRegs];
         FloatRegBits i[TheISA::NumFloatRegs];
     } floatRegs;
+    TheISA::IntReg intRegs[TheISA::NumIntRegs];
     TheISA::ISA isa;    // one "instance" of the current ISA.
 
   public:
@@ -230,6 +232,7 @@ class SimpleThread : public ThreadState
     void clearArchRegs()
     {
         regs.clear();
+        memset(intRegs, 0, sizeof(intRegs));
         memset(floatRegs.i, 0, sizeof(floatRegs.i));
     }
 
@@ -239,7 +242,7 @@ class SimpleThread : public ThreadState
     uint64_t readIntReg(int reg_idx)
     {
         int flatIndex = isa.flattenIntIndex(reg_idx);
-        return regs.readIntReg(flatIndex);
+        return intRegs[flatIndex];
     }
 
     FloatReg readFloatReg(int reg_idx)
@@ -257,7 +260,7 @@ class SimpleThread : public ThreadState
     void setIntReg(int reg_idx, uint64_t val)
     {
         int flatIndex = isa.flattenIntIndex(reg_idx);
-        regs.setIntReg(flatIndex, val);
+        intRegs[flatIndex] = val;
     }
 
     void setFloatReg(int reg_idx, FloatReg val)