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author | Nuwan Jayasena <Nuwan.Jayasena@amd.com> | 2012-07-10 22:51:54 -0700 |
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committer | Nuwan Jayasena <Nuwan.Jayasena@amd.com> | 2012-07-10 22:51:54 -0700 |
commit | c10f348120ae4a61c782815280673fba5ee71157 (patch) | |
tree | 71ff97dd09f65e0532bd02d4651125be2989816a | |
parent | 1740c4c448a65dee8b27dcdcdccdc1a6e8b4d6b6 (diff) | |
download | gem5-c10f348120ae4a61c782815280673fba5ee71157.tar.xz |
ruby: adds reset function to Ruby memory controllers
-rw-r--r-- | src/mem/ruby/system/MemoryControl.cc | 6 | ||||
-rw-r--r-- | src/mem/ruby/system/MemoryControl.hh | 1 | ||||
-rw-r--r-- | src/mem/ruby/system/RubyMemoryControl.cc | 44 | ||||
-rw-r--r-- | src/mem/ruby/system/RubyMemoryControl.hh | 1 | ||||
-rw-r--r-- | src/mem/ruby/system/System.cc | 7 | ||||
-rw-r--r-- | src/mem/ruby/system/System.hh | 4 |
6 files changed, 62 insertions, 1 deletions
diff --git a/src/mem/ruby/system/MemoryControl.cc b/src/mem/ruby/system/MemoryControl.cc index cf6a618e0..c3b34d965 100644 --- a/src/mem/ruby/system/MemoryControl.cc +++ b/src/mem/ruby/system/MemoryControl.cc @@ -41,7 +41,11 @@ #include "mem/ruby/system/System.hh" using namespace std; -MemoryControl::MemoryControl(const Params *p) : SimObject(p), m_event(this) {}; +MemoryControl::MemoryControl(const Params *p) : SimObject(p), m_event(this) +{ + g_system_ptr->registerMemController(this); +} + MemoryControl::~MemoryControl() {}; RubyMemoryControl * diff --git a/src/mem/ruby/system/MemoryControl.hh b/src/mem/ruby/system/MemoryControl.hh index eb3de8aef..7e35ef7a0 100644 --- a/src/mem/ruby/system/MemoryControl.hh +++ b/src/mem/ruby/system/MemoryControl.hh @@ -53,6 +53,7 @@ class MemoryControl : public: MemoryControl(const Params *p); virtual void init() = 0; + virtual void reset() = 0; ~MemoryControl(); diff --git a/src/mem/ruby/system/RubyMemoryControl.cc b/src/mem/ruby/system/RubyMemoryControl.cc index e777762e3..4879f4fa6 100644 --- a/src/mem/ruby/system/RubyMemoryControl.cc +++ b/src/mem/ruby/system/RubyMemoryControl.cc @@ -222,6 +222,50 @@ RubyMemoryControl::init() m_tfaw_count[i] = 0; } } +void +RubyMemoryControl::reset() +{ + m_msg_counter = 0; + + assert(m_tFaw <= 62); // must fit in a uint64 shift register + + m_total_banks = m_banks_per_rank * m_ranks_per_dimm * m_dimms_per_channel; + m_total_ranks = m_ranks_per_dimm * m_dimms_per_channel; + m_refresh_period_system = m_refresh_period / m_total_banks; + + assert(m_bankQueues); + + assert(m_bankBusyCounter); + + assert(m_oldRequest); + + for (int i = 0; i < m_total_banks; i++) { + m_bankBusyCounter[i] = 0; + m_oldRequest[i] = 0; + } + + m_busBusyCounter_Basic = 0; + m_busBusyCounter_Write = 0; + m_busBusyCounter_ReadNewRank = 0; + m_busBusy_WhichRank = 0; + + m_roundRobin = 0; + m_refresh_count = 1; + m_need_refresh = 0; + m_refresh_bank = 0; + m_idleCount = 0; + m_ageCounter = 0; + + // Each tfaw shift register keeps a moving bit pattern + // which shows when recent activates have occurred. + // m_tfaw_count keeps track of how many 1 bits are set + // in each shift register. When m_tfaw_count is >= 4, + // new activates are not allowed. + for (int i = 0; i < m_total_ranks; i++) { + m_tfaw_shift[i] = 0; + m_tfaw_count[i] = 0; + } +} RubyMemoryControl::~RubyMemoryControl() { diff --git a/src/mem/ruby/system/RubyMemoryControl.hh b/src/mem/ruby/system/RubyMemoryControl.hh index 2480865ea..af915c807 100644 --- a/src/mem/ruby/system/RubyMemoryControl.hh +++ b/src/mem/ruby/system/RubyMemoryControl.hh @@ -59,6 +59,7 @@ class RubyMemoryControl : public MemoryControl typedef RubyMemoryControlParams Params; RubyMemoryControl(const Params *p); void init(); + void reset(); ~RubyMemoryControl(); diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc index 078e35492..3efa74a6a 100644 --- a/src/mem/ruby/system/System.cc +++ b/src/mem/ruby/system/System.cc @@ -125,6 +125,11 @@ RubySystem::registerSparseMemory(SparseMemory* s) m_sparse_memory_vector.push_back(s); } +void +RubySystem::registerMemController(MemoryControl *mc) { + m_memory_controller = mc; +} + RubySystem::~RubySystem() { delete m_network_ptr; @@ -390,6 +395,8 @@ RubySystem::startup() delete m_cache_recorder; m_cache_recorder = NULL; m_warmup_enabled = false; + // reset DRAM + m_memory_controller->reset(); // Restore eventq head eventq_head = eventq->replaceHead(eventq_head); // Restore curTick diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh index d7d01bcac..3d86c3e02 100644 --- a/src/mem/ruby/system/System.hh +++ b/src/mem/ruby/system/System.hh @@ -47,6 +47,7 @@ class Network; class Profiler; +class MemoryControl; class RubySystem : public SimObject { @@ -128,6 +129,7 @@ class RubySystem : public SimObject void registerProfiler(Profiler*); void registerAbstractController(AbstractController*); void registerSparseMemory(SparseMemory*); + void registerMemController(MemoryControl *mc); bool eventQueueEmpty() { return eventq->empty(); } void enqueueRubyEvent(Tick tick) @@ -161,6 +163,8 @@ class RubySystem : public SimObject static int m_memory_size_bits; static Network* m_network_ptr; + MemoryControl *m_memory_controller; + public: static Profiler* m_profiler_ptr; static MemoryVector* m_mem_vec_ptr; |