diff options
| author | Kevin Lim <ktlim@umich.edu> | 2006-06-13 14:39:05 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-06-13 14:39:05 -0400 |
| commit | dcf02c25e380b113bcf05e3b3a5bf79fc19b3150 (patch) | |
| tree | b908be0b694673ca4e274c2fac25bc491faeda0f | |
| parent | 4ad3d47464734e5747efe9f4158d32bdedc73abc (diff) | |
| download | gem5-dcf02c25e380b113bcf05e3b3a5bf79fc19b3150.tar.xz | |
Make syscalls serialize after instructions so they work properly on the new CPU model.
--HG--
extra : convert_revision : c2cea5771e41d3c97d0e44559316363718d89abd
| -rw-r--r-- | src/arch/alpha/isa/decoder.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 2ecd9f5ad..d2908b27a 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -701,7 +701,7 @@ decode OPCODE default Unknown::unknown() { }}, IsNonSpeculative); 0x83: callsys({{ xc->syscall(R0); - }}, IsNonSpeculative); + }}, IsSerializeAfter, IsNonSpeculative); // Read uniq reg into ABI return value register (r0) 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); // Write uniq reg with value from ABI arg register (r16) |