diff options
| author | Gabe Black <gabeblack@google.com> | 2018-01-05 23:52:29 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-01-20 08:08:06 +0000 |
| commit | fd678694ee6bf9defe10d76e01c3e728a25d1871 (patch) | |
| tree | fae5d677b57395bd48e85b0ab8c37726718f872f | |
| parent | 703662624ca9f6f5454b4d1ac773475c0af1bec5 (diff) | |
| download | gem5-fd678694ee6bf9defe10d76e01c3e728a25d1871.tar.xz | |
x86, mem: Get rid of PageTableOps::getBasePtr.
Pass this constant into the page table constructor.
Change-Id: Icbf730f18d9dfcfebd10a196f7f799514728b0fb
Reviewed-on: https://gem5-review.googlesource.com/7345
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
| -rw-r--r-- | src/arch/x86/pagetable.hh | 8 | ||||
| -rw-r--r-- | src/arch/x86/process.cc | 8 | ||||
| -rw-r--r-- | src/mem/multi_level_page_table.hh | 3 | ||||
| -rw-r--r-- | src/mem/multi_level_page_table_impl.hh | 10 |
4 files changed, 9 insertions, 20 deletions
diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh index 354fb5a5c..490a2591b 100644 --- a/src/arch/x86/pagetable.hh +++ b/src/arch/x86/pagetable.hh @@ -179,14 +179,6 @@ namespace X86ISA PTE.u = flags & PTE_Supervisor ? 0 : 1; } - /** returns the physical memory address of the page table */ - Addr getBasePtr(ThreadContext* tc) - { - CR3 cr3 = pageTablePhysAddr; - DPRINTF(MMU, "CR3: %d\n", cr3); - return cr3.longPdtb; - } - /** returns the page number out of a page table entry */ Addr getPnum(PageTableEntry PTE) { diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 627750cbd..0a94ac417 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -100,9 +100,11 @@ X86Process::X86Process(ProcessParams *params, ObjectFile *objFile, SyscallDesc *_syscallDescs, int _numSyscallDescs) : Process(params, params->useArchPT ? static_cast<EmulationPageTable *>( - new ArchPageTable(params->name, params->pid, - params->system, PageBytes, - PageTableLayout)) : + new ArchPageTable( + params->name, params->pid, + params->system, PageBytes, + PageTableLayout, + pageTablePhysAddr >> PageShift)) : new EmulationPageTable(params->name, params->pid, PageBytes), objFile), diff --git a/src/mem/multi_level_page_table.hh b/src/mem/multi_level_page_table.hh index f71dc0dbc..7cbbd8c0e 100644 --- a/src/mem/multi_level_page_table.hh +++ b/src/mem/multi_level_page_table.hh @@ -140,7 +140,8 @@ class MultiLevelPageTable : public EmulationPageTable public: MultiLevelPageTable(const std::string &__name, uint64_t _pid, System *_sys, Addr pageSize, - const std::vector<uint8_t> &layout); + const std::vector<uint8_t> &layout, + Addr _basePtr); ~MultiLevelPageTable(); void initState(ThreadContext* tc) override; diff --git a/src/mem/multi_level_page_table_impl.hh b/src/mem/multi_level_page_table_impl.hh index 2d7ddc4e4..3356c9ea2 100644 --- a/src/mem/multi_level_page_table_impl.hh +++ b/src/mem/multi_level_page_table_impl.hh @@ -47,10 +47,9 @@ using namespace TheISA; template <class ISAOps> MultiLevelPageTable<ISAOps>::MultiLevelPageTable( const std::string &__name, uint64_t _pid, System *_sys, - Addr pageSize, const std::vector<uint8_t> &layout) + Addr pageSize, const std::vector<uint8_t> &layout, Addr _basePtr) : EmulationPageTable(__name, _pid, pageSize), system(_sys), - logLevelSize(layout), - numLevels(logLevelSize.size()) + basePtr(_basePtr), logLevelSize(layout), numLevels(logLevelSize.size()) { } @@ -63,11 +62,6 @@ template <class ISAOps> void MultiLevelPageTable<ISAOps>::initState(ThreadContext* tc) { - basePtr = pTableISAOps.getBasePtr(tc); - if (basePtr == 0) - basePtr++; - DPRINTF(MMU, "basePtr: %d\n", basePtr); - system->pagePtr = basePtr; /* setting first level of the page table */ |