diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-09-11 09:34:40 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-09-11 09:34:40 -0500 |
| commit | fe5deb4a22260b3e67839fb1efa978cff51e79ba (patch) | |
| tree | d8768dfdaccd6beed5a95fa2b3d305b9f018d7e9 | |
| parent | f47c2f64156ee031c481af8d1516ada9d19da775 (diff) | |
| download | gem5-fe5deb4a22260b3e67839fb1efa978cff51e79ba.tar.xz | |
x86 Regressions: Update stats due to register predication
69 files changed, 4118 insertions, 3890 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 2ecc483cf..97b29a376 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -11,11 +11,12 @@ type=LinuxX86System children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus acpi_description_table_pointer=system.acpi_description_table_pointer boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 +clock=1 e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -51,23 +52,21 @@ oem_table_id= [system.apicbridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 -write_ack=false master=system.membus.slave[0] slave=system.iobus.master[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[1] @@ -139,7 +138,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -173,6 +171,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -201,6 +200,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -209,6 +209,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -497,6 +498,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -519,9 +521,10 @@ mem_side=system.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[4] int_slave=system.membus.master[3] @@ -535,6 +538,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -543,6 +547,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -945,6 +950,7 @@ type=BaseCache addr_ranges=0:134217727 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 is_top_level=false @@ -970,6 +976,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -1004,9 +1011,10 @@ slave=system.apicbridge.master system.system_port system.iocache.mem_side system [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -1026,9 +1034,10 @@ system=system [system.pc.behind_pci] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854779128 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1043,8 +1052,9 @@ pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 children=terminal +clock=1 pio_addr=9223372036854776824 -pio_latency=1000 +pio_latency=100000 platform=system.pc system=system terminal=system.pc.com_1.terminal @@ -1066,9 +1076,10 @@ port=3456 [system.pc.fake_com_2] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776568 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1082,9 +1093,10 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776808 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1098,9 +1110,10 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776552 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1114,9 +1127,10 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776818 -pio_latency=1000 +pio_latency=100000 pio_size=2 ret_bad_addr=false ret_data16=65535 @@ -1130,9 +1144,10 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854775936 -pio_latency=1000 +pio_latency=100000 pio_size=1 ret_bad_addr=false ret_data16=65535 @@ -1147,7 +1162,8 @@ pio=system.iobus.master[11] [system.pc.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1 +pio_latency=30000 platform=system.pc size=16777216 system=system @@ -1162,7 +1178,6 @@ io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 pic2=system.pc.south_bridge.pic2 -pio_latency=1000 pit=system.pc.south_bridge.pit platform=system.pc speaker=system.pc.south_bridge.speaker @@ -1170,9 +1185,10 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos children=int_pin +clock=1 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 -pio_latency=1000 +pio_latency=100000 system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.master[1] @@ -1182,8 +1198,9 @@ type=X86IntSourcePin [system.pc.south_bridge.dma1] type=I8237 +clock=1 pio_addr=9223372036854775808 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1228,16 +1245,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=4 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.pc system=system config=system.iobus.master[4] @@ -1261,7 +1277,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1281,7 +1297,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1364,10 +1380,11 @@ number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 +clock=1 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.iobus.slave[2] pio=system.iobus.master[10] @@ -1375,12 +1392,13 @@ pio=system.iobus.master[10] [system.pc.south_bridge.keyboard] type=I8042 children=keyboard_int_pin mouse_int_pin +clock=1 command_port=9223372036854775908 data_port=9223372036854775904 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[5] @@ -1393,10 +1411,11 @@ type=X86IntSourcePin [system.pc.south_bridge.pic1] type=I8259 children=output +clock=1 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 -pio_latency=1000 +pio_latency=100000 slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.master[6] @@ -1407,10 +1426,11 @@ type=X86IntSourcePin [system.pc.south_bridge.pic2] type=I8259 children=output +clock=1 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 -pio_latency=1000 +pio_latency=100000 slave=Null system=system pio=system.iobus.master[7] @@ -1421,9 +1441,10 @@ type=X86IntSourcePin [system.pc.south_bridge.pit] type=I8254 children=int_pin +clock=1 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[8] @@ -1432,14 +1453,16 @@ type=X86IntSourcePin [system.pc.south_bridge.speaker] type=PcSpeaker +clock=1 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 98becac20..54a312ff8 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -8,7 +8,6 @@ warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc warn: instruction 'fxsave' unimplemented warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 22a267134..a7e5df44c 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:30:36 -gem5 started Jul 27 2012 00:44:18 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:31:43 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5172910256500 because m5_exit instruction encountered +Exiting @ tick 5167941639500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 2d55f3c33..199522594 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.172174 # Number of seconds simulated -sim_ticks 5172174196500 # Number of ticks simulated -final_tick 5172174196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.167942 # Number of seconds simulated +sim_ticks 5167941639500 # Number of ticks simulated +final_tick 5167941639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197854 # Simulator instruction rate (inst/s) -host_op_rate 391125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2509698416 # Simulator tick rate (ticks/s) -host_mem_usage 367744 # Number of bytes of host memory used -host_seconds 2060.87 # Real time elapsed on the host -sim_insts 407751921 # Number of instructions simulated -sim_ops 806059216 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2469504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1070336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10446016 # Number of bytes read from this memory -system.physmem.bytes_read::total 13989120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1070336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1070336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9206912 # Number of bytes written to this memory -system.physmem.bytes_written::total 9206912 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38586 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16724 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 163219 # Number of read requests responded to by this memory -system.physmem.num_reads::total 218580 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143858 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143858 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 477460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 206941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2019657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2704688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 206941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 206941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1780085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1780085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1780085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 477460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 206941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2019657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4484774 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 107330 # number of replacements -system.l2c.tagsinuse 64831.864344 # Cycle average of tags in use -system.l2c.total_refs 3982185 # Total number of references to valid blocks. -system.l2c.sampled_refs 171532 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.215406 # Average number of references to valid blocks. +host_inst_rate 128954 # Simulator instruction rate (inst/s) +host_op_rate 254914 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1633898837 # Simulator tick rate (ticks/s) +host_mem_usage 412792 # Number of bytes of host memory used +host_seconds 3162.95 # Real time elapsed on the host +sim_insts 407876198 # Number of instructions simulated +sim_ops 806280456 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2473280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1074496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10579456 # Number of bytes read from this memory +system.physmem.bytes_read::total 14130624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1074496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1074496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9348288 # Number of bytes written to this memory +system.physmem.bytes_written::total 9348288 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38645 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16789 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165304 # Number of read requests responded to by this memory +system.physmem.num_reads::total 220791 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 146067 # Number of write requests responded to by this memory +system.physmem.num_writes::total 146067 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 478581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 207916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2047131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2734285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 207916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 207916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1808900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1808900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1808900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 478581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 207916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2047131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4543184 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 109808 # number of replacements +system.l2c.tagsinuse 64836.655656 # Cycle average of tags in use +system.l2c.total_refs 3979638 # Total number of references to valid blocks. +system.l2c.sampled_refs 173786 # Sample count of references to valid blocks. +system.l2c.avg_refs 22.899647 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50277.913573 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 9.980895 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.169682 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3388.636576 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11155.163618 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.767180 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000152 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051706 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.170214 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989256 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 111938 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 8555 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1051956 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1345107 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2517556 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1612922 # number of Writeback hits -system.l2c.Writeback_hits::total 1612922 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 325 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 325 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 163659 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 163659 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 111938 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 8555 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1051956 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1508766 # number of demand (read+write) hits -system.l2c.demand_hits::total 2681215 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 111938 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 8555 # number of overall hits -system.l2c.overall_hits::cpu.inst 1051956 # number of overall hits -system.l2c.overall_hits::cpu.data 1508766 # number of overall hits -system.l2c.overall_hits::total 2681215 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 44 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 16726 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 35201 # number of ReadReq misses -system.l2c.ReadReq_misses::total 51978 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1498 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1498 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 128962 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128962 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 44 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 16726 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 164163 # number of demand (read+write) misses -system.l2c.demand_misses::total 180940 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 44 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu.inst 16726 # number of overall misses -system.l2c.overall_misses::cpu.data 164163 # number of overall misses -system.l2c.overall_misses::total 180940 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2308000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 887926997 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1876685493 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2767284490 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 37648500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 37648500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6721908000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6721908000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2308000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 887926997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8598593493 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9489192490 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2308000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 887926997 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8598593493 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9489192490 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 111982 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 8562 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1068682 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1380308 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2569534 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1612922 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1612922 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 292621 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292621 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 111982 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 8562 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1068682 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1672929 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2862155 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 111982 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 8562 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1068682 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1672929 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2862155 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000393 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.015651 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.025502 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020229 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.821722 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.821722 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.440713 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.440713 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000393 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000818 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.015651 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.098129 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.063218 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000393 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000818 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.015651 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.098129 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.063218 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52454.545455 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 53086.631412 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 53313.414193 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 53239.533841 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25132.510013 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 25132.510013 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.168065 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52123.168065 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52454.545455 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 53086.631412 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52378.389119 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52443.862551 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52454.545455 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 53086.631412 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52378.389119 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52443.862551 # average overall miss latency +system.l2c.occ_blocks::writebacks 50087.148367 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 11.882077 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.155165 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3382.932484 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11354.537562 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.764269 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000181 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.051619 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.173256 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989329 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 103999 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 8349 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1054675 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1347003 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2514026 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1610152 # number of Writeback hits +system.l2c.Writeback_hits::total 1610152 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 315 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 315 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 158022 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 158022 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 103999 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 8349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1054675 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1505025 # number of demand (read+write) hits +system.l2c.demand_hits::total 2672048 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 103999 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 8349 # number of overall hits +system.l2c.overall_hits::cpu.inst 1054675 # number of overall hits +system.l2c.overall_hits::cpu.data 1505025 # number of overall hits +system.l2c.overall_hits::total 2672048 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 47 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 16790 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 35954 # number of ReadReq misses +system.l2c.ReadReq_misses::total 52797 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 3370 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3370 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 130295 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130295 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 47 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 16790 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 166249 # number of demand (read+write) misses +system.l2c.demand_misses::total 183092 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 47 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses +system.l2c.overall_misses::cpu.inst 16790 # number of overall misses +system.l2c.overall_misses::cpu.data 166249 # number of overall misses +system.l2c.overall_misses::total 183092 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2467000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 312500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 890951999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1919150991 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2812882490 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 39655500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 39655500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6791571999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6791571999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 2467000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 890951999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8710722990 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9604454489 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 2467000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 312500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 890951999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8710722990 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9604454489 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 104046 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 8355 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1071465 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1382957 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2566823 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1610152 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1610152 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3685 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3685 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 288317 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 288317 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 104046 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 8355 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1071465 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1671274 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2855140 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 104046 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 8355 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1071465 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1671274 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2855140 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000718 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.015670 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.025998 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020569 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.914518 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.914518 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.451916 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.451916 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000718 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.015670 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.099474 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.064127 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000718 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.015670 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.099474 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.064127 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52489.361702 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52083.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53064.443061 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 53377.954915 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 53277.316704 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 11767.210682 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 11767.210682 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52124.578833 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52124.578833 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52489.361702 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53064.443061 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52395.641417 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52456.986045 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52489.361702 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53064.443061 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52395.641417 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52456.986045 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -189,99 +189,99 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 97191 # number of writebacks -system.l2c.writebacks::total 97191 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 99400 # number of writebacks +system.l2c.writebacks::total 99400 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 44 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 16724 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 35200 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 51975 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 1498 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1498 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 128962 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 128962 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 44 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 16724 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 164162 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 180937 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 44 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 16724 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 164162 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 180937 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 1774500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 683968997 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 1446479000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2132502497 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 60328500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 60328500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5168491500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5168491500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 1774500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 683968997 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6614970500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7300993997 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 1774500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 683968997 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6614970500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7300993997 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 88673683000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 88673683000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2309054000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2309054000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 90982737000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 90982737000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025502 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020227 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.821722 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.821722 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.440713 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.440713 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.098128 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063217 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.098128 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063217 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average ReadReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 47 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 16789 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 35952 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 52794 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 3370 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3370 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 130295 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 130295 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 47 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 16789 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 166247 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 183089 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 47 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 16789 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 166247 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 183089 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 1896500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 686209999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1479692999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2168039498 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 135202500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 135202500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5222060002 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5222060002 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 1896500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 686209999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6701753001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7390099500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 1896500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 686209999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6701753001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7390099500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 88673823000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 88673823000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2308951500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2308951500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 90982774500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 90982774500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000718 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015669 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025996 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020568 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.914518 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.914518 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.451916 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.451916 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000718 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015669 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.099473 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.064126 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000718 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015669 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.099473 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.064126 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40351.063830 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40897.452583 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41093.153409 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 41029.389072 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40272.696929 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40272.696929 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40077.631395 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40077.631395 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40872.595092 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41157.459919 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41066.020722 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40119.436202 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40119.436202 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.744403 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.744403 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40351.063830 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40897.452583 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.382001 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40351.028242 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40872.595092 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40312.023682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40363.427076 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40351.063830 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40897.452583 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.382001 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40351.028242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40872.595092 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40312.023682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40363.427076 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47572 # number of replacements -system.iocache.tagsinuse 0.197153 # Cycle average of tags in use +system.iocache.replacements 47571 # number of replacements +system.iocache.tagsinuse 0.197047 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47587 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5000849406000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.197153 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.012322 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.012322 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses +system.iocache.warmup_cycle 4996693441000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.197047 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.012315 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.012315 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses +system.iocache.ReadReq_misses::total 906 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses -system.iocache.demand_misses::total 47627 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses -system.iocache.overall_misses::total 47627 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136172932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 136172932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6920648160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6920648160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 7056821092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7056821092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 7056821092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7056821092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses +system.iocache.demand_misses::total 47626 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses +system.iocache.overall_misses::total 47626 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136049932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 136049932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6913813160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6913813160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 7049863092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7049863092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 7049863092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7049863092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,14 +330,14 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150135.536935 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 150135.536935 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148130.311644 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 148130.311644 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148168.498793 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 148168.498793 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148168.498793 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 148168.498793 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150165.487859 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 150165.487859 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147984.014555 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 147984.014555 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148025.513207 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 148025.513207 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148025.513207 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 148025.513207 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked @@ -348,22 +348,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88977000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88977000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4490887946 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4490887946 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4579864946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4579864946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4579864946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4579864946 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47626 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47626 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47626 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88906000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88906000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4484057918 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4484057918 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4572963918 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4572963918 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4572963918 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4572963918 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98100.330761 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 98100.330761 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96123.457748 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 96123.457748 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 96161.104961 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 96161.104961 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98130.242826 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 98130.242826 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95977.267080 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 95977.267080 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96018.223617 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 96018.223617 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96018.223617 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 96018.223617 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,411 +393,411 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 475031565 # number of cpu cycles simulated +system.cpu.numCycles 465854401 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86684856 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86684856 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1176632 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 82122133 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79543196 # Number of BTB hits +system.cpu.BPredUnit.lookups 86523106 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86523106 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1197724 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 82002674 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79454296 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31269539 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 428184771 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86684856 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79543196 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164289785 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5325147 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 164614 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 76824227 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37234 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 45914 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 429 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9378048 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 536886 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4957 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 276741596 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.053538 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.401990 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31142494 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427260156 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86523106 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79454296 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164033620 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5133412 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 157235 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 72542740 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 65499 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9290212 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 538342 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3947 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 271874324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.102439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.406784 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 112886536 40.79% 40.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1619655 0.59% 41.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71962795 26.00% 67.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 983886 0.36% 67.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1644119 0.59% 68.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2486257 0.90% 69.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1139995 0.41% 69.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1450599 0.52% 70.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82567754 29.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 108271510 39.82% 39.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1601345 0.59% 40.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71956301 26.47% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 975717 0.36% 67.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1623613 0.60% 67.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2452165 0.90% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1122687 0.41% 69.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1426947 0.52% 69.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82444039 30.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 276741596 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.182482 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.901382 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35010017 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 74311956 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159865423 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3444346 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4109854 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 841785392 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 993 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4109854 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38173067 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 41532647 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11823127 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159691932 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 21410969 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 837988743 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10561 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14331873 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3961467 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8380256 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1328629800 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2380702001 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2380701417 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 584 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1282020322 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46609471 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 469457 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 477289 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 33840968 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17569417 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10446486 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1246814 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1007946 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 831743249 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1259421 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823989117 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 123035 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26027822 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 53490149 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 209479 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 276741596 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.977468 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.409448 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 271874324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185730 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.917154 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34951113 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 69967599 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159705810 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3354905 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3894897 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840212837 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1268 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3894897 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37909479 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43328722 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11932417 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159774211 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15034598 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836385126 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 33598 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7166437 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5990052 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 17455 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998119194 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816357971 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816357131 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 840 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964226207 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33892980 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 468339 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 476044 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 32058525 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17336195 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10280230 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1246899 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 991215 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 830038809 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1256743 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824423080 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186157 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23985276 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36420028 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 206597 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 271874324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.032368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.413899 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 86092872 31.11% 31.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17946523 6.48% 37.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 12957239 4.68% 42.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7826219 2.83% 45.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 76249367 27.55% 72.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3109383 1.12% 73.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 71927366 25.99% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 520136 0.19% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 112491 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82559406 30.37% 30.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18414875 6.77% 37.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10591768 3.90% 41.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7608288 2.80% 43.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75794422 27.88% 71.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3619554 1.33% 73.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72418483 26.64% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 726775 0.27% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 140753 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 276741596 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 271874324 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 163103 18.01% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 583729 64.45% 82.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 158924 17.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 331331 32.21% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547593 53.24% 85.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 149610 14.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 296041 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796340985 96.64% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17916922 2.17% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9435169 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308279 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796609033 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18024617 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9481151 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823989117 # Type of FU issued -system.cpu.iq.rate 1.734599 # Inst issue rate -system.cpu.iq.fu_busy_cnt 905756 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001099 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1925886604 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 859041376 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819484767 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 824598744 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 88 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1578458 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824423080 # Type of FU issued +system.cpu.iq.rate 1.769701 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1028534 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001248 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1922068884 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 855291159 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819794003 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 201 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 398 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825143243 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1662305 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3618337 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20593 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12016 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2047079 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3372855 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25441 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11901 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1870494 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1917340 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4451 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1917611 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21826 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4109854 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27168187 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1772103 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 833002670 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 300864 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17569417 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10446486 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 728436 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 974858 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15486 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12016 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 697910 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 625387 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1323297 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822095189 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17489841 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1893927 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3894897 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28837700 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2469058 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831295552 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 338895 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17336195 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10280230 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 727529 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1778064 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16969 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11901 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 715653 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 628490 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1344143 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822456639 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17610649 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1966440 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26681633 # number of memory reference insts executed -system.cpu.iew.exec_branches 83151598 # Number of branches executed -system.cpu.iew.exec_stores 9191792 # Number of stores executed -system.cpu.iew.exec_rate 1.730612 # Inst execution rate -system.cpu.iew.wb_sent 821608460 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819484817 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640296111 # num instructions producing a value -system.cpu.iew.wb_consumers 1828731330 # num instructions consuming a value +system.cpu.iew.exec_refs 26845315 # number of memory reference insts executed +system.cpu.iew.exec_branches 83298308 # Number of branches executed +system.cpu.iew.exec_stores 9234666 # Number of stores executed +system.cpu.iew.exec_rate 1.765480 # Inst execution rate +system.cpu.iew.wb_sent 821926439 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819794057 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639752157 # num instructions producing a value +system.cpu.iew.wb_consumers 1045352654 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.725117 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.350131 # average fanout of values written-back +system.cpu.iew.wb_rate 1.759765 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611996 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 407751921 # The number of committed instructions -system.cpu.commit.commitCommittedOps 806059216 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26839677 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1049940 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1181775 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 272647181 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.956419 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.843352 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 407876198 # The number of committed instructions +system.cpu.commit.commitCommittedOps 806280456 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24913133 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1050144 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1202812 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267994872 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.008567 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.862606 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 98573076 36.15% 36.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13223290 4.85% 41.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4246957 1.56% 42.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 75817327 27.81% 70.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2710299 0.99% 71.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1789124 0.66% 72.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1087866 0.40% 72.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71017917 26.05% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4181325 1.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95708063 35.71% 35.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12360558 4.61% 40.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3940570 1.47% 41.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74894252 27.95% 69.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2417220 0.90% 70.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1553799 0.58% 71.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1057768 0.39% 71.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70929617 26.47% 98.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5133025 1.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 272647181 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407751921 # Number of instructions committed -system.cpu.commit.committedOps 806059216 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267994872 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407876198 # Number of instructions committed +system.cpu.commit.committedOps 806280456 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22350484 # Number of memory references committed -system.cpu.commit.loads 13951077 # Number of loads committed -system.cpu.commit.membars 471695 # Number of memory barriers committed -system.cpu.commit.branches 82163258 # Number of branches committed +system.cpu.commit.refs 22373073 # Number of memory references committed +system.cpu.commit.loads 13963337 # Number of loads committed +system.cpu.commit.membars 471701 # Number of memory barriers committed +system.cpu.commit.branches 82186197 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735013406 # Number of committed integer instructions. +system.cpu.commit.int_insts 735221140 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4181325 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5133025 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1101286190 # The number of ROB reads -system.cpu.rob.rob_writes 1669922447 # The number of ROB writes -system.cpu.timesIdled 1659907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 198289969 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9869314281 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407751921 # Number of Instructions Simulated -system.cpu.committedOps 806059216 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407751921 # Number of Instructions Simulated -system.cpu.cpi 1.165001 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.165001 # CPI: Total CPI of All Threads -system.cpu.ipc 0.858368 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.858368 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2053713870 # number of integer regfile reads -system.cpu.int_regfile_writes 1297159076 # number of integer regfile writes -system.cpu.fp_regfile_reads 50 # number of floating regfile reads -system.cpu.misc_regfile_reads 265135377 # number of misc regfile reads -system.cpu.misc_regfile_writes 402339 # number of misc regfile writes -system.cpu.icache.replacements 1068223 # number of replacements -system.cpu.icache.tagsinuse 510.418027 # Cycle average of tags in use -system.cpu.icache.total_refs 8239400 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1068735 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.709488 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 57281567000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.418027 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996910 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996910 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8239400 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8239400 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8239400 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8239400 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8239400 # number of overall hits -system.cpu.icache.overall_hits::total 8239400 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1138645 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1138645 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1138645 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1138645 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1138645 # number of overall misses -system.cpu.icache.overall_misses::total 1138645 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18814976480 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18814976480 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18814976480 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18814976480 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18814976480 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18814976480 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9378045 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9378045 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9378045 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9378045 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9378045 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9378045 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121416 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121416 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121416 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121416 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121416 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121416 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16524.005709 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16524.005709 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16524.005709 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16524.005709 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16524.005709 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16524.005709 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3200487 # number of cycles access was blocked +system.cpu.rob.rob_reads 1093976833 # The number of ROB reads +system.cpu.rob.rob_writes 1666301286 # The number of ROB writes +system.cpu.timesIdled 1419086 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 193980077 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9870026331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407876198 # Number of Instructions Simulated +system.cpu.committedOps 806280456 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407876198 # Number of Instructions Simulated +system.cpu.cpi 1.142147 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.142147 # CPI: Total CPI of All Threads +system.cpu.ipc 0.875544 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.875544 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508347107 # number of integer regfile reads +system.cpu.int_regfile_writes 977902256 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.misc_regfile_reads 265221380 # number of misc regfile reads +system.cpu.misc_regfile_writes 402568 # number of misc regfile writes +system.cpu.icache.replacements 1070981 # number of replacements +system.cpu.icache.tagsinuse 510.788530 # Cycle average of tags in use +system.cpu.icache.total_refs 8144587 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1071493 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.601157 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 147426882000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.788530 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997634 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997634 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8144587 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8144587 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8144587 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8144587 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8144587 # number of overall hits +system.cpu.icache.overall_hits::total 8144587 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1145619 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1145619 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1145619 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1145619 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1145619 # number of overall misses +system.cpu.icache.overall_misses::total 1145619 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18957217490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18957217490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18957217490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18957217490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18957217490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18957217490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9290206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9290206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9290206 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9290206 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9290206 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9290206 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123315 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123315 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123315 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123315 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123315 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123315 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16547.576018 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16547.576018 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16547.576018 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16547.576018 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16547.576018 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16547.576018 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3193494 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 386 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 405 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8291.417098 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7885.170370 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69787 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69787 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69787 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69787 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69787 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69787 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1068858 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1068858 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1068858 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1068858 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1068858 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1068858 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14704003987 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14704003987 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14704003987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14704003987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14704003987 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14704003987 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113975 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.113975 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.113975 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13756.742230 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13756.742230 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13756.742230 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13756.742230 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13756.742230 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13756.742230 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72182 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 72182 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 72182 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 72182 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 72182 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 72182 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1073437 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1073437 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1073437 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1073437 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1073437 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1073437 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14797672994 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14797672994 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14797672994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14797672994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14797672994 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14797672994 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115545 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115545 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115545 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115545 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115545 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115545 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13785.320418 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13785.320418 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13785.320418 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13785.320418 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13785.320418 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13785.320418 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10021 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.028958 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 32291 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10034 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.218158 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5136098133000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.028958 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376810 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376810 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 32310 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 32310 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9807 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.044173 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 32941 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9822 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 3.353798 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5136134294000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.044173 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377761 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.377761 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 32940 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 32940 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 32313 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 32313 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 32313 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 32313 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10911 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10911 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10911 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10911 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10911 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10911 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183901500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183901500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183901500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 183901500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183901500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 183901500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43221 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 32943 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 32943 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 32943 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 32943 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10696 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10696 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10696 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10696 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10696 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10696 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176478000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176478000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176478000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 176478000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176478000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 176478000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43636 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 43636 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43224 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 43224 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43224 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 43224 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.252447 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.252447 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.252429 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.252429 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.252429 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.252429 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16854.687930 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16854.687930 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16854.687930 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16854.687930 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16854.687930 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16854.687930 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43639 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 43639 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43639 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 43639 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.245119 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.245119 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.245102 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.245102 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.245102 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.245102 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16499.439043 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16499.439043 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16499.439043 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16499.439043 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16499.439043 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16499.439043 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,78 +806,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1563 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1563 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10911 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10911 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10911 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10911 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10911 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10911 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 150559535 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 150559535 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 150559535 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 150559535 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 150559535 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 150559535 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.252447 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.252447 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.252429 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.252429 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.252429 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.252429 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13798.875905 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13798.875905 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13798.875905 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1799 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1799 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10696 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10696 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10696 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10696 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10696 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10696 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143761538 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143761538 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143761538 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143761538 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143761538 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143761538 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245119 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245119 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245102 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245102 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245102 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245102 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13440.682311 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13440.682311 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13440.682311 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 116564 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.971477 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 137576 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 116580 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.180100 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5113123336000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.971477 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810717 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.810717 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137576 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 137576 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137576 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 137576 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137576 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 137576 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117614 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 117614 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117614 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 117614 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117614 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 117614 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2140596500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2140596500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2140596500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2140596500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2140596500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2140596500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255190 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 255190 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255190 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 255190 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255190 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 255190 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.460888 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.460888 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.460888 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.460888 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.460888 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.460888 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18200.184502 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18200.184502 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18200.184502 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18200.184502 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18200.184502 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18200.184502 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 109374 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.962684 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 139077 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109389 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.271398 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5108961672000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.962684 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810168 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.810168 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139087 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 139087 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139087 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 139087 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139087 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 139087 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110364 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110364 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110364 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110364 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110364 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110364 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2009314000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2009314000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2009314000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2009314000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2009314000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2009314000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249451 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 249451 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249451 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 249451 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249451 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 249451 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442428 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442428 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442428 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442428 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442428 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442428 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18206.244790 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18206.244790 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18206.244790 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18206.244790 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18206.244790 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18206.244790 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,146 +886,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 39184 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 39184 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117614 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117614 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117614 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 117614 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117614 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 117614 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1785080011 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1785080011 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1785080011 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.460888 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.460888 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.460888 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15177.444956 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15177.444956 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15177.444956 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35688 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35688 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110364 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110364 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110364 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110364 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110364 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110364 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1675589507 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1675589507 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1675589507 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442428 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442428 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442428 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15182.391967 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15182.391967 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15182.391967 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673020 # number of replacements -system.cpu.dcache.tagsinuse 511.997654 # Cycle average of tags in use -system.cpu.dcache.total_refs 19008279 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673532 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.358181 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997654 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10932679 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10932679 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8073031 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8073031 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19005710 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19005710 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19005710 # number of overall hits -system.cpu.dcache.overall_hits::total 19005710 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2430444 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2430444 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317095 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317095 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2747539 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2747539 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2747539 # number of overall misses -system.cpu.dcache.overall_misses::total 2747539 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45216991000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45216991000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10602716492 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10602716492 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55819707492 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55819707492 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55819707492 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55819707492 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13363123 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13363123 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8390126 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8390126 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21753249 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21753249 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21753249 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21753249 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181877 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.181877 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037794 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037794 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.126305 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.126305 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.126305 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.126305 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18604.415901 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18604.415901 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33437.034617 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33437.034617 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.256654 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20316.256654 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.256654 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20316.256654 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 27551492 # number of cycles access was blocked +system.cpu.dcache.replacements 1671342 # number of replacements +system.cpu.dcache.tagsinuse 511.998194 # Cycle average of tags in use +system.cpu.dcache.total_refs 19219573 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1671854 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.495964 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35774000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.998194 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11132776 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11132776 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8081984 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8081984 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19214760 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19214760 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19214760 # number of overall hits +system.cpu.dcache.overall_hits::total 19214760 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2269875 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2269875 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318465 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318465 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2588340 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2588340 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2588340 # number of overall misses +system.cpu.dcache.overall_misses::total 2588340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48782293500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48782293500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10759861985 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10759861985 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 59542155485 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 59542155485 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 59542155485 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 59542155485 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13402651 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13402651 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8400449 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8400449 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21803100 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21803100 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21803100 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21803100 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169360 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169360 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037910 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037910 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118714 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118714 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118714 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118714 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21491.180572 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21491.180572 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33786.638987 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33786.638987 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23003.993094 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23003.993094 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23003.993094 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23003.993094 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 188390485 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4916 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 47569 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5604.453214 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3960.362526 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1572175 # number of writebacks -system.cpu.dcache.writebacks::total 1572175 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1048961 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1048961 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22710 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22710 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1071671 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1071671 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1071671 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1071671 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381483 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1381483 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294385 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 294385 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1675868 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1675868 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1675868 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1675868 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23305790513 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23305790513 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9339566493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9339566493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32645357006 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32645357006 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32645357006 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32645357006 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96733569500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96733569500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2477085000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2477085000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99210654500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99210654500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103380 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103380 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077040 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077040 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077040 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16870.124723 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16870.124723 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31725.687426 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31725.687426 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19479.670837 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19479.670837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19479.670837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19479.670837 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1572665 # number of writebacks +system.cpu.dcache.writebacks::total 1572665 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 885789 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 885789 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26582 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26582 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912371 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912371 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912371 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912371 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1384086 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1384086 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291883 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291883 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1675969 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1675969 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1675969 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1675969 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25963695523 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25963695523 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9454770488 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9454770488 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35418466011 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 35418466011 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35418466011 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 35418466011 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96735790500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96735790500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2476089500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2476089500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99211880000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99211880000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076868 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076868 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076868 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076868 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18758.729965 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18758.729965 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32392.330105 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32392.330105 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21133.127171 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21133.127171 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21133.127171 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21133.127171 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 6a8db2c50..0bbc8945c 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -39,7 +39,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812499
+result 7812531
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats index 5488faf0f..094befb99 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,24 +1,24 @@ -Real time: Sep/10/2012 12:39:22 +Real time: Sep/10/2012 23:29:19 Profiler Stats -------------- -Elapsed_time_in_seconds: 743 -Elapsed_time_in_minutes: 12.3833 -Elapsed_time_in_hours: 0.206389 -Elapsed_time_in_days: 0.00859954 +Elapsed_time_in_seconds: 752 +Elapsed_time_in_minutes: 12.5333 +Elapsed_time_in_hours: 0.208889 +Elapsed_time_in_days: 0.0087037 -Virtual_time_in_seconds: 741.97 -Virtual_time_in_minutes: 12.3662 -Virtual_time_in_hours: 0.206103 -Virtual_time_in_days: 0.00858762 +Virtual_time_in_seconds: 751.42 +Virtual_time_in_minutes: 12.5237 +Virtual_time_in_hours: 0.208728 +Virtual_time_in_days: 0.00869699 Ruby_current_time: 10410013848 Ruby_start_time: 0 Ruby_cycles: 10410013848 -mbytes_resident: 256.176 -mbytes_total: 493.555 -resident_ratio: 0.51905 +mbytes_resident: 256.566 +mbytes_total: 493.43 +resident_ratio: 0.519973 ruby_cycles_executed: [ 10410013849 10410013849 ] @@ -87,13 +87,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4899404 average: 0.0429665 | Resource Usage -------------- page_size: 4096 -user_time: 741 +user_time: 751 system_time: 0 -page_reclaims: 56598 +page_reclaims: 57058 page_faults: 18 swaps: 0 -block_inputs: 28712 -block_outputs: 496 +block_inputs: 16016 +block_outputs: 528 Network Stats ------------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index 7cba7ff73..a4aaa0fce 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-bo gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 12:26:53 -gem5 started Sep 10 2012 12:26:58 +gem5 compiled Sep 10 2012 23:16:41 +gem5 started Sep 10 2012 23:16:46 gem5 executing on ribera.cs.wisc.edu command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory warning: add_child('terminal'): child 'terminal' already has parent diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index 2c7da93fe..ccb436843 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.205007 # Nu sim_ticks 5205006924000 # Number of ticks simulated final_tick 5205006924000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145510 # Simulator instruction rate (inst/s) -host_op_rate 279202 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7001191594 # Simulator tick rate (ticks/s) -host_mem_usage 505404 # Number of bytes of host memory used -host_seconds 743.45 # Real time elapsed on the host +host_inst_rate 143770 # Simulator instruction rate (inst/s) +host_op_rate 275863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6917470976 # Simulator tick rate (ticks/s) +host_mem_usage 505276 # Number of bytes of host memory used +host_seconds 752.44 # Real time elapsed on the host sim_insts 108178578 # Number of instructions simulated sim_ops 207571464 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35216 # Number of bytes read from this memory @@ -125,8 +125,8 @@ system.cpu0.num_func_calls 0 # nu system.cpu0.num_conditional_control_insts 16553172 # number of instructions that are conditional controls system.cpu0.num_int_insts 169447650 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 526613811 # number of times the integer registers were read -system.cpu0.num_int_register_writes 279904453 # number of times the integer registers were written +system.cpu0.num_int_register_reads 418656867 # number of times the integer registers were read +system.cpu0.num_int_register_writes 211655789 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written system.cpu0.num_mem_refs 20197632 # number of memory refs @@ -149,8 +149,8 @@ system.cpu1.num_func_calls 0 # nu system.cpu1.num_conditional_control_insts 1864532 # number of instructions that are conditional controls system.cpu1.num_int_insts 27537877 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 83543948 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39599816 # number of times the integer registers were written +system.cpu1.num_int_register_reads 71380294 # number of times the integer registers were read +system.cpu1.num_int_register_writes 31003707 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written system.cpu1.num_mem_refs 6975131 # number of memory refs diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index c34a24e32..abf2e74d2 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,6 +129,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -157,6 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -428,6 +430,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -450,9 +453,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -466,6 +470,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -474,6 +479,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -515,7 +521,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -538,6 +544,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index df6cae2da..dbf6b4770 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:23:13 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:44:55 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,8 +20,8 @@ Uncompressing Data info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly -Compressing Input Data, level 3 info: Increasing stack size by one page. +Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -40,4 +42,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 636923447500 because target called exit() +Exiting @ tick 609566727000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index e0bb93d0f..747c74984 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,279 +1,279 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.636923 # Number of seconds simulated -sim_ticks 636923447500 # Number of ticks simulated -final_tick 636923447500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.609567 # Number of seconds simulated +sim_ticks 609566727000 # Number of ticks simulated +final_tick 609566727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70364 # Simulator instruction rate (inst/s) -host_op_rate 129650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50926468 # Simulator tick rate (ticks/s) -host_mem_usage 235448 # Number of bytes of host memory used -host_seconds 12506.73 # Real time elapsed on the host +host_inst_rate 62263 # Simulator instruction rate (inst/s) +host_op_rate 114724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43127912 # Simulator tick rate (ticks/s) +host_mem_usage 276908 # Number of bytes of host memory used +host_seconds 14133.93 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493925 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1694720 # Number of bytes read from this memory -system.physmem.bytes_read::total 1753664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 163072 # Number of bytes written to this memory -system.physmem.bytes_written::total 163072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26480 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27401 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2548 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2548 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2660791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2753336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 256031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 256031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 256031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2660791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3009366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 58368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1694464 # Number of bytes read from this memory +system.physmem.bytes_read::total 1752832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162880 # Number of bytes written to this memory +system.physmem.bytes_written::total 162880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 912 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26476 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2545 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2545 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 95753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2779784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2875538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 95753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 95753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 267206 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 267206 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 267206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 95753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2779784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3142744 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1273846896 # number of cpu cycles simulated +system.cpu.numCycles 1219133455 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 155381473 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 155381473 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26661992 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 76481328 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 76085061 # Number of BTB hits +system.cpu.BPredUnit.lookups 154519843 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 154519843 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26678926 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77274626 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76985066 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180777781 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1491151373 # Number of instructions fetch has processed -system.cpu.fetch.Branches 155381473 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 76085061 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 402336644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 93587210 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 623938160 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1139 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 185942531 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8615707 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1273819882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.001935 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.237130 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180157368 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1482244654 # Number of instructions fetch has processed +system.cpu.fetch.Branches 154519843 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76985066 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 400441074 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 91643666 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 573697614 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186403933 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9747583 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1219106465 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.078734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.272852 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 878702474 68.98% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24435713 1.92% 70.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15105270 1.19% 72.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18072889 1.42% 73.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26727903 2.10% 75.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18276740 1.43% 77.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28604131 2.25% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39838610 3.13% 82.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 224056152 17.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 825883799 67.75% 67.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24475369 2.01% 69.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15188361 1.25% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18161843 1.49% 72.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26717986 2.19% 74.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18155688 1.49% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28775832 2.36% 78.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39425650 3.23% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 222321937 18.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1273819882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121978 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.170589 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 300142098 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 537000439 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 281769365 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88141967 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 66766013 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2369867389 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 66766013 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 352580189 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124109997 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1918 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302594361 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 427767404 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2274189452 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 293406849 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 103032322 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3464260390 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7121426016 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 7121418052 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7964 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 2493860878 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 970399512 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 94 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 94 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 745525627 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 545851562 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222235793 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 352099065 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 146974262 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2027094513 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 587 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1785918647 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 140586 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 405462466 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1049512028 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 537 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1273819882 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.402018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.312119 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1219106465 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126746 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215818 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 289371714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497062295 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 275168406 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92693923 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 64810127 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2355715170 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 64810127 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 337830723 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 122995154 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1813 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 305493642 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387975006 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2259654010 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242278891 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120849469 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2627164074 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5766696541 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5766690921 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5620 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 740268817 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 96 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 96 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 730471883 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 541137404 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220343917 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 347951990 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144808328 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2010997367 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 534 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1784139180 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 263264 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 389085977 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 810611327 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 484 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1219106465 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.463481 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.418984 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 346849812 27.23% 27.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 447400536 35.12% 62.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 243205365 19.09% 81.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151321871 11.88% 93.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 40825213 3.20% 96.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 32566088 2.56% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9897563 0.78% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1402374 0.11% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 351060 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 363767078 29.84% 29.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 365542734 29.98% 59.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234442506 19.23% 79.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141155043 11.58% 90.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 61085427 5.01% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39802416 3.26% 98.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10825326 0.89% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1946919 0.16% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 539016 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1273819882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1219106465 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 260443 10.10% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2141420 83.03% 93.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 177309 6.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 465020 16.12% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2178971 75.55% 91.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 240132 8.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812744 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1067089927 59.75% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479538721 26.85% 89.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192477255 10.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46815442 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065636060 59.73% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478995198 26.85% 89.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192692480 10.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1785918647 # Type of FU issued -system.cpu.iq.rate 1.401988 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2579172 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001444 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4848376217 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2432738390 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1727118998 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 717 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2336 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1741684846 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 229 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 208839211 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1784139180 # Type of FU issued +system.cpu.iq.rate 1.463449 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2884123 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001617 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4790531580 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2400258808 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1725049081 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 632 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1764 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 163 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740207554 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209593506 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 126809441 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36531 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 190384 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 34049736 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 122095283 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38780 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 181714 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 32157860 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2138 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 453 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2258 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 452 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 66766013 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 400873 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 86074 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2027095100 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63749855 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 545851562 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222235793 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48364 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 665 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 190384 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2138396 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24649145 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26787541 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1767801211 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 473822669 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18117436 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 64810127 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 288054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 51315 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2010997901 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63873969 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 541137404 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220343917 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 29041 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 466 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 181714 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2119314 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24709049 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26828363 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766210973 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474185905 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17928207 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665669278 # number of memory reference insts executed -system.cpu.iew.exec_branches 109723805 # Number of branches executed -system.cpu.iew.exec_stores 191846609 # Number of stores executed -system.cpu.iew.exec_rate 1.387766 # Inst execution rate -system.cpu.iew.wb_sent 1728448502 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1727119074 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1262324846 # num instructions producing a value -system.cpu.iew.wb_consumers 2985456049 # num instructions consuming a value +system.cpu.iew.exec_refs 666011474 # number of memory reference insts executed +system.cpu.iew.exec_branches 110196607 # Number of branches executed +system.cpu.iew.exec_stores 191825569 # Number of stores executed +system.cpu.iew.exec_rate 1.448743 # Inst execution rate +system.cpu.iew.wb_sent 1726341541 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1725049244 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267580159 # num instructions producing a value +system.cpu.iew.wb_consumers 1828717326 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.355829 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.422825 # average fanout of values written-back +system.cpu.iew.wb_rate 1.414980 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.693153 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 880025277 # The number of committed instructions system.cpu.commit.commitCommittedOps 1621493925 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 405606358 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 389506426 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26662143 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1207053869 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.343348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.659934 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26678961 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1154296338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.404747 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.831971 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 437041200 36.21% 36.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 432850092 35.86% 72.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 93447270 7.74% 79.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 134928627 11.18% 90.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35706636 2.96% 93.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23539949 1.95% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 25505485 2.11% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8872667 0.74% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15161943 1.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 420857241 36.46% 36.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 413520492 35.82% 72.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87361055 7.57% 79.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122186130 10.59% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24494860 2.12% 92.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23109073 2.00% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18457710 1.60% 96.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12056348 1.04% 97.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32253429 2.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1207053869 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1154296338 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,68 +284,68 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15161943 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32253429 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3218992209 # The number of ROB reads -system.cpu.rob.rob_writes 4120983322 # The number of ROB writes -system.cpu.timesIdled 600 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3133043260 # The number of ROB reads +system.cpu.rob.rob_writes 4086848885 # The number of ROB writes +system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26990 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.447512 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.447512 # CPI: Total CPI of All Threads -system.cpu.ipc 0.690841 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.690841 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4473913165 # number of integer regfile reads -system.cpu.int_regfile_writes 2590095162 # number of integer regfile writes -system.cpu.fp_regfile_reads 76 # number of floating regfile reads -system.cpu.misc_regfile_reads 911461004 # number of misc regfile reads -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 826.529270 # Cycle average of tags in use -system.cpu.icache.total_refs 185941160 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 930 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 199936.731183 # Average number of references to valid blocks. +system.cpu.cpi 1.385339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.385339 # CPI: Total CPI of All Threads +system.cpu.ipc 0.721845 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.721845 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3541474948 # number of integer regfile reads +system.cpu.int_regfile_writes 1975063996 # number of integer regfile writes +system.cpu.fp_regfile_reads 163 # number of floating regfile reads +system.cpu.misc_regfile_reads 910391945 # number of misc regfile reads +system.cpu.icache.replacements 26 # number of replacements +system.cpu.icache.tagsinuse 823.006550 # Cycle average of tags in use +system.cpu.icache.total_refs 186402559 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 924 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 201734.371212 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 826.529270 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403579 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403579 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 185941162 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 185941162 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 185941162 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 185941162 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 185941162 # number of overall hits -system.cpu.icache.overall_hits::total 185941162 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1369 # number of overall misses -system.cpu.icache.overall_misses::total 1369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47914000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47914000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47914000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47914000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47914000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47914000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 185942531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 185942531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 185942531 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 185942531 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 185942531 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 185942531 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 823.006550 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.401859 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.401859 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186402560 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186402560 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186402560 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186402560 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186402560 # number of overall hits +system.cpu.icache.overall_hits::total 186402560 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1373 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1373 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1373 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1373 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1373 # number of overall misses +system.cpu.icache.overall_misses::total 1373 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48027000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48027000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48027000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48027000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48027000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48027000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186403933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186403933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186403933 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186403933 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186403933 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186403933 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34999.269540 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34999.269540 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34999.269540 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34999.269540 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34999.269540 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34999.269540 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34979.606701 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34979.606701 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34979.606701 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34979.606701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34979.606701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34979.606701 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 435 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 435 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 435 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 435 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 435 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 435 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 934 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 934 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 934 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 934 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 934 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 934 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34118000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34118000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34118000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34118000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34118000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34118000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 446 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 446 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 446 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 446 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 446 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 446 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 927 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 927 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 927 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 927 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 927 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 927 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33886000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33886000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33886000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33886000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33886000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33886000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36528.907923 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36528.907923 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36528.907923 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36528.907923 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36528.907923 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36528.907923 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36554.476807 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36554.476807 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36554.476807 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36554.476807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36554.476807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36554.476807 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445452 # number of replacements -system.cpu.dcache.tagsinuse 4093.428018 # Cycle average of tags in use -system.cpu.dcache.total_refs 452712586 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449548 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1007.039484 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 738623000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.428018 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999372 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999372 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264772769 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264772769 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939813 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939813 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452712582 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452712582 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452712582 # number of overall hits -system.cpu.dcache.overall_hits::total 452712582 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 206710 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 206710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 246244 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 246244 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 452954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 452954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 452954 # number of overall misses -system.cpu.dcache.overall_misses::total 452954 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1296370500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1296370500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2046596000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2046596000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 3342966500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 3342966500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 3342966500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 3342966500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264979479 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264979479 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 445317 # number of replacements +system.cpu.dcache.tagsinuse 4093.312668 # Cycle average of tags in use +system.cpu.dcache.total_refs 452320188 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 449413 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1006.468856 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 738501000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.312668 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999344 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999344 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264380337 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264380337 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939848 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939848 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452320185 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452320185 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452320185 # number of overall hits +system.cpu.dcache.overall_hits::total 452320185 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 208370 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 208370 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246209 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246209 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 454579 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 454579 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 454579 # number of overall misses +system.cpu.dcache.overall_misses::total 454579 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1325128000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1325128000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2053821500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2053821500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 3378949500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 3378949500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 3378949500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 3378949500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264588707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264588707 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 453165536 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 453165536 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 453165536 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 453165536 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6271.445503 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 6271.445503 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8311.252254 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8311.252254 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7380.366439 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7380.366439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7380.366439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7380.366439 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 452774764 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452774764 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452774764 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452774764 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000788 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000788 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001004 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001004 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001004 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001004 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6359.495129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 6359.495129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8341.780763 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8341.780763 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7433.140334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7433.140334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7433.140334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7433.140334 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,136 +450,136 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428527 # number of writebacks -system.cpu.dcache.writebacks::total 428527 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3377 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3377 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 23 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 23 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3400 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3400 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3400 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3400 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203333 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203333 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246221 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246221 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449554 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449554 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 449554 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 449554 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 608060000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 608060000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1250112000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1250112000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1858172000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1858172000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1858172000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1858172000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 428431 # number of writebacks +system.cpu.dcache.writebacks::total 428431 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5144 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5144 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 5161 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5161 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5161 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5161 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203226 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203226 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246192 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246192 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 449418 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 449418 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 449418 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 449418 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 609204500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 609204500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1249438500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1249438500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1858643000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1858643000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1858643000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1858643000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000768 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000768 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2990.463919 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2990.463919 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5077.194878 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5077.194878 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4133.367738 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 4133.367738 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4133.367738 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4133.367738 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000993 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000993 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2997.670082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2997.670082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5075.057272 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5075.057272 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4135.666573 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 4135.666573 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4135.666573 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 4135.666573 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2664 # number of replacements -system.cpu.l2cache.tagsinuse 22218.876300 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517817 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24235 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.366495 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22189.826884 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517514 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24220 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.367217 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20808.584757 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 736.081009 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 674.210534 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.635028 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022463 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020575 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.678066 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 9 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 198770 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 198779 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428527 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428527 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224300 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224300 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 423070 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 423079 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 423070 # number of overall hits -system.cpu.l2cache.overall_hits::total 423079 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 921 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 20789.410931 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 729.827386 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 670.588567 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.634442 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.022273 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020465 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.677180 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 198670 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 198682 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 428431 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 428431 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 224269 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 224269 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 422939 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 422951 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 422939 # number of overall hits +system.cpu.l2cache.overall_hits::total 422951 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 912 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 4549 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5470 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21931 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21931 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 921 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26480 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27401 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 921 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26480 # number of overall misses -system.cpu.l2cache.overall_misses::total 27401 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32620000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 157237500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 189857500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 752514000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 752514000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32620000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 909751500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 942371500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32620000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 909751500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 942371500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 930 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 203319 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 204249 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 428527 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 428527 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246231 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246231 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 930 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 449550 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 450480 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 930 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 449550 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 450480 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.990323 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022374 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.026781 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089067 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089067 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990323 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.058903 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060826 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990323 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058903 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060826 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35418.023887 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34565.289075 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34708.866545 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34312.799234 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34312.799234 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35418.023887 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34356.174471 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34391.865260 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35418.023887 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34356.174471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34391.865260 # average overall miss latency +system.cpu.l2cache.ReadReq_misses::total 5461 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21927 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21927 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 912 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26476 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27388 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 912 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26476 # number of overall misses +system.cpu.l2cache.overall_misses::total 27388 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32383500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 156437000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 188820500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 751713500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 751713500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32383500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 908150500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 940534000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32383500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 908150500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 940534000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 924 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 203219 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 204143 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 428431 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 428431 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246196 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246196 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 924 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 449415 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 450339 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 924 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 449415 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 450339 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.987013 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022385 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.026751 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089063 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089063 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.987013 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060816 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.987013 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060816 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35508.223684 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34389.316333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34576.176524 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34282.551193 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34282.551193 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35508.223684 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34300.895150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34341.098291 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35508.223684 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34300.895150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34341.098291 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -588,52 +588,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2548 # number of writebacks -system.cpu.l2cache.writebacks::total 2548 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 921 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 2545 # number of writebacks +system.cpu.l2cache.writebacks::total 2545 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 912 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4549 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5470 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21931 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21931 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 921 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26480 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27401 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 921 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26480 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27401 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29694500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141471000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171165500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 680167500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 680167500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29694500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 821638500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 851333000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29694500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 821638500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 851333000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990323 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022374 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026781 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089067 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089067 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990323 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058903 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060826 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990323 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058903 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060826 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32241.585233 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31099.362497 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31291.681901 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.975651 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.975651 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32241.585233 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31028.644260 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31069.413525 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32241.585233 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31028.644260 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31069.413525 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::total 5461 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21927 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21927 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 912 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 912 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26476 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27388 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29474000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141532500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171006500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 680035500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 680035500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29474000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 821568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 851042000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29474000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 821568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 851042000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.987013 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022385 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026751 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.987013 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060816 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.987013 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060816 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32317.982456 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31112.881952 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31314.136605 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.613353 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.613353 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32317.982456 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31030.669285 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31073.535855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32317.982456 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31030.669285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31073.535855 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini index 6d1d261c9..065406dee 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,7 +106,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index 177dd7f45..128fee1f8 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:24:05 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:07 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index a463fb589..bf8fc96e2 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.963993 # Nu sim_ticks 963992671000 # Number of ticks simulated final_tick 963992671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1263596 # Simulator instruction rate (inst/s) -host_op_rate 2328243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1384161146 # Simulator tick rate (ticks/s) -host_mem_usage 224820 # Number of bytes of host memory used -host_seconds 696.45 # Real time elapsed on the host +host_inst_rate 939514 # Simulator instruction rate (inst/s) +host_op_rate 1731105 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1029157174 # Simulator tick rate (ticks/s) +host_mem_usage 266280 # Number of bytes of host memory used +host_seconds 936.68 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls system.cpu.num_int_insts 1621354436 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 5129483910 # number of times the integer registers were read -system.cpu.num_int_register_writes 2493860878 # number of times the integer registers were written +system.cpu.num_int_register_reads 4204103507 # number of times the integer registers were read +system.cpu.num_int_register_writes 1886895257 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 607228178 # number of memory refs diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 05ff130e5..fe83ea738 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -184,7 +190,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 371c8d53f..02ca976d3 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:30:12 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:43:43 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 12b9ffa30..045a8ad7b 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.801980 # Nu sim_ticks 1801979679000 # Number of ticks simulated final_tick 1801979679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 670221 # Simulator instruction rate (inst/s) -host_op_rate 1234919 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1372375195 # Simulator tick rate (ticks/s) -host_mem_usage 233400 # Number of bytes of host memory used -host_seconds 1313.04 # Real time elapsed on the host +host_inst_rate 528145 # Simulator instruction rate (inst/s) +host_op_rate 973136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1081454463 # Simulator tick rate (ticks/s) +host_mem_usage 274856 # Number of bytes of host memory used +host_seconds 1666.26 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory @@ -46,8 +46,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls system.cpu.num_int_insts 1621354436 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 5129483910 # number of times the integer registers were read -system.cpu.num_int_register_writes 2493860878 # number of times the integer registers were written +system.cpu.num_int_register_reads 4204103507 # number of times the integer registers were read +system.cpu.num_int_register_writes 1886895257 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 607228178 # number of memory refs diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index c43765666..b61f2399d 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,6 +129,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -157,6 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -428,6 +430,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -450,9 +453,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -466,6 +470,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -474,6 +479,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -515,9 +521,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -538,6 +544,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 29d21ef45..70c115e37 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:35:52 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 23:05:45 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -16,6 +18,7 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 +info: Increasing stack size by one page. flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 @@ -23,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 68408131000 because target called exit() +Exiting @ tick 64346039000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 740e607ea..927f8d15a 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,279 +1,279 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068408 # Number of seconds simulated -sim_ticks 68408131000 # Number of ticks simulated -final_tick 68408131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064346 # Number of seconds simulated +sim_ticks 64346039000 # Number of ticks simulated +final_tick 64346039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92617 # Simulator instruction rate (inst/s) -host_op_rate 163083 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40102422 # Simulator tick rate (ticks/s) -host_mem_usage 370556 # Number of bytes of host memory used -host_seconds 1705.84 # Real time elapsed on the host +host_inst_rate 77016 # Simulator instruction rate (inst/s) +host_op_rate 135613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31367260 # Simulator tick rate (ticks/s) +host_mem_usage 410996 # Number of bytes of host memory used +host_seconds 2051.38 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1892736 # Number of bytes read from this memory -system.physmem.bytes_read::total 1961088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1893376 # Number of bytes read from this memory +system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20352 # Number of bytes written to this memory -system.physmem.bytes_written::total 20352 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 20416 # Number of bytes written to this memory +system.physmem.bytes_written::total 20416 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29574 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30642 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 318 # Number of write requests responded to by this memory -system.physmem.num_writes::total 318 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 999179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 27668290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 28667469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 999179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 999179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 297508 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 297508 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 297508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 999179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 27668290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 28964978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 29584 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory +system.physmem.num_writes::total 319 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 29424904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 317284 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 29424904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30804445 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 136816263 # number of cpu cycles simulated +system.cpu.numCycles 128692079 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 36128371 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 36128371 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1086051 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25676514 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25568930 # Number of BTB hits +system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 35576702 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1085312 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25399500 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25270525 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28040484 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 196465722 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36128371 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25568930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59455138 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8440333 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 41957570 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 207 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 27323760 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 153045 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136778320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.524833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.343005 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27884150 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 193525000 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35576702 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25270525 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 58636506 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7358089 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 35916291 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 27160167 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 295674 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 128658357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.644591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.372169 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 80075177 58.54% 58.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2168654 1.59% 60.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2999031 2.19% 62.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4111689 3.01% 65.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8029506 5.87% 71.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5053851 3.69% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2898853 2.12% 77.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1472297 1.08% 78.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29969262 21.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 72765830 56.56% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2056683 1.60% 58.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3006413 2.34% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4027268 3.13% 63.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8003806 6.22% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5026752 3.91% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2893556 2.25% 76.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1437345 1.12% 77.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29440704 22.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136778320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.264065 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.435982 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40775641 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 32574420 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46270758 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9832617 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7324884 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 341365831 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7324884 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 46092133 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6411510 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9224 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 50365166 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 26575403 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 337580749 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5005 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 24325640 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 73870 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 414916926 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1010481124 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1010477953 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3171 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 341010848 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 73906078 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 481 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57495301 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 108229908 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37227556 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 46399442 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8017088 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 331952532 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2380 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 311468511 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188619 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53509766 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 93151802 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1934 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136778320 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.277177 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.722818 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 128658357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.276448 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.503783 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 39452105 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 27727798 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46961382 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8295915 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6221157 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336436945 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 6221157 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44164076 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5970160 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9070 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 50268632 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22025262 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 331751360 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 262 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6842 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20121054 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 216 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 334012838 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 880453680 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 880451759 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1921 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 54800094 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 485 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 480 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 50437110 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104594760 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36334761 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 41480583 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6245732 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 323452648 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1758 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 307818254 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 198387 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 45033296 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65280307 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1312 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 128658357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.392524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.788521 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29621399 21.66% 21.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18208303 13.31% 34.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26183268 19.14% 54.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31189173 22.80% 76.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 17472478 12.77% 89.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8789771 6.43% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3781191 2.76% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1461656 1.07% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 71081 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25721748 19.99% 19.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18649480 14.50% 34.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 23014823 17.89% 52.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 27362657 21.27% 73.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 17010472 13.22% 86.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9600725 7.46% 94.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6243189 4.85% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 895594 0.70% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 159669 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136778320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 128658357 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 22736 1.09% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1942986 92.77% 93.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 128630 6.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35279 1.70% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1868126 90.18% 91.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 168108 8.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 29247 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177262228 56.91% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 143 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99693377 32.01% 88.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34483516 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 29245 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174946374 56.83% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99043059 32.18% 89.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33799538 10.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 311468511 # Type of FU issued -system.cpu.iq.rate 2.276546 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2094352 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006724 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 761997211 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 385495678 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 308386892 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1102 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1693 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 371 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 313533109 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 507 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52559129 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 307818254 # Type of FU issued +system.cpu.iq.rate 2.391897 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2071513 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006730 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 746564211 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 368519272 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 304587112 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 554 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 943 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 186 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 309860246 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 276 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52574701 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17450524 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 94828 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33225 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5787805 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13815376 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 44181 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33341 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4895010 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3313 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3290 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 36659 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7324884 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 821379 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 106718 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 331954912 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 49233 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 108229908 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37227556 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1080 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29147 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33225 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 614391 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 577456 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1191847 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 309549319 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 99164391 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1919192 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6221157 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 782061 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 89817 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 323454406 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 362446 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104594760 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36334761 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 480 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 611 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 22270 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33341 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 595275 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 582931 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1178206 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 305708901 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98426933 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2109353 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 133267604 # number of memory reference insts executed -system.cpu.iew.exec_branches 31551799 # Number of branches executed -system.cpu.iew.exec_stores 34103213 # Number of stores executed -system.cpu.iew.exec_rate 2.262518 # Inst execution rate -system.cpu.iew.wb_sent 308913193 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 308387263 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227149501 # num instructions producing a value -system.cpu.iew.wb_consumers 466434365 # num instructions consuming a value +system.cpu.iew.exec_refs 131805652 # number of memory reference insts executed +system.cpu.iew.exec_branches 31122940 # Number of branches executed +system.cpu.iew.exec_stores 33378719 # Number of stores executed +system.cpu.iew.exec_rate 2.375507 # Inst execution rate +system.cpu.iew.wb_sent 305078305 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 304587298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 225979119 # num instructions producing a value +system.cpu.iew.wb_consumers 311384301 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.254025 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.486991 # average fanout of values written-back +system.cpu.iew.wb_rate 2.366791 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.725724 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 157988547 # The number of committed instructions system.cpu.commit.commitCommittedOps 278192462 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 53766564 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 45269554 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1086077 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 129453436 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.148977 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.662392 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1085338 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122437200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.272124 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.827291 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48953386 37.82% 37.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24330343 18.79% 56.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17047293 13.17% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12542277 9.69% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3298814 2.55% 82.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3552746 2.74% 84.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2756547 2.13% 86.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1133806 0.88% 87.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15838224 12.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 46942462 38.34% 38.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 21185475 17.30% 55.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15973782 13.05% 68.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12948459 10.58% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1961875 1.60% 80.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1887285 1.54% 82.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1388960 1.13% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 594855 0.49% 84.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 19554047 15.97% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 129453436 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122437200 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,69 +284,69 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15838224 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 19554047 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 445574238 # The number of ROB reads -system.cpu.rob.rob_writes 671251501 # The number of ROB writes -system.cpu.timesIdled 1985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 37943 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 426345169 # The number of ROB reads +system.cpu.rob.rob_writes 653150724 # The number of ROB writes +system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33722 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.865988 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.865988 # CPI: Total CPI of All Threads -system.cpu.ipc 1.154750 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.154750 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 705392602 # number of integer regfile reads -system.cpu.int_regfile_writes 373276329 # number of integer regfile writes -system.cpu.fp_regfile_reads 441 # number of floating regfile reads -system.cpu.fp_regfile_writes 230 # number of floating regfile writes -system.cpu.misc_regfile_reads 197984249 # number of misc regfile reads -system.cpu.icache.replacements 87 # number of replacements -system.cpu.icache.tagsinuse 844.199846 # Cycle average of tags in use -system.cpu.icache.total_refs 27322358 # Total number of references to valid blocks. +system.cpu.cpi 0.814566 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.814566 # CPI: Total CPI of All Threads +system.cpu.ipc 1.227648 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.227648 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 598601369 # number of integer regfile reads +system.cpu.int_regfile_writes 305356910 # number of integer regfile writes +system.cpu.fp_regfile_reads 165 # number of floating regfile reads +system.cpu.fp_regfile_writes 88 # number of floating regfile writes +system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads +system.cpu.icache.replacements 92 # number of replacements +system.cpu.icache.tagsinuse 843.498154 # Cycle average of tags in use +system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25392.526022 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 844.199846 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.412207 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.412207 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27322358 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27322358 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27322358 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27322358 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27322358 # number of overall hits -system.cpu.icache.overall_hits::total 27322358 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1402 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1402 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1402 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1402 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1402 # number of overall misses -system.cpu.icache.overall_misses::total 1402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51713500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51713500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51713500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51713500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51713500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51713500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27323760 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27323760 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27323760 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27323760 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27323760 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27323760 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 843.498154 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27158782 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27158782 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27158782 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27158782 # number of overall hits +system.cpu.icache.overall_hits::total 27158782 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses +system.cpu.icache.overall_misses::total 1385 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51448500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51448500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51448500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51448500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51448500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51448500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27160167 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27160167 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27160167 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36885.520685 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36885.520685 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36885.520685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36885.520685 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37146.931408 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37146.931408 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37146.931408 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37146.931408 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,94 +355,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 325 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 325 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 325 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 325 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39505500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39505500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39505500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39505500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39505500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39505500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36681.058496 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36681.058496 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36681.058496 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36681.058496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36681.058496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36681.058496 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 307 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 307 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 307 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 307 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39433000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39433000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39433000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39433000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39433000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39433000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36579.777365 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36579.777365 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072121 # number of replacements -system.cpu.dcache.tagsinuse 4072.371520 # Cycle average of tags in use -system.cpu.dcache.total_refs 75597840 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076217 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36.411339 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 22802887000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.371520 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994231 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994231 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 44240568 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 44240568 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31357263 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31357263 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 75597831 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 75597831 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 75597831 # number of overall hits -system.cpu.dcache.overall_hits::total 75597831 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2315103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2315103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 82488 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 82488 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2397591 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2397591 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2397591 # number of overall misses -system.cpu.dcache.overall_misses::total 2397591 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16770812000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16770812000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571570000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1571570000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18342382000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18342382000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18342382000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18342382000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46555671 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46555671 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2072148 # number of replacements +system.cpu.dcache.tagsinuse 4072.029897 # Cycle average of tags in use +system.cpu.dcache.total_refs 74824983 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076244 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36.038627 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21783897000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.029897 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994148 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994148 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 43467724 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 43467724 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31357249 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31357249 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 74824973 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 74824973 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 74824973 # number of overall hits +system.cpu.dcache.overall_hits::total 74824973 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2321557 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2321557 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 82502 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 82502 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2404059 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2404059 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2404059 # number of overall misses +system.cpu.dcache.overall_misses::total 2404059 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19393584000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19393584000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571938000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1571938000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20965522000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20965522000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20965522000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20965522000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45789281 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45789281 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77995422 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77995422 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77995422 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77995422 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049728 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049728 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 77229032 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77229032 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77229032 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77229032 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050701 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050701 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002624 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.030740 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.030740 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.030740 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.030740 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7244.088924 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7244.088924 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19052.104549 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 19052.104549 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7650.338194 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7650.338194 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.031129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.031129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8353.697109 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8353.697109 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19053.332040 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19053.332040 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8720.884970 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8720.884970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8720.884970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8720.884970 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,138 +451,140 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2065063 # number of writebacks -system.cpu.dcache.writebacks::total 2065063 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 320901 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 320901 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 469 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 321370 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 321370 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 321370 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 321370 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994202 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994202 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82019 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82019 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076221 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076221 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076221 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076221 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6183631000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6183631000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1313937000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1313937000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7497568000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7497568000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7497568000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7497568000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042835 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042835 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026620 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026620 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3100.804733 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3100.804733 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16019.910021 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16019.910021 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2064775 # number of writebacks +system.cpu.dcache.writebacks::total 2064775 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 327358 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 327358 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 453 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 453 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 327811 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 327811 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 327811 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 327811 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994199 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82049 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82049 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076248 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076248 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076248 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076248 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8452133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8452133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1314555500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1314555500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9766689000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9766689000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9766689000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9766689000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043552 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043552 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026884 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026884 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026884 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026884 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4238.360114 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4238.360114 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16021.590757 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16021.590757 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4704.008866 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1458 # number of replacements -system.cpu.l2cache.tagsinuse 20067.979072 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4027415 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30622 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 131.520312 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1466 # number of replacements +system.cpu.l2cache.tagsinuse 19909.538266 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4027133 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30632 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 131.468171 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19572.608886 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 263.032470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 232.337716 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.597309 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.008027 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007090 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.612426 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 19409.012511 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 268.281429 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 232.244325 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.592316 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.008187 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007088 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.607591 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993505 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993513 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2065063 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2065063 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53141 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53141 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993503 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993511 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2064775 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2064775 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 53159 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53159 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2046646 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2046654 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2046662 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2046670 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2046646 # number of overall hits -system.cpu.l2cache.overall_hits::total 2046654 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2046662 # number of overall hits +system.cpu.l2cache.overall_hits::total 2046670 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 1068 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 582 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1650 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 588 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1656 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 28992 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 28992 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29574 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30642 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29584 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30652 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29574 # number of overall misses -system.cpu.l2cache.overall_misses::total 30642 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37986000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20700500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 58686500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 989313000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 989313000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37986000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1010013500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1047999500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37986000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1010013500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1047999500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 29584 # number of overall misses +system.cpu.l2cache.overall_misses::total 30652 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37875000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20966500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 58841500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 988882500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 988882500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37875000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1009849000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1047724000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37875000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1009849000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1047724000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1994087 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1995163 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2065063 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2065063 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82133 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82133 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994091 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995167 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2064775 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2064775 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82155 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82155 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076220 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076246 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077322 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076220 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076246 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077322 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992565 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000292 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000827 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352988 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352988 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000295 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000830 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352943 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352943 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014244 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014751 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014249 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014756 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014244 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014751 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35567.415730 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35567.869416 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35567.575758 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.654801 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.654801 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34201.406566 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34201.406566 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014249 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014756 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35463.483146 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35657.312925 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35532.306763 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34181.260603 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34181.260603 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,60 +593,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 318 # number of writebacks -system.cpu.l2cache.writebacks::total 318 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 319 # number of writebacks +system.cpu.l2cache.writebacks::total 319 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 582 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1650 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 588 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1656 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28992 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28992 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29574 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30642 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29584 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29574 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30642 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34610000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18859500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53469500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34493000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53606000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899045000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899045000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34610000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 917904500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 952514500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34610000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 917904500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 952514500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34493000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 952804000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34493000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 952804000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000827 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352988 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352988 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352943 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352943 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014751 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014751 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32406.367041 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32404.639175 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32405.757576 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32296.816479 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.102041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32370.772947 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.106236 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.106236 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index 2bc190729..21c7d0296 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,9 +106,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index 36c1a507a..809429d83 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:40:35 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:54:55 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 624b796e9..0a05e5832 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950039000 # Number of ticks simulated final_tick 168950039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1227990 # Simulator instruction rate (inst/s) -host_op_rate 2162293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1313189467 # Simulator tick rate (ticks/s) -host_mem_usage 359036 # Number of bytes of host memory used -host_seconds 128.66 # Real time elapsed on the host +host_inst_rate 917389 # Simulator instruction rate (inst/s) +host_op_rate 1615374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 981038557 # Simulator tick rate (ticks/s) +host_mem_usage 400492 # Number of bytes of host memory used +host_seconds 172.22 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls system.cpu.num_int_insts 278186171 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 834011732 # number of times the integer registers were read -system.cpu.num_int_register_writes 341010822 # number of times the integer registers were written +system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read +system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written system.cpu.num_mem_refs 122219135 # number of memory refs diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index fb9534d75..519e44990 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -184,9 +190,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 25187946e..0ff981af8 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:42:54 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 23:03:49 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index be2824a9d..197e85700 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.368209 # Nu sim_ticks 368209206000 # Number of ticks simulated final_tick 368209206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 651126 # Simulator instruction rate (inst/s) -host_op_rate 1146527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1517517563 # Simulator tick rate (ticks/s) -host_mem_usage 367484 # Number of bytes of host memory used -host_seconds 242.64 # Real time elapsed on the host +host_inst_rate 501886 # Simulator instruction rate (inst/s) +host_op_rate 883741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1169699500 # Simulator tick rate (ticks/s) +host_mem_usage 408944 # Number of bytes of host memory used +host_seconds 314.79 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory @@ -46,8 +46,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls system.cpu.num_int_insts 278186171 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 834011732 # number of times the integer registers were read -system.cpu.num_int_register_writes 341010822 # number of times the integer registers were written +system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read +system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written system.cpu.num_mem_refs 122219135 # number of memory refs diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index e88ab98aa..7d5241595 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,6 +129,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -157,6 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -428,6 +430,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -450,9 +453,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -466,6 +470,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -474,6 +479,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -515,9 +521,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -538,6 +544,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 5b84c1efd..31324de53 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,15 +1,30 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:47:07 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:33:09 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: ***********************info: Increasing stack size by one page. -************************** +info: Increasing stack size by one page. + Reading the dictionary files: *********info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +**************************************** 58924 words stored in 3784810 bytes @@ -22,8 +37,6 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's -info: Increasing stack size by one page. -info: Increasing stack size by one page. * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor * how fast the program is it * I am wondering whether to invite to the party @@ -69,4 +82,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 460397003000 because target called exit() +Exiting @ tick 433562236500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 622f1b256..875124d6c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,280 +1,279 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.460397 # Number of seconds simulated -sim_ticks 460397003000 # Number of ticks simulated -final_tick 460397003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.433562 # Number of seconds simulated +sim_ticks 433562236500 # Number of ticks simulated +final_tick 433562236500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79363 # Simulator instruction rate (inst/s) -host_op_rate 146752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44188751 # Simulator tick rate (ticks/s) -host_mem_usage 271496 # Number of bytes of host memory used -host_seconds 10418.87 # Real time elapsed on the host +host_inst_rate 69861 # Simulator instruction rate (inst/s) +host_op_rate 129182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36630948 # Simulator tick rate (ticks/s) +host_mem_usage 312956 # Number of bytes of host memory used +host_seconds 11835.95 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27602816 # Number of bytes read from this memory -system.physmem.bytes_read::total 27823424 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20793216 # Number of bytes written to this memory -system.physmem.bytes_written::total 20793216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431294 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434741 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 324894 # Number of write requests responded to by this memory -system.physmem.num_writes::total 324894 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 479169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 59954378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 60433547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 479169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 479169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45163665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45163665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45163665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 479169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 59954378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 105597212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 223808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27615936 # Number of bytes read from this memory +system.physmem.bytes_read::total 27839744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 223808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 223808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20802240 # Number of bytes written to this memory +system.physmem.bytes_written::total 20802240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431499 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434996 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 325035 # Number of write requests responded to by this memory +system.physmem.num_writes::total 325035 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 516207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 63695437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64211644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 516207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 47979824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 47979824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 47979824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 516207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 63695437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 112191469 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 920794007 # number of cpu cycles simulated +system.cpu.numCycles 867124474 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 225794462 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 225794462 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14310990 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 160522970 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155979425 # Number of BTB hits +system.cpu.BPredUnit.lookups 221451605 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 221451605 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14391219 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 156554468 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 152744780 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 191744262 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1263331162 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225794462 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155979425 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 392171634 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 98591454 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 238962985 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25426 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259827 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 183595750 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3654130 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 907193017 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.581432 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.385361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 187033735 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1232378576 # Number of instructions fetch has processed +system.cpu.fetch.Branches 221451605 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 152744780 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 382759458 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 92090467 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 211510860 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30313 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 293412 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 179381043 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4119516 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 859080204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.662810 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.408007 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 519485485 57.26% 57.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25996327 2.87% 60.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 29110749 3.21% 63.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 30309742 3.34% 66.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 19641750 2.17% 68.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25638200 2.83% 71.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32631023 3.60% 75.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30872435 3.40% 78.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 193507306 21.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 480734760 55.96% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25482181 2.97% 58.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28110276 3.27% 62.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29422032 3.42% 65.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18933642 2.20% 67.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25065200 2.92% 70.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31695568 3.69% 74.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30727505 3.58% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 188909040 21.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 907193017 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.245217 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.372002 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 253820361 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 190155093 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 329181376 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50007304 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 84028883 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2290797520 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 84028883 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 290488558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 45108603 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15221 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 340002879 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 147548873 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2240764057 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2605 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24418127 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 107087338 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11838 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2887342076 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6494384791 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6493512354 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 872437 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993077392 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 894264684 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1272 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1264 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 351172253 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 540287564 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217471494 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 211537272 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 61160620 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2143475674 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 68305 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1846648177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1590040 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 612877032 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1231244444 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 67752 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 907193017 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.035563 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.801610 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 859080204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.255386 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.421225 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 243920658 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 168382016 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 324921479 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 44403625 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 77452426 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2234163398 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 77452426 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 277622568 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38425038 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15999 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 333490253 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 132073920 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2182629484 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 24122 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19618394 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 98320386 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 151 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282631567 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5519360713 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5519123398 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 237315 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 668590716 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1589 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1547 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 322287185 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528399687 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210789135 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 202484637 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58642789 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2088380391 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24636 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1835578469 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 977153 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 553508636 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 915245477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24083 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 859080204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.136679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.890485 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 248716450 27.42% 27.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 159225433 17.55% 44.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 153829003 16.96% 61.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 148683388 16.39% 78.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 98997552 10.91% 89.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 59757299 6.59% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 27989930 3.09% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8953405 0.99% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1040557 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233267501 27.15% 27.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 144027396 16.77% 43.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 136780566 15.92% 59.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 136553598 15.90% 75.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 99295309 11.56% 87.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59689212 6.95% 94.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35426860 4.12% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12177405 1.42% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1862357 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 907193017 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 859080204 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2618041 18.27% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8472648 59.14% 77.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3236053 22.59% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5022876 32.65% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7731976 50.26% 82.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2628669 17.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2706611 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1219512996 66.04% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 447033831 24.21% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177394739 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2701218 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1210723498 65.96% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 444235410 24.20% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177918343 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1846648177 # Type of FU issued -system.cpu.iq.rate 2.005495 # Inst issue rate -system.cpu.iq.fu_busy_cnt 14326742 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007758 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4616398570 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2756384375 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1806263116 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 7583 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 297698 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 240 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1858265657 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2651 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 168095723 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1835578469 # Type of FU issued +system.cpu.iq.rate 2.116857 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15383521 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008381 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4546556112 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2642088218 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1793025560 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 41704 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 79014 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 9750 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1848241436 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 19336 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170057316 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 156185408 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 429800 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 272503 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 68311550 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144297531 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 517217 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 266012 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61629484 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6430 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10771 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 84028883 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6582029 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1299784 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2143543979 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2844739 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 540287564 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217471735 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5098 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 982320 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 66743 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 272503 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10083086 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5258850 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 15341936 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1818766036 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 438618649 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27882141 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 77452426 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5095399 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 776506 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2088405027 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2538461 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528399687 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210789669 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5336 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 420481 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 70453 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 266012 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10035135 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4886780 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 14921915 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1805657318 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 435939313 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29921151 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 610454199 # number of memory reference insts executed -system.cpu.iew.exec_branches 170875981 # Number of branches executed -system.cpu.iew.exec_stores 171835550 # Number of stores executed -system.cpu.iew.exec_rate 1.975215 # Inst execution rate -system.cpu.iew.wb_sent 1813520986 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1806263356 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1378693447 # num instructions producing a value -system.cpu.iew.wb_consumers 2933323666 # num instructions consuming a value +system.cpu.iew.exec_refs 608546299 # number of memory reference insts executed +system.cpu.iew.exec_branches 171183701 # Number of branches executed +system.cpu.iew.exec_stores 172606986 # Number of stores executed +system.cpu.iew.exec_rate 2.082351 # Inst execution rate +system.cpu.iew.wb_sent 1800375599 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1793035310 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1362115146 # num instructions producing a value +system.cpu.iew.wb_consumers 1993206857 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.961637 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.470011 # average fanout of values written-back +system.cpu.iew.wb_rate 2.067795 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.683379 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 826877109 # The number of committed instructions system.cpu.commit.commitCommittedOps 1528988699 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 614579352 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 559448088 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14336742 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823164134 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.857453 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.320209 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14421135 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 781627778 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.956160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.445660 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 305087340 37.06% 37.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 205283379 24.94% 62.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 74494797 9.05% 71.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 96404931 11.71% 82.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29976642 3.64% 86.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28775074 3.50% 89.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15838255 1.92% 91.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11740263 1.43% 93.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 55563453 6.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 285492936 36.53% 36.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 197198069 25.23% 61.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62579121 8.01% 69.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 91937051 11.76% 81.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26882169 3.44% 84.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 29023123 3.71% 88.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9810981 1.26% 89.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10323566 1.32% 91.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68380762 8.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823164134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 781627778 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -285,69 +284,69 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 55563453 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 68380762 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2911168732 # The number of ROB reads -system.cpu.rob.rob_writes 4371280103 # The number of ROB writes -system.cpu.timesIdled 309541 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13600990 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2801683803 # The number of ROB reads +system.cpu.rob.rob_writes 4254544815 # The number of ROB writes +system.cpu.timesIdled 198794 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8044270 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.113580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.113580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898004 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898004 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4004208844 # number of integer regfile reads -system.cpu.int_regfile_writes 2286339718 # number of integer regfile writes -system.cpu.fp_regfile_reads 238 # number of floating regfile reads +system.cpu.cpi 1.048674 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.048674 # CPI: Total CPI of All Threads +system.cpu.ipc 0.953585 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.953585 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3391389205 # number of integer regfile reads +system.cpu.int_regfile_writes 1872893526 # number of integer regfile writes +system.cpu.fp_regfile_reads 9748 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.misc_regfile_reads 1001924846 # number of misc regfile reads -system.cpu.icache.replacements 5564 # number of replacements -system.cpu.icache.tagsinuse 1044.277661 # Cycle average of tags in use -system.cpu.icache.total_refs 183360161 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25519.855393 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 993246616 # number of misc regfile reads +system.cpu.icache.replacements 5750 # number of replacements +system.cpu.icache.tagsinuse 1040.901542 # Cycle average of tags in use +system.cpu.icache.total_refs 179166863 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7354 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24363.185069 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1044.277661 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.509901 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.509901 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 183377049 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 183377049 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 183377049 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 183377049 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 183377049 # number of overall hits -system.cpu.icache.overall_hits::total 183377049 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 218701 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 218701 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 218701 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 218701 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 218701 # number of overall misses -system.cpu.icache.overall_misses::total 218701 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1530978500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1530978500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1530978500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1530978500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1530978500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1530978500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 183595750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 183595750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 183595750 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 183595750 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 183595750 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 183595750 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001191 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001191 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001191 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001191 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001191 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001191 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7000.326930 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 7000.326930 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7000.326930 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 7000.326930 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7000.326930 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 7000.326930 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1040.901542 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.508253 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.508253 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 179183149 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179183149 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179183149 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179183149 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179183149 # number of overall hits +system.cpu.icache.overall_hits::total 179183149 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 197894 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 197894 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 197894 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 197894 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 197894 # number of overall misses +system.cpu.icache.overall_misses::total 197894 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1518962500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1518962500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1518962500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1518962500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1518962500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1518962500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179381043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179381043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179381043 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179381043 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179381043 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179381043 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001103 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001103 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001103 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001103 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001103 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001103 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7675.636957 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 7675.636957 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7675.636957 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 7675.636957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7675.636957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 7675.636957 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -356,94 +355,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1667 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1667 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1667 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1667 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1667 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1667 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 217034 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 217034 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 217034 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 217034 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 217034 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 217034 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 795818000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 795818000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 795818000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 795818000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 795818000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 795818000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001182 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001182 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001182 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3666.789535 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3666.789535 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3666.789535 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3666.789535 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3666.789535 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3666.789535 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1612 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1612 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1612 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1612 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1612 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1612 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 196282 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 196282 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 196282 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 196282 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 196282 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 196282 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 850572000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 850572000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 850572000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 850572000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 850572000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 850572000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001094 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001094 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001094 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4333.418245 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4333.418245 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4333.418245 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4333.418245 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4333.418245 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4333.418245 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2526946 # number of replacements -system.cpu.dcache.tagsinuse 4087.012033 # Cycle average of tags in use -system.cpu.dcache.total_refs 415079459 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531042 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.995484 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2118352000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.012033 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997806 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997806 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 266229970 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 266229970 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148176522 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148176522 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 414406492 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414406492 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414406492 # number of overall hits -system.cpu.dcache.overall_hits::total 414406492 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2652987 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2652987 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 983679 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 983679 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3636666 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3636666 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3636666 # number of overall misses -system.cpu.dcache.overall_misses::total 3636666 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36715559000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36715559000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18841751000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18841751000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55557310000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55557310000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55557310000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55557310000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 268882957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 268882957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2529239 # number of replacements +system.cpu.dcache.tagsinuse 4087.824868 # Cycle average of tags in use +system.cpu.dcache.total_refs 410277951 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533335 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 161.951716 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1779749000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.824868 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998004 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998004 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 261532697 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 261532697 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148197019 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148197019 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 409729716 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 409729716 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 409729716 # number of overall hits +system.cpu.dcache.overall_hits::total 409729716 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2781068 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2781068 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 963182 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 963182 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3744250 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3744250 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3744250 # number of overall misses +system.cpu.dcache.overall_misses::total 3744250 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36062982500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36062982500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18107985000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18107985000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54170967500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54170967500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54170967500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54170967500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264313765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264313765 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418043158 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418043158 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418043158 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418043158 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009867 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009867 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006595 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006595 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008699 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008699 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008699 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008699 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13839.328651 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13839.328651 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19154.369464 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 19154.369464 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15276.989968 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15276.989968 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15276.989968 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15276.989968 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 413473966 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 413473966 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 413473966 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 413473966 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010522 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010522 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006457 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006457 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009056 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009056 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009056 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009056 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12967.314176 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12967.314176 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18800.169646 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18800.169646 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14467.775255 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14467.775255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14467.775255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14467.775255 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -452,144 +451,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2302737 # number of writebacks -system.cpu.dcache.writebacks::total 2302737 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 892793 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 892793 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3022 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3022 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 895815 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 895815 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 895815 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 895815 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1760194 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1760194 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 980657 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 980657 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2740851 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2740851 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2740851 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2740851 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12492277176 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12492277176 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15700711503 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 15700711503 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28192988679 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28192988679 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28192988679 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28192988679 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006546 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006546 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006575 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006575 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7097.102465 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7097.102465 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16010.400683 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16010.400683 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10286.217193 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10286.217193 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10286.217193 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10286.217193 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2304434 # number of writebacks +system.cpu.dcache.writebacks::total 2304434 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1018833 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1018833 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3201 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3201 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1022034 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1022034 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1022034 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1022034 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762235 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762235 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 959981 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 959981 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2722216 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2722216 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2722216 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2722216 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12600404545 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12600404545 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15024414005 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15024414005 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27624818550 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27624818550 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27624818550 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27624818550 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006667 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006667 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006584 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006584 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006584 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006584 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7150.240771 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7150.240771 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15650.741009 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15650.741009 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10147.915724 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10147.915724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10147.915724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10147.915724 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 408579 # number of replacements -system.cpu.l2cache.tagsinuse 29311.103059 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3608561 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 440913 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 8.184293 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 220580493000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21085.621991 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 148.428865 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8077.052203 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.643482 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.004530 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.246492 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.894504 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3663 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1537262 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1540925 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2302737 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2302737 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1268 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1268 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 562455 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 562455 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3663 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2099717 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2103380 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3663 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2099717 # number of overall hits -system.cpu.l2cache.overall_hits::total 2103380 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3447 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 222139 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 225586 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 208539 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 208539 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 209188 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 209188 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3447 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 431327 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 434774 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3447 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 431327 # number of overall misses -system.cpu.l2cache.overall_misses::total 434774 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120849500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7624606932 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 7745456432 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 10570500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 10570500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7166508500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7166508500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 120849500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14791115432 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14911964932 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 120849500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14791115432 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14911964932 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7110 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1759401 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1766511 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2302737 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2302737 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209807 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 209807 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771643 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771643 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7110 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2531044 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2538154 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7110 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2531044 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2538154 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.484810 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126258 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.127701 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993956 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993956 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271094 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.271094 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.484810 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.170415 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.171295 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484810 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.170415 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.171295 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35059.326951 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34323.585377 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34334.827658 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 50.688360 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 50.688360 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.697918 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.697918 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35059.326951 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.115801 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34298.198448 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35059.326951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.115801 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34298.198448 # average overall miss latency +system.cpu.l2cache.replacements 408708 # number of replacements +system.cpu.l2cache.tagsinuse 29318.138904 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3612304 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 441048 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 8.190274 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 211122250000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21095.553590 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 147.717431 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8074.867883 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.643785 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.004508 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.246425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.894719 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3822 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1539081 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1542903 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2304434 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2304434 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1450 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1450 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 562721 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 562721 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3822 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2101802 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2105624 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3822 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2101802 # number of overall hits +system.cpu.l2cache.overall_hits::total 2105624 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 222258 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 225755 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 187429 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 187429 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 209277 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 209277 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3497 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 431535 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 435032 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3497 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 431535 # number of overall misses +system.cpu.l2cache.overall_misses::total 435032 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 122603000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7630191458 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 7752794458 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 10556000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 10556000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7168357500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7168357500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 122603000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14798548958 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14921151958 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 122603000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14798548958 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14921151958 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7319 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1761339 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1768658 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2304434 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2304434 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 188879 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 188879 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771998 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771998 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7319 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2533337 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2540656 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7319 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2533337 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2540656 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.477798 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126187 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.127642 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992323 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992323 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271085 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.271085 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.477798 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.170343 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.171228 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.477798 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.170343 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.171228 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35059.479554 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34330.334377 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34341.629014 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 56.319993 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 56.319993 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34252.963775 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34252.963775 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35059.479554 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.812768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34298.975611 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35059.479554 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.812768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34298.975611 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -598,60 +597,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 324894 # number of writebacks -system.cpu.l2cache.writebacks::total 324894 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3447 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222139 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 225586 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208539 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 208539 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209188 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 209188 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3447 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 431327 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 434774 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3447 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 431327 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 434774 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109944000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6934594999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7044538999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6467053500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6467053500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6486625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6486625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109944000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13421220499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13531164499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109944000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13421220499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13531164499 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.484810 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126258 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993956 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993956 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271094 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271094 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.484810 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170415 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.171295 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.484810 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170415 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.171295 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31895.561358 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31217.368400 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31227.731326 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31011.242501 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31011.242501 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.592749 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.592749 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31895.561358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.114917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.294569 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31895.561358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.114917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.294569 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 325035 # number of writebacks +system.cpu.l2cache.writebacks::total 325035 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3497 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222257 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 225754 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 187429 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 187429 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209277 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 209277 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3497 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 431534 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 435031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3497 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 431534 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 435031 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111510500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6940045999 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7051556499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5812216000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5812216000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6490373500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6490373500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111510500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13430419499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13541929999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111510500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13430419499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13541929999 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.477798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126186 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127641 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992323 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992323 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271085 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271085 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.477798 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170342 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171228 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.477798 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170342 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171228 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31887.474979 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31225.320233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31235.577217 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31010.227873 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31010.227873 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.314889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.314889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31887.474979 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31122.505988 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31128.655197 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31887.474979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31122.505988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31128.655197 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 631aee4c4..dd8a28481 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,9 +106,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 2e1cac91e..8d28e1b89 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:52:16 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:08 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 84b45e732..370f14990 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229327000 # Number of ticks simulated final_tick 885229327000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1279506 # Simulator instruction rate (inst/s) -host_op_rate 2365950 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1369799774 # Simulator tick rate (ticks/s) -host_mem_usage 228100 # Number of bytes of host memory used -host_seconds 646.25 # Real time elapsed on the host +host_inst_rate 957113 # Simulator instruction rate (inst/s) +host_op_rate 1769809 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1024655834 # Simulator tick rate (ticks/s) +host_mem_usage 269560 # Number of bytes of host memory used +host_seconds 863.93 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317558 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read -system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written +system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read +system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 533262341 # number of memory refs diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 5307ccc0b..1740f8aee 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -184,9 +190,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index d712433e8..66dfa99a7 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 19:03:12 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:27 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 9139f6ef0..20a253054 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.652607 # Nu sim_ticks 1652606827000 # Number of ticks simulated final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 715148 # Simulator instruction rate (inst/s) -host_op_rate 1322389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1429304042 # Simulator tick rate (ticks/s) -host_mem_usage 236556 # Number of bytes of host memory used -host_seconds 1156.23 # Real time elapsed on the host +host_inst_rate 548890 # Simulator instruction rate (inst/s) +host_op_rate 1014960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1097019218 # Simulator tick rate (ticks/s) +host_mem_usage 278012 # Number of bytes of host memory used +host_seconds 1506.45 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory @@ -46,8 +46,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317558 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read -system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written +system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read +system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 533262341 # number of memory refs diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index d332c41fc..66b4a9e4a 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,7 +106,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 3c6a6098c..7e9cf379d 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 19:04:29 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:07 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index f428cd228..292417104 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007226500 # Number of ticks simulated final_tick 2846007226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1386030 # Simulator instruction rate (inst/s) -host_op_rate 2159560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1311351119 # Simulator tick rate (ticks/s) -host_mem_usage 224788 # Number of bytes of host memory used -host_seconds 2170.29 # Real time elapsed on the host +host_inst_rate 1027178 # Simulator instruction rate (inst/s) +host_op_rate 1600436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 971834142 # Simulator tick rate (ticks/s) +host_mem_usage 265228 # Number of bytes of host memory used +host_seconds 2928.49 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862594 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls system.cpu.num_int_insts 4686862523 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read -system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written +system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read +system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1677713082 # number of memory refs diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 4471a2bb3..bb8d06fce 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -179,12 +185,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 93d28d354..9df33af9d 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 19:22:39 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:08 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index b95834217..a47f0fd8f 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.901049 # Nu sim_ticks 5901048883000 # Number of ticks simulated final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 766833 # Simulator instruction rate (inst/s) -host_op_rate 1194795 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1504320663 # Simulator tick rate (ticks/s) -host_mem_usage 233368 # Number of bytes of host memory used -host_seconds 3922.73 # Real time elapsed on the host +host_inst_rate 582820 # Simulator instruction rate (inst/s) +host_op_rate 908086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1143336514 # Simulator tick rate (ticks/s) +host_mem_usage 274832 # Number of bytes of host memory used +host_seconds 5161.25 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862594 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory @@ -46,8 +46,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls system.cpu.num_int_insts 4686862523 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read -system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written +system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read +system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1677713082 # number of memory refs diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 1bbc05455..c4bf026a2 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,6 +129,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -157,6 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -428,6 +430,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -450,9 +453,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -466,6 +470,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -474,6 +479,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -515,7 +521,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -538,6 +544,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 4fc266b67..37b3dd11b 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 19:40:50 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:07 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 @@ -24,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 87745680500 because target called exit() +122 123 124 Exiting @ tick 84416735500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index a2fae1867..2682ff067 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,272 +1,271 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.087746 # Number of seconds simulated -sim_ticks 87745680500 # Number of ticks simulated -final_tick 87745680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084417 # Number of seconds simulated +sim_ticks 84416735500 # Number of ticks simulated +final_tick 84416735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74091 # Simulator instruction rate (inst/s) -host_op_rate 124183 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49224615 # Simulator tick rate (ticks/s) -host_mem_usage 243944 # Number of bytes of host memory used -host_seconds 1782.56 # Real time elapsed on the host +host_inst_rate 63787 # Simulator instruction rate (inst/s) +host_op_rate 106913 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40771301 # Simulator tick rate (ticks/s) +host_mem_usage 285396 # Number of bytes of host memory used +host_seconds 2070.49 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362960 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125632 # Number of bytes read from this memory -system.physmem.bytes_read::total 345536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219904 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3436 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1963 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5399 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2506152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1431774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3937926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2506152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2506152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2506152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1431774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3937926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 219392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124672 # Number of bytes read from this memory +system.physmem.bytes_read::total 344064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219392 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3428 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1948 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5376 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2598916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1476864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4075779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2598916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2598916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2598916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1476864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4075779 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 175491362 # number of cpu cycles simulated +system.cpu.numCycles 168833472 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20912942 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20912942 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2216763 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15581100 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13825679 # Number of BTB hits +system.cpu.BPredUnit.lookups 20699953 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20699953 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2254791 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15116204 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13734495 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27332947 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227227686 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20912942 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13825679 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59890374 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19506044 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 71169937 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25808663 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 466739 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 175411287 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.139847 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.302571 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27236198 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227395589 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20699953 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13734495 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59717541 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19334489 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 64998537 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 379 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2980 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25696290 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 472102 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 168753880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.217952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336457 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 117195884 66.81% 66.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3196193 1.82% 68.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2495974 1.42% 70.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3146701 1.79% 71.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3544894 2.02% 73.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3750522 2.14% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4536949 2.59% 78.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2782229 1.59% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34761941 19.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 110699150 65.60% 65.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3224321 1.91% 67.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2475319 1.47% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3099058 1.84% 70.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3522120 2.09% 72.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3727832 2.21% 75.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4580737 2.71% 77.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2798912 1.66% 79.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34626431 20.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 175411287 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119168 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.294808 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40672745 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60972096 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46577224 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10177659 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17011563 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 366355504 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17011563 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48566329 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16269709 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22974 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48161797 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45378915 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 357087422 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 17 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20597536 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22542401 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2240 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 506970122 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1130784117 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1120479639 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10304478 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 320143897 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 186826225 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1722 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1714 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 95149637 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89685413 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 33120690 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58937447 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19448557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344768238 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7633 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 271173389 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 254823 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122910358 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 296566546 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6387 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 175411287 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.545929 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.469162 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 168753880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122606 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40114666 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55275027 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46754888 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9811054 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16798245 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365144878 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16798245 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47659212 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14495562 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23044 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48366883 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41410934 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355937871 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17144692 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22141197 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 410198872 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 987348929 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 977397781 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9951148 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 150770269 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1731 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1722 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89681152 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89661303 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32849139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58579836 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19046101 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343008159 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4651 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 272074168 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 315487 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 121115880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 246174480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3405 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 168753880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.612254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.516605 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 49124172 28.01% 28.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 52503398 29.93% 57.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34371281 19.59% 77.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18965832 10.81% 88.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12724485 7.25% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4970567 2.83% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2095715 1.19% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 541828 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 114009 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47246333 28.00% 28.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46593223 27.61% 55.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33100078 19.61% 75.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20197900 11.97% 87.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13442909 7.97% 95.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5008835 2.97% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2434360 1.44% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 576818 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 153424 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 175411287 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 168753880 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 95040 3.65% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2235381 85.95% 89.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 270412 10.40% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133668 5.05% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2245630 84.89% 89.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 265941 10.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212866 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 176481640 65.08% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1593197 0.59% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68356368 25.21% 91.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23529318 8.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212775 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177115116 65.10% 65.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1587982 0.58% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68640688 25.23% 91.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23517607 8.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 271173389 # Type of FU issued -system.cpu.iq.rate 1.545224 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2600833 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009591 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 715305678 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 463103362 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 263539409 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5308043 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4883539 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2551351 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 269902017 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2659339 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18957330 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 272074168 # Type of FU issued +system.cpu.iq.rate 1.611494 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2645239 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009722 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 710552167 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 459825601 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 264280356 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5310775 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4610743 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2547999 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 270845077 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2661555 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19085225 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33035827 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30313 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 305871 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12604974 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33011717 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33669 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 313308 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12333423 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 47688 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 49764 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17011563 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 523331 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 253149 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 344775871 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 305918 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89685413 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 33120690 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1684 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 166880 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 32620 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 305871 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1304049 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1033069 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2337118 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 268044549 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67281784 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3128840 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16798245 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 578433 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 255971 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343012810 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 262853 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89661303 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32849139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1696 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 171518 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 28262 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 313308 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1334034 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1025575 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2359609 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 268880206 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67501088 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3193962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90419534 # number of memory reference insts executed -system.cpu.iew.exec_branches 14798772 # Number of branches executed -system.cpu.iew.exec_stores 23137750 # Number of stores executed -system.cpu.iew.exec_rate 1.527395 # Inst execution rate -system.cpu.iew.wb_sent 266978184 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266090760 # cumulative count of insts written-back -system.cpu.iew.wb_producers 214617061 # num instructions producing a value -system.cpu.iew.wb_consumers 504567875 # num instructions consuming a value +system.cpu.iew.exec_refs 90609613 # number of memory reference insts executed +system.cpu.iew.exec_branches 14778913 # Number of branches executed +system.cpu.iew.exec_stores 23108525 # Number of stores executed +system.cpu.iew.exec_rate 1.592576 # Inst execution rate +system.cpu.iew.wb_sent 267790153 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 266828355 # cumulative count of insts written-back +system.cpu.iew.wb_producers 215466239 # num instructions producing a value +system.cpu.iew.wb_consumers 378707057 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.516261 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.425348 # average fanout of values written-back +system.cpu.iew.wb_rate 1.580423 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.568952 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 132071192 # The number of committed instructions system.cpu.commit.commitCommittedOps 221362960 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 123521765 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 121732782 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2217341 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158399724 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.397496 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.795426 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2255092 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151955635 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.456760 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.933041 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 54208957 34.22% 34.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 60399478 38.13% 72.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15563923 9.83% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12697970 8.02% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4547982 2.87% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2968547 1.87% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2080222 1.31% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1235429 0.78% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4697216 2.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52584491 34.61% 34.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57288776 37.70% 72.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13942421 9.18% 81.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11933178 7.85% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4288993 2.82% 92.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2988620 1.97% 94.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1076250 0.71% 94.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 990012 0.65% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6862894 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158399724 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 151955635 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -277,70 +276,70 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4697216 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6862894 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 498587233 # The number of ROB reads -system.cpu.rob.rob_writes 706819353 # The number of ROB writes -system.cpu.timesIdled 1778 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80075 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 488188483 # The number of ROB reads +system.cpu.rob.rob_writes 703031879 # The number of ROB writes +system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79592 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.328763 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.328763 # CPI: Total CPI of All Threads -system.cpu.ipc 0.752579 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.752579 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 657890956 # number of integer regfile reads -system.cpu.int_regfile_writes 365630254 # number of integer regfile writes -system.cpu.fp_regfile_reads 3509539 # number of floating regfile reads -system.cpu.fp_regfile_writes 2224150 # number of floating regfile writes -system.cpu.misc_regfile_reads 139559443 # number of misc regfile reads +system.cpu.cpi 1.278352 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.278352 # CPI: Total CPI of All Threads +system.cpu.ipc 0.782257 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.782257 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 568126600 # number of integer regfile reads +system.cpu.int_regfile_writes 302940757 # number of integer regfile writes +system.cpu.fp_regfile_reads 3504532 # number of floating regfile reads +system.cpu.fp_regfile_writes 2218521 # number of floating regfile writes +system.cpu.misc_regfile_reads 139578385 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5776 # number of replacements -system.cpu.icache.tagsinuse 1633.892050 # Cycle average of tags in use -system.cpu.icache.total_refs 25799407 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7743 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3331.965259 # Average number of references to valid blocks. +system.cpu.icache.replacements 5271 # number of replacements +system.cpu.icache.tagsinuse 1637.773069 # Cycle average of tags in use +system.cpu.icache.total_refs 25687510 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7238 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3548.979000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1633.892050 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.797799 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.797799 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25799407 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25799407 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25799407 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25799407 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25799407 # number of overall hits -system.cpu.icache.overall_hits::total 25799407 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9256 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9256 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9256 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9256 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9256 # number of overall misses -system.cpu.icache.overall_misses::total 9256 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 196263500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 196263500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 196263500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 196263500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 196263500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 196263500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25808663 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25808663 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25808663 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25808663 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25808663 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25808663 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000359 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000359 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000359 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21203.921780 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21203.921780 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21203.921780 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21203.921780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21203.921780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21203.921780 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1637.773069 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.799694 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.799694 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25687510 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25687510 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25687510 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25687510 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25687510 # number of overall hits +system.cpu.icache.overall_hits::total 25687510 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8780 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8780 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8780 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8780 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8780 # number of overall misses +system.cpu.icache.overall_misses::total 8780 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 192794500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 192794500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 192794500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 192794500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 192794500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 192794500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25696290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25696290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25696290 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25696290 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25696290 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25696290 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000342 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000342 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000342 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000342 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000342 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000342 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21958.371298 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21958.371298 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21958.371298 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21958.371298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21958.371298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21958.371298 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,94 +348,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1390 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1390 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1390 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1390 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1390 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1390 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7866 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7866 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7866 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7866 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7866 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7866 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 137281500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 137281500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 137281500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 137281500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 137281500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 137281500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000305 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000305 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000305 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000305 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000305 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000305 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17452.517162 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17452.517162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17452.517162 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17452.517162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17452.517162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17452.517162 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1357 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1357 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1357 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1357 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1357 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1357 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7423 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7423 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7423 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7423 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7423 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7423 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 135764500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 135764500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 135764500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 135764500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 135764500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 135764500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000289 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000289 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000289 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18289.707665 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18289.707665 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18289.707665 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18289.707665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18289.707665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18289.707665 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1432.539933 # Cycle average of tags in use -system.cpu.dcache.total_refs 68667989 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2001 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34316.836082 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1420.532831 # Cycle average of tags in use +system.cpu.dcache.total_refs 68760800 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1983 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34675.138679 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1432.539933 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.349741 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.349741 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48153803 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48153803 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514043 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514043 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68667846 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68667846 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68667846 # number of overall hits -system.cpu.dcache.overall_hits::total 68667846 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 738 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 738 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1687 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1687 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2425 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2425 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2425 # number of overall misses -system.cpu.dcache.overall_misses::total 2425 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26760000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26760000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64476000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64476000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91236000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91236000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91236000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91236000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48154541 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48154541 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1420.532831 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.346810 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.346810 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48246578 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48246578 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513979 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513979 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68760557 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68760557 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68760557 # number of overall hits +system.cpu.dcache.overall_hits::total 68760557 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 811 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 811 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1751 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1751 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2562 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2562 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2562 # number of overall misses +system.cpu.dcache.overall_misses::total 2562 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28099500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28099500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66966000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66966000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95065500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95065500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95065500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95065500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48247389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48247389 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 68670271 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68670271 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68670271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68670271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36260.162602 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36260.162602 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38219.324244 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38219.324244 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37623.092784 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37623.092784 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37623.092784 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37623.092784 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 68763119 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68763119 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68763119 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68763119 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34647.965475 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34647.965475 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38244.431753 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38244.431753 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37105.971897 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37105.971897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37105.971897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37105.971897 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,138 +444,140 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 295 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 4 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 299 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 299 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 299 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 299 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 443 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 443 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1683 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1683 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2126 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2126 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2126 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2126 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15550500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15550500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74872500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 74872500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74872500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 74872500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 14 # number of writebacks +system.cpu.dcache.writebacks::total 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 389 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 389 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 422 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2170 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2170 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2170 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2170 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14825500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14825500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61621000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61621000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 76446500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 76446500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 76446500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 76446500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35102.708804 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35102.708804 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35247.771836 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35247.771836 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35217.544685 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35217.544685 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35217.544685 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35217.544685 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35131.516588 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35131.516588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35252.288330 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35252.288330 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35228.801843 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35228.801843 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35228.801843 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35228.801843 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2579.346605 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4342 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3848 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.128378 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2557.455601 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3843 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3822 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.005495 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.813756 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2277.631269 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 299.901579 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000055 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069508 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.009152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.078715 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 4307 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 4339 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4307 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 40 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 4347 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4307 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 40 # number of overall hits -system.cpu.l2cache.overall_hits::total 4347 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3436 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 410 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3846 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 123 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 123 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1553 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1553 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3436 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5399 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3436 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1963 # number of overall misses -system.cpu.l2cache.overall_misses::total 5399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120547500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14888000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 135435500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53463500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 53463500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 120547500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 68351500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 188899000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 120547500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 68351500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 188899000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7743 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 442 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 8185 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 123 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 123 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1561 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1561 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7743 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2003 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9746 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7743 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2003 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9746 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.443756 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.927602 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.469884 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994875 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994875 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.443756 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980030 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.553971 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.443756 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980030 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.553971 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35083.672875 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36312.195122 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35214.638586 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34425.949775 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34425.949775 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35083.672875 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34819.918492 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34987.775514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35083.672875 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34819.918492 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34987.775514 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 1.544201 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2269.052334 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 286.859067 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000047 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.069246 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.008754 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.078047 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3810 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3840 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3810 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 37 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3847 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3810 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 37 # number of overall hits +system.cpu.l2cache.overall_hits::total 3847 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3428 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 391 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3819 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 184 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 184 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1557 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1557 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3428 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1948 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5376 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3428 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1948 # number of overall misses +system.cpu.l2cache.overall_misses::total 5376 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120468000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14185500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 134653500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53721000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 53721000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 120468000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 67906500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 188374500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 120468000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 67906500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 188374500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 421 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7659 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 185 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 185 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1564 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1564 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7238 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1985 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9223 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7238 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1985 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9223 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.473611 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.928741 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.498629 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994595 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.994595 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995524 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.995524 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.473611 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.981360 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.582891 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.473611 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.981360 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.582891 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35142.357060 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36280.051151 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35258.837392 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34502.890173 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34502.890173 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35142.357060 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34859.599589 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 35039.899554 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35142.357060 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34859.599589 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 35039.899554 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,58 +586,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3436 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 410 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3846 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 123 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 123 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1553 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1553 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3436 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5399 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3436 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5399 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109561500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13591500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123153000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3813000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3813000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48619000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48619000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109561500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 62210500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 171772000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109561500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 62210500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 171772000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.443756 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927602 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.469884 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994875 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994875 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.443756 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980030 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.553971 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.443756 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980030 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.553971 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31886.350407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33150 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32021.060842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3428 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 391 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3819 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 184 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 184 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1557 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1557 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3428 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1948 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5376 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3428 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1948 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5376 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109517000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12953500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 122470500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5704000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5704000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48730500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48730500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109517000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61684000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 171201000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109517000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61684000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 171201000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.928741 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.498629 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994595 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994595 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981360 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.582891 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981360 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.582891 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31947.782964 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33129.156010 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32068.735271 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31306.503542 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31306.503542 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31886.350407 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31691.543556 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31815.521393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31886.350407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31691.543556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31815.521393 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31297.687861 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31297.687861 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31947.782964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31665.297741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31845.424107 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31947.782964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31665.297741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31845.424107 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index a704c3927..0981b56ea 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,7 +106,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index 7016aa168..bf4b86929 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 20:10:43 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:08 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 3993acb05..5240c75ca 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393067000 # Number of ticks simulated final_tick 131393067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1300121 # Simulator instruction rate (inst/s) -host_op_rate 2179118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1293445391 # Simulator tick rate (ticks/s) -host_mem_usage 231396 # Number of bytes of host memory used -host_seconds 101.58 # Real time elapsed on the host +host_inst_rate 917611 # Simulator instruction rate (inst/s) +host_op_rate 1537997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 912899116 # Simulator tick rate (ticks/s) +host_mem_usage 272856 # Number of bytes of host memory used +host_seconds 143.93 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls system.cpu.num_int_insts 220339550 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 705008645 # number of times the integer registers were read -system.cpu.num_int_register_writes 318312494 # number of times the integer registers were written +system.cpu.num_int_register_reads 616958548 # number of times the integer registers were read +system.cpu.num_int_register_writes 257597200 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written system.cpu.num_mem_refs 77165302 # number of memory refs diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 6a05638c8..15a571204 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -184,7 +190,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index 54930ae6e..623b8af30 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 20:12:35 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:57:57 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index b04007fc9..2dc96ffd3 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250981 # Nu sim_ticks 250980994000 # Number of ticks simulated final_tick 250980994000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 746540 # Simulator instruction rate (inst/s) -host_op_rate 1251266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1418683559 # Simulator tick rate (ticks/s) -host_mem_usage 239848 # Number of bytes of host memory used -host_seconds 176.91 # Real time elapsed on the host +host_inst_rate 540200 # Simulator instruction rate (inst/s) +host_op_rate 905422 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1026566177 # Simulator tick rate (ticks/s) +host_mem_usage 281300 # Number of bytes of host memory used +host_seconds 244.49 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -39,8 +39,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls system.cpu.num_int_insts 220339550 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 705008645 # number of times the integer registers were read -system.cpu.num_int_register_writes 318312494 # number of times the integer registers were written +system.cpu.num_int_register_reads 616958548 # number of times the integer registers were read +system.cpu.num_int_register_writes 257597200 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written system.cpu.num_mem_refs 77165302 # number of memory refs diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 725aa519b..497b35da8 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -11,11 +11,12 @@ type=LinuxX86System children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus acpi_description_table_pointer=system.acpi_description_table_pointer boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 +clock=1 e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic memories=system.physmem @@ -51,23 +52,21 @@ oem_table_id= [system.apicbridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 -write_ack=false master=system.membus.slave[0] slave=system.iobus.master[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[1] @@ -92,7 +91,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -109,6 +107,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -137,6 +136,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -145,6 +145,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -170,6 +171,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -192,9 +194,10 @@ mem_side=system.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[4] int_slave=system.membus.master[3] @@ -208,6 +211,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -216,6 +220,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -618,6 +623,7 @@ type=BaseCache addr_ranges=0:134217727 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 is_top_level=true @@ -643,6 +649,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -677,9 +684,10 @@ slave=system.apicbridge.master system.system_port system.iocache.mem_side system [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -699,9 +707,10 @@ system=system [system.pc.behind_pci] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854779128 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -716,8 +725,9 @@ pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 children=terminal +clock=1 pio_addr=9223372036854776824 -pio_latency=1000 +pio_latency=100000 platform=system.pc system=system terminal=system.pc.com_1.terminal @@ -739,9 +749,10 @@ port=3456 [system.pc.fake_com_2] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776568 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -755,9 +766,10 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776808 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -771,9 +783,10 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776552 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -787,9 +800,10 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776818 -pio_latency=1000 +pio_latency=100000 pio_size=2 ret_bad_addr=false ret_data16=65535 @@ -803,9 +817,10 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854775936 -pio_latency=1000 +pio_latency=100000 pio_size=1 ret_bad_addr=false ret_data16=65535 @@ -820,7 +835,8 @@ pio=system.iobus.master[11] [system.pc.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1 +pio_latency=30000 platform=system.pc size=16777216 system=system @@ -835,7 +851,6 @@ io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 pic2=system.pc.south_bridge.pic2 -pio_latency=1000 pit=system.pc.south_bridge.pit platform=system.pc speaker=system.pc.south_bridge.speaker @@ -843,9 +858,10 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos children=int_pin +clock=1 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 -pio_latency=1000 +pio_latency=100000 system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.master[1] @@ -855,8 +871,9 @@ type=X86IntSourcePin [system.pc.south_bridge.dma1] type=I8237 +clock=1 pio_addr=9223372036854775808 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] @@ -901,16 +918,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=4 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.pc system=system config=system.iobus.master[4] @@ -934,7 +950,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -954,7 +970,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1037,10 +1053,11 @@ number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 +clock=1 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.iobus.slave[2] pio=system.iobus.master[10] @@ -1048,12 +1065,13 @@ pio=system.iobus.master[10] [system.pc.south_bridge.keyboard] type=I8042 children=keyboard_int_pin mouse_int_pin +clock=1 command_port=9223372036854775908 data_port=9223372036854775904 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[5] @@ -1066,10 +1084,11 @@ type=X86IntSourcePin [system.pc.south_bridge.pic1] type=I8259 children=output +clock=1 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 -pio_latency=1000 +pio_latency=100000 slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.master[6] @@ -1080,10 +1099,11 @@ type=X86IntSourcePin [system.pc.south_bridge.pic2] type=I8259 children=output +clock=1 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 -pio_latency=1000 +pio_latency=100000 slave=Null system=system pio=system.iobus.master[7] @@ -1094,9 +1114,10 @@ type=X86IntSourcePin [system.pc.south_bridge.pit] type=I8254 children=int_pin +clock=1 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[8] @@ -1105,14 +1126,16 @@ type=X86IntSourcePin [system.pc.south_bridge.speaker] type=PcSpeaker +clock=1 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 7a86428b1..c9e113bf6 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:30:36 -gem5 started Jul 26 2012 22:49:04 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 21:50:34 +gem5 started Sep 10 2012 21:50:39 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112043255000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 4f10e01e9..58cc29985 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112043 # Nu sim_ticks 5112043255000 # Number of ticks simulated final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1419112 # Simulator instruction rate (inst/s) -host_op_rate 2905734 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36306590178 # Simulator tick rate (ticks/s) -host_mem_usage 362152 # Number of bytes of host memory used -host_seconds 140.80 # Real time elapsed on the host +host_inst_rate 1011485 # Simulator instruction rate (inst/s) +host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25877843451 # Simulator tick rate (ticks/s) +host_mem_usage 397304 # Number of bytes of host memory used +host_seconds 197.55 # Real time elapsed on the host sim_insts 199813914 # Number of instructions simulated sim_ops 409133298 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory @@ -221,8 +221,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls system.cpu.num_int_insts 374297264 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 1159028989 # number of times the integer registers were read -system.cpu.num_int_register_writes 636431681 # number of times the integer registers were written +system.cpu.num_int_register_reads 915470380 # number of times the integer registers were read +system.cpu.num_int_register_writes 480331069 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 35626517 # number of memory refs diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index ae091f3af..4abbfe44c 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -11,11 +11,12 @@ type=LinuxX86System children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus acpi_description_table_pointer=system.acpi_description_table_pointer boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 +clock=1 e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -51,23 +52,21 @@ oem_table_id= [system.apicbridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 -write_ack=false master=system.membus.slave[0] slave=system.iobus.master[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[1] @@ -91,7 +90,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -105,6 +103,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -133,6 +132,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -141,6 +141,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -166,6 +167,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -188,9 +190,10 @@ mem_side=system.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[4] int_slave=system.membus.master[3] @@ -204,6 +207,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -212,6 +216,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -614,6 +619,7 @@ type=BaseCache addr_ranges=0:134217727 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 is_top_level=false @@ -639,6 +645,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -673,9 +680,10 @@ slave=system.apicbridge.master system.system_port system.iocache.mem_side system [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -695,9 +703,10 @@ system=system [system.pc.behind_pci] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854779128 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -712,8 +721,9 @@ pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 children=terminal +clock=1 pio_addr=9223372036854776824 -pio_latency=1000 +pio_latency=100000 platform=system.pc system=system terminal=system.pc.com_1.terminal @@ -735,9 +745,10 @@ port=3456 [system.pc.fake_com_2] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776568 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -751,9 +762,10 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776808 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -767,9 +779,10 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776552 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -783,9 +796,10 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776818 -pio_latency=1000 +pio_latency=100000 pio_size=2 ret_bad_addr=false ret_data16=65535 @@ -799,9 +813,10 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854775936 -pio_latency=1000 +pio_latency=100000 pio_size=1 ret_bad_addr=false ret_data16=65535 @@ -816,7 +831,8 @@ pio=system.iobus.master[11] [system.pc.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1 +pio_latency=30000 platform=system.pc size=16777216 system=system @@ -831,7 +847,6 @@ io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 pic2=system.pc.south_bridge.pic2 -pio_latency=1000 pit=system.pc.south_bridge.pit platform=system.pc speaker=system.pc.south_bridge.speaker @@ -839,9 +854,10 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos children=int_pin +clock=1 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 -pio_latency=1000 +pio_latency=100000 system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.master[1] @@ -851,8 +867,9 @@ type=X86IntSourcePin [system.pc.south_bridge.dma1] type=I8237 +clock=1 pio_addr=9223372036854775808 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] @@ -897,16 +914,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=4 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.pc system=system config=system.iobus.master[4] @@ -930,7 +946,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -950,7 +966,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1033,10 +1049,11 @@ number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 +clock=1 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.iobus.slave[2] pio=system.iobus.master[10] @@ -1044,12 +1061,13 @@ pio=system.iobus.master[10] [system.pc.south_bridge.keyboard] type=I8042 children=keyboard_int_pin mouse_int_pin +clock=1 command_port=9223372036854775908 data_port=9223372036854775904 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[5] @@ -1062,10 +1080,11 @@ type=X86IntSourcePin [system.pc.south_bridge.pic1] type=I8259 children=output +clock=1 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 -pio_latency=1000 +pio_latency=100000 slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.master[6] @@ -1076,10 +1095,11 @@ type=X86IntSourcePin [system.pc.south_bridge.pic2] type=I8259 children=output +clock=1 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 -pio_latency=1000 +pio_latency=100000 slave=Null system=system pio=system.iobus.master[7] @@ -1090,9 +1110,10 @@ type=X86IntSourcePin [system.pc.south_bridge.pit] type=I8254 children=int_pin +clock=1 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[8] @@ -1101,14 +1122,16 @@ type=X86IntSourcePin [system.pc.south_bridge.speaker] type=PcSpeaker +clock=1 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 4564af214..954f254a4 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simout +Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:30:36 -gem5 started Jul 26 2012 22:51:36 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 21:50:34 +gem5 started Sep 10 2012 21:50:39 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5191766314000 because m5_exit instruction encountered +Exiting @ tick 5196043137000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 2aa8a86ab..5fafbec2b 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.196043 # Nu sim_ticks 5196043137000 # Number of ticks simulated final_tick 5196043137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1241473 # Simulator instruction rate (inst/s) -host_op_rate 2393258 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50303585789 # Simulator tick rate (ticks/s) -host_mem_usage 354304 # Number of bytes of host memory used -host_seconds 103.29 # Real time elapsed on the host +host_inst_rate 682761 # Simulator instruction rate (inst/s) +host_op_rate 1316197 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27664981075 # Simulator tick rate (ticks/s) +host_mem_usage 397336 # Number of bytes of host memory used +host_seconds 187.82 # Real time elapsed on the host sim_insts 128236332 # Number of instructions simulated sim_ops 247208442 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2881344 # Number of bytes read from this memory @@ -365,8 +365,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 23151326 # number of instructions that are conditional controls system.cpu.num_int_insts 231946757 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 720715933 # number of times the integer registers were read -system.cpu.num_int_register_writes 387556667 # number of times the integer registers were written +system.cpu.num_int_register_reads 566912178 # number of times the integer registers were read +system.cpu.num_int_register_writes 293147449 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 22230275 # number of memory refs diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 5085616c4..6978d28ee 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,6 +129,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -157,6 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -428,6 +430,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -450,9 +453,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -466,6 +470,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -474,6 +479,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -515,7 +521,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -538,6 +544,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index f4d9273f5..1bec04837 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:22:30 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 21:50:34 +gem5 started Sep 10 2012 21:50:39 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 12789500 because target called exit() +Exiting @ tick 12607000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 89fb2bf27..1be5d9ebb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,272 +1,271 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12789500 # Number of ticks simulated -final_tick 12789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12607000 # Number of ticks simulated +final_tick 12607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20973 # Simulator instruction rate (inst/s) -host_op_rate 37987 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49851854 # Simulator tick rate (ticks/s) -host_mem_usage 232356 # Number of bytes of host memory used +host_inst_rate 20393 # Simulator instruction rate (inst/s) +host_op_rate 36936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47780701 # Simulator tick rate (ticks/s) +host_mem_usage 271708 # Number of bytes of host memory used host_seconds 0.26 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory -system.physmem.bytes_read::total 28736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9216 # Number of bytes read from this memory +system.physmem.bytes_read::total 28672 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1521247899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 725595215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2246843113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1521247899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1521247899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1521247899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 725595215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2246843113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1543269612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 731022448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2274292060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1543269612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1543269612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1543269612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 731022448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2274292060 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 25580 # number of cpu cycles simulated +system.cpu.numCycles 25215 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3138 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3138 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 562 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2607 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 814 # Number of BTB hits +system.cpu.BPredUnit.lookups 3186 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3186 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 582 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2623 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15123 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3138 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 814 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4093 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2492 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3369 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 17601 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.521504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.991998 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8059 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15139 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3186 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4132 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2534 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3329 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 126 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1963 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 17595 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.538335 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.007747 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 13611 77.33% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 183 1.04% 78.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 154 0.87% 79.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 201 1.14% 80.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 179 1.02% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 174 0.99% 82.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 262 1.49% 83.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 168 0.95% 84.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2669 15.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 13576 77.16% 77.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 181 1.03% 78.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 155 0.88% 79.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 205 1.17% 80.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 167 0.95% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 166 0.94% 82.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 255 1.45% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 187 1.06% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2703 15.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 17601 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122674 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.591204 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8517 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3363 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3698 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1897 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25566 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1897 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8847 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2031 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 471 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3459 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 896 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24019 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 44 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 760 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 34373 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 69151 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 69135 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 17595 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126353 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.600397 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8491 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3340 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3724 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 111 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1929 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25781 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1929 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8836 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2060 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 411 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3455 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 904 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24174 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 785 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 26591 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 58087 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 58071 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 14595 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 19778 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 35 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21439 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17729 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11045 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 19872 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 17601 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.007272 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.841273 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 15531 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2042 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1780 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21436 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18052 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 228 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14920 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 17595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.025973 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.871104 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12034 68.37% 68.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1562 8.87% 77.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1007 5.72% 82.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 685 3.89% 86.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 692 3.93% 90.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 711 4.04% 94.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 630 3.58% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 245 1.39% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 35 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12050 68.49% 68.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1507 8.56% 77.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 947 5.38% 82.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 676 3.84% 86.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 766 4.35% 90.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 693 3.94% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 642 3.65% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 270 1.53% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 44 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 17601 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 17595 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 137 74.46% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 28 15.22% 89.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 10.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 141 77.47% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21 11.54% 89.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 20 10.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14250 80.38% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1990 11.22% 91.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1485 8.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14462 80.11% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2078 11.51% 91.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1508 8.35% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17729 # Type of FU issued -system.cpu.iq.rate 0.693081 # Inst issue rate -system.cpu.iq.fu_busy_cnt 184 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010378 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53330 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32532 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16277 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18052 # Type of FU issued +system.cpu.iq.rate 0.715923 # Inst issue rate +system.cpu.iq.fu_busy_cnt 182 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010082 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 54101 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32345 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16592 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17905 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18226 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 132 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1339 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 869 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1897 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21480 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 37 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1929 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21473 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2405 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1780 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 699 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16697 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1851 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1032 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 642 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 708 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17072 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1925 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 980 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3217 # number of memory reference insts executed -system.cpu.iew.exec_branches 1636 # Number of branches executed -system.cpu.iew.exec_stores 1366 # Number of stores executed -system.cpu.iew.exec_rate 0.652737 # Inst execution rate -system.cpu.iew.wb_sent 16474 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16281 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10466 # num instructions producing a value -system.cpu.iew.wb_consumers 23993 # num instructions consuming a value +system.cpu.iew.exec_refs 3318 # number of memory reference insts executed +system.cpu.iew.exec_branches 1690 # Number of branches executed +system.cpu.iew.exec_stores 1393 # Number of stores executed +system.cpu.iew.exec_rate 0.677057 # Inst execution rate +system.cpu.iew.wb_sent 16795 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16596 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10614 # num instructions producing a value +system.cpu.iew.wb_consumers 16437 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.636474 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.436211 # average fanout of values written-back +system.cpu.iew.wb_rate 0.658180 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.645738 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5380 # The number of committed instructions system.cpu.commit.commitCommittedOps 9745 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11734 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11727 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 583 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15704 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.620543 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459156 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 596 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15666 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.622048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.485565 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11988 76.34% 76.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1532 9.76% 86.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 562 3.58% 89.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 734 4.67% 94.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 373 2.38% 96.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 129 0.82% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 134 0.85% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70 0.45% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 182 1.16% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12031 76.80% 76.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1491 9.52% 86.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 525 3.35% 89.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 708 4.52% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 369 2.36% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 134 0.86% 97.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 127 0.81% 98.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 76 0.49% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 205 1.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15704 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15666 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -277,68 +276,68 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9650 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 182 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 205 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 37001 # The number of ROB reads -system.cpu.rob.rob_writes 44889 # The number of ROB writes -system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7979 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 36933 # The number of ROB reads +system.cpu.rob.rob_writes 44901 # The number of ROB writes +system.cpu.timesIdled 145 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7620 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 4.754647 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.754647 # CPI: Total CPI of All Threads -system.cpu.ipc 0.210321 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.210321 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 35250 # number of integer regfile reads -system.cpu.int_regfile_writes 21824 # number of integer regfile writes +system.cpu.cpi 4.686803 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.686803 # CPI: Total CPI of All Threads +system.cpu.ipc 0.213365 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.213365 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 30057 # number of integer regfile reads +system.cpu.int_regfile_writes 17963 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7352 # number of misc regfile reads +system.cpu.misc_regfile_reads 7481 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.590340 # Cycle average of tags in use -system.cpu.icache.total_refs 1562 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 145.992239 # Cycle average of tags in use +system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.121311 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.134426 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.590340 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071089 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071089 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1562 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1562 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1562 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1562 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1562 # number of overall hits -system.cpu.icache.overall_hits::total 1562 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 388 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 388 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 388 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 388 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 388 # number of overall misses -system.cpu.icache.overall_misses::total 388 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14396500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14396500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14396500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14396500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14396500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14396500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198974 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.198974 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.198974 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.198974 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.198974 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.198974 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37104.381443 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37104.381443 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37104.381443 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37104.381443 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37104.381443 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37104.381443 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 145.992239 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071285 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071285 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits +system.cpu.icache.overall_hits::total 1566 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 397 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 397 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 397 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 397 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 397 # number of overall misses +system.cpu.icache.overall_misses::total 397 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14592000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14592000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14592000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14592000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14592000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14592000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1963 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1963 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1963 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1963 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.202241 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.202241 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.202241 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.202241 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.202241 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.202241 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36755.667506 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36755.667506 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36755.667506 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36755.667506 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36755.667506 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36755.667506 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -347,94 +346,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 83 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 83 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 83 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 305 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 305 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 305 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11253500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11253500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11253500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11253500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11253500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11253500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.156410 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.156410 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.156410 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.156410 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.156410 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.156410 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36896.721311 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36896.721311 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36896.721311 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36896.721311 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36896.721311 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36896.721311 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11283000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11283000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11283000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155374 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.155374 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.155374 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36993.442623 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36993.442623 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36993.442623 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36993.442623 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36993.442623 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36993.442623 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.110838 # Cycle average of tags in use -system.cpu.dcache.total_refs 2373 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.479167 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.306580 # Cycle average of tags in use +system.cpu.dcache.total_refs 2452 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 17.146853 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.110838 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020291 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020291 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1515 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1515 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 83.306580 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020339 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020339 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1594 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1594 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits -system.cpu.dcache.overall_hits::total 2373 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2452 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2452 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2452 # number of overall hits +system.cpu.dcache.overall_hits::total 2452 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses -system.cpu.dcache.overall_misses::total 190 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4446000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4446000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3078000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3078000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7524000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7524000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7524000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7524000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1629 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1629 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses +system.cpu.dcache.overall_misses::total 209 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5163500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5163500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3068500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3068500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8232000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8232000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8232000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8232000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1727 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1727 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2563 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2563 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2563 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2563 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.069982 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.069982 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2661 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2661 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2661 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2661 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077012 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.077012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074132 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074132 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074132 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074132 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40500 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39600 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39600 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.078542 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.078542 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.078542 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.078542 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38823.308271 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38823.308271 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40375 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40375 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39387.559809 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39387.559809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39387.559809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39387.559809 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -443,56 +442,56 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 65 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 68 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 68 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 145 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 145 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 145 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 145 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2719000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2719000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2850000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2850000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5569000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5569000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5569000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5569000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042357 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042357 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2714500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2714500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2840500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2840500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5555000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5555000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5555000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5555000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039375 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056574 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056574 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056574 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056574 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39405.797101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39405.797101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38406.896552 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38406.896552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38406.896552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38406.896552 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054115 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054115 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054115 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054115 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39919.117647 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39919.117647 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37375 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37375 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38576.388889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38576.388889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38576.388889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38576.388889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 178.404292 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.358150 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 372 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002688 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 371 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002695 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 145.559104 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.845188 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004442 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005444 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 145.966975 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.391174 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004455 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000989 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005443 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -500,60 +499,60 @@ system.cpu.l2cache.demand_hits::total 1 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 304 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 69 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 68 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 372 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 145 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 144 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 448 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 145 # number of overall misses -system.cpu.l2cache.overall_misses::total 449 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2646000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13590000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2771500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2771500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10944000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5417500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16361500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10944000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5417500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16361500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 144 # number of overall misses +system.cpu.l2cache.overall_misses::total 448 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10974500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2644000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13618500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2762000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2762000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10974500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5406000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16380500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10974500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5406000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16380500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 305 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 69 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 68 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 373 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 305 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 145 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 450 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 305 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 145 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 450 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996721 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997319 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996721 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997778 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997773 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996721 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997778 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38347.826087 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36434.316354 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36467.105263 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36467.105263 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37362.068966 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36439.866370 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37362.068966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36439.866370 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997773 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36100.328947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38882.352941 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36608.870968 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36342.105263 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36342.105263 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36100.328947 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37541.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36563.616071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36100.328947 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37541.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36563.616071 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,49 +562,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 68 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 372 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 145 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 449 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 448 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 145 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 449 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9981000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2435500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12416500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2541500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2541500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9981000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4977000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14958000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9981000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4977000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14958000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 448 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10010000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2437500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12447500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2532000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2532000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10010000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4969500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14979500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10010000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4969500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14979500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997319 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997778 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997773 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997778 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32832.236842 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35297.101449 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33288.203753 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33440.789474 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33440.789474 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32832.236842 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34324.137931 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33314.031180 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32832.236842 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34324.137931 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33314.031180 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997773 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32927.631579 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35845.588235 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33461.021505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33315.789474 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33315.789474 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32927.631579 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34510.416667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33436.383929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32927.631579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34510.416667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33436.383929 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index 1c047bcde..d417ce700 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,7 +106,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index 2878f37c1..a8facaf1f 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:22:41 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 21:50:34 +gem5 started Sep 10 2012 21:50:39 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 288f81674..67f89709c 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5614000 # Number of ticks simulated final_tick 5614000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93021 # Simulator instruction rate (inst/s) -host_op_rate 168430 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96993365 # Simulator tick rate (ticks/s) -host_mem_usage 222752 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 59958 # Simulator instruction rate (inst/s) +host_op_rate 108572 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62528382 # Simulator tick rate (ticks/s) +host_mem_usage 261084 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls system.cpu.num_int_insts 9651 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29744 # number of times the integer registers were read -system.cpu.num_int_register_writes 14595 # number of times the integer registers were written +system.cpu.num_int_register_reads 24812 # number of times the integer registers were read +system.cpu.num_int_register_writes 11060 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1986 # number of memory refs diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 09c807544..8e358d7bf 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -73,7 +73,7 @@ type=X86LocalApic clock=1 int_latency=1 pio_addr=2305843009213693952 -pio_latency=1 +pio_latency=100 system=system int_master=system.l1_cntrl0.sequencer.slave[4] int_slave=system.l1_cntrl0.sequencer.master[1] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index cd9956361..5f61ae7e1 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -1,4 +1,4 @@ -Real time: Sep/09/2012 13:51:25 +Real time: Sep/10/2012 21:50:40 Profiler Stats -------------- @@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.53 -Virtual_time_in_minutes: 0.00883333 -Virtual_time_in_hours: 0.000147222 -Virtual_time_in_days: 6.13426e-06 +Virtual_time_in_seconds: 0.48 +Virtual_time_in_minutes: 0.008 +Virtual_time_in_hours: 0.000133333 +Virtual_time_in_days: 5.55556e-06 Ruby_current_time: 121759 Ruby_start_time: 0 Ruby_cycles: 121759 -mbytes_resident: 59.5742 -mbytes_total: 275.16 -resident_ratio: 0.216522 +mbytes_resident: 57.9453 +mbytes_total: 275.082 +resident_ratio: 0.210662 ruby_cycles_executed: [ 121760 ] @@ -89,11 +89,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11362 +page_reclaims: 11940 page_faults: 0 swaps: 0 -block_inputs: 0 -block_outputs: 80 +block_inputs: 24 +block_outputs: 88 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 290b12614..33d7b7dce 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 9 2012 13:51:17 -gem5 started Sep 9 2012 13:51:25 +gem5 compiled Sep 10 2012 21:50:34 +gem5 started Sep 10 2012 21:50:39 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 5b3d1f38b..6f7115490 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 4061 # Simulator instruction rate (inst/s) -host_op_rate 7355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91887 # Simulator tick rate (ticks/s) -host_mem_usage 243480 # Number of bytes of host memory used -host_seconds 1.33 # Real time elapsed on the host +host_inst_rate 21174 # Simulator instruction rate (inst/s) +host_op_rate 38347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 479042 # Simulator tick rate (ticks/s) +host_mem_usage 281688 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory @@ -51,8 +51,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls system.cpu.num_int_insts 9651 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29744 # number of times the integer registers were read -system.cpu.num_int_register_writes 14595 # number of times the integer registers were written +system.cpu.num_int_register_reads 24812 # number of times the integer registers were read +system.cpu.num_int_register_writes 11060 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1986 # number of memory refs diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 3f04b065a..e0483161d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -184,7 +190,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 4ca1a9d26..6c9c7da05 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:22:51 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 21:50:34 +gem5 started Sep 10 2012 21:50:39 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index c89020746..c50a3998a 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu sim_ticks 29676000 # Number of ticks simulated final_tick 29676000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192246 # Simulator instruction rate (inst/s) -host_op_rate 347982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1058982197 # Simulator tick rate (ticks/s) -host_mem_usage 231200 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 72347 # Simulator instruction rate (inst/s) +host_op_rate 131001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 398795084 # Simulator tick rate (ticks/s) +host_mem_usage 269536 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory @@ -39,8 +39,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls system.cpu.num_int_insts 9651 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29744 # number of times the integer registers were read -system.cpu.num_int_register_writes 14595 # number of times the integer registers were written +system.cpu.num_int_register_reads 24812 # number of times the integer registers were read +system.cpu.num_int_register_writes 11060 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1986 # number of memory refs |