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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-09 00:27:41 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-09 00:27:41 -0400 |
| commit | 0087061681869c9aaab81c3797020b083a83d46a (patch) | |
| tree | 81fdaea886a5564e7e9554936a05ba5d920595c7 | |
| parent | 4f93c43d34f66b164cc67f87e7a75fc500a79fa6 (diff) | |
| download | gem5-0087061681869c9aaab81c3797020b083a83d46a.tar.xz | |
Don't create a response if one isn't needed.
--HG--
extra : convert_revision : 37bd230f527f64eb12779157869aae9dcfdde7fd
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 9ce8f515d..ac2d7af8b 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -620,7 +620,9 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort lat = memSidePort->sendAtomic(busPkt); //Be sure to flip the response to a request for coherence - busPkt->makeAtomicResponse(); + if (busPkt->needsResponse()) { + busPkt->makeAtomicResponse(); + } /* if (!(busPkt->flags & SATISFIED)) { // blocked at a higher level, just return |