diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-28 09:32:01 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-28 09:32:01 -0500 |
| commit | 1af9369779466df9b3086150164dcb5de034abc9 (patch) | |
| tree | 50aa8eb6a3a1f08fe4a2d73ef5a4781dd0ffb942 | |
| parent | 4646369afd408b486fd3515c35d6c6bbe8960839 (diff) | |
| download | gem5-1af9369779466df9b3086150164dcb5de034abc9.tar.xz | |
regressions: update eio stats due to cache latency fix
4 files changed, 639 insertions, 643 deletions
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 8d9896222..6a2952c7b 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -29,11 +31,11 @@ system_port=system.membus.slave[1] [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -41,15 +43,16 @@ dtb=system.cpu0.dtb function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu0.tracer workload=system.cpu0.workload @@ -61,21 +64,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -90,21 +90,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -113,6 +110,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=AlphaInterrupts +[system.cpu0.isa] +type=AlphaISA + [system.cpu0.itb] type=AlphaTLB size=48 @@ -124,7 +124,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -132,11 +132,11 @@ system=system [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=1 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -144,15 +144,16 @@ dtb=system.cpu1.dtb function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu1.tracer workload=system.cpu1.workload @@ -164,21 +165,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -193,21 +191,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -216,6 +211,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=AlphaInterrupts +[system.cpu1.isa] +type=AlphaISA + [system.cpu1.itb] type=AlphaTLB size=48 @@ -227,7 +225,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -235,11 +233,11 @@ system=system [system.cpu2] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=2 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -247,15 +245,16 @@ dtb=system.cpu2.dtb function_trace=false function_trace_start=0 interrupts=system.cpu2.interrupts +isa=system.cpu2.isa itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu2.tracer workload=system.cpu2.workload @@ -267,21 +266,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port @@ -296,21 +292,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port @@ -319,6 +312,9 @@ mem_side=system.toL2Bus.slave[4] [system.cpu2.interrupts] type=AlphaInterrupts +[system.cpu2.isa] +type=AlphaISA + [system.cpu2.itb] type=AlphaTLB size=48 @@ -330,7 +326,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -338,11 +334,11 @@ system=system [system.cpu3] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=3 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -350,15 +346,16 @@ dtb=system.cpu3.dtb function_trace=false function_trace_start=0 interrupts=system.cpu3.interrupts +isa=system.cpu3.isa itb=system.cpu3.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu3.tracer workload=system.cpu3.workload @@ -370,21 +367,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port @@ -399,21 +393,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port @@ -422,6 +413,9 @@ mem_side=system.toL2Bus.slave[6] [system.cpu3.interrupts] type=AlphaInterrupts +[system.cpu3.isa] +type=AlphaISA + [system.cpu3.itb] type=AlphaTLB size=48 @@ -433,7 +427,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -444,21 +438,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=20 size=4194304 -subblock_size=0 system=system -tgts_per_mshr=16 -trace_addr=0 +tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] @@ -469,6 +460,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -476,8 +468,9 @@ slave=system.l2c.mem_side system.system_port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1000 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 @@ -489,8 +482,9 @@ port=system.membus.master[0] [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr index 8b296506e..4399b76d5 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -8,3 +8,5 @@ gzip: stdout: Broken pipe gzip: stdout: Broken pipe gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index ed2a31412..2900cfcc7 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -1,12 +1,12 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr +Redirecting stdout to build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout +Redirecting stderr to build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 20:21:46 -gem5 started Jul 23 2012 00:28:55 -gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp +gem5 compiled Mar 28 2013 09:19:43 +gem5 started Mar 28 2013 09:22:33 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries @@ -17,4 +17,4 @@ main dictionary has 1245 entries 49508 bytes wasted 49508 bytes wasted 49508 bytes wasted ->>>>Exiting @ tick 731328000 because a thread reached the max instruction count +>>>>Exiting @ tick 729071000 because a thread reached the max instruction count diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 80f4c7ad2..0ede4e331 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000729 # Number of seconds simulated -sim_ticks 728599000 # Number of ticks simulated -final_tick 728599000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 729071000 # Number of ticks simulated +final_tick 729071000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1327611 # Simulator instruction rate (inst/s) -host_op_rate 1327594 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 483660925 # Simulator tick rate (ticks/s) -host_mem_usage 267288 # Number of bytes of host memory used -host_seconds 1.51 # Real time elapsed on the host -sim_insts 1999897 # Number of instructions simulated -sim_ops 1999897 # Number of ops (including micro ops) simulated +host_inst_rate 1157540 # Simulator instruction rate (inst/s) +host_op_rate 1157526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 421963637 # Simulator tick rate (ticks/s) +host_mem_usage 274580 # Number of bytes of host memory used +host_seconds 1.73 # Real time elapsed on the host +sim_insts 1999959 # Number of instructions simulated +sim_ops 1999959 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory @@ -34,29 +34,29 @@ system.physmem.num_reads::cpu2.data 454 # Nu system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 35399445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39879275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35399445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 39879275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 35399445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 39879275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 35399445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 39879275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 301114879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 35399445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35399445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 35399445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 35399445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141597779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 35399445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39879275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35399445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 39879275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 35399445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 39879275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 35399445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 39879275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 301114879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 35376527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 39853457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35376527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 39853457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 35376527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 39853457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 35376527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 39853457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 300919938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 35376527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35376527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 35376527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 35376527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141506108 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 35376527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 39853457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35376527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 39853457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 35376527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 39853457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 35376527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 39853457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 300919938 # Total bandwidth to/from this memory (bytes/s) system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv @@ -90,7 +90,7 @@ system.cpu0.itb.data_misses 0 # DT system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.workload.num_syscalls 18 # Number of system calls -system.cpu0.numCycles 1457198 # number of cpu cycles simulated +system.cpu0.numCycles 1458142 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 500001 # Number of instructions committed @@ -109,18 +109,18 @@ system.cpu0.num_mem_refs 180793 # nu system.cpu0.num_load_insts 124443 # Number of load instructions system.cpu0.num_store_insts 56350 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 1457198 # Number of busy cycles +system.cpu0.num_busy_cycles 1458142 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 152 # number of replacements -system.cpu0.icache.tagsinuse 216.402080 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 216.378486 # Cycle average of tags in use system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 216.402080 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.422660 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.422660 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 216.378486 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.422614 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.422614 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits @@ -133,12 +133,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 463 # system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses system.cpu0.icache.overall_misses::total 463 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23115500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23115500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 23115500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23115500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 23115500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23115500 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23142000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23142000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 23142000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23142000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 23142000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23142000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses @@ -151,12 +151,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49925.485961 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 49925.485961 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49925.485961 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 49925.485961 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49925.485961 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 49925.485961 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49982.721382 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 49982.721382 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49982.721382 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 49982.721382 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49982.721382 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 49982.721382 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,34 +171,34 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22189500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22189500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22189500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22189500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22189500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22189500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22216000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22216000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22216000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22216000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22216000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22216000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47925.485961 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47925.485961 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47925.485961 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 47925.485961 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47925.485961 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 47925.485961 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47982.721382 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47982.721382 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47982.721382 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 47982.721382 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47982.721382 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 47982.721382 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 61 # number of replacements -system.cpu0.dcache.tagsinuse 273.541050 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 273.500836 # Cycle average of tags in use system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 273.541050 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.534260 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.534260 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 273.500836 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.534181 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.534181 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits @@ -215,14 +215,14 @@ system.cpu0.dcache.demand_misses::cpu0.data 463 # system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses system.cpu0.dcache.overall_misses::total 463 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17473000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17473000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7671500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7671500 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 25144500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25144500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 25144500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25144500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17475500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 17475500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7669500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 25145000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 25145000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 25145000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 25145000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses) @@ -239,14 +239,14 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53929.012346 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 53929.012346 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55190.647482 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 55190.647482 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54307.775378 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 54307.775378 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54307.775378 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 54307.775378 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53936.728395 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 53936.728395 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55176.258993 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54308.855292 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 54308.855292 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54308.855292 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 54308.855292 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -265,14 +265,14 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16825000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16825000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7393500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7393500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24218500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24218500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24218500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 24218500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16827500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16827500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7391500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24219000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24219000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24219000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 24219000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses @@ -281,35 +281,35 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51929.012346 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 51929.012346 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53190.647482 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53190.647482 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52307.775378 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52307.775378 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52307.775378 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52307.775378 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51936.728395 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 51936.728395 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53176.258993 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52308.855292 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52308.855292 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52308.855292 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52308.855292 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 124427 # DTB read hits +system.cpu1.dtb.read_hits 124435 # DTB read hits system.cpu1.dtb.read_misses 8 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 124435 # DTB read accesses +system.cpu1.dtb.read_accesses 124443 # DTB read accesses system.cpu1.dtb.write_hits 56339 # DTB write hits system.cpu1.dtb.write_misses 10 # DTB write misses system.cpu1.dtb.write_acv 0 # DTB write access violations system.cpu1.dtb.write_accesses 56349 # DTB write accesses -system.cpu1.dtb.data_hits 180766 # DTB hits +system.cpu1.dtb.data_hits 180774 # DTB hits system.cpu1.dtb.data_misses 18 # DTB misses system.cpu1.dtb.data_acv 0 # DTB access violations -system.cpu1.dtb.data_accesses 180784 # DTB accesses -system.cpu1.itb.fetch_hits 499991 # ITB hits +system.cpu1.dtb.data_accesses 180792 # DTB accesses +system.cpu1.itb.fetch_hits 500012 # ITB hits system.cpu1.itb.fetch_misses 13 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 500004 # ITB accesses +system.cpu1.itb.fetch_accesses 500025 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -323,73 +323,73 @@ system.cpu1.itb.data_misses 0 # DT system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.workload.num_syscalls 18 # Number of system calls -system.cpu1.numCycles 1457198 # number of cpu cycles simulated +system.cpu1.numCycles 1458142 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 499972 # Number of instructions committed -system.cpu1.committedOps 499972 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 474661 # Number of integer alu accesses +system.cpu1.committedInsts 499993 # Number of instructions committed +system.cpu1.committedOps 499993 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 474681 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses system.cpu1.num_func_calls 14357 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 38176 # number of instructions that are conditional controls -system.cpu1.num_int_insts 474661 # number of integer instructions +system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls +system.cpu1.num_int_insts 474681 # number of integer instructions system.cpu1.num_fp_insts 32 # number of float instructions -system.cpu1.num_int_register_reads 654248 # number of times the integer registers were read -system.cpu1.num_int_register_writes 371519 # number of times the integer registers were written +system.cpu1.num_int_register_reads 654273 # number of times the integer registers were read +system.cpu1.num_int_register_writes 371536 # number of times the integer registers were written system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu1.num_mem_refs 180784 # number of memory refs -system.cpu1.num_load_insts 124435 # Number of load instructions +system.cpu1.num_mem_refs 180792 # number of memory refs +system.cpu1.num_load_insts 124443 # Number of load instructions system.cpu1.num_store_insts 56349 # Number of store instructions system.cpu1.num_idle_cycles 0 # Number of idle cycles -system.cpu1.num_busy_cycles 1457198 # Number of busy cycles +system.cpu1.num_busy_cycles 1458142 # Number of busy cycles system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles system.cpu1.icache.replacements 152 # number of replacements -system.cpu1.icache.tagsinuse 216.396228 # Cycle average of tags in use -system.cpu1.icache.total_refs 499528 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 216.374608 # Cycle average of tags in use +system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 1078.894168 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 216.396228 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.422649 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.422649 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 499528 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 499528 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 499528 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 499528 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 499528 # number of overall hits -system.cpu1.icache.overall_hits::total 499528 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 216.374608 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.422607 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.422607 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 499549 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 499549 # number of overall hits +system.cpu1.icache.overall_hits::total 499549 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses system.cpu1.icache.overall_misses::total 463 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 23148500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 23148500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 23148500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 23148500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 23148500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 23148500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 499991 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 499991 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 499991 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 499991 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 499991 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 499991 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 23145500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 23145500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 23145500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 23145500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 23145500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 23145500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 500012 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 500012 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 500012 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 500012 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 500012 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 500012 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 49996.760259 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 49996.760259 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 49996.760259 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 49996.760259 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49996.760259 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 49996.760259 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 49990.280778 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 49990.280778 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 49990.280778 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 49990.280778 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49990.280778 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 49990.280778 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -404,42 +404,42 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22222500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 22222500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22222500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 22222500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22222500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 22222500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22219500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 22219500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22219500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 22219500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22219500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 22219500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47996.760259 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 47996.760259 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47996.760259 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 47996.760259 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47996.760259 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 47996.760259 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47990.280778 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 47990.280778 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47990.280778 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 47990.280778 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47990.280778 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 47990.280778 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 61 # number of replacements -system.cpu1.dcache.tagsinuse 273.532406 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180303 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 273.495853 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 389.423326 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 273.532406 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.534243 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.534243 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 124103 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 124103 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 273.495853 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.534172 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.534172 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 56200 # number of WriteReq hits -system.cpu1.dcache.demand_hits::cpu1.data 180303 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 180303 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 180303 # number of overall hits -system.cpu1.dcache.overall_hits::total 180303 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 180311 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 180311 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 180311 # number of overall hits +system.cpu1.dcache.overall_hits::total 180311 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses @@ -448,22 +448,22 @@ system.cpu1.dcache.demand_misses::cpu1.data 463 # system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses system.cpu1.dcache.overall_misses::total 463 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17471500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 17471500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7678000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7678000 # number of WriteReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 25149500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 25149500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 25149500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 25149500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 124427 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 124427 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17480000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 17480000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7670500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7670500 # number of WriteReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 25150500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 25150500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 25150500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 25150500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 180766 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 180766 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 180766 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 180766 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 180774 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 180774 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses @@ -472,14 +472,14 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53924.382716 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 53924.382716 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55237.410072 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 55237.410072 # average WriteReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54318.574514 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 54318.574514 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54318.574514 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 54318.574514 # average overall miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53950.617284 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 53950.617284 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55183.453237 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 55183.453237 # average WriteReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54320.734341 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 54320.734341 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54320.734341 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 54320.734341 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,14 +498,14 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16823500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16823500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7400000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7400000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24223500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 24223500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24223500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 24223500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16832000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16832000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7392500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7392500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24224500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 24224500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24224500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 24224500 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses @@ -514,35 +514,35 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51924.382716 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 51924.382716 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53237.410072 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53237.410072 # average WriteReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52318.574514 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52318.574514 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52318.574514 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52318.574514 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51950.617284 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 51950.617284 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53183.453237 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53183.453237 # average WriteReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52320.734341 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52320.734341 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52320.734341 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52320.734341 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 124424 # DTB read hits +system.cpu2.dtb.read_hits 124433 # DTB read hits system.cpu2.dtb.read_misses 8 # DTB read misses system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_accesses 124432 # DTB read accesses +system.cpu2.dtb.read_accesses 124441 # DTB read accesses system.cpu2.dtb.write_hits 56339 # DTB write hits system.cpu2.dtb.write_misses 10 # DTB write misses system.cpu2.dtb.write_acv 0 # DTB write access violations system.cpu2.dtb.write_accesses 56349 # DTB write accesses -system.cpu2.dtb.data_hits 180763 # DTB hits +system.cpu2.dtb.data_hits 180772 # DTB hits system.cpu2.dtb.data_misses 18 # DTB misses system.cpu2.dtb.data_acv 0 # DTB access violations -system.cpu2.dtb.data_accesses 180781 # DTB accesses -system.cpu2.itb.fetch_hits 499984 # ITB hits +system.cpu2.dtb.data_accesses 180790 # DTB accesses +system.cpu2.itb.fetch_hits 500005 # ITB hits system.cpu2.itb.fetch_misses 13 # ITB misses system.cpu2.itb.fetch_acv 0 # ITB acv -system.cpu2.itb.fetch_accesses 499997 # ITB accesses +system.cpu2.itb.fetch_accesses 500018 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -556,73 +556,73 @@ system.cpu2.itb.data_misses 0 # DT system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses system.cpu2.workload.num_syscalls 18 # Number of system calls -system.cpu2.numCycles 1457198 # number of cpu cycles simulated +system.cpu2.numCycles 1458142 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 499965 # Number of instructions committed -system.cpu2.committedOps 499965 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 474654 # Number of integer alu accesses +system.cpu2.committedInsts 499986 # Number of instructions committed +system.cpu2.committedOps 499986 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 474674 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses system.cpu2.num_func_calls 14357 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 38175 # number of instructions that are conditional controls -system.cpu2.num_int_insts 474654 # number of integer instructions +system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls +system.cpu2.num_int_insts 474674 # number of integer instructions system.cpu2.num_fp_insts 32 # number of float instructions -system.cpu2.num_int_register_reads 654241 # number of times the integer registers were read -system.cpu2.num_int_register_writes 371514 # number of times the integer registers were written +system.cpu2.num_int_register_reads 654263 # number of times the integer registers were read +system.cpu2.num_int_register_writes 371529 # number of times the integer registers were written system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu2.num_mem_refs 180780 # number of memory refs -system.cpu2.num_load_insts 124432 # Number of load instructions -system.cpu2.num_store_insts 56348 # Number of store instructions +system.cpu2.num_mem_refs 180790 # number of memory refs +system.cpu2.num_load_insts 124441 # Number of load instructions +system.cpu2.num_store_insts 56349 # Number of store instructions system.cpu2.num_idle_cycles 0 # Number of idle cycles -system.cpu2.num_busy_cycles 1457198 # Number of busy cycles +system.cpu2.num_busy_cycles 1458142 # Number of busy cycles system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles system.cpu2.icache.replacements 152 # number of replacements -system.cpu2.icache.tagsinuse 216.391431 # Cycle average of tags in use -system.cpu2.icache.total_refs 499521 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 216.370489 # Cycle average of tags in use +system.cpu2.icache.total_refs 499542 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 1078.879050 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 1078.924406 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 216.391431 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.422640 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.422640 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 499521 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 499521 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 499521 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 499521 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 499521 # number of overall hits -system.cpu2.icache.overall_hits::total 499521 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 216.370489 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.422599 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.422599 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 499542 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 499542 # number of overall hits +system.cpu2.icache.overall_hits::total 499542 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses system.cpu2.icache.overall_misses::total 463 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 23151000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 23151000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 23151000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 23151000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 23151000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 23151000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 499984 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 499984 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 499984 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 499984 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 499984 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 499984 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 23141000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 23141000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 23141000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 23141000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 23141000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 23141000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 500005 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 500005 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 500005 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 500005 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 500005 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 500005 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 50002.159827 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 50002.159827 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 50002.159827 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 50002.159827 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 50002.159827 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 50002.159827 # average overall miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 49980.561555 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 49980.561555 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 49980.561555 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 49980.561555 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 49980.561555 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 49980.561555 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,42 +637,42 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22225000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 22225000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22225000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 22225000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22225000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 22225000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22215000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 22215000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22215000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 22215000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22215000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 22215000 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48002.159827 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48002.159827 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48002.159827 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 48002.159827 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48002.159827 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 48002.159827 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47980.561555 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 47980.561555 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47980.561555 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 47980.561555 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47980.561555 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 47980.561555 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 61 # number of replacements -system.cpu2.dcache.tagsinuse 273.525060 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180300 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 273.490811 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 389.416847 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 273.525060 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.534229 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.534229 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 124100 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 124100 # number of ReadReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 273.490811 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.534162 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.534162 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::total 56200 # number of WriteReq hits -system.cpu2.dcache.demand_hits::cpu2.data 180300 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 180300 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 180300 # number of overall hits -system.cpu2.dcache.overall_hits::total 180300 # number of overall hits +system.cpu2.dcache.demand_hits::cpu2.data 180309 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 180309 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 180309 # number of overall hits +system.cpu2.dcache.overall_hits::total 180309 # number of overall hits system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses @@ -681,22 +681,22 @@ system.cpu2.dcache.demand_misses::cpu2.data 463 # system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses system.cpu2.dcache.overall_misses::total 463 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17480500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 17480500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7676500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 7676500 # number of WriteReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 25157000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 25157000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 25157000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 25157000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 124424 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 124424 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17485000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 17485000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7679000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 7679000 # number of WriteReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 25164000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 25164000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 25164000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 25164000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 124433 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 180763 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 180763 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 180763 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 180763 # number of overall (read+write) accesses +system.cpu2.dcache.demand_accesses::cpu2.data 180772 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 180772 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses @@ -705,14 +705,14 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53952.160494 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 53952.160494 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55226.618705 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 55226.618705 # average WriteReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54334.773218 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 54334.773218 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54334.773218 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 54334.773218 # average overall miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53966.049383 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 53966.049383 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55244.604317 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 55244.604317 # average WriteReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54349.892009 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 54349.892009 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54349.892009 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 54349.892009 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -731,14 +731,14 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16832500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16832500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7398500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7398500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24231000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 24231000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24231000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 24231000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16837000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16837000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7401000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7401000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24238000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 24238000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24238000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 24238000 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses @@ -747,35 +747,35 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51952.160494 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 51952.160494 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53226.618705 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53226.618705 # average WriteReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52334.773218 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52334.773218 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52334.773218 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52334.773218 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51966.049383 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 51966.049383 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53244.604317 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53244.604317 # average WriteReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52349.892009 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52349.892009 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52349.892009 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52349.892009 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dtb.fetch_hits 0 # ITB hits system.cpu3.dtb.fetch_misses 0 # ITB misses system.cpu3.dtb.fetch_acv 0 # ITB acv system.cpu3.dtb.fetch_accesses 0 # ITB accesses -system.cpu3.dtb.read_hits 124423 # DTB read hits +system.cpu3.dtb.read_hits 124431 # DTB read hits system.cpu3.dtb.read_misses 8 # DTB read misses system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_accesses 124431 # DTB read accesses -system.cpu3.dtb.write_hits 56336 # DTB write hits +system.cpu3.dtb.read_accesses 124439 # DTB read accesses +system.cpu3.dtb.write_hits 56339 # DTB write hits system.cpu3.dtb.write_misses 10 # DTB write misses system.cpu3.dtb.write_acv 0 # DTB write access violations -system.cpu3.dtb.write_accesses 56346 # DTB write accesses -system.cpu3.dtb.data_hits 180759 # DTB hits +system.cpu3.dtb.write_accesses 56349 # DTB write accesses +system.cpu3.dtb.data_hits 180770 # DTB hits system.cpu3.dtb.data_misses 18 # DTB misses system.cpu3.dtb.data_acv 0 # DTB access violations -system.cpu3.dtb.data_accesses 180777 # DTB accesses -system.cpu3.itb.fetch_hits 499978 # ITB hits +system.cpu3.dtb.data_accesses 180788 # DTB accesses +system.cpu3.itb.fetch_hits 499998 # ITB hits system.cpu3.itb.fetch_misses 13 # ITB misses system.cpu3.itb.fetch_acv 0 # ITB acv -system.cpu3.itb.fetch_accesses 499991 # ITB accesses +system.cpu3.itb.fetch_accesses 500011 # ITB accesses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.read_acv 0 # DTB read access violations @@ -789,73 +789,73 @@ system.cpu3.itb.data_misses 0 # DT system.cpu3.itb.data_acv 0 # DTB access violations system.cpu3.itb.data_accesses 0 # DTB accesses system.cpu3.workload.num_syscalls 18 # Number of system calls -system.cpu3.numCycles 1457198 # number of cpu cycles simulated +system.cpu3.numCycles 1458142 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 499959 # Number of instructions committed -system.cpu3.committedOps 499959 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 474648 # Number of integer alu accesses +system.cpu3.committedInsts 499979 # Number of instructions committed +system.cpu3.committedOps 499979 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 474668 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses system.cpu3.num_func_calls 14357 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 38175 # number of instructions that are conditional controls -system.cpu3.num_int_insts 474648 # number of integer instructions +system.cpu3.num_conditional_control_insts 38178 # number of instructions that are conditional controls +system.cpu3.num_int_insts 474668 # number of integer instructions system.cpu3.num_fp_insts 32 # number of float instructions -system.cpu3.num_int_register_reads 654231 # number of times the integer registers were read -system.cpu3.num_int_register_writes 371510 # number of times the integer registers were written +system.cpu3.num_int_register_reads 654256 # number of times the integer registers were read +system.cpu3.num_int_register_writes 371524 # number of times the integer registers were written system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu3.num_mem_refs 180777 # number of memory refs -system.cpu3.num_load_insts 124431 # Number of load instructions -system.cpu3.num_store_insts 56346 # Number of store instructions +system.cpu3.num_mem_refs 180788 # number of memory refs +system.cpu3.num_load_insts 124439 # Number of load instructions +system.cpu3.num_store_insts 56349 # Number of store instructions system.cpu3.num_idle_cycles 0 # Number of idle cycles -system.cpu3.num_busy_cycles 1457198 # Number of busy cycles +system.cpu3.num_busy_cycles 1458142 # Number of busy cycles system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles system.cpu3.icache.replacements 152 # number of replacements -system.cpu3.icache.tagsinuse 216.387275 # Cycle average of tags in use -system.cpu3.icache.total_refs 499515 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 216.366465 # Cycle average of tags in use +system.cpu3.icache.total_refs 499535 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 1078.866091 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 1078.909287 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 216.387275 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.422631 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.422631 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 499515 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 499515 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 499515 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 499515 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 499515 # number of overall hits -system.cpu3.icache.overall_hits::total 499515 # number of overall hits +system.cpu3.icache.occ_blocks::cpu3.inst 216.366465 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.422591 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.422591 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 499535 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 499535 # number of overall hits +system.cpu3.icache.overall_hits::total 499535 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses system.cpu3.icache.overall_misses::total 463 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23158000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 23158000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 23158000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 23158000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 23158000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 23158000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 499978 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 499978 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 499978 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 499978 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 499978 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 499978 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23153500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 23153500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 23153500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 23153500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 23153500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 23153500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 499998 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 499998 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 499998 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 499998 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 499998 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 499998 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 50017.278618 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 50017.278618 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 50017.278618 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 50017.278618 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 50017.278618 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 50017.278618 # average overall miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 50007.559395 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 50007.559395 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 50007.559395 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 50007.559395 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 50007.559395 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 50007.559395 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,42 +870,42 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22232000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 22232000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22232000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 22232000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22232000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 22232000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22227500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 22227500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22227500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 22227500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22227500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 22227500 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48017.278618 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48017.278618 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48017.278618 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 48017.278618 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48017.278618 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 48017.278618 # average overall mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48007.559395 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48007.559395 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48007.559395 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 48007.559395 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48007.559395 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 48007.559395 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 61 # number of replacements -system.cpu3.dcache.tagsinuse 273.518608 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180296 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 273.485807 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 389.408207 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 273.518608 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.534216 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.534216 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 124099 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 124099 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 56197 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 56197 # number of WriteReq hits -system.cpu3.dcache.demand_hits::cpu3.data 180296 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 180296 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 180296 # number of overall hits -system.cpu3.dcache.overall_hits::total 180296 # number of overall hits +system.cpu3.dcache.occ_blocks::cpu3.data 273.485807 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.534152 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.534152 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits +system.cpu3.dcache.demand_hits::cpu3.data 180307 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 180307 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 180307 # number of overall hits +system.cpu3.dcache.overall_hits::total 180307 # number of overall hits system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses @@ -916,20 +916,20 @@ system.cpu3.dcache.overall_misses::cpu3.data 463 system.cpu3.dcache.overall_misses::total 463 # number of overall misses system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17480000 # number of ReadReq miss cycles system.cpu3.dcache.ReadReq_miss_latency::total 17480000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7680000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 7680000 # number of WriteReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 25160000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 25160000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 25160000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 25160000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 124423 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 124423 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 56336 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 56336 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 180759 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 180759 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 180759 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 180759 # number of overall (read+write) accesses +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7680500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 7680500 # number of WriteReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 25160500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 25160500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 25160500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 25160500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 124431 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 124431 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 180770 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 180770 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 180770 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 180770 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses @@ -940,12 +940,12 @@ system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53950.617284 # average ReadReq miss latency system.cpu3.dcache.ReadReq_avg_miss_latency::total 53950.617284 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55251.798561 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 55251.798561 # average WriteReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54341.252700 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 54341.252700 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54341.252700 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 54341.252700 # average overall miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55255.395683 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 55255.395683 # average WriteReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54342.332613 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 54342.332613 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54342.332613 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 54342.332613 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -966,12 +966,12 @@ system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16832000 # number of ReadReq MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16832000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7402000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7402000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24234000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 24234000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24234000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 24234000 # number of overall MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7402500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7402500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24234500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 24234500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24234500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 24234500 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses @@ -982,38 +982,38 @@ system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 51950.617284 # average ReadReq mshr miss latency system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 51950.617284 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53251.798561 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53251.798561 # average WriteReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52341.252700 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52341.252700 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52341.252700 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52341.252700 # average overall mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53255.395683 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53255.395683 # average WriteReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52342.332613 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52342.332613 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52342.332613 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52342.332613 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 1943.413172 # Cycle average of tags in use +system.l2c.tagsinuse 1943.183618 # Cycle average of tags in use system.l2c.total_refs 332 # Total number of references to valid blocks. system.l2c.sampled_refs 2932 # Sample count of references to valid blocks. system.l2c.avg_refs 0.113233 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 17.229148 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 265.044597 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 216.521054 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 265.036666 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 216.514723 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 265.030239 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 216.508669 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 265.024752 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 216.503324 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 17.224365 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 265.013770 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 216.489826 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 265.008551 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 216.485888 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 265.003220 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 216.481949 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 264.998020 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 216.478029 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.003304 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.003304 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.003304 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.003304 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.029654 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.029651 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits @@ -1075,38 +1075,38 @@ system.l2c.overall_misses::cpu2.data 454 # nu system.l2c.overall_misses::cpu3.inst 403 # number of overall misses system.l2c.overall_misses::cpu3.data 454 # number of overall misses system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 21098000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 16409000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 21108000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 16409000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 21117000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 16414500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 21134000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 16417000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 150106500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 21102500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 16409500 # 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number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 21102500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 23662000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 21114500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 23667000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 21126000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 23677000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 21137000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.data 23674500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 179123000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 21098000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 23661500 # 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number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 21137000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.data 23674500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 179123000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 179160500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses) @@ -1173,38 +1173,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.980562 # mi system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52352.357320 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52092.063492 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52377.171216 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52092.063492 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52399.503722 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52109.523810 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52441.687345 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 52117.460317 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52265.494429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52363.523573 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52093.650794 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52393.300248 # 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