Support for recent port changes.

src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/python/m5/objects/OzoneCPU.py:
    Support Ron's recent port changes.
src/cpu/ozone/lw_back_end_impl.hh:
    Support Ron's recent port changes.  Also support handling faults in SE.

--HG--
extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891

9 files changed, 38 insertions, 33 deletions

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 8993781ea..1ec8b70e6 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -372,6 +372,8 @@ class OzoneCPU : public BaseCPU
     PhysicalMemory *physmem;
 #endif
 
+    virtual Port *getPort(const std::string &name, int idx);
+
     MemObject *mem;
 
     FrontEnd *frontEnd;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index ccb1c8418..50ed94312 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -419,6 +419,18 @@ OzoneCPU<Impl>::init()
 }
 
 template <class Impl>
+Port *
+OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
+{
+    if (if_name == "dcache_port")
+        return backEnd->getDcachePort();
+    else if (if_name == "icache_port")
+        return frontEnd->getIcachePort();
+    else
+        panic("No Such Port\n");
+}
+
+template <class Impl>
 void
 OzoneCPU<Impl>::serialize(std::ostream &os)
 {
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 181609098..3ed3c4d18 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -119,6 +119,8 @@ class FrontEnd
 
     void regStats();
 
+    Port *getIcachePort() { return &icachePort; }
+
     void tick();
     Fault fetchCacheLine();
     void processInst(DynInstPtr &inst);
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 40042489d..9da937320 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -36,6 +36,7 @@
 #include "cpu/thread_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/ozone/front_end.hh"
+#include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
 
@@ -138,10 +139,6 @@ FrontEnd<Impl>::setCPU(CPUType *cpu_ptr)
 
     icachePort.setName(this->name() + "-iport");
 
-    Port *mem_dport = mem->getPort("");
-    icachePort.setPeer(mem_dport);
-    mem_dport->setPeer(&icachePort);
-
 #if USE_CHECKER
     if (cpu->checker) {
         cpu->checker->setIcachePort(&icachePort);
diff --git a/src/cpu/ozone/lw_back_end.hh b/src/cpu/ozone/lw_back_end.hh
index bb3ef3a72..cc36c611e 100644
--- a/src/cpu/ozone/lw_back_end.hh
+++ b/src/cpu/ozone/lw_back_end.hh
@@ -114,6 +114,8 @@ class LWBackEnd
 
     void setCommBuffer(TimeBuffer<CommStruct> *_comm);
 
+    Port *getDcachePort() { return LSQ.getDcachePort(); }
+
     void tick();
     void squash();
     void generateTCEvent() { tcSquash = true; }
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index a73d3ee6e..a4f1d805e 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -142,7 +142,7 @@ LWBackEnd<Impl>::replayMemInst(DynInstPtr &inst)
 template <class Impl>
 LWBackEnd<Impl>::LWBackEnd(Params *params)
     : d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5),
-      trapSquash(false), tcSquash(false), LSQ(params),
+      trapSquash(false), tcSquash(false),
       width(params->backEndWidth), exactFullStall(true)
 {
     numROBEntries = params->numROBEntries;
@@ -557,6 +557,7 @@ LWBackEnd<Impl>::checkInterrupts()
         }
     }
 }
+#endif
 
 template <class Impl>
 void
@@ -580,7 +581,6 @@ LWBackEnd<Impl>::handleFault(Fault &fault, Tick latency)
     // Generate trap squash event.
     generateTrapEvent(latency);
 }
-#endif
 
 template <class Impl>
 void
@@ -602,6 +602,7 @@ LWBackEnd<Impl>::tick()
 
 #if FULL_SYSTEM
     checkInterrupts();
+#endif
 
     if (trapSquash) {
         assert(!tcSquash);
@@ -609,7 +610,6 @@ LWBackEnd<Impl>::tick()
     } else if (tcSquash) {
         squashFromTC();
     }
-#endif
 
     if (dispatchStatus != Blocked) {
         dispatchInsts();
@@ -1137,13 +1137,9 @@ LWBackEnd<Impl>::commitInst(int inst_num)
 
         thread->setInst(
             static_cast<TheISA::MachInst>(inst->staticInst->machInst));
-#if FULL_SYSTEM
+
         handleFault(inst_fault);
         return false;
-#else // !FULL_SYSTEM
-        panic("fault (%d) detected @ PC %08p", inst_fault,
-              inst->PC);
-#endif // FULL_SYSTEM
     }
 
     int freed_regs = 0;
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index c749e3aee..2eb09d01a 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -91,8 +91,7 @@ class OzoneLWLSQ {
     void setBE(BackEnd *be_ptr)
     { be = be_ptr; }
 
-    /** Sets the page table pointer. */
-//    void setPageTable(PageTable *pt_ptr);
+    Port *getDcachePort() { return &dcachePort; }
 
     /** Ticks the LSQ unit, which in this case only resets the number of
      * used cache ports.
@@ -241,13 +240,11 @@ class OzoneLWLSQ {
     class DcachePort : public Port
     {
       protected:
-        OzoneCPU *cpu;
-
         OzoneLWLSQ *lsq;
 
       public:
-        DcachePort(OzoneCPU *_cpu, OzoneLWLSQ *_lsq)
-            : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
+        DcachePort(OzoneLWLSQ *_lsq)
+            : lsq(_lsq)
         { }
 
       protected:
@@ -266,11 +263,8 @@ class OzoneLWLSQ {
         virtual void recvRetry();
     };
 
-    /** Pointer to the D-cache. */
-    DcachePort *dcachePort;
-
-    /** Pointer to the page table. */
-//    PageTable *pTable;
+    /** D-cache port. */
+    DcachePort dcachePort;
 
   public:
     struct SQEntry {
@@ -639,7 +633,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
     data_pkt->senderState = state;
 
     // if we have a cache, do cache access too
-    if (!dcachePort->sendTiming(data_pkt)) {
+    if (!dcachePort.sendTiming(data_pkt)) {
         // There's an older load that's already going to squash.
         if (isLoadBlocked && blockedLoadSeqNum < inst->seqNum)
             return NoFault;
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index a65a2a4d3..88e9c218f 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -131,8 +131,9 @@ OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt)
 
 template <class Impl>
 OzoneLWLSQ<Impl>::OzoneLWLSQ()
-    : switchedOut(false), loads(0), stores(0), storesToWB(0), stalled(false),
-      isStoreBlocked(false), isLoadBlocked(false), loadBlockedHandled(false)
+    : switchedOut(false), dcachePort(this), loads(0), stores(0),
+      storesToWB(0), stalled(false), isStoreBlocked(false),
+      isLoadBlocked(false), loadBlockedHandled(false)
 {
 }
 
@@ -175,15 +176,11 @@ void
 OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
 {
     cpu = cpu_ptr;
-    dcachePort = new DcachePort(cpu, this);
-
-    Port *mem_dport = mem->getPort("");
-    dcachePort->setPeer(mem_dport);
-    mem_dport->setPeer(dcachePort);
+    dcachePort.setName(this->name() + "-dport");
 
 #if USE_CHECKER
     if (cpu->checker) {
-        cpu->checker->setDcachePort(dcachePort);
+        cpu->checker->setDcachePort(&dcachePort);
     }
 #endif
 }
@@ -614,7 +611,7 @@ OzoneLWLSQ<Impl>::writebackStores()
             state->noWB = true;
         }
 
-        if (!dcachePort->sendTiming(data_pkt)) {
+        if (!dcachePort.sendTiming(data_pkt)) {
             // Need to handle becoming blocked on a store.
             isStoreBlocked = true;
             assert(retryPkt == NULL);
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py
index 8aff89203..88fb63c74 100644
--- a/src/python/m5/objects/OzoneCPU.py
+++ b/src/python/m5/objects/OzoneCPU.py
@@ -9,6 +9,9 @@ class DerivOzoneCPU(BaseCPU):
 
     checker = Param.BaseCPU("Checker CPU")
 
+    icache_port = Port("Instruction Port")
+    dcache_port = Port("Data Port")
+
     width = Param.Unsigned("Width")
     frontEndWidth = Param.Unsigned("Front end width")
     backEndWidth = Param.Unsigned("Back end width")