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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-15 13:31:52 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-03-08 10:11:36 +0000 |
| commit | 5a72d77fa5ff80c5d7d4d35791a84ce7ee46f0f0 (patch) | |
| tree | 4ac3426297570115d5c5aecb71500092ef825e7f | |
| parent | 72ecef7a759f10b4816ecf13a1289fc6d9443c92 (diff) | |
| download | gem5-5a72d77fa5ff80c5d7d4d35791a84ce7ee46f0f0.tar.xz | |
arch-arm: Enable Debug IFSC when faulting to aarch64 mode
Previous code was aborting simulation when a debug exception taken in
aarch64 mode was encountered. This because an invalid (0xff)
instruction fault status code was produced.
Change-Id: I289f93f672be70cfbdc404be536809835160bdaf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8363
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/arch/arm/faults.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index a1952d664..a048fa8b2 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -177,7 +177,7 @@ uint8_t ArmFault::aarch64FaultSources[] = { 0x0d, // PermissionL1 0x0e, // PermissionL2 0x0f, // PermissionL3 - 0xff, // DebugEvent (INVALID) + 0x22, // DebugEvent 0x10, // SynchronousExternalAbort 0x30, // TLBConflictAbort 0x18, // SynchPtyErrOnMemoryAccess |