diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
| commit | 607c2772915628c2c67c1c5bfdefaa33ae66a06e (patch) | |
| tree | f8f23fd4012f9a0053d65ac91792a7dc61d6baff | |
| parent | 71c982ff708cc3adc7c0eccf536fea34c20cc5f0 (diff) | |
| download | gem5-607c2772915628c2c67c1c5bfdefaa33ae66a06e.tar.xz | |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
145 files changed, 8892 insertions, 7913 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 3b8894174..0140edf9d 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.893221 # Nu sim_ticks 1893220881500 # Number of ticks simulated final_tick 1893220881500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 15759 # Simulator instruction rate (inst/s) -host_op_rate 15759 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 531367557 # Simulator tick rate (ticks/s) -host_mem_usage 390932 # Number of bytes of host memory used -host_seconds 3562.92 # Real time elapsed on the host +host_inst_rate 27932 # Simulator instruction rate (inst/s) +host_op_rate 27932 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 941819152 # Simulator tick rate (ticks/s) +host_mem_usage 393408 # Number of bytes of host memory used +host_seconds 2010.17 # Real time elapsed on the host sim_insts 56147815 # Number of instructions simulated sim_ops 56147815 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -389,7 +389,9 @@ system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction @@ -411,8 +413,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::MemRead 9320403 16.60% 86.95% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6373341 11.35% 98.31% # Class of committed instruction +system.cpu.op_class_0::MemRead 9175906 16.34% 86.70% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6235361 11.11% 97.80% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction system.cpu.op_class_0::IprAccess 951232 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 56147815 # Class of committed instruction diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 2752814bd..bdc20c8ec 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.907549 # Nu sim_ticks 1907549438500 # Number of ticks simulated final_tick 1907549438500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120882 # Simulator instruction rate (inst/s) -host_op_rate 120882 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4068519298 # Simulator tick rate (ticks/s) -host_mem_usage 339992 # Number of bytes of host memory used -host_seconds 468.86 # Real time elapsed on the host +host_inst_rate 238870 # Simulator instruction rate (inst/s) +host_op_rate 238870 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8039623402 # Simulator tick rate (ticks/s) +host_mem_usage 342472 # Number of bytes of host memory used +host_seconds 237.27 # Real time elapsed on the host sim_insts 56676315 # Number of instructions simulated sim_ops 56676315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -474,37 +474,41 @@ system.cpu0.iq.issued_per_cycle::min_value 0 # system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::total 113902133 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 168885 16.84% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 512937 51.15% 67.99% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 321005 32.01% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 168885 16.81% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 486832 48.47% 65.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 300564 29.92% 95.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 26620 2.65% 97.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 21571 2.15% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued @@ -515,7 +519,9 @@ system.cpu0.iq.FU_type_0::FloatAdd 25398 0.05% 68.79% # Ty system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued @@ -537,22 +543,24 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9844131 18.71% 87.50% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5797742 11.02% 98.52% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9721676 18.48% 87.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5686986 10.81% 98.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 122455 0.23% 98.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 110756 0.21% 98.52% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 778716 1.48% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::total 52616152 # Type of FU issued system.cpu0.iq.rate 0.440369 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1002827 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019059 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 219643662 # Number of integer instruction queue reads +system.cpu0.iq.fu_busy_cnt 1004472 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019091 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 219643746 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_writes 65164078 # Number of integer instruction queue writes system.cpu0.iq.int_inst_queue_wakeup_accesses 50897823 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 567855 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_reads 569416 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 274599 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 257683 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53309936 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 306506 # Number of floating point alu accesses +system.cpu0.iq.int_alu_accesses 53310020 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 308067 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 606515 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread0.squashedLoads 1936563 # Number of loads squashed @@ -631,7 +639,9 @@ system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Cl system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction @@ -653,8 +663,10 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8056819 16.24% 87.53% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5408346 10.90% 98.43% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7943636 16.02% 87.30% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5298998 10.68% 97.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 113183 0.23% 98.21% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 109348 0.22% 98.43% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 778715 1.57% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::total 49598051 # Class of committed instruction @@ -1083,37 +1095,41 @@ system.cpu1.iq.issued_per_cycle::min_value 0 # system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::total 16648116 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 33628 10.30% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 182347 55.85% 66.15% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 110540 33.85% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 33628 10.29% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 174409 53.35% 63.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 103464 31.65% 95.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 7989 2.44% 97.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 7397 2.26% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued @@ -1124,7 +1140,9 @@ system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.29% # Ty system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.29% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.29% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.29% # Type of FU issued system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.31% # Type of FU issued system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued @@ -1146,22 +1164,24 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2555661 22.28% 84.58% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1468866 12.80% 97.39% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2510604 21.88% 84.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1425191 12.42% 96.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 45057 0.39% 97.01% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 43675 0.38% 97.39% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 299742 2.61% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::total 11472464 # Type of FU issued system.cpu1.iq.rate 0.653939 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 326515 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028461 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 39721820 # Number of integer instruction queue reads +system.cpu1.iq.fu_busy_cnt 326887 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028493 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 39721827 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_writes 15008897 # Number of integer instruction queue writes system.cpu1.iq.int_inst_queue_wakeup_accesses 10951678 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 225266 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_reads 225631 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 107813 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 104885 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11674098 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 120130 # Number of floating point alu accesses +system.cpu1.iq.int_alu_accesses 11674105 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120495 # Number of floating point alu accesses system.cpu1.iew.lsq.thread0.forwLoads 118360 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread0.squashedLoads 553503 # Number of loads squashed @@ -1240,7 +1260,9 @@ system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.54% # Cl system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.54% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.54% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.54% # Class of committed instruction system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.56% # Class of committed instruction system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.56% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.56% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.56% # Class of committed instruction @@ -1262,8 +1284,10 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.56% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.56% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.56% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 2036847 19.50% 84.06% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1365632 13.07% 97.13% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1992105 19.07% 83.63% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1323963 12.67% 96.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 44742 0.43% 96.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 41669 0.40% 97.13% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 299742 2.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::total 10447204 # Class of committed instruction diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index b9078b8f1..5dd8fb675 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.865012 # Nu sim_ticks 1865011607500 # Number of ticks simulated final_tick 1865011607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117207 # Simulator instruction rate (inst/s) -host_op_rate 117207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4126745503 # Simulator tick rate (ticks/s) -host_mem_usage 335896 # Number of bytes of host memory used -host_seconds 451.93 # Real time elapsed on the host +host_inst_rate 237504 # Simulator instruction rate (inst/s) +host_op_rate 237504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8362303090 # Simulator tick rate (ticks/s) +host_mem_usage 338380 # Number of bytes of host memory used +host_seconds 223.03 # Real time elapsed on the host sim_insts 52969539 # Number of instructions simulated sim_ops 52969539 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -466,37 +466,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 123532763 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 207032 16.67% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 637905 51.36% 68.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 397118 31.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 207032 16.63% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 606591 48.74% 65.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 372500 29.93% 95.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 31949 2.57% 97.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 26498 2.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7276 0.01% 0.01% # Type of FU issued @@ -507,7 +511,9 @@ system.cpu.iq.FU_type_0::FloatAdd 38560 0.06% 67.76% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued @@ -529,22 +535,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 11677570 19.29% 87.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6886648 11.38% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 11521390 19.03% 86.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6745321 11.14% 97.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 156180 0.26% 98.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 141327 0.23% 98.43% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 60540114 # Type of FU issued system.cpu.iq.rate 0.467035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1242056 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020516 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 245211443 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 1244571 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020558 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 245211528 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 76534751 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 58316055 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 737234 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 739664 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 359442 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 336937 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 61379174 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 395720 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 61379259 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 398150 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 691177 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 2573780 # Number of loads squashed @@ -623,7 +631,9 @@ system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction @@ -645,8 +655,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9317120 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6383168 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9172524 16.33% 86.69% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6245101 11.12% 97.81% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 56159642 # Class of committed instruction diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 636a3faf7..c0e015b81 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.848927 # Nu sim_ticks 2848926718000 # Number of ticks simulated final_tick 2848926718000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113585 # Simulator instruction rate (inst/s) -host_op_rate 137549 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2529912934 # Simulator tick rate (ticks/s) -host_mem_usage 622248 # Number of bytes of host memory used -host_seconds 1126.10 # Real time elapsed on the host +host_inst_rate 263408 # Simulator instruction rate (inst/s) +host_op_rate 318982 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5866973599 # Simulator tick rate (ticks/s) +host_mem_usage 626336 # Number of bytes of host memory used +host_seconds 485.59 # Real time elapsed on the host sim_insts 127907365 # Number of instructions simulated sim_ops 154893549 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -595,7 +595,9 @@ system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Cl system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatMisc 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction @@ -617,8 +619,10 @@ system.cpu0.op_class_0::SimdFloatMisc 8071 0.01% 66.54% # Cl system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::MemRead 16807812 17.52% 84.07% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 15281291 15.93% 100.00% # Class of committed instruction +system.cpu0.op_class_0::MemRead 16805556 17.52% 84.07% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15273907 15.92% 99.99% # Class of committed instruction +system.cpu0.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction +system.cpu0.op_class_0::FloatMemWrite 7384 0.01% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::total 95912008 # Class of committed instruction @@ -1547,7 +1551,9 @@ system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Cl system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::FloatCvt 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::FloatMult 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatMultAcc 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::FloatDiv 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatMisc 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::SimdAdd 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.93% # Class of committed instruction @@ -1569,8 +1575,10 @@ system.cpu1.op_class_0::SimdFloatMisc 3353 0.01% 68.93% # Cl system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::MemRead 11147247 18.90% 87.83% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 7177177 12.17% 100.00% # Class of committed instruction +system.cpu1.op_class_0::MemRead 11146731 18.90% 87.83% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 7175909 12.17% 100.00% # Class of committed instruction +system.cpu1.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction +system.cpu1.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::total 58981541 # Class of committed instruction diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index f3f991d90..9c3703a65 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.854926 # Nu sim_ticks 2854925996500 # Number of ticks simulated final_tick 2854925996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115917 # Simulator instruction rate (inst/s) -host_op_rate 140154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2954234125 # Simulator tick rate (ticks/s) -host_mem_usage 584856 # Number of bytes of host memory used -host_seconds 966.38 # Real time elapsed on the host +host_inst_rate 259837 # Simulator instruction rate (inst/s) +host_op_rate 314167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6622138542 # Simulator tick rate (ticks/s) +host_mem_usage 588096 # Number of bytes of host memory used +host_seconds 431.12 # Real time elapsed on the host sim_insts 112020669 # Number of instructions simulated sim_ops 135443008 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -563,7 +563,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.13% # Class of committed instruction @@ -585,8 +587,10 @@ system.cpu.op_class_0::SimdFloatMisc 8481 0.01% 67.13% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::MemRead 24250620 17.90% 85.04% # Class of committed instruction -system.cpu.op_class_0::MemWrite 20263468 14.96% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 24247912 17.90% 85.04% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20254880 14.95% 99.99% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 8588 0.01% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 135443008 # Class of committed instruction diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index a281a2cd6..71091171c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.826595 # Nu sim_ticks 2826594924500 # Number of ticks simulated final_tick 2826594924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79087 # Simulator instruction rate (inst/s) -host_op_rate 95944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1861516367 # Simulator tick rate (ticks/s) -host_mem_usage 623016 # Number of bytes of host memory used -host_seconds 1518.44 # Real time elapsed on the host +host_inst_rate 172097 # Simulator instruction rate (inst/s) +host_op_rate 208779 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4050742494 # Simulator tick rate (ticks/s) +host_mem_usage 626976 # Number of bytes of host memory used +host_seconds 697.80 # Real time elapsed on the host sim_insts 120088860 # Number of instructions simulated sim_ops 145685275 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -720,7 +720,9 @@ system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.95% # at system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.95% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.95% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 43.95% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 43.95% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.95% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.95% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.95% # attempts to use FU when none available @@ -742,8 +744,10 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.95% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.95% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.95% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5628152 22.87% 66.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8167261 33.18% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5625612 22.86% 66.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8160344 33.16% 99.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 2838 0.01% 99.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 7018 0.03% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued @@ -754,7 +758,9 @@ system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.65% # Ty system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.65% # Type of FU issued @@ -776,22 +782,24 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 7864 0.01% 67.65% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 24369410 18.32% 85.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 18647698 14.02% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 24366318 18.32% 85.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 18639513 14.02% 99.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 3092 0.00% 99.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 8185 0.01% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::total 132985122 # Type of FU issued system.cpu0.iq.rate 0.649427 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 24611630 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.185071 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 491314323 # Number of integer instruction queue reads +system.cpu0.iq.fu_busy_cnt 24612029 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.185074 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 491314637 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_writes 147160457 # Number of integer instruction queue writes system.cpu0.iq.int_inst_queue_wakeup_accesses 129454820 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32339 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_reads 32424 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 11262 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 157573424 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21055 # Number of floating point alu accesses +system.cpu0.iq.int_alu_accesses 157573738 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21140 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 367821 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread0.squashedLoads 1916447 # Number of loads squashed @@ -814,19 +822,19 @@ system.cpu0.iew.iewDispNonSpecInsts 876464 # Nu system.cpu0.iew.iewIQFullEvents 27795 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 194810 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 19267 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 261439 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 261441 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 400306 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 661745 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 131953488 # Number of executed instructions +system.cpu0.iew.branchMispredicts 661747 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 131953487 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 23926851 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 965273 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecSquashedInsts 965274 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 152902 # number of nop insts executed system.cpu0.iew.exec_refs 42414312 # number of memory reference insts executed system.cpu0.iew.exec_branches 25613561 # Number of branches executed system.cpu0.iew.exec_stores 18487461 # Number of stores executed system.cpu0.iew.exec_rate 0.644389 # Inst execution rate -system.cpu0.iew.wb_sent 131398393 # cumulative count of insts sent to commit +system.cpu0.iew.wb_sent 131398392 # cumulative count of insts sent to commit system.cpu0.iew.wb_count 129464537 # cumulative count of insts written-back system.cpu0.iew.wb_producers 66052971 # num instructions producing a value system.cpu0.iew.wb_consumers 106772912 # num instructions consuming a value @@ -870,7 +878,9 @@ system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Cl system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction @@ -892,8 +902,10 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 7863 0.01% 67.58% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 22690736 18.00% 85.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18186875 14.43% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 22688480 18.00% 85.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18179427 14.42% 99.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 7448 0.01% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::total 126078442 # Class of committed instruction @@ -911,11 +923,11 @@ system.cpu0.ipc 0.507895 # IP system.cpu0.ipc_total 0.507895 # IPC: Total IPC of All Threads system.cpu0.int_regfile_reads 142940096 # number of integer regfile reads system.cpu0.int_regfile_writes 81795281 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8203 # number of floating regfile reads +system.cpu0.fp_regfile_reads 8197 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 465685863 # number of cc regfile reads +system.cpu0.cc_regfile_reads 465685860 # number of cc regfile reads system.cpu0.cc_regfile_writes 49834738 # number of cc regfile writes -system.cpu0.misc_regfile_reads 394201906 # number of misc regfile reads +system.cpu0.misc_regfile_reads 394201898 # number of misc regfile reads system.cpu0.misc_regfile_writes 1226279 # number of misc regfile writes system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 711042 # number of replacements @@ -1966,7 +1978,9 @@ system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.52% # at system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.52% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.52% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 29.52% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 29.52% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.52% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.52% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.52% # attempts to use FU when none available @@ -1988,8 +2002,10 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.52% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.52% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.52% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1602534 33.64% 63.16% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1754875 36.84% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1601939 33.63% 63.15% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1753523 36.81% 99.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 663 0.01% 99.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 1366 0.03% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued @@ -2000,7 +2016,9 @@ system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.85% # Ty system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.85% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.85% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 61.85% # Type of FU issued system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 61.85% # Type of FU issued system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.85% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.85% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.85% # Type of FU issued @@ -2022,22 +2040,24 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 3265 0.02% 61.86% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4356029 20.74% 82.61% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3652086 17.39% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4355305 20.74% 82.60% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3650681 17.38% 99.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 724 0.00% 99.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 1405 0.01% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::total 20999121 # Type of FU issued system.cpu1.iq.rate 0.601763 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4763564 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226846 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 80779382 # Number of integer instruction queue reads +system.cpu1.iq.fu_busy_cnt 4763646 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226850 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 80779454 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_writes 23748142 # Number of integer instruction queue writes system.cpu1.iq.int_inst_queue_wakeup_accesses 20541259 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6284 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_reads 6294 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 2076 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1790 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 25758471 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4148 # Number of floating point alu accesses +system.cpu1.iq.int_alu_accesses 25758543 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4158 # Number of floating point alu accesses system.cpu1.iew.lsq.thread0.forwLoads 87109 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread0.squashedLoads 405898 # Number of loads squashed @@ -2116,7 +2136,9 @@ system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Cl system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction @@ -2138,8 +2160,10 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 3265 0.02% 61.96% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.96% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.96% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 3994199 20.21% 82.17% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3522534 17.83% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 3993683 20.21% 82.17% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3521266 17.82% 99.99% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 99.99% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.01% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::total 19761740 # Class of committed instruction diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 85eda68ae..31402aa9f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.829113 # Nu sim_ticks 2829112944500 # Number of ticks simulated final_tick 2829112944500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77107 # Simulator instruction rate (inst/s) -host_op_rate 93526 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1927521729 # Simulator tick rate (ticks/s) -host_mem_usage 584852 # Number of bytes of host memory used -host_seconds 1467.75 # Real time elapsed on the host +host_inst_rate 178657 # Simulator instruction rate (inst/s) +host_op_rate 216701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4466095842 # Simulator tick rate (ticks/s) +host_mem_usage 588180 # Number of bytes of host memory used +host_seconds 633.46 # Real time elapsed on the host sim_insts 113173049 # Number of instructions simulated sim_ops 137272583 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -690,7 +690,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available @@ -712,8 +714,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5621614 25.12% 57.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9424915 42.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5619374 25.11% 57.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9416245 42.07% 99.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 2403 0.01% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 8750 0.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued @@ -724,7 +728,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued @@ -746,22 +752,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8550 0.01% 67.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26140422 18.27% 85.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20943854 14.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26137714 18.26% 85.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20934166 14.63% 99.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 2708 0.00% 99.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 9688 0.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 143117357 # Type of FU issued system.cpu.iq.rate 0.533619 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22382070 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156390 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 570225766 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 22382313 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 570225949 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 153558624 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 140063898 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35895 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 35955 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11500 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165473596 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23494 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 165473779 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23554 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 325086 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1430934 # Number of loads squashed @@ -840,7 +848,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction @@ -862,8 +872,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 8549 0.01% 66.88% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24919214 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20597478 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24916506 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20588698 14.98% 99.99% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 8780 0.01% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 137427488 # Class of committed instruction diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 202c4ef0d..3b6b744bc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.554910 # Nu sim_ticks 47554910274000 # Number of ticks simulated final_tick 47554910274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172972 # Simulator instruction rate (inst/s) -host_op_rate 203472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9377554592 # Simulator tick rate (ticks/s) -host_mem_usage 769556 # Number of bytes of host memory used -host_seconds 5071.14 # Real time elapsed on the host +host_inst_rate 271941 # Simulator instruction rate (inst/s) +host_op_rate 319891 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14743065549 # Simulator tick rate (ticks/s) +host_mem_usage 772792 # Number of bytes of host memory used +host_seconds 3225.58 # Real time elapsed on the host sim_insts 877166784 # Number of instructions simulated sim_ops 1031833041 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -625,34 +625,38 @@ system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Cl system.cpu0.op_class_0::IntAlu 368287155 69.25% 69.25% # Class of committed instruction system.cpu0.op_class_0::IntMult 1118982 0.21% 69.46% # Class of committed instruction system.cpu0.op_class_0::IntDiv 57276 0.01% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 8 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 13 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 21 0.00% 69.47% # Class of committed instruction system.cpu0.op_class_0::FloatMult 0 0.00% 69.47% # Class of committed instruction +system.cpu0.op_class_0::FloatMultAcc 0 0.00% 69.47% # Class of committed instruction system.cpu0.op_class_0::FloatDiv 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 8 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 13 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 21 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.47% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 85306 0.02% 69.48% # Class of committed instruction +system.cpu0.op_class_0::FloatMisc 85306 0.02% 69.48% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 69.48% # Class of committed instruction system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.op_class_0::MemRead 84402084 15.87% 85.35% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 77900254 14.65% 100.00% # Class of committed instruction +system.cpu0.op_class_0::MemRead 84333617 15.86% 85.34% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 77481840 14.57% 99.91% # Class of committed instruction +system.cpu0.op_class_0::FloatMemRead 68467 0.01% 99.92% # Class of committed instruction +system.cpu0.op_class_0::FloatMemWrite 418414 0.08% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::total 531851100 # Class of committed instruction @@ -1639,30 +1643,34 @@ system.cpu1.op_class_0::FloatAdd 0 0.00% 69.45% # Cl system.cpu1.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction system.cpu1.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction system.cpu1.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.45% # Class of committed instruction system.cpu1.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 26657 0.01% 69.46% # Class of committed instruction +system.cpu1.op_class_0::FloatMisc 26657 0.01% 69.46% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.46% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 69.46% # Class of committed instruction system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu1.op_class_0::MemRead 80579122 16.12% 85.58% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 72116197 14.42% 100.00% # Class of committed instruction +system.cpu1.op_class_0::MemRead 80537576 16.11% 85.57% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 71850356 14.37% 99.94% # Class of committed instruction +system.cpu1.op_class_0::FloatMemRead 41546 0.01% 99.95% # Class of committed instruction +system.cpu1.op_class_0::FloatMemWrite 265841 0.05% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::total 499981941 # Class of committed instruction diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 1319d3c2e..5d6718d90 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.688775 # Nu sim_ticks 51688774990000 # Number of ticks simulated final_tick 51688774990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210815 # Simulator instruction rate (inst/s) -host_op_rate 247704 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11507504763 # Simulator tick rate (ticks/s) -host_mem_usage 684036 # Number of bytes of host memory used -host_seconds 4491.74 # Real time elapsed on the host +host_inst_rate 278192 # Simulator instruction rate (inst/s) +host_op_rate 326870 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15185295340 # Simulator tick rate (ticks/s) +host_mem_usage 686764 # Number of bytes of host memory used +host_seconds 3403.87 # Real time elapsed on the host sim_insts 946928269 # Number of instructions simulated sim_ops 1112623169 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -588,11 +588,13 @@ system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Cl system.cpu.op_class_0::IntAlu 771151081 69.31% 69.31% # Class of committed instruction system.cpu.op_class_0::IntMult 2302642 0.21% 69.52% # Class of committed instruction system.cpu.op_class_0::IntDiv 99189 0.01% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 8 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 13 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 21 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 108989 0.01% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction @@ -605,17 +607,19 @@ system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.53% # Cl system.cpu.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 108989 0.01% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::MemRead 177312606 15.94% 85.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 161648619 14.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 177200146 15.93% 85.46% # Class of committed instruction +system.cpu.op_class_0::MemWrite 160983743 14.47% 99.93% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 112460 0.01% 99.94% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 664876 0.06% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1112623169 # Class of committed instruction diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 79f2acec9..e5ad0fb86 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.384943 # Number of seconds simulated -sim_ticks 47384942719000 # Number of ticks simulated -final_tick 47384942719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.384924 # Number of seconds simulated +sim_ticks 47384923997000 # Number of ticks simulated +final_tick 47384923997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146603 # Simulator instruction rate (inst/s) -host_op_rate 172405 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7419029838 # Simulator tick rate (ticks/s) -host_mem_usage 776468 # Number of bytes of host memory used -host_seconds 6386.95 # Real time elapsed on the host -sim_insts 936348150 # Number of instructions simulated -sim_ops 1101141201 # Number of ops (including micro ops) simulated +host_inst_rate 222565 # Simulator instruction rate (inst/s) +host_op_rate 253955 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9938840366 # Simulator tick rate (ticks/s) +host_mem_usage 775220 # Number of bytes of host memory used +host_seconds 4767.65 # Real time elapsed on the host +sim_insts 1061113479 # Number of instructions simulated +sim_ops 1210768532 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 225984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 211072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4210272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 17875336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 22288384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 132032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 98944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3431264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10538960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 15414592 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory -system.physmem.bytes_read::total 74864536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4210272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3431264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7641536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 90448704 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 111296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 112064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3744224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13424584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13993600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 40000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 28480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2827552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 6560336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 5891392 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory +system.physmem.bytes_read::total 47171096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3744224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2827552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6571776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65473344 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 90469288 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3531 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3298 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 81738 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 279315 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 348256 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 53657 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 164684 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 240853 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1185780 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1413261 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 65493928 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 74456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 209772 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 218650 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 102518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 92053 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory +system.physmem.num_reads::total 753070 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1023021 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1415835 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 88853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 377237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 470368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2786 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 72413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 325306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1579922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 88853 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 72413 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 161265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1908807 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1025595 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 79017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 283309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 295318 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 138448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 124331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 995487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 79017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59672 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 138689 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1381734 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1909241 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1908807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 88853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 377671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 470368 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 72413 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 325306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3489164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1185780 # Number of read requests accepted -system.physmem.writeReqs 1415835 # Number of write requests accepted -system.physmem.readBursts 1185780 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1415835 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 75867200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue -system.physmem.bytesWritten 90467840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 74864536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 90469288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1382168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1381734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 79017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 283743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 295318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 138448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 124331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2377655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 753070 # Number of read requests accepted +system.physmem.writeReqs 1025595 # Number of write requests accepted +system.physmem.readBursts 753070 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1025595 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 48174848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue +system.physmem.bytesWritten 65493376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 47171096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65493928 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74918 # Per bank write bursts -system.physmem.perBankRdBursts::1 82946 # Per bank write bursts -system.physmem.perBankRdBursts::2 75146 # Per bank write bursts -system.physmem.perBankRdBursts::3 74319 # Per bank write bursts -system.physmem.perBankRdBursts::4 73960 # Per bank write bursts -system.physmem.perBankRdBursts::5 83356 # Per bank write bursts -system.physmem.perBankRdBursts::6 71088 # Per bank write bursts -system.physmem.perBankRdBursts::7 75076 # Per bank write bursts -system.physmem.perBankRdBursts::8 69225 # Per bank write bursts -system.physmem.perBankRdBursts::9 91582 # Per bank write bursts -system.physmem.perBankRdBursts::10 63014 # Per bank write bursts -system.physmem.perBankRdBursts::11 68676 # Per bank write bursts -system.physmem.perBankRdBursts::12 68042 # Per bank write bursts -system.physmem.perBankRdBursts::13 71091 # Per bank write bursts -system.physmem.perBankRdBursts::14 73017 # Per bank write bursts -system.physmem.perBankRdBursts::15 69969 # Per bank write bursts -system.physmem.perBankWrBursts::0 88621 # Per bank write bursts -system.physmem.perBankWrBursts::1 92960 # Per bank write bursts -system.physmem.perBankWrBursts::2 88280 # Per bank write bursts -system.physmem.perBankWrBursts::3 90026 # Per bank write bursts -system.physmem.perBankWrBursts::4 89701 # Per bank write bursts -system.physmem.perBankWrBursts::5 97248 # Per bank write bursts -system.physmem.perBankWrBursts::6 87218 # Per bank write bursts -system.physmem.perBankWrBursts::7 89230 # Per bank write bursts -system.physmem.perBankWrBursts::8 86326 # Per bank write bursts -system.physmem.perBankWrBursts::9 88636 # Per bank write bursts -system.physmem.perBankWrBursts::10 82100 # Per bank write bursts -system.physmem.perBankWrBursts::11 87622 # Per bank write bursts -system.physmem.perBankWrBursts::12 86001 # Per bank write bursts -system.physmem.perBankWrBursts::13 87485 # Per bank write bursts -system.physmem.perBankWrBursts::14 85741 # Per bank write bursts -system.physmem.perBankWrBursts::15 86365 # Per bank write bursts +system.physmem.perBankRdBursts::0 46580 # Per bank write bursts +system.physmem.perBankRdBursts::1 53938 # Per bank write bursts +system.physmem.perBankRdBursts::2 49260 # Per bank write bursts +system.physmem.perBankRdBursts::3 49621 # Per bank write bursts +system.physmem.perBankRdBursts::4 42595 # Per bank write bursts +system.physmem.perBankRdBursts::5 51807 # Per bank write bursts +system.physmem.perBankRdBursts::6 43920 # Per bank write bursts +system.physmem.perBankRdBursts::7 48776 # Per bank write bursts +system.physmem.perBankRdBursts::8 40673 # Per bank write bursts +system.physmem.perBankRdBursts::9 65073 # Per bank write bursts +system.physmem.perBankRdBursts::10 36606 # Per bank write bursts +system.physmem.perBankRdBursts::11 43439 # Per bank write bursts +system.physmem.perBankRdBursts::12 41245 # Per bank write bursts +system.physmem.perBankRdBursts::13 45785 # Per bank write bursts +system.physmem.perBankRdBursts::14 46575 # Per bank write bursts +system.physmem.perBankRdBursts::15 46839 # Per bank write bursts +system.physmem.perBankWrBursts::0 64495 # Per bank write bursts +system.physmem.perBankWrBursts::1 70494 # Per bank write bursts +system.physmem.perBankWrBursts::2 68186 # Per bank write bursts +system.physmem.perBankWrBursts::3 67192 # Per bank write bursts +system.physmem.perBankWrBursts::4 60923 # Per bank write bursts +system.physmem.perBankWrBursts::5 66733 # Per bank write bursts +system.physmem.perBankWrBursts::6 61182 # Per bank write bursts +system.physmem.perBankWrBursts::7 63809 # Per bank write bursts +system.physmem.perBankWrBursts::8 61319 # Per bank write bursts +system.physmem.perBankWrBursts::9 65628 # Per bank write bursts +system.physmem.perBankWrBursts::10 58470 # Per bank write bursts +system.physmem.perBankWrBursts::11 62975 # Per bank write bursts +system.physmem.perBankWrBursts::12 59380 # Per bank write bursts +system.physmem.perBankWrBursts::13 62220 # Per bank write bursts +system.physmem.perBankWrBursts::14 64833 # Per bank write bursts +system.physmem.perBankWrBursts::15 65495 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51113 # Number of times write queue was full causing retry -system.physmem.totGap 47384941205500 # Total gap between requests +system.physmem.numWrRetry 51084 # Number of times write queue was full causing retry +system.physmem.totGap 47384922418500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1164422 # Read request sizes (log2) +system.physmem.readPktSize::6 731712 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1413261 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 492558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 272193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 123866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 49827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 41505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 35214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 31591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 5210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 3059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1023021 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 370845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 159212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 67904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 40989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 21454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 19383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 16144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 215 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,147 +189,148 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 37414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 43560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 48703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 53588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 65839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 73927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 78606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 82389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 81499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 83906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 89741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 97285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 86545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 80600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 3105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 5197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 25051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 120445 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1083045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 153.580618 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.695829 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 199.684011 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 694535 64.13% 64.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 223527 20.64% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 61545 5.68% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27125 2.50% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21919 2.02% 94.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12312 1.14% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8465 0.78% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6818 0.63% 97.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 26799 2.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1083045 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 67614 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.532168 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 68.484066 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 67610 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 18155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 21368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 29807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 34041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 37200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 39344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 42468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 45306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 48762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 49512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 52922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 55311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 53100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 53471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 56934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 54202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 50890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 25036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 120369 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 764267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 148.727500 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 100.859518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 194.434520 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 493267 64.54% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 163474 21.39% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 41666 5.45% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17289 2.26% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12509 1.64% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7716 1.01% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5337 0.70% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4250 0.56% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18759 2.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 764267 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 44107 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.065908 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 84.736057 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 44102 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 67614 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 67614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.906321 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.453992 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 533.973047 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-2047 67611 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 44107 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 44107 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.201170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.952947 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 661.116222 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-2047 44104 99.99% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::12288-14335 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::43008-45055 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::129024-131071 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 67614 # Writes before turning the bus around for reads -system.physmem.totQLat 72498378118 # Total ticks spent queuing -system.physmem.totMemAccLat 94725096868 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5927125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 61158.13 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 44107 # Writes before turning the bus around for reads +system.physmem.totQLat 41283708010 # Total ticks spent queuing +system.physmem.totMemAccLat 55397433010 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3763660000 # Total ticks spent in databus transfers +system.physmem.avgQLat 54845.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 79908.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.91 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 73595.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.38 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing -system.physmem.readRowHits 894792 # Number of row buffer hits during reads -system.physmem.writeRowHits 621147 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.94 # Row buffer hit rate for writes -system.physmem.avgGap 18213663.90 # Average gap between requests -system.physmem.pageHitRate 58.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4041154320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2147920665 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4361176260 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3775542480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33222521280.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 42262106220 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1577144160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 67404809070 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 44351104800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11290594038405 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11493753562350 # Total energy per rank (pJ) -system.physmem_0.averagePower 242.561305 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47288119152834 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 2641670410 # Time in different power states -system.physmem_0.memoryStateTime::REF 14105156000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 47024804557250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 115497548988 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80076687506 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 147817098846 # Time in different power states -system.physmem_1.actEnergy 3691794120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1962235110 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4102758240 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3603240720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 31839581280.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 42875044890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1564584000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 59886050220 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 43118785440 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11295073117425 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11487733544595 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.434260 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47286801320918 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2657158504 # Time in different power states -system.physmem_1.memoryStateTime::REF 13520630000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 47043190241000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 112288389331 # Time in different power states -system.physmem_1.memoryStateTime::ACT 81956603828 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 131329696337 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing +system.physmem.readRowHits 561323 # Number of row buffer hits during reads +system.physmem.writeRowHits 450469 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 44.02 # Row buffer hit rate for writes +system.physmem.avgGap 26640723.47 # Average gap between requests +system.physmem.pageHitRate 56.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2854700520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1517297925 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2759588580 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2730133080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29211995280.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 33494587950 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1472320320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 56725165950 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 41153148000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11302922668065 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11474856149160 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.162595 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47307603847909 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 2604858642 # Time in different power states +system.physmem_0.memoryStateTime::REF 12408932000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 47076037433500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 107169572536 # Time in different power states +system.physmem_0.memoryStateTime::ACT 62306306199 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 124396894123 # Time in different power states +system.physmem_1.actEnergy 2602215840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1383095340 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2614917900 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2611670400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 28356416400.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 34195829880 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1463733600 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 50772105900 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 40848981120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11305996104720 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11470859465250 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.078250 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47306089548027 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2606555105 # Time in different power states +system.physmem_1.memoryStateTime::REF 12048152000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 47088369465500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 106377666151 # Time in different power states +system.physmem_1.memoryStateTime::ACT 64179741868 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 111342416376 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -356,30 +357,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 139745078 # Number of BP lookups -system.cpu0.branchPred.condPredicted 92256746 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6767345 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 98774130 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 61692324 # Number of BTB hits +system.cpu0.branchPred.lookups 171085788 # Number of BP lookups +system.cpu0.branchPred.condPredicted 118750961 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6834189 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 131203024 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 82797286 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 62.457978 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 19130272 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 187780 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4236971 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2716946 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1520025 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 386103 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 63.106233 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 18455974 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 190741 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4318211 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2658051 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1660160 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 412902 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -409,87 +410,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 642249 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 642249 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14371 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 105891 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 311173 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 331076 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2394.451727 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14284.464178 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 328283 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 2041 0.62% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 492 0.15% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 140 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 49 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 15 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 532616 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 532616 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9645 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 81431 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 247073 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 285543 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2264.919819 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12542.152959 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 283669 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1336 0.47% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 422 0.15% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 71 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 12 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 331076 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 352054 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 21918.096372 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18874.221671 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 17893.290078 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 347548 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2975 0.85% 99.57% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 632 0.18% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 594 0.17% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 153 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 118 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 25 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 352054 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 539733877528 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.599244 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.552867 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 538149503028 99.71% 99.71% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 904434000 0.17% 99.87% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 320975500 0.06% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 139201000 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 110066000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 60836000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 22060500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 25840500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 959500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 539733877528 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 105891 88.05% 88.05% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 14371 11.95% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 120262 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 642249 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 285543 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 266524 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21513.586019 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18398.741629 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 18436.018606 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 263851 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1863 0.70% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 357 0.13% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 245 0.09% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 96 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 28 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 12 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 57 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::720896-786431 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 266524 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 526829631640 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.594347 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.546107 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 525653507140 99.78% 99.78% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 581220000 0.11% 99.89% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 279235500 0.05% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 118625000 0.02% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 95795000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 61233500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 16684500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 22309000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 986000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 36000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 526829631640 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 81432 89.41% 89.41% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9645 10.59% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 91077 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 532616 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 642249 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 120262 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 532616 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 91077 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 120262 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 762511 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 91077 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 623693 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 102850435 # DTB read hits -system.cpu0.dtb.read_misses 467880 # DTB read misses -system.cpu0.dtb.write_hits 83320332 # DTB write hits -system.cpu0.dtb.write_misses 174369 # DTB write misses -system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 121664189 # DTB read hits +system.cpu0.dtb.read_misses 378617 # DTB read misses +system.cpu0.dtb.write_hits 79494049 # DTB write hits +system.cpu0.dtb.write_misses 153999 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 42516 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 599 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7036 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36225 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 277 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 5846 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 38961 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 103318315 # DTB read accesses -system.cpu0.dtb.write_accesses 83494701 # DTB write accesses +system.cpu0.dtb.perms_faults 36132 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 122042806 # DTB read accesses +system.cpu0.dtb.write_accesses 79648048 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 186170767 # DTB hits -system.cpu0.dtb.misses 642249 # DTB misses -system.cpu0.dtb.accesses 186813016 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 201158238 # DTB hits +system.cpu0.dtb.misses 532616 # DTB misses +system.cpu0.dtb.accesses 201690854 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -519,1177 +522,1186 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 84160 # Table walker walks requested -system.cpu0.itb.walker.walksLong 84160 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1044 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58792 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10193 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 73967 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1726.006192 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 15527.215020 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 73402 99.24% 99.24% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 457 0.62% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 56 0.08% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 7 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-393215 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::589824-655359 22 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 73967 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 70029 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 27234.188693 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23423.171681 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 26401.977199 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 67612 96.55% 96.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1634 2.33% 98.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 479 0.68% 99.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 184 0.26% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 27 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 16 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 21 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 84620 # Table walker walks requested +system.cpu0.itb.walker.walksLong 84620 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1064 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60290 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9899 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 74721 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1224.749401 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 11693.335691 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-65535 74465 99.66% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-131071 211 0.28% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-196607 17 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-327679 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::589824-655359 13 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 74721 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 71253 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25715.211991 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 22899.199736 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 22689.495972 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 69781 97.93% 97.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 978 1.37% 99.31% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 312 0.44% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 90 0.13% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 29 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 23 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 70029 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 423766533036 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.875739 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.330248 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 52705402108 12.44% 12.44% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 371016436928 87.55% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 42131000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1939000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 624000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 423766533036 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58792 98.26% 98.26% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1044 1.74% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 59836 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 71253 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 385068972872 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.863923 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.343128 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 52431106232 13.62% 13.62% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 332607446140 86.38% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 28719500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1617500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 83500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 385068972872 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 60290 98.27% 98.27% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1064 1.73% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 61354 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84160 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84160 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84620 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84620 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59836 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59836 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 143996 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 220066677 # ITB inst hits -system.cpu0.itb.inst_misses 84160 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61354 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61354 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 145974 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 247137553 # ITB inst hits +system.cpu0.itb.inst_misses 84620 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 30584 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26024 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 203568 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 210277 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 220150837 # ITB inst accesses -system.cpu0.itb.hits 220066677 # DTB hits -system.cpu0.itb.misses 84160 # DTB misses -system.cpu0.itb.accesses 220150837 # DTB accesses -system.cpu0.numPwrStateTransitions 10070 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 5035 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 9333517887.918768 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 154504325024.809692 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3827 76.01% 76.01% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 1181 23.46% 99.46% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.60% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.68% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.74% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 13 0.26% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 247222173 # ITB inst accesses +system.cpu0.itb.hits 247137553 # DTB hits +system.cpu0.itb.misses 84620 # DTB misses +system.cpu0.itb.accesses 247222173 # DTB accesses +system.cpu0.numPwrStateTransitions 10024 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 5012 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 9377758605.326616 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 105865716307.531311 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3741 74.64% 74.64% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1240 24.74% 99.38% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.40% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 4 0.08% 99.48% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.50% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.52% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.54% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 3 0.06% 99.60% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.64% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 18 0.36% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 6914082505000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 5035 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 390680153329 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46994262565671 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 781361530 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 1988782107984 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 5012 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 383597867103 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 47001326129897 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 767196996 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 89977379 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 618690334 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 139745078 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 83539542 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 647313928 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14578052 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1993554 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 302966 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 5990682 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 771527 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 852599 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 219863904 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1701332 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 27447 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 754491661 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.959990 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.215112 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 91423789 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 677610005 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 171085788 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 103911311 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 634233277 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14647700 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1877525 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 301361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 5874017 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 723644 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 823593 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 246927402 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1755267 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 27806 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 742581056 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.048226 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.216568 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 407421945 54.00% 54.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 135112889 17.91% 71.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 46679176 6.19% 78.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 165277651 21.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 362128339 48.77% 48.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 152866679 20.59% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 57232327 7.71% 77.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 170353711 22.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 754491661 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.178848 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.791811 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 107863691 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 373653702 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 228590583 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39162463 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5221222 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 20030707 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2107727 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 640747867 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23352656 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5221222 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 144093047 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 59069591 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 244366962 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 230957488 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 70783351 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 623359263 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6158447 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 11021555 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 440656 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 940490 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 33921586 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11494 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 594689945 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 962815337 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 736259751 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 682623 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 536299590 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 58390349 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16178274 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14135285 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78489785 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 102915286 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 86617273 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9593817 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8133429 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 600294247 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16347683 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 605471525 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2720884 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54918264 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 35662191 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 285806 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 754491661 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.802489 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.061507 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 742581056 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.223001 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.883228 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 106308771 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 322958086 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 273818410 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 34299444 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5196345 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 25584090 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2168541 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 698124632 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23697866 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5196345 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 140217201 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 48265126 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 214765524 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 273791275 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 60345585 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 681004210 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6177353 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 9309706 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 255993 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 440694 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 28265124 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11577 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 651054888 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1024843126 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 780850511 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 751131 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 593650334 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 57404539 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 14068671 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 12084501 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 69307711 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 122420852 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 82711928 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 8893855 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 7669271 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 660071199 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 14190254 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 662533207 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2711266 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 53711593 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 34745859 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 272694 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 742581056 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.892203 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.090645 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 423297632 56.10% 56.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 139867580 18.54% 74.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 116427415 15.43% 90.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 66852551 8.86% 98.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8040953 1.07% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5530 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 387058469 52.12% 52.12% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 139937745 18.84% 70.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 131660547 17.73% 88.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76428143 10.29% 98.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7490821 1.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5331 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 754491661 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 742581056 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62202700 45.10% 45.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 65869 0.05% 45.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 12866 0.01% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 27 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 36951420 26.79% 71.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 38701650 28.06% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 66589128 48.32% 48.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 76488 0.06% 48.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 21054 0.02% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 7 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 48.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 34108431 24.75% 73.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 36653931 26.60% 99.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 35680 0.03% 99.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 336881 0.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 413123878 68.23% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1535668 0.25% 68.49% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 80204 0.01% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 6 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 45354 0.01% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 106103331 17.52% 86.03% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 84583031 13.97% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 19 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 455471856 68.75% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1439073 0.22% 68.96% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 77169 0.01% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 26 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 52155 0.01% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 4 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 124717383 18.82% 87.81% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 80374226 12.13% 99.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 54363 0.01% 99.95% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 346932 0.05% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 605471525 # Type of FU issued -system.cpu0.iq.rate 0.774893 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 137934532 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227813 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2104985611 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 671273361 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 587796479 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1104514 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 436534 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 408765 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 742719141 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 686865 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2818576 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 662533207 # Type of FU issued +system.cpu0.iq.rate 0.863576 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 137821600 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.208022 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2206895899 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 727628917 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 645910972 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1284434 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 480253 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 448459 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 799528739 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 826049 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2613047 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12827708 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17934 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 150945 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5597965 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12294694 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 15978 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 137291 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5350030 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2832815 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4794177 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2543221 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4059606 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5221222 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8523162 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2018525 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 616773219 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5196345 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6516939 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1752683 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 674395512 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 102915286 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 86617273 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13889545 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 69101 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1866975 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 150945 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1955799 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3092868 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5048667 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 597424685 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 102845914 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7413191 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 122420852 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 82711928 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 11855960 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 50620 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1645630 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 137291 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 1918568 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3145797 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5064365 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 654555035 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 121653240 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7451061 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 131289 # number of nop insts executed -system.cpu0.iew.exec_refs 186166471 # number of memory reference insts executed -system.cpu0.iew.exec_branches 112308682 # Number of branches executed -system.cpu0.iew.exec_stores 83320557 # Number of stores executed -system.cpu0.iew.exec_rate 0.764594 # Inst execution rate -system.cpu0.iew.wb_sent 588977240 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 588205244 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 286222957 # num instructions producing a value -system.cpu0.iew.wb_consumers 469478170 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.752795 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609662 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 48006701 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16061877 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4699541 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 745382545 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.753605 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.560188 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 134059 # number of nop insts executed +system.cpu0.iew.exec_refs 201144943 # number of memory reference insts executed +system.cpu0.iew.exec_branches 144279686 # Number of branches executed +system.cpu0.iew.exec_stores 79491703 # Number of stores executed +system.cpu0.iew.exec_rate 0.853177 # Inst execution rate +system.cpu0.iew.wb_sent 647087647 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 646359431 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 309251056 # num instructions producing a value +system.cpu0.iew.wb_consumers 520070148 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.842495 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.594633 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 46740214 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 13917560 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4706684 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 733649612 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.845840 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.553610 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 499589625 67.02% 67.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 127846284 17.15% 84.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 54154407 7.27% 91.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18022208 2.42% 93.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 12958039 1.74% 95.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8991225 1.21% 96.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6101110 0.82% 97.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3650180 0.49% 98.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14069467 1.89% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 452365639 61.66% 61.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 136210339 18.57% 80.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 77415879 10.55% 90.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 24022740 3.27% 94.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 12736407 1.74% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8516612 1.16% 96.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5825168 0.79% 97.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3494792 0.48% 98.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 13062036 1.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 745382545 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 478330111 # Number of instructions committed -system.cpu0.commit.committedOps 561723659 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 733649612 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 541241308 # Number of instructions committed +system.cpu0.commit.committedOps 620549845 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 171106885 # Number of memory references committed -system.cpu0.commit.loads 90087577 # Number of loads committed -system.cpu0.commit.membars 3940521 # Number of memory barriers committed -system.cpu0.commit.branches 106744395 # Number of branches committed -system.cpu0.commit.fp_insts 400838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 515553500 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14275050 # Number of function calls committed. +system.cpu0.commit.refs 187488051 # Number of memory references committed +system.cpu0.commit.loads 110126156 # Number of loads committed +system.cpu0.commit.membars 3681828 # Number of memory barriers committed +system.cpu0.commit.branches 138866442 # Number of branches committed +system.cpu0.commit.fp_insts 440023 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 558745881 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13735984 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 389225467 69.29% 69.29% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1288146 0.23% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 63590 0.01% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 39571 0.01% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 90087577 16.04% 85.58% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 81019308 14.42% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 431741221 69.57% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1213492 0.20% 69.77% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 61406 0.01% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.78% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 45675 0.01% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.79% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 110075333 17.74% 87.53% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77018370 12.41% 99.94% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 50823 0.01% 99.94% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 343525 0.06% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 561723659 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14069467 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1336864700 # The number of ROB reads -system.cpu0.rob.rob_writes 1228532736 # The number of ROB writes -system.cpu0.timesIdled 1001309 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26869869 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93988523944 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 478330111 # Number of Instructions Simulated -system.cpu0.committedOps 561723659 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.633519 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.633519 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.612175 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.612175 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 705719528 # number of integer regfile reads -system.cpu0.int_regfile_writes 419138035 # number of integer regfile writes -system.cpu0.fp_regfile_reads 669802 # number of floating regfile reads -system.cpu0.fp_regfile_writes 321532 # number of floating regfile writes -system.cpu0.cc_regfile_reads 129631161 # number of cc regfile reads -system.cpu0.cc_regfile_writes 130314957 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1341639409 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16172326 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6359267 # number of replacements -system.cpu0.dcache.tags.tagsinuse 478.495579 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 158196405 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6359779 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 24.874513 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 620549845 # Class of committed instruction +system.cpu0.commit.bw_lim_events 13062036 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1383927534 # The number of ROB reads +system.cpu0.rob.rob_writes 1343471696 # The number of ROB writes +system.cpu0.timesIdled 977066 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24615940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 94002651032 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 541241308 # Number of Instructions Simulated +system.cpu0.committedOps 620549845 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.417477 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.417477 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.705479 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.705479 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 749870098 # number of integer regfile reads +system.cpu0.int_regfile_writes 449143556 # number of integer regfile writes +system.cpu0.fp_regfile_reads 735783 # number of floating regfile reads +system.cpu0.fp_regfile_writes 351380 # number of floating regfile writes +system.cpu0.cc_regfile_reads 158312331 # number of cc regfile reads +system.cpu0.cc_regfile_writes 158973081 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1390796279 # number of misc regfile reads +system.cpu0.misc_regfile_writes 13965731 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5697124 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.351019 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 176571011 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5697636 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.990223 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2049282000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.495579 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934562 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.934562 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.351019 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992873 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.992873 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 355337560 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 355337560 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 83119639 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83119639 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 70042361 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 70042361 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205739 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 205739 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 143941 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 143941 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1893040 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1893040 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1948071 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1948071 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153305941 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153305941 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153511680 # number of overall hits -system.cpu0.dcache.overall_hits::total 153511680 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7167523 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7167523 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7883078 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7883078 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 755741 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 755741 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796292 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 796292 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 289192 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 289192 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197314 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 197314 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15846893 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15846893 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 16602634 # number of overall misses -system.cpu0.dcache.overall_misses::total 16602634 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 116616484000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 116616484000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 160918615442 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 160918615442 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 30600076090 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 30600076090 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4458676000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4458676000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4713253000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4713253000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2519000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2519000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 308135175532 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 308135175532 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 308135175532 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 308135175532 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90287162 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90287162 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77925439 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77925439 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 961480 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 961480 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 940233 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 940233 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2182232 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2182232 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2145385 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2145385 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169152834 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 169152834 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170114314 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 170114314 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079386 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.079386 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101162 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.101162 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.786018 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.786018 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.846909 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.846909 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132521 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132521 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091971 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091971 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.093684 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.093684 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097597 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097597 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16270.123444 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16270.123444 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20413.170521 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20413.170521 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 38428.209865 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 38428.209865 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.701734 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.701734 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23887.068328 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23887.068328 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 387310320 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 387310320 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 104266262 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 104266262 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67643317 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 67643317 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201589 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 201589 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 157769 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 157769 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1740953 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1740953 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1780734 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1780734 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 172067348 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 172067348 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 172268937 # number of overall hits +system.cpu0.dcache.overall_hits::total 172268937 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6301527 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6301527 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6793475 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 6793475 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 634052 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 634052 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 800857 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 800857 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 257653 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 257653 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 179906 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 179906 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 13895859 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13895859 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 14529911 # number of overall misses +system.cpu0.dcache.overall_misses::total 14529911 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 95042221000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 95042221000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 131968145043 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 131968145043 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29372616680 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 29372616680 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3694169500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3694169500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4281937500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4281937500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3493500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3493500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 256382982723 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 256382982723 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 256382982723 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 256382982723 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 110567789 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 110567789 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74436792 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74436792 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 835641 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 835641 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 958626 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 958626 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1998606 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1998606 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1960640 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1960640 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 185963207 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 185963207 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 186798848 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 186798848 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.056992 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.056992 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.091265 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.091265 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758761 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.758761 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.835422 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.835422 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.128916 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.128916 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091759 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091759 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.074724 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.074724 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.077784 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.077784 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15082.411136 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15082.411136 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19425.720275 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19425.720275 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36676.481170 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36676.481170 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14337.770179 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14337.770179 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23800.971063 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23800.971063 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19444.516697 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19444.516697 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18559.415062 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18559.415062 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9297521 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 24817691 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 744023 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 779199 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.496282 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 31.850260 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6359403 # number of writebacks -system.cpu0.dcache.writebacks::total 6359403 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3686639 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3686639 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6327255 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6327255 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4271 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4271 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 148971 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 148971 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 10018165 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 10018165 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 10018165 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 10018165 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3480884 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3480884 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1555823 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1555823 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 748893 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 748893 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792021 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 792021 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140221 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140221 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197311 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 197311 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5828728 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5828728 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6577621 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6577621 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16980 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18801 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35781 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 53164892500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 53164892500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34944889021 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34944889021 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18458336500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18458336500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 29638184090 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 29638184090 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1982757000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1982757000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4516003000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4516003000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2458000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2458000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 117747965611 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 117747965611 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136206302111 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 136206302111 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3133590500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3133590500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3133590500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3133590500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038553 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038553 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019966 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019966 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.778896 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.778896 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.842367 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.842367 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091970 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091970 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034458 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034458 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038666 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.038666 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15273.388168 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15273.388168 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22460.709876 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22460.709876 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24647.495036 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24647.495036 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 37420.957386 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 37420.957386 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14140.228639 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14140.228639 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22887.740673 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22887.740673 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18450.315502 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18450.315502 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17645.186039 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17645.186039 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8869783 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 19194961 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 737578 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 651751 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.025553 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 29.451372 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 5697132 # number of writebacks +system.cpu0.dcache.writebacks::total 5697132 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3191836 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3191836 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5417328 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 5417328 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4607 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4607 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 132998 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 132998 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 8613771 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 8613771 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 8613771 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 8613771 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3109691 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3109691 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1376147 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1376147 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 627210 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 627210 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 796250 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 796250 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 124655 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 124655 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 179906 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 179906 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5282088 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5282088 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5909298 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5909298 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16022 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16022 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17403 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17403 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33425 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 33425 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44727315000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44727315000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29679279164 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29679279164 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15040987500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15040987500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28394000680 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28394000680 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1654283000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1654283000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4102116500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4102116500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3408500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3408500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102800594844 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 102800594844 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 117841582344 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 117841582344 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2952800500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2952800500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2952800500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2952800500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028125 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028125 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750574 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.750574 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.830616 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.830616 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062371 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062371 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091759 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091759 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028404 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028404 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031635 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14383.202382 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14383.202382 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21566.939552 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21566.939552 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23980.783948 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23980.783948 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35659.655485 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35659.655485 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13270.891661 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13270.891661 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22801.443532 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22801.443532 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20201.314182 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20201.314182 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20707.532725 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20707.532725 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184545.965842 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184545.965842 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87576.940276 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87576.940276 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 6086800 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.960315 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 213393241 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6087312 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.055414 # Average number of references to valid blocks. +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19462.113248 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19462.113248 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19941.722747 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19941.722747 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184296.623393 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184296.623393 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88341.077038 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88341.077038 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 6253789 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.960237 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 240286309 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6254301 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 38.419371 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 13476237000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960315 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960237 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999922 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 445759262 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 445759262 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 213393241 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 213393241 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 213393241 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 213393241 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 213393241 # number of overall hits -system.cpu0.icache.overall_hits::total 213393241 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6442715 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6442715 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6442715 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6442715 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6442715 # number of overall misses -system.cpu0.icache.overall_misses::total 6442715 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71477790896 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 71477790896 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 71477790896 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 71477790896 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 71477790896 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 71477790896 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 219835956 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 219835956 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 219835956 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 219835956 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 219835956 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 219835956 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029307 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029307 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029307 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029307 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029307 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029307 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11094.358651 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11094.358651 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11094.358651 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11094.358651 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11094.358651 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11094.358651 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10557387 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 2753 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 752829 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.023619 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 196.642857 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 6086800 # number of writebacks -system.cpu0.icache.writebacks::total 6086800 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355365 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 355365 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 355365 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 355365 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 355365 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 355365 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6087350 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6087350 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6087350 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6087350 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6087350 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6087350 # number of overall MSHR misses +system.cpu0.icache.tags.tag_accesses 500053900 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 500053900 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 240286309 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 240286309 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 240286309 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 240286309 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 240286309 # number of overall hits +system.cpu0.icache.overall_hits::total 240286309 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6613282 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6613282 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6613282 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6613282 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6613282 # number of overall misses +system.cpu0.icache.overall_misses::total 6613282 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70780975211 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 70780975211 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 70780975211 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 70780975211 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 70780975211 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 70780975211 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 246899591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 246899591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 246899591 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 246899591 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 246899591 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 246899591 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.026785 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.026785 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.026785 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.026785 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.026785 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.026785 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10702.851506 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10702.851506 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10702.851506 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10702.851506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10702.851506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10702.851506 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10321318 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 2209 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 763925 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.510905 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 169.923077 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 6253789 # number of writebacks +system.cpu0.icache.writebacks::total 6253789 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 358564 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 358564 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 358564 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 358564 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 358564 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 358564 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6254718 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6254718 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6254718 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6254718 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6254718 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6254718 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64448796094 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 64448796094 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64448796094 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 64448796094 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64448796094 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 64448796094 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 63975689306 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 63975689306 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 63975689306 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 63975689306 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 63975689306 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 63975689306 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2027158498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2027158498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027690 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027690 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027690 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10587.332106 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10587.332106 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10587.332106 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.025333 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.025333 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.025333 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.025333 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.025333 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.025333 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10228.389083 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10228.389083 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10228.389083 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10228.389083 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10228.389083 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10228.389083 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8595677 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8603285 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 6909 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7458642 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7464953 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 5714 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1123339 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2781248 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15839.093178 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 10966307 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2797118 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.920574 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1000455 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2364779 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15742.421414 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 10647963 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2380148 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.473656 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 2357977000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.164563 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.011471 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 18.049668 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000001 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 268.867475 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.947215 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002015 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001102 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016410 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.966742 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 337 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15450 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 116 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1708 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7197 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4776 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1564 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020569 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.942993 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 434183760 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 434183760 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 639992 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 185315 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 825307 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4159646 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4159646 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 8284827 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 8284827 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 23 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits +system.cpu0.l2cache.tags.occ_blocks::writebacks 15396.444809 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 43.122287 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 36.767067 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 266.087250 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.939724 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002632 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002244 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016241 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.960841 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 419 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14866 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 62 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 139 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 112 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 106 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 584 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 984 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5812 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1898 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.025574 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.907349 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 415506231 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 415506231 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 543348 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 189541 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 732889 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 3712844 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 3712844 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 8236224 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 8236224 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 995756 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 995756 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5493946 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5493946 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3273779 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3273779 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 166627 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 166627 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 639992 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 185315 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5493946 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4269535 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10588788 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 639992 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 185315 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5493946 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4269535 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10588788 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 23429 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 11592 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 35021 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 269158 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 269158 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 197304 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 197304 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 301043 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 301043 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 593373 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 593373 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1093007 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1093007 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 623543 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 623543 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 23429 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 11592 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 593373 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1394050 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2022444 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 23429 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 11592 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 593373 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1394050 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2022444 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 862921500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 562577500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1425499000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 983366500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 983366500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 308777000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 308777000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2366500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2366500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18857416997 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 18857416997 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22027267000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22027267000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 45190340989 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 45190340989 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 290057500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 290057500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 862921500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 562577500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22027267000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 64047757986 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 87500523986 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 862921500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 562577500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22027267000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 64047757986 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 87500523986 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 663421 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 196907 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 860328 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4159646 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4159646 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 8284827 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 8284827 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 269181 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 269181 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197306 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 197306 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1296799 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1296799 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6087319 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 6087319 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4366786 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4366786 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 790170 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 790170 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 663421 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 196907 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 6087319 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5663585 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 12611232 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 663421 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 196907 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 6087319 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5663585 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 12611232 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035315 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058870 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.040707 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999915 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999915 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999990 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999990 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 869040 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 869040 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5709661 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 5709661 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2921433 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2921433 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 213137 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 213137 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 543348 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 189541 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5709661 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3790473 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 10233023 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 543348 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 189541 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5709661 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3790473 # number of overall hits +system.cpu0.l2cache.overall_hits::total 10233023 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20175 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10263 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 30438 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 244720 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 244720 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 179898 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 179898 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 270342 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 270342 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 544652 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 544652 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 938726 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 938726 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 581343 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 581343 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20175 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10263 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 544652 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1209068 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1784158 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20175 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10263 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 544652 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1209068 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1784158 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 624969500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 390263000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1015232500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 927455000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 927455000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 261460000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 261460000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3280500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3280500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15324669997 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 15324669997 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 19971642000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 19971642000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 36150023478 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 36150023478 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 295919000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 295919000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 624969500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 390263000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 19971642000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 51474693475 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 72461567975 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 624969500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 390263000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 19971642000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 51474693475 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 72461567975 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 563523 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 199804 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 763327 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3712844 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 3712844 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 8236224 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 8236224 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 244748 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 244748 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 179900 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 179900 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1139382 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1139382 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6254313 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 6254313 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3860159 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 3860159 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794480 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 794480 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 563523 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 199804 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 6254313 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4999541 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 12017181 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 563523 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 199804 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 6254313 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4999541 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 12017181 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035802 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051365 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.039875 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999886 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999886 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999989 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999989 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.232143 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.232143 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.097477 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.097477 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.250300 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.250300 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.789125 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.789125 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035315 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058870 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.097477 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246143 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.160368 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035315 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058870 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.097477 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246143 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.160368 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36831.341500 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48531.530366 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 40704.120385 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3653.491629 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3653.491629 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1564.980943 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1564.980943 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 473300 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 473300 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62640.277293 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62640.277293 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37122.125543 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37122.125543 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41344.969418 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41344.969418 # average ReadSharedReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 465.176419 # average InvalidateReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 465.176419 # average InvalidateReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36831.341500 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48531.530366 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37122.125543 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45943.659113 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 43264.745024 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36831.341500 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48531.530366 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37122.125543 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45943.659113 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 43264.745024 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 1347 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.237271 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.237271 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.087084 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.087084 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.243183 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.243183 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731728 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731728 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035802 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051365 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.087084 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241836 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.148467 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035802 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051365 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.087084 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241836 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.148467 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30977.422553 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38026.210660 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33354.113279 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3789.861883 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3789.861883 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1453.379137 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1453.379137 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 546750 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 546750 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56686.234462 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56686.234462 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 36668.628776 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 36668.628776 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38509.664671 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38509.664671 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 509.026513 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 509.026513 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30977.422553 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38026.210660 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 36668.628776 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42573.861416 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 40613.873869 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30977.422553 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38026.210660 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 36668.628776 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42573.861416 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 40613.873869 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 48.107143 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 46.333333 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 49330 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 1802209 # number of writebacks -system.cpu0.l2cache.writebacks::total 1802209 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 136 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 303 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 439 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 20845 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 20845 # number of ReadExReq MSHR hits +system.cpu0.l2cache.unused_prefetches 43433 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 1509114 # number of writebacks +system.cpu0.l2cache.writebacks::total 1509114 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 106 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 285 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 391 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 13345 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 13345 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 2 # number of ReadCleanReq MSHR hits system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 4784 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 4784 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 6 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 136 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 303 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 4691 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 4691 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 106 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 285 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 25629 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 26070 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 136 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 303 # number of overall MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 18036 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 18429 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 106 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 285 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 25629 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 26070 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 23293 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11289 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 34582 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 895757 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 895757 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 269158 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 269158 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 197304 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 197304 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 280198 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 280198 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 593371 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 593371 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1088223 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1088223 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 623537 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::total 623537 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 23293 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11289 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 593371 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1368421 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1996374 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 23293 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11289 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 593371 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1368421 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 895757 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2892131 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 18036 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 18429 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 20069 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9978 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 30047 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 744254 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 744254 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 244720 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 244720 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 179898 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 179898 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 256997 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 256997 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 544650 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 544650 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 934035 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 934035 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 581341 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 581341 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 20069 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9978 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 544650 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1191032 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1765729 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 20069 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9978 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 544650 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1191032 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 744254 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2509983 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 38273 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18801 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16022 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 37315 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17403 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17403 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 57074 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 720471000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 489799000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1210270000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 58575065392 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 58575065392 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4984780995 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4984780995 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3032798496 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3032798496 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2000500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2000500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14111841497 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14111841497 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18467014500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18467014500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 38294410989 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 38294410989 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 22764184995 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 22764184995 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 720471000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 489799000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18467014500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 52406252486 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 72083536986 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 720471000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 489799000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18467014500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 52406252486 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 58575065392 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 130658602378 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 33425 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 54718 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 502459000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 325652000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 828111000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36749075781 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36749075781 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4570856487 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4570856487 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2749581992 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2749581992 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2770500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2770500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12067143997 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12067143997 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16703715500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16703715500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30202721978 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30202721978 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 21448570498 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 21448570498 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 502459000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 325652000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16703715500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 42269865975 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 59801692475 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 502459000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 325652000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16703715500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 42269865975 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36749075781 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 96550768256 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2997239500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4864699500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2824191500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4691651500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2997239500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4864699500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040196 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2824191500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4691651500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035613 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049939 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.039363 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999915 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999915 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999990 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999990 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999886 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999886 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999989 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999989 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216069 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216069 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097477 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249205 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249205 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.789118 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.789118 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.241617 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.158301 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.241617 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.225558 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.225558 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.087084 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087084 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.241968 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241968 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.731725 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.731725 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035613 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049939 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.087084 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238228 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.146934 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035613 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049939 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.087084 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238228 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229330 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34997.108322 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65391.691488 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18519.906505 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18519.906505 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15371.196205 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15371.196205 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400100 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400100 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50363.819503 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50363.819503 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31122.206006 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35189.856297 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35189.856297 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36508.154280 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36508.154280 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38296.878290 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36107.230903 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38296.878290 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45177.276679 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.208866 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25036.573820 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32637.001403 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27560.521849 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49377.061838 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49377.061838 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18677.903265 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18677.903265 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15284.116510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15284.116510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461750 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461750 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 46954.415799 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 46954.415799 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30668.714771 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30668.714771 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32335.749707 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32335.749707 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36894.990200 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36894.990200 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25036.573820 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32637.001403 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30668.714771 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35490.117793 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33867.990204 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25036.573820 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32637.001403 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30668.714771 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35490.117793 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49377.061838 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38466.702068 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176515.871614 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127105.256970 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176269.598053 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125730.979499 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83766.230681 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85234.949364 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 25828303 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13287358 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1712 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 676521 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 676518 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 990165 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11537181 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 18801 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 18801 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5966642 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8286555 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1378403 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1136481 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 480580 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352407 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 530357 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1327096 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1303956 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6087350 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5339261 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 842479 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 790170 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18304055 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20435509 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 413815 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1398403 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 40551782 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 779484304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 775974521 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1575256 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5307368 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1562341449 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5999180 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 122789024 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 19760108 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.053277 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.224586 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 84493.388182 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85742.379107 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 24756799 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12708263 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2196 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 629051 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 629043 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 8 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 884546 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11093405 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 17403 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 17403 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5225908 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8238069 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1170453 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 945799 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 463366 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 326275 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 490425 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 190 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1168917 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1146769 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6254718 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4769163 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 850255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 794480 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18805406 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18368662 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 418571 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1191985 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 38784624 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 800859216 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 691176446 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1598432 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4508184 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1498142278 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5240375 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 104025792 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 18364082 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.052502 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.223039 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 18707349 94.67% 94.67% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 1052756 5.33% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 17399941 94.75% 94.75% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 964133 5.25% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 19760108 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 25687014453 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 18364082 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 24622778944 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 182391125 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 185315667 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9158694684 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9409532092 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9158841551 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8142032744 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 217386526 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 219209106 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 735766915 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 629194022 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 134369829 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89463085 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6609561 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 94230263 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 58109960 # Number of BTB hits +system.cpu1.branchPred.lookups 166724968 # Number of BP lookups +system.cpu1.branchPred.condPredicted 126846962 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6061099 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 131629441 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 75453810 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 61.668044 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17839939 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 183627 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4347444 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2695405 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1652039 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 417102 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 57.322898 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16000678 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 166104 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3768010 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2280408 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1487602 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 378018 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1719,86 +1731,84 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 561952 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 561952 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11814 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 88087 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 261651 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 300301 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2363.057399 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13317.227915 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 298048 99.25% 99.25% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1567 0.52% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 436 0.15% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 167 0.06% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 40 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 300301 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 287935 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21029.369476 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18280.568505 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15111.837725 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 285795 99.26% 99.26% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1436 0.50% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 377 0.13% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 181 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 86 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 287935 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 466714959496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.597643 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.555516 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 465490623496 99.74% 99.74% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 621983000 0.13% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 266845500 0.06% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 131382500 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 96036000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 60845000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 18797500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 27878000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 546500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 22000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 466714959496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 88088 88.17% 88.17% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11814 11.83% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 99902 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 561952 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 467692 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 467692 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8751 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 70596 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 217424 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 250268 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2074.929675 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 11460.901897 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 248915 99.46% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 899 0.36% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 341 0.14% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 97 0.04% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 250268 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 236712 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20830.925344 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18161.943529 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14226.641322 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 235430 99.46% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1000 0.42% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 142 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 87 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 6 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 6 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 38 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 236712 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 410863041148 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.552097 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.557280 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 409906147648 99.77% 99.77% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 459057000 0.11% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 219368000 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 102318000 0.02% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 84455000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 58029500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 14454500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 18772000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 430000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 410863041148 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 70596 88.97% 88.97% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8751 11.03% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 79347 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 467692 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 561952 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 99902 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 467692 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 79347 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 99902 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 661854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 79347 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 547039 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 97791245 # DTB read hits -system.cpu1.dtb.read_misses 385118 # DTB read misses -system.cpu1.dtb.write_hits 81245431 # DTB write hits -system.cpu1.dtb.write_misses 176834 # DTB write misses -system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 135065828 # DTB read hits +system.cpu1.dtb.read_misses 329885 # DTB read misses +system.cpu1.dtb.write_hits 69791052 # DTB write hits +system.cpu1.dtb.write_misses 137807 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36850 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 268 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6109 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36136 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 592 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 4990 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 40755 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 98176363 # DTB read accesses -system.cpu1.dtb.write_accesses 81422265 # DTB write accesses +system.cpu1.dtb.perms_faults 39336 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 135395713 # DTB read accesses +system.cpu1.dtb.write_accesses 69928859 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 179036676 # DTB hits -system.cpu1.dtb.misses 561952 # DTB misses -system.cpu1.dtb.accesses 179598628 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 204856880 # DTB hits +system.cpu1.dtb.misses 467692 # DTB misses +system.cpu1.dtb.accesses 205324572 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1828,1166 +1838,1181 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 84407 # Table walker walks requested -system.cpu1.itb.walker.walksLong 84407 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1027 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60740 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 10156 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 74251 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1057.238286 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8622.114888 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 74015 99.68% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 199 0.27% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 18 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 74251 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71923 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24988.821378 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22597.090075 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18666.984039 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70820 98.47% 98.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 715 0.99% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 265 0.37% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 63 0.09% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 24 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 78571 # Table walker walks requested +system.cpu1.itb.walker.walksLong 78571 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 897 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57010 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9455 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 69116 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 778.444933 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6785.315207 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 69062 99.92% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 44 0.06% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::589824-655359 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69116 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 67362 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24032.236276 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22252.228108 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 15053.113927 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 66909 99.33% 99.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 314 0.47% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 86 0.13% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 23 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 6 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71923 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 410850107648 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.878728 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.326631 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 49848543788 12.13% 12.13% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 360979116860 87.86% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 21177000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1227500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 42500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 410850107648 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 60740 98.34% 98.34% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1027 1.66% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 61767 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 67362 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 372208258984 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.850822 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.356391 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 55541061216 14.92% 14.92% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 316652457768 85.07% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 13820000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 844000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 76000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 372208258984 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57010 98.45% 98.45% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 897 1.55% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 57907 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 84407 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 84407 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 78571 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 78571 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61767 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61767 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 146174 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 210802915 # ITB inst hits -system.cpu1.itb.inst_misses 84407 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57907 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57907 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 136478 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 233650950 # ITB inst hits +system.cpu1.itb.inst_misses 78571 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26222 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 38825 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25813 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 208943 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 177997 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 210887322 # ITB inst accesses -system.cpu1.itb.hits 210802915 # DTB hits -system.cpu1.itb.misses 84407 # DTB misses -system.cpu1.itb.accesses 210887322 # DTB accesses -system.cpu1.numPwrStateTransitions 27667 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 13834 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3399006591.183533 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 87524078188.715500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3453 24.96% 24.96% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 10352 74.83% 99.79% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.04% 99.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 233729521 # ITB inst accesses +system.cpu1.itb.hits 233650950 # DTB hits +system.cpu1.itb.misses 78571 # DTB misses +system.cpu1.itb.accesses 233729521 # DTB accesses +system.cpu1.numPwrStateTransitions 26654 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 13327 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3530319846.850679 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 118121656427.394104 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3111 23.34% 23.34% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10193 76.48% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.91% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.92% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.95% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 7 0.05% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7390880477084 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 13834 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 363085536567 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47021857182433 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 726181462 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7351151457424 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 13327 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 336351398021 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47048572598979 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 672713020 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 86390303 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 594062843 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 134369829 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 78645304 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 601498232 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 14253482 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1820697 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 287238 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5988786 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 713679 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 819715 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 210572695 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1658938 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27666 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 704645391 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.988963 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.222689 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 79728286 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 642468992 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 166724968 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 93734896 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 559167861 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13053646 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1631240 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 271905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 4961771 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 667976 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 769069 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 233453036 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1554763 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 25728 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 653724931 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.120109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.251817 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 370929364 52.64% 52.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 130277469 18.49% 71.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 43725033 6.21% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 159713525 22.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 313299605 47.93% 47.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 112972876 17.28% 65.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 63087328 9.65% 74.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 164365122 25.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 704645391 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.185036 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.818064 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 103020673 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 337373962 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 222407115 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 36734416 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5109225 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18739170 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2055775 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 616426802 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 23026844 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5109225 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 137867421 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 45074504 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 232811775 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 223900939 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 59881527 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 599411621 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 6042296 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9969882 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 242190 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 299313 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 25537080 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11262 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 571214843 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 926423560 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 707359605 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 805393 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 514629531 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 56585312 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15957043 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 14048251 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 73992297 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 98060208 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 84478655 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8950565 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7675207 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 576680308 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 16104006 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 581772484 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2680133 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 53366771 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 34273904 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 266458 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 704645391 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.825624 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.067009 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 653724931 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.247840 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.955042 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 92976248 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 279392919 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 246557278 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 30153950 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4644536 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 16507277 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1918533 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 660010839 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21083339 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4644536 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 123063367 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 35472140 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 196207454 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 246305385 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 48032049 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 644623401 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5459169 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8046987 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 175179 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 243838 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19778119 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 13544 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 568046285 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 920205364 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 738028680 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 778046 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 516650091 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 51396188 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 12941129 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 11231119 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 61203121 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 135763785 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 72651809 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8023262 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7007249 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 625560135 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 13098005 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 628187829 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2397096 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 48439446 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 31062607 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 245074 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 653724931 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.960936 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.128164 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 385934490 54.77% 54.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 135280434 19.20% 73.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 111501247 15.82% 89.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 64231431 9.12% 98.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7693682 1.09% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4107 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 329147367 50.35% 50.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 114620484 17.53% 67.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 122782429 18.78% 86.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 80699819 12.34% 99.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6471130 0.99% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3702 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 704645391 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 653724931 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 58591735 44.23% 44.23% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 49305 0.04% 44.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 21310 0.02% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 60 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 35005485 26.43% 70.71% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 38791699 29.29% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 51549181 44.86% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 41748 0.04% 44.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 12676 0.01% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 10 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 30585339 26.62% 71.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 32314734 28.12% 99.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 48210 0.04% 99.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 356758 0.31% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 36 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 397008075 68.24% 68.24% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1247296 0.21% 68.46% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 70487 0.01% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 78078 0.01% 68.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.48% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 100884939 17.34% 85.82% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 82483526 14.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 418102293 66.56% 66.56% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1205881 0.19% 66.75% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 68687 0.01% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 9 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 15 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 25 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 73390 0.01% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 137792676 21.93% 88.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 70525871 11.23% 99.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 69235 0.01% 99.94% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 349710 0.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 581772484 # Type of FU issued -system.cpu1.iq.rate 0.801139 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 132459594 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227683 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 2001993843 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 645760406 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 564750025 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1336243 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 531893 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 495883 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 713403384 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 828658 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2572358 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 628187829 # Type of FU issued +system.cpu1.iq.rate 0.933813 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 114908656 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.182921 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 2026010950 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 686704768 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 613194933 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1395389 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 519993 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 487253 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 742199086 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 897363 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2245530 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12226985 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16460 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 142391 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5497757 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11142517 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 14462 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 128111 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 4846687 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2564544 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4190277 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2292036 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3380084 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5109225 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6111838 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1648605 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 592918318 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4644536 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5369264 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1350152 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 638773601 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 98060208 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 84478655 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13792326 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 62841 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1527139 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 142391 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1885740 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 3046567 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4932307 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 573876367 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 97784309 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 7346483 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 135763785 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 72651809 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 10993874 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 39251 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1271644 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 128111 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1722302 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2773233 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4495535 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 621090126 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 135058369 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6634352 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 134004 # number of nop insts executed -system.cpu1.iew.exec_refs 179029158 # number of memory reference insts executed -system.cpu1.iew.exec_branches 107707763 # Number of branches executed -system.cpu1.iew.exec_stores 81244849 # Number of stores executed -system.cpu1.iew.exec_rate 0.790266 # Inst execution rate -system.cpu1.iew.wb_sent 565995055 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 565245908 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 273023556 # num instructions producing a value -system.cpu1.iew.wb_consumers 448078183 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.778381 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.609321 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 46535716 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15837548 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4592045 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 695790390 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.775259 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.568649 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 115461 # number of nop insts executed +system.cpu1.iew.exec_refs 204845438 # number of memory reference insts executed +system.cpu1.iew.exec_branches 142702777 # Number of branches executed +system.cpu1.iew.exec_stores 69787069 # Number of stores executed +system.cpu1.iew.exec_rate 0.923262 # Inst execution rate +system.cpu1.iew.wb_sent 614366699 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 613682186 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 312164308 # num instructions producing a value +system.cpu1.iew.wb_consumers 462317181 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.912250 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.675217 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 42230538 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 12852931 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4178812 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 645679168 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.914105 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.588407 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 457970279 65.82% 65.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 124243355 17.86% 83.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 52434114 7.54% 91.21% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 17645088 2.54% 93.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12549968 1.80% 95.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8433891 1.21% 96.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5802471 0.83% 97.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3503250 0.50% 98.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 13207974 1.90% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 392186508 60.74% 60.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 104643933 16.21% 76.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 70768120 10.96% 87.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 40497706 6.27% 94.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10687024 1.66% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7435797 1.15% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5000033 0.77% 97.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3062259 0.47% 98.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 11397788 1.77% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 695790390 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 458018039 # Number of instructions committed -system.cpu1.commit.committedOps 539417542 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 645679168 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 519872171 # Number of instructions committed +system.cpu1.commit.committedOps 590218687 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 164814121 # Number of memory references committed -system.cpu1.commit.loads 85833223 # Number of loads committed -system.cpu1.commit.membars 3719425 # Number of memory barriers committed -system.cpu1.commit.branches 102343051 # Number of branches committed -system.cpu1.commit.fp_insts 486729 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 494686776 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13237013 # Number of function calls committed. +system.cpu1.commit.refs 192426389 # Number of memory references committed +system.cpu1.commit.loads 124621267 # Number of loads committed +system.cpu1.commit.membars 28164164 # Number of memory barriers committed +system.cpu1.commit.branches 137852750 # Number of branches committed +system.cpu1.commit.fp_insts 479347 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 552778663 # Number of committed integer instructions. +system.cpu1.commit.function_calls 11814414 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 373462182 69.23% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1014464 0.19% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 55738 0.01% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 70995 0.01% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 85833223 15.91% 85.36% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 78980898 14.64% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 396713394 67.21% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 957424 0.16% 67.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 54002 0.01% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 8 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 13 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 21 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 67436 0.01% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 124556243 21.10% 88.50% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 67458277 11.43% 99.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 65024 0.01% 99.94% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 346845 0.06% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 539417542 # Class of committed instruction -system.cpu1.commit.bw_lim_events 13207974 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1264391907 # The number of ROB reads -system.cpu1.rob.rob_writes 1180722952 # The number of ROB writes -system.cpu1.timesIdled 944459 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 21536071 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94043695657 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 458018039 # Number of Instructions Simulated -system.cpu1.committedOps 539417542 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.585487 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.585487 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.630721 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.630721 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 677403787 # number of integer regfile reads -system.cpu1.int_regfile_writes 401367044 # number of integer regfile writes -system.cpu1.fp_regfile_reads 791707 # number of floating regfile reads -system.cpu1.fp_regfile_writes 438600 # number of floating regfile writes -system.cpu1.cc_regfile_reads 124889457 # number of cc regfile reads -system.cpu1.cc_regfile_writes 125620500 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1260290191 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15974322 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5362331 # number of replacements -system.cpu1.dcache.tags.tagsinuse 456.510727 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 153804268 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5362842 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.679620 # Average number of references to valid blocks. +system.cpu1.commit.op_class_0::total 590218687 # Class of committed instruction +system.cpu1.commit.bw_lim_events 11397788 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1262985389 # The number of ROB reads +system.cpu1.rob.rob_writes 1272910770 # The number of ROB writes +system.cpu1.timesIdled 874445 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18988089 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94097134999 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 519872171 # Number of Instructions Simulated +system.cpu1.committedOps 590218687 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.293997 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.293997 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.772799 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.772799 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 710414372 # number of integer regfile reads +system.cpu1.int_regfile_writes 423863042 # number of integer regfile writes +system.cpu1.fp_regfile_reads 765235 # number of floating regfile reads +system.cpu1.fp_regfile_writes 456552 # number of floating regfile writes +system.cpu1.cc_regfile_reads 104682480 # number of cc regfile reads +system.cpu1.cc_regfile_writes 105389899 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1284615439 # number of misc regfile reads +system.cpu1.misc_regfile_writes 12778028 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 4692670 # number of replacements +system.cpu1.dcache.tags.tagsinuse 431.602875 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 183292694 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4693181 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.055109 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8517840775000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.510727 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891623 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.891623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 431.602875 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.842974 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.842974 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 341608540 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 341608540 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 79940930 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79940930 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 69078558 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 69078558 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191831 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 191831 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 170764 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 170764 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1820637 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1820637 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1828950 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1828950 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 149190252 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 149190252 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 149382083 # number of overall hits -system.cpu1.dcache.overall_hits::total 149382083 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6220385 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6220385 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7237581 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7237581 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 689658 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 689658 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 463987 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 463987 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 244543 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 244543 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192296 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 192296 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13921953 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13921953 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14611611 # number of overall misses -system.cpu1.dcache.overall_misses::total 14611611 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96362388500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 96362388500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 134833660621 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 134833660621 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11613680644 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 11613680644 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3499456000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3499456000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4567503000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4567503000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3019500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3019500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 242809729765 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 242809729765 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 242809729765 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 242809729765 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 86161315 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 86161315 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 76316139 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 76316139 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 881489 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 881489 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 634751 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 634751 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2065180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2065180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2021246 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2021246 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 163112205 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 163112205 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 163993694 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 163993694 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072195 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.072195 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094837 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.094837 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.782378 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.782378 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.730975 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.730975 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118412 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118412 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095137 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095137 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085352 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.085352 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089099 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.089099 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15491.386546 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15491.386546 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18629.658255 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18629.658255 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25030.185423 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25030.185423 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14310.186757 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14310.186757 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23752.459750 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23752.459750 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 395805519 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 395805519 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 119760214 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 119760214 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 59584318 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 59584318 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 168476 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 168476 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 151679 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 151679 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1458987 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1458987 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1477989 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1477989 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 179496211 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 179496211 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 179664687 # number of overall hits +system.cpu1.dcache.overall_hits::total 179664687 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 5543636 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 5543636 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 5953679 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 5953679 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 548675 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 548675 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 445037 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 445037 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 238823 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 238823 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 180840 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 180840 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 11942352 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 11942352 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 12491027 # number of overall misses +system.cpu1.dcache.overall_misses::total 12491027 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 78644271500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 78644271500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 105227667186 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 105227667186 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11004402882 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 11004402882 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3255486500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3255486500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4308460000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4308460000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4407500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4407500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 194876341568 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 194876341568 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 194876341568 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 194876341568 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 125303850 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 125303850 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 65537997 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 65537997 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 717151 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 717151 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 596716 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 596716 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1697810 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1697810 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1658829 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1658829 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 191438563 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 191438563 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 192155714 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 192155714 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044242 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044242 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.090843 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.090843 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765076 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.765076 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.745810 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.745810 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140665 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140665 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109017 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109017 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.062382 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.062382 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.065005 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.065005 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14186.406088 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14186.406088 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17674.393797 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17674.393797 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24726.939293 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24726.939293 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13631.377631 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13631.377631 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23824.706923 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23824.706923 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17440.780741 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17440.780741 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16617.587873 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16617.587873 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 3018250 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 21738633 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 378529 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 731712 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.973629 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 29.709275 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5362354 # number of writebacks -system.cpu1.dcache.writebacks::total 5362354 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3187456 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3187456 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5861363 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5861363 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3594 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3594 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 128092 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 128092 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9052413 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9052413 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9052413 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9052413 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3032929 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3032929 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1376218 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1376218 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 689576 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 689576 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460393 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 460393 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116451 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116451 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192288 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 192288 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4869540 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4869540 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5559116 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5559116 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21291 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21291 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19410 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40701 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40701 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42726170500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42726170500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26732145261 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26732145261 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16635879000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16635879000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11021618644 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11021618644 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1587191500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1587191500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4375287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4375287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2947500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2947500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 80479934405 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 80479934405 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 97115813405 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 97115813405 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3797634000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3797634000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3797634000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3797634000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035201 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035201 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018033 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018033 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.782285 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.782285 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.725313 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.725313 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056388 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056388 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095133 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095133 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029854 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029854 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033898 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033898 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14087.428522 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14087.428522 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19424.353744 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19424.353744 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24124.794076 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.794076 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23939.587796 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23939.587796 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13629.694034 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13629.694034 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22753.822391 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22753.822391 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16318.087222 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16318.087222 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15601.306567 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15601.306567 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2879860 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 16425129 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 370474 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 590630 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.773447 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 27.809507 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 4692685 # number of writebacks +system.cpu1.dcache.writebacks::total 4692685 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2832127 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 2832127 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 4784793 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 4784793 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3576 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3576 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 122254 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 122254 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 7620496 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 7620496 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 7620496 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 7620496 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2711509 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2711509 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1168886 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1168886 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 548581 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 548581 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 441461 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 441461 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116569 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116569 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 180840 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 180840 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4321856 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4321856 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4870437 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4870437 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22628 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22628 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21158 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21158 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 43786 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 43786 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35845036500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35845036500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21809849574 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21809849574 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12123846500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12123846500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10446547382 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10446547382 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1530530500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1530530500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4127725000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4127725000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4302500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4302500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68101433456 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 68101433456 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 80225279956 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 80225279956 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4008317000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4008317000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4008317000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4008317000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.021639 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.021639 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.764945 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.764945 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.739818 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.739818 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068658 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068658 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109017 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109017 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.022576 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.022576 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.025346 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.025346 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13219.589719 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13219.589719 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18658.662670 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18658.662670 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22100.376243 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22100.376243 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23663.579301 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23663.579301 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13129.824396 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13129.824396 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22825.287547 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22825.287547 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16527.214974 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16527.214974 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17469.650463 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17469.650463 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178368.042835 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178368.042835 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 93305.668165 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 93305.668165 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5902862 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.529159 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 204324856 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5903374 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.611538 # Average number of references to valid blocks. +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15757.450840 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15757.450840 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16471.885368 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16471.885368 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177139.694184 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177139.694184 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91543.347189 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91543.347189 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5471432 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.529158 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 227657285 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5471944 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 41.604462 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8518180301500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.529159 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.529158 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979549 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.979549 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 427035149 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 427035149 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 204324856 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 204324856 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 204324856 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 204324856 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 204324856 # number of overall hits -system.cpu1.icache.overall_hits::total 204324856 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6241016 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6241016 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6241016 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6241016 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6241016 # number of overall misses -system.cpu1.icache.overall_misses::total 6241016 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 68483006769 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 68483006769 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 68483006769 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 68483006769 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 68483006769 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 68483006769 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 210565872 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 210565872 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 210565872 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 210565872 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 210565872 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 210565872 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029639 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029639 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029639 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029639 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029639 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029639 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10973.054190 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10973.054190 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10973.054190 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10973.054190 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10973.054190 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10973.054190 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 10089385 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 780 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 729550 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.829600 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 390 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5902862 # number of writebacks -system.cpu1.icache.writebacks::total 5902862 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 337611 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 337611 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 337611 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 337611 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 337611 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 337611 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5903405 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5903405 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5903405 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5903405 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5903405 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5903405 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 472364897 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 472364897 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 227657285 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 227657285 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 227657285 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 227657285 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 227657285 # number of overall hits +system.cpu1.icache.overall_hits::total 227657285 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5789178 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5789178 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5789178 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5789178 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5789178 # number of overall misses +system.cpu1.icache.overall_misses::total 5789178 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 62743690584 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 62743690584 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 62743690584 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 62743690584 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 62743690584 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 62743690584 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 233446463 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 233446463 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 233446463 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 233446463 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 233446463 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 233446463 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024799 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024799 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024799 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024799 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024799 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024799 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10838.100087 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10838.100087 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10838.100087 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10838.100087 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10838.100087 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10838.100087 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9340365 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 160 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 688454 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.567159 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 160 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 5471432 # number of writebacks +system.cpu1.icache.writebacks::total 5471432 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 317207 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 317207 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 317207 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 317207 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 317207 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 317207 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5471971 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5471971 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5471971 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5471971 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5471971 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5471971 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 61792345334 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 61792345334 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 61792345334 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 61792345334 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 61792345334 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 61792345334 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56670933881 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 56670933881 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56670933881 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 56670933881 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56670933881 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 56670933881 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7079498 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7079498 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7079498 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 7079498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028036 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028036 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028036 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10467.238032 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10467.238032 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10467.238032 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023440 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023440 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023440 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023440 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023440 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023440 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10356.585201 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10356.585201 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10356.585201 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10356.585201 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10356.585201 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10356.585201 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 105664.149254 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 105664.149254 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7372835 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7380898 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 7290 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6370815 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6378826 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 7261 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 895622 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2111480 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 12950.875249 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10279593 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2126904 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.833125 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 806238 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 1756578 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12752.912837 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 9300002 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1772385 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.247168 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12615.195694 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 33.253837 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 24.384299 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 278.041418 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.769970 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002030 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001488 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.016970 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.790459 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 414 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14899 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 65 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 114 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 107 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 89 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 279 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1377 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5586 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5487 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2170 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.025269 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909363 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 393006433 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 393006433 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 563217 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 188120 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 751337 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3404083 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3404083 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 7859423 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7859423 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 37 # number of UpgradeReq hits +system.cpu1.l2cache.tags.occ_blocks::writebacks 12466.059831 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 25.971588 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 14.261261 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 246.620158 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.760868 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001585 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000870 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.015052 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.778376 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 338 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15390 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 109 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 42 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1774 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7283 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4523 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1607 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020630 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.939331 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 354225697 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 354225697 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 466688 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 176018 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 642706 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 2940618 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 2940618 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 7221695 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 7221695 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 24 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 897837 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 897837 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5343474 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 5343474 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2865962 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2865962 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 200218 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 200218 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 563217 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 188120 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5343474 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3763799 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9858610 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 563217 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 188120 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5343474 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3763799 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9858610 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 20588 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9811 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 30399 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 230170 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 230170 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 192283 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 192283 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 257129 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 257129 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 559914 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 559914 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 968987 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 968987 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 258105 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 258105 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 20588 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9811 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 559914 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1226116 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1816429 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 20588 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9811 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 559914 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1226116 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1816429 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 677842000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 364880500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1042722500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 983294000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 983294000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 271676000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 271676000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2839500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2839500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12532259990 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 12532259990 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20571950500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20571950500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 36061918479 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 36061918479 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 340389000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 340389000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 677842000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 364880500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20571950500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 48594178469 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 70208851469 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 677842000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 364880500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20571950500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 48594178469 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 70208851469 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 583805 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 197931 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 781736 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3404083 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3404083 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 7859423 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 7859423 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 230207 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 230207 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 192284 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 192284 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1154966 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1154966 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5903388 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 5903388 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3834949 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3834949 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 458323 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 458323 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 583805 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 197931 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5903388 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4989915 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 11675039 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 583805 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 197931 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5903388 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4989915 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 11675039 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.035265 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.049568 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.038887 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999839 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999839 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 733730 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 733730 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4959233 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4959233 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2549054 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2549054 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 189318 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 189318 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 466688 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 176018 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4959233 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3282784 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8884723 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 466688 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 176018 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4959233 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3282784 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8884723 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 17962 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8568 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 26530 # number of ReadReq misses +system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses +system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208947 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 208947 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 180832 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 180832 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 231689 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 231689 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 512718 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 512718 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 826805 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 826805 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 250101 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 250101 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 17962 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8568 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 512718 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1058494 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1597742 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 17962 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8568 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 512718 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1058494 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1597742 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 482745500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 237334000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 720079500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 968697500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 968697500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 281964000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 281964000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4142498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4142498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9580217985 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 9580217985 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18416294000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18416294000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 27460876973 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 27460876973 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 376767000 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 376767000 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 482745500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 237334000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18416294000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 37041094958 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 56177468458 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 482745500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 237334000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18416294000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 37041094958 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 56177468458 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 484650 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 184586 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 669236 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 2940618 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 2940618 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 7221696 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 7221696 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 208971 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 208971 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 180833 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 180833 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 965419 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 965419 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5471951 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 5471951 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3375859 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3375859 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 439419 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 439419 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 484650 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 184586 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5471951 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4341278 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10482465 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 484650 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 184586 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5471951 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4341278 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10482465 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037062 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046417 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.039642 # miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses +system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999885 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999885 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999994 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999994 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.222629 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.222629 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.094846 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.094846 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.252673 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.252673 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.563151 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.563151 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.035265 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.049568 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094846 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.245719 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.155582 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.035265 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.049568 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094846 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.245719 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.155582 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32924.130561 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37190.959128 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34301.210566 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4272.033714 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4272.033714 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1412.896616 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1412.896616 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 709875 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 709875 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48739.193129 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48739.193129 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36741.268302 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36741.268302 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37216.101433 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37216.101433 # average ReadSharedReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1318.800488 # average InvalidateReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1318.800488 # average InvalidateReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32924.130561 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37190.959128 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36741.268302 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39632.611000 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 38652.130895 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32924.130561 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37190.959128 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36741.268302 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39632.611000 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 38652.130895 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.239988 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.239988 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.093699 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.093699 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.244917 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.244917 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.569163 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.569163 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037062 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046417 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.093699 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.243821 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.152420 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037062 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046417 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.093699 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.243821 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.152420 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 26875.932524 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 27700.046685 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27142.084433 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4636.091928 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4636.091928 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1559.259423 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1559.259423 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 591785.428571 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 591785.428571 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41349.472720 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41349.472720 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35918.953499 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35918.953499 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33213.244928 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33213.244928 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1506.459390 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1506.459390 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 26875.932524 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 27700.046685 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35918.953499 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34994.147306 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 35160.538096 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 26875.932524 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 27700.046685 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35918.953499 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34994.147306 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 35160.538096 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 270 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 42085 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 1170856 # number of writebacks -system.cpu1.l2cache.writebacks::total 1170856 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 68 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 195 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 13529 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 13529 # number of ReadExReq MSHR hits +system.cpu1.l2cache.unused_prefetches 38780 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 938959 # number of writebacks +system.cpu1.l2cache.writebacks::total 938959 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 75 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 292 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6099 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 6099 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4671 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4671 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 68 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 195 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4092 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4092 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 9 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::total 9 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 75 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 292 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 18200 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 18466 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 68 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 195 # number of overall MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 10191 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 10561 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 75 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 292 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 18200 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 18466 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 20520 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9616 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 30136 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 763352 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 763352 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 230170 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 230170 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 192283 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 192283 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 243600 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 243600 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 559911 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 559911 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 964316 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 964316 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 258100 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::total 258100 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 20520 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9616 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 559911 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1207916 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1797963 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 20520 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9616 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 559911 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1207916 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 763352 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2561315 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 10191 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 10561 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 17887 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8276 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 26163 # number of ReadReq MSHR misses +system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses +system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 611441 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 611441 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 208947 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 208947 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 180832 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 180832 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 225590 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 225590 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 512715 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 512715 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 822713 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 822713 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 250092 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 250092 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 17887 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8276 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 512715 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1048303 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1587181 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 17887 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8276 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 512715 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1048303 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 611441 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2198622 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21291 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21358 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 19410 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22628 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22695 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21158 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21158 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 40701 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 40768 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 553404000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 304119000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 857523000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 42319154022 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 42319154022 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4307815491 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4307815491 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2930523994 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2930523994 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2407500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2407500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8988147495 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8988147495 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17212365000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17212365000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29935787486 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29935787486 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6963364497 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6963364497 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 553404000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 304119000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17212365000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 38923934981 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 56993822981 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 553404000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 304119000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17212365000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 38923934981 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 42319154022 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 99312977003 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 43786 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43853 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 373994500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 182890500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 556885000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 18622917019 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 18622917019 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3934960495 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3934960495 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2768973490 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2768973490 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3512498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3512498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7383230990 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7383230990 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 15339884500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 15339884500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 22227595980 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 22227595980 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6539695498 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6539695498 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 373994500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 182890500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15339884500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 29610826970 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 45507596470 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 373994500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 182890500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15339884500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 29610826970 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 18622917019 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 64130513489 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6576000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3627092000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3633668000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3827109500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3833685500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6576000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3627092000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3633668000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.038550 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3827109500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3833685500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.036907 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.044835 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.039094 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999839 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999839 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999885 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999885 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999994 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999994 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.210915 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.210915 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094846 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251455 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251455 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.563140 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.563140 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242071 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154001 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242071 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.233671 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.233671 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.093699 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093699 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.243705 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243705 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.569142 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.569142 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.036907 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044835 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093699 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.241473 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.151413 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.036907 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044835 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093699 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.241473 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.219384 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28455.103531 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55438.584063 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18715.799153 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18715.799153 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15240.681672 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15240.681672 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 601875 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 601875 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36897.157204 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36897.157204 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30741.251735 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31043.545359 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31043.545359 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26979.327768 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26979.327768 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32224.041226 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31699.107813 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32224.041226 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38774.214418 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.209743 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 20908.732599 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 22098.900435 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21285.211941 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30457.422742 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30457.422742 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18832.337842 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18832.337842 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15312.408700 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15312.408700 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 501785.428571 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 501785.428571 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32728.538455 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32728.538455 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29918.930595 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29918.930595 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27017.436190 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27017.436190 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26149.159101 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26149.159101 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 20908.732599 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 22098.900435 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29918.930595 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28246.439217 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28671.963985 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 20908.732599 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 22098.900435 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29918.930595 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28246.439217 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30457.422742 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29168.503494 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170357.991640 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170131.472984 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169131.584762 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168922.031284 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 89115.549986 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 89130.396389 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 23401917 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12050394 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1685 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 583324 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 583320 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 895492 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10720388 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 19410 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 19410 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4582624 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7861129 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1298468 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 967756 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 436519 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348532 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 480708 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1183332 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1160512 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5903405 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4845353 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 522418 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 458323 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17709789 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17335665 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416038 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1239832 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36701324 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 755601072 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 668583302 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1583448 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4670440 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1430438262 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5153113 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 82064432 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 17599300 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.053842 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.225707 # Request fanout histogram +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87404.866852 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87421.282466 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 21096907 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10844448 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1776 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 550847 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 550845 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 772948 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9709968 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 21158 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 21158 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 3884973 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7223497 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1103932 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 773517 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 20 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 412740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 326097 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 449655 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 92 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 190 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 993079 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 971172 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5471971 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4312998 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 499008 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 439419 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16415488 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15276269 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 387820 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1031669 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 33111246 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 700377584 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 584403341 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1476688 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3877200 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1290134813 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4431345 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 67169608 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 15631904 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.053925 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.225870 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 16651717 94.62% 94.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 947579 5.38% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14788958 94.61% 94.61% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 842944 5.39% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 17599300 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 23252082447 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 15631904 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20975087949 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 167523282 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 172744273 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8861086123 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8213479520 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7965231666 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 6968060036 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 218506693 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 203672612 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 656902733 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 547726569 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40332 # Transaction distribution -system.iobus.trans_dist::ReadResp 40332 # Transaction distribution -system.iobus.trans_dist::WriteReq 136631 # Transaction distribution -system.iobus.trans_dist::WriteResp 136631 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40379 # Transaction distribution +system.iobus.trans_dist::ReadResp 40379 # Transaction distribution +system.iobus.trans_dist::WriteReq 136662 # Transaction distribution +system.iobus.trans_dist::WriteResp 136662 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47802 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3000,13 +3025,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353926 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354082 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47822 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3019,13 +3044,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155843 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496841 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36933004 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497009 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37065503 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -3047,75 +3072,75 @@ system.iobus.reqLayer16.occupancy 13000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24511500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24279001 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36406001 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36411000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569333352 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569676929 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92805000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147958000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115627 # number of replacements -system.iocache.tags.tagsinuse 11.209625 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115614 # number of replacements +system.iocache.tags.tagsinuse 11.210449 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115643 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9156281985000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.417323 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.792302 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463583 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.237019 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.700602 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.838554 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.371895 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239910 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.460743 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.700653 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041036 # Number of tag accesses -system.iocache.tags.data_accesses 1041036 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1041054 # Number of tag accesses +system.iocache.tags.data_accesses 1041054 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8942 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115631 # number of demand (read+write) misses -system.iocache.demand_misses::total 115671 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses +system.iocache.demand_misses::total 115673 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115631 # number of overall misses -system.iocache.overall_misses::total 115671 # number of overall misses +system.iocache.overall_misses::realview.ide 115633 # number of overall misses +system.iocache.overall_misses::total 115673 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1786499757 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1791699757 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1855240026 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1860440026 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13185420595 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13185420595 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13135197903 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13135197903 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14971920352 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14977489352 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14990437929 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14996006929 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14971920352 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14977489352 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14990437929 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14996006929 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115631 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115671 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115631 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115671 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3130,52 +3155,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 200662.670673 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 200413.843065 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 208336.892308 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 208056.366137 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123542.281266 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 123542.281266 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123071.714105 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 123071.714105 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129480.159750 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129483.529597 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129638.061185 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129641.376371 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129480.159750 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129483.529597 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 39692 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 129638.061185 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129641.376371 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 43392 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3537 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3516 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.221939 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.341297 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115631 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115671 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115631 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115671 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1341349757 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1344699757 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1409990026 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1413340026 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7839860905 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7839860905 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7789853273 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7789853273 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9181210662 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9184779662 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9199843299 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9203412299 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9181210662 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9184779662 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9199843299 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9203412299 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3190,658 +3215,663 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150662.670673 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 150413.843065 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 158336.892308 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 158056.366137 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73456.458521 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73456.458521 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 72987.906388 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 72987.906388 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79400.944920 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79404.342160 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 79560.707575 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 79564.049510 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79400.944920 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79404.342160 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1712520 # number of replacements -system.l2c.tags.tagsinuse 65207.555116 # Cycle average of tags in use -system.l2c.tags.total_refs 7020190 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1774780 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.955527 # Average number of references to valid blocks. +system.iocache.overall_avg_mshr_miss_latency::realview.ide 79560.707575 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 79564.049510 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1186255 # number of replacements +system.l2c.tags.tagsinuse 65124.636684 # Cycle average of tags in use +system.l2c.tags.total_refs 6073175 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1247618 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.867816 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 3083323500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10815.100932 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 305.602667 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 366.195320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3964.024216 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 19638.791484 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14261.868883 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.853339 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 181.379081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3223.101636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5938.767305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6360.870252 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.165025 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004663 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.005588 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.060486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.299664 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217619 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002317 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002768 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049181 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.090618 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.097059 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994988 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11498 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 249 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50513 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1395 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 577 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9525 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 12698.793405 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 377.952725 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 459.111638 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5017.563285 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 20561.842939 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15825.160631 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.393148 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 11.333355 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4086.466074 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4153.822571 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1916.196912 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.193768 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005767 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.007005 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.076562 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.313749 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.241473 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000250 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000173 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.062355 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.063382 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029239 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993723 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11140 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 238 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49985 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 998 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 444 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9685 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2497 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4893 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42814 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.175446 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003799 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.770767 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 80570058 # Number of tag accesses -system.l2c.tags.data_accesses 80570058 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2973062 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2973062 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 212913 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 179277 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 392190 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 55777 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 49656 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 105433 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 53324 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56619 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109943 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12274 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4633 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 532793 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 642111 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 285366 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12502 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5292 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 506134 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 588825 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 298655 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2888585 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 133712 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 132940 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 266652 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 12274 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4633 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 532793 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 695435 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 285366 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5292 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 506134 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 645444 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 298655 # number of demand (read+write) hits -system.l2c.demand_hits::total 2998528 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 12274 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4633 # number of overall hits -system.l2c.overall_hits::cpu0.inst 532793 # number of overall hits -system.l2c.overall_hits::cpu0.data 695435 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 285366 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12502 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5292 # number of overall hits -system.l2c.overall_hits::cpu1.inst 506134 # number of overall hits -system.l2c.overall_hits::cpu1.data 645444 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 298655 # number of overall hits -system.l2c.overall_hits::total 2998528 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 25668 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 25681 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 51349 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 646 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 809 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1455 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 94289 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 48061 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142350 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3531 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3298 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 60576 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 185593 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 348444 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2063 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1546 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 53773 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 117277 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 240910 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 1017011 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 478287 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 112149 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 590436 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3531 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3298 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 60576 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 279882 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 348444 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2063 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1546 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 53773 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 165338 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 240910 # number of demand (read+write) misses -system.l2c.demand_misses::total 1159361 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3531 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3298 # number of overall misses -system.l2c.overall_misses::cpu0.inst 60576 # number of overall misses -system.l2c.overall_misses::cpu0.data 279882 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 348444 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2063 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1546 # number of overall misses -system.l2c.overall_misses::cpu1.inst 53773 # number of overall misses -system.l2c.overall_misses::cpu1.data 165338 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 240910 # number of overall misses -system.l2c.overall_misses::total 1159361 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 172222000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 155225500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 327447500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 9175000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5803000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 14978000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 10233917991 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5260660499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 15494578490 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 356299000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 337167500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6654556500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 20784674000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 53218202875 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 218154000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 160424000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6046329000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 13882177499 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 36908535986 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 138566520360 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu0.data 31590000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 32968000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::total 64558000 # number of InvalidateReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 356299000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 337167500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 6654556500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 31018591991 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 53218202875 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 218154000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 160424000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 6046329000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 19142837998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 36908535986 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 154061098850 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 356299000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 337167500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 6654556500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 31018591991 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 53218202875 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 218154000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 160424000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 6046329000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 19142837998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 36908535986 # number of overall miss cycles -system.l2c.overall_miss_latency::total 154061098850 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2973062 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2973062 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 238581 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 204958 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 443539 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 56423 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 50465 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 106888 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 147613 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 104680 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 252293 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15805 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7931 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 593369 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 827704 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 633810 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 14565 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6838 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 559907 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 706102 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 539565 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3905596 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 611999 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 245089 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 857088 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 15805 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7931 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 593369 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 975317 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 633810 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 14565 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6838 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 559907 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 810782 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 539565 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4157889 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 15805 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7931 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 593369 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 975317 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 633810 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 14565 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6838 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 559907 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 810782 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 539565 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4157889 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.107586 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.125299 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.115771 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.011449 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016031 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.013612 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.638758 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.459123 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.564225 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.223410 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.415837 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102088 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.224226 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.549761 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.141641 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.226089 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.096039 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.166091 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.446489 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.260398 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.781516 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.457585 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.688886 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.223410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.415837 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.102088 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.286965 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.549761 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.141641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.226089 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.096039 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.203924 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.446489 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.278834 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.223410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.415837 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.102088 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.286965 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.549761 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.141641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.226089 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.096039 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.203924 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.446489 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.278834 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6709.599501 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6044.371325 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6376.901205 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14202.786378 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7173.053152 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 10294.158076 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108537.772073 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109457.990866 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 108848.461468 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100905.975644 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 102233.929654 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109854.670166 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111990.613870 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 105746.000969 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103767.141009 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112441.727261 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 118370.844232 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 136248.792157 # average ReadSharedReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 66.048210 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 293.966063 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::total 109.339539 # average InvalidateReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100905.975644 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 102233.929654 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 109854.670166 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 110827.391511 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 105746.000969 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103767.141009 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 112441.727261 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 115780.026358 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 132884.493139 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100905.975644 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 102233.929654 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 109854.670166 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 110827.391511 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 105746.000969 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103767.141009 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 112441.727261 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 115780.026358 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 132884.493139 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 11042 # number of cycles access was blocked +system.l2c.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2186 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4431 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 43064 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.169983 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003632 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.762711 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 67662545 # Number of tag accesses +system.l2c.tags.data_accesses 67662545 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2448073 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2448073 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 187008 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 155703 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 342711 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 47244 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 46938 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 94182 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 49738 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 49766 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 99504 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 10294 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4584 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 491338 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 542857 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 273502 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11332 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5195 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 468446 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 501967 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 298805 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2608320 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 119780 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 141213 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 260993 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 10294 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4584 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 491338 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 592595 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 273502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 11332 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5195 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 468446 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 551733 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 298805 # number of demand (read+write) hits +system.l2c.demand_hits::total 2707824 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 10294 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4584 # number of overall hits +system.l2c.overall_hits::cpu0.inst 491338 # number of overall hits +system.l2c.overall_hits::cpu0.data 592595 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 273502 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 11332 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5195 # number of overall hits +system.l2c.overall_hits::cpu1.inst 468446 # number of overall hits +system.l2c.overall_hits::cpu1.data 551733 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 298805 # number of overall hits +system.l2c.overall_hits::total 2707824 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 26412 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 27413 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 53825 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 620 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 935 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1555 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 77626 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 34061 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 111687 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1740 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1751 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 53308 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 132778 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 218721 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 625 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 445 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 44267 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 69080 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 92227 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 614942 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 449753 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 95020 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 544773 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1740 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1751 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 53308 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 210404 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 218721 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 625 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 445 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 44267 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 103141 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 92227 # number of demand (read+write) misses +system.l2c.demand_misses::total 726629 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1740 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1751 # number of overall misses +system.l2c.overall_misses::cpu0.inst 53308 # number of overall misses +system.l2c.overall_misses::cpu0.data 210404 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 218721 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 625 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 445 # number of overall misses +system.l2c.overall_misses::cpu1.inst 44267 # number of overall misses +system.l2c.overall_misses::cpu1.data 103141 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 92227 # number of overall misses +system.l2c.overall_misses::total 726629 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 156600500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 179260000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 335860500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 7385500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7603500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 14989000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8419952993 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3811911998 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 12231864991 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 181407500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 181058000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5842083500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 15044752500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 31699112000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 72331000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 50453500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5031753500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 8306098000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 13356551793 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 79765601293 # number of ReadSharedReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu0.data 31743500 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu1.data 39384500 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::total 71128000 # number of InvalidateReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 181407500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 181058000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 5842083500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 23464705493 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 31699112000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 72331000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 50453500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 5031753500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 12118009998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 13356551793 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 91997466284 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 181407500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 181058000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 5842083500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 23464705493 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 31699112000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 72331000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 50453500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 5031753500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 12118009998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 13356551793 # number of overall miss cycles +system.l2c.overall_miss_latency::total 91997466284 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 2448073 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2448073 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 213420 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 183116 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 396536 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 47864 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 47873 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 95737 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 127364 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 83827 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 211191 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 12034 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6335 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 544646 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 675635 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 492223 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 11957 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5640 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 512713 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 571047 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 391032 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 3223262 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 569533 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 236233 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 805766 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 12034 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6335 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 544646 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 802999 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 492223 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 11957 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5640 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 512713 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 654874 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 391032 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3434453 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 12034 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6335 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 544646 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 802999 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 492223 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 11957 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5640 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 512713 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 654874 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 391032 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3434453 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.123756 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.149703 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.135738 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.012953 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.019531 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.016242 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.609481 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.406325 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.528844 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.144590 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.276401 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.097876 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.196523 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.444353 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.052271 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.078901 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.086339 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.120971 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.235855 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.190783 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.789687 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.402230 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.676093 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.144590 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.276401 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.097876 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.262023 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.444353 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.052271 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.078901 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.086339 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.157497 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.235855 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.211571 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.144590 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.276401 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.097876 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.262023 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.444353 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.052271 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.078901 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.086339 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.157497 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.235855 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.211571 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5929.142057 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6539.233211 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6239.860660 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11912.096774 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8132.085561 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 9639.228296 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108468.206439 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 111914.271395 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 109519.147179 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 104257.183908 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 103402.627070 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109591.121408 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 113307.569778 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 144929.439789 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 115729.600000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 113378.651685 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113668.274335 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 120238.824551 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 144822.576827 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 129712.397743 # average ReadSharedReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 70.579852 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 414.486424 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::total 130.564474 # average InvalidateReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 104257.183908 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 103402.627070 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 109591.121408 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 111522.145458 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 144929.439789 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 115729.600000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 113378.651685 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 113668.274335 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 117489.747026 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 144822.576827 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 126608.580560 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 104257.183908 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 103402.627070 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 109591.121408 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 111522.145458 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 144929.439789 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 115729.600000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 113378.651685 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 113668.274335 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 117489.747026 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 144822.576827 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 126608.580560 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 2054 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 109 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 36 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 101.302752 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 57.055556 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1306567 # number of writebacks -system.l2c.writebacks::total 1306567 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 94 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 23 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 174 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 24 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 315 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 94 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 174 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 94 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 174 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 315 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 73117 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 73117 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 25668 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 25681 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 51349 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 646 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 809 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1455 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 94289 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 48061 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 142350 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3531 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3298 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 60482 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 185570 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 348444 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2063 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1546 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 53599 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 117253 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 240910 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 1016696 # number of ReadSharedReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu0.data 478287 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu1.data 112149 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::total 590436 # number of InvalidateReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 3531 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3298 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 60482 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 279859 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 348444 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2063 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1546 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 53599 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 165314 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 240910 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1159046 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 3531 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3298 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 60482 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 279859 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 348444 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2063 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1546 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 53599 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 165314 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 240910 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1159046 # number of overall MSHR misses +system.l2c.writebacks::writebacks 916327 # number of writebacks +system.l2c.writebacks::total 916327 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 108 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 101 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 252 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 108 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 101 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 252 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 108 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 101 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 252 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 42778 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 42778 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 26412 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 27413 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 53825 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 620 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 935 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1555 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 77626 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 34061 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 111687 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1739 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1751 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 53200 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 132753 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 218721 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 625 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 445 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44166 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 69063 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 92227 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 614690 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu0.data 449753 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 95020 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 544773 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1739 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1751 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 53200 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 210379 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 218721 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 625 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 445 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 44166 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 103124 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 92227 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 726377 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1739 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1751 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 53200 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 210379 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 218721 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 625 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 445 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 44166 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 103124 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 92227 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 726377 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16022 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 21289 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 59629 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38211 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22626 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 60008 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17403 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 21158 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38561 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33425 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 40699 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 97840 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 520949500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 534002500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1054952000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15625500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19999000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 35624500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9290880791 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4779832460 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 14070713251 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 320987004 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 304187500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6041672064 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 18926430190 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 49733607723 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 197523002 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 144964000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5494647043 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 12706523221 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 34499199531 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 128369741278 # number of ReadSharedReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11811554063 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2326727500 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::total 14138281563 # number of InvalidateReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 320987004 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 304187500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 6041672064 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 28217310981 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 49733607723 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197523002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 144964000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 5494647043 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 17486355681 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 34499199531 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 142440454529 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 320987004 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 304187500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 6041672064 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 28217310981 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 49733607723 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197523002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 144964000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 5494647043 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 17486355681 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 34499199531 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 142440454529 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 43784 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 98569 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 531562000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 578264000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1109826000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15032500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22996000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 38028500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7643531840 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3471120868 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 11114652708 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 163920001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 163546503 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5300161563 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 13714460643 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 29511745867 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 66080002 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 46003500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4581236045 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 7611577636 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 12434204472 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 73592936232 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11245662562 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1996724000 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 13242386562 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 163920001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 163546503 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 5300161563 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 21357992483 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 29511745867 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 66080002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 46003500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 4581236045 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 11082698504 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 12434204472 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 84707588940 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 163920001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 163546503 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 5300161563 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 21357992483 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 29511745867 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 66080002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 46003500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 4581236045 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 11082698504 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 12434204472 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 84707588940 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2691376000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2535460001 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5368000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3243740000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7424669500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3419647503 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7444661004 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2691376000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2535460001 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5368000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3243740000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 7424669500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3419647503 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 7444661004 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.107586 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.125299 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.115771 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.011449 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016031 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.013612 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.638758 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.459123 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.564225 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.224199 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166057 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260318 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.781516 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.457585 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.688886 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.286942 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.203895 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.278758 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.286942 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.203895 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.278758 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20295.679445 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20793.680153 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20544.742838 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24188.080495 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24720.642769 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24484.192440 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98536.210915 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99453.454152 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 98845.895687 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101990.786172 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108368.427426 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126261.676330 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24695.536494 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20746.752089 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23945.493776 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100826.884185 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105776.617110 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 122894.565469 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100826.884185 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105776.617110 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 122894.565469 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.123756 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.149703 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.135738 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012953 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.019531 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.016242 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.609481 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.406325 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.528844 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.144507 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.276401 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.097678 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.196486 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444353 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.052271 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.078901 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086142 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.120941 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.235855 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.190704 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.789687 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.402230 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.676093 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.144507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.276401 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.261992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444353 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.052271 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.078901 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.086142 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.157472 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.235855 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.211497 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.144507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.276401 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.261992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444353 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.052271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.078901 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.086142 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.157472 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.235855 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.211497 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20125.776162 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21094.517200 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20619.154668 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24245.967742 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24594.652406 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24455.627010 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98466.130420 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 101908.953583 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 99516.082516 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 94261.070155 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93401.772130 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99627.097049 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 103308.103342 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 134928.725943 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 105728.003200 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 103378.651685 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103727.664833 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 110212.090931 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134821.738450 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 119723.659458 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 25004.085714 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 21013.723427 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24308.081645 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 94261.070155 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93401.772130 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99627.097049 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 101521.503967 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 134928.725943 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 105728.003200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 103378.651685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103727.664833 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 107469.633684 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134821.738450 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 116616.562666 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 94261.070155 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93401.772130 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99627.097049 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 101521.503967 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 134928.725943 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 105728.003200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 103378.651685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103727.664833 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 107469.633684 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134821.738450 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 116616.562666 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158502.709069 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158248.658158 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152366.950068 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124514.405742 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 151137.960886 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124061.141914 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75218.020737 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75855.198235 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 79700.729748 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 75885.828904 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 4262418 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2509154 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3063 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 78102.674561 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 75527.407238 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3300545 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2017233 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3015 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 59629 # Transaction distribution -system.membus.trans_dist::ReadResp 1085265 # Transaction distribution -system.membus.trans_dist::WriteReq 38211 # Transaction distribution -system.membus.trans_dist::WriteResp 38211 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1413261 # Transaction distribution -system.membus.trans_dist::CleanEvict 284296 # Transaction distribution -system.membus.trans_dist::UpgradeReq 353595 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 284030 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 60008 # Transaction distribution +system.membus.trans_dist::ReadResp 683640 # Transaction distribution +system.membus.trans_dist::WriteReq 38561 # Transaction distribution +system.membus.trans_dist::WriteResp 38561 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1023021 # Transaction distribution +system.membus.trans_dist::CleanEvict 202426 # Transaction distribution +system.membus.trans_dist::UpgradeReq 359792 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 266371 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::ReadExReq 155418 # Transaction distribution -system.membus.trans_dist::ReadExResp 141619 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1025636 # Transaction distribution -system.membus.trans_dist::InvalidateReq 695069 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 125029 # Transaction distribution +system.membus.trans_dist::ReadExResp 110917 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 623632 # Transaction distribution +system.membus.trans_dist::InvalidateReq 649188 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122736 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5185454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5333270 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238137 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238137 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5571407 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3790913 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3940187 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4178311 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155843 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 158067712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 158274271 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7266112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 165540383 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 598647 # Total snoops (count) -system.membus.snoopTraffic 181312 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2611590 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013385 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.114916 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52924 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 105399040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 105608363 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7265984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7265984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 112874347 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 584671 # Total snoops (count) +system.membus.snoopTraffic 181568 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2122585 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015284 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.122681 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2576634 98.66% 98.66% # Request fanout histogram -system.membus.snoop_fanout::1 34956 1.34% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2090143 98.47% 98.47% # Request fanout histogram +system.membus.snoop_fanout::1 32442 1.53% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2611590 # Request fanout histogram -system.membus.reqLayer0.occupancy 98274995 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2122585 # Request fanout histogram +system.membus.reqLayer0.occupancy 98177996 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20993495 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22142995 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9731390131 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7123082230 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6232103011 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3974452270 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45620246 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45639777 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3884,82 +3914,83 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12430379 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6756092 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1976828 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 231635 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 213178 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 18457 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 59631 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4752657 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38211 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38211 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4279629 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2861492 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 742959 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 389463 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1132422 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 304770 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 304770 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4693673 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 888953 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 857088 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10167135 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8009990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18177125 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 258318649 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198738470 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 457057119 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3168754 # Total snoops (count) -system.toL2Bus.snoopTraffic 137382864 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8831298 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.353414 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.482382 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10730258 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5842336 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1839840 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 143689 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 131126 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 12563 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384923997000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 60010 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4055865 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38561 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38561 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3364400 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2413469 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 699420 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 360553 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1059973 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 190 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 190 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262551 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262551 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3996472 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 835150 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 805766 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8799068 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6846513 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15645581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 216011198 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 161148653 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 377159851 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2609772 # Total snoops (count) +system.toL2Bus.snoopTraffic 111390096 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7440116 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.386181 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.490329 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5728650 64.87% 64.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3084191 34.92% 99.79% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 18457 0.21% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4579449 61.55% 61.55% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2848104 38.28% 99.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 12563 0.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8831298 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9716591105 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7440116 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8239335116 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2596400 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2574912 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4626263938 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4018530287 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3958447661 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3394272097 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5035 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 5012 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13834 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 13327 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 2bd86426a..400af0c45 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.558698 # Number of seconds simulated -sim_ticks 51558697863000 # Number of ticks simulated -final_tick 51558697863000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.558690 # Number of seconds simulated +sim_ticks 51558690384000 # Number of ticks simulated +final_tick 51558690384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167711 # Simulator instruction rate (inst/s) -host_op_rate 197118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7760882097 # Simulator tick rate (ticks/s) -host_mem_usage 692228 # Number of bytes of host memory used -host_seconds 6643.41 # Real time elapsed on the host -sim_insts 1114173091 # Number of instructions simulated -sim_ops 1309536110 # Number of ops (including micro ops) simulated +host_inst_rate 207581 # Simulator instruction rate (inst/s) +host_op_rate 243983 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9602431196 # Simulator tick rate (ticks/s) +host_mem_usage 695472 # Number of bytes of host memory used +host_seconds 5369.34 # Real time elapsed on the host +sim_insts 1114574366 # Number of instructions simulated +sim_ops 1310024478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 691712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 570944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6573600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 114559048 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428096 # Number of bytes read from this memory -system.physmem.bytes_read::total 122823400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6573600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6573600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 143392768 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 681408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 573376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6481504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112175560 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 429184 # Number of bytes read from this memory +system.physmem.bytes_read::total 120341032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6481504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6481504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 141267776 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 143413348 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 118665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1789998 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6689 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1935081 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2240512 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 141288356 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10647 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 117226 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1752756 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6706 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1896294 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2207309 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2243085 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 13416 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 11074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 127497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2221915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2382205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 127497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 127497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2781156 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 2209882 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 13216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 11121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 125711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2175687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2334059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 125711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 125711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2739941 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2781555 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2781156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 13416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 11074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 127497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2222314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5163760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1935081 # Number of read requests accepted -system.physmem.writeReqs 2243085 # Number of write requests accepted -system.physmem.readBursts 1935081 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2243085 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 123796992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 48192 # Total number of bytes read from write queue -system.physmem.bytesWritten 143410368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 122823400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 143413348 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 753 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2282 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 2740340 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2739941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 13216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 11121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 125711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2176086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5074399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1896294 # Number of read requests accepted +system.physmem.writeReqs 2209882 # Number of write requests accepted +system.physmem.readBursts 1896294 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2209882 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 121325696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue +system.physmem.bytesWritten 141284736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 120341032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 141288356 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114857 # Per bank write bursts -system.physmem.perBankRdBursts::1 123887 # Per bank write bursts -system.physmem.perBankRdBursts::2 121380 # Per bank write bursts -system.physmem.perBankRdBursts::3 115864 # Per bank write bursts -system.physmem.perBankRdBursts::4 115150 # Per bank write bursts -system.physmem.perBankRdBursts::5 124779 # Per bank write bursts -system.physmem.perBankRdBursts::6 116343 # Per bank write bursts -system.physmem.perBankRdBursts::7 120532 # Per bank write bursts -system.physmem.perBankRdBursts::8 117169 # Per bank write bursts -system.physmem.perBankRdBursts::9 147715 # Per bank write bursts -system.physmem.perBankRdBursts::10 116324 # Per bank write bursts -system.physmem.perBankRdBursts::11 125031 # Per bank write bursts -system.physmem.perBankRdBursts::12 116553 # Per bank write bursts -system.physmem.perBankRdBursts::13 122187 # Per bank write bursts -system.physmem.perBankRdBursts::14 118707 # Per bank write bursts -system.physmem.perBankRdBursts::15 117850 # Per bank write bursts -system.physmem.perBankWrBursts::0 135590 # Per bank write bursts -system.physmem.perBankWrBursts::1 141676 # Per bank write bursts -system.physmem.perBankWrBursts::2 140587 # Per bank write bursts -system.physmem.perBankWrBursts::3 138605 # Per bank write bursts -system.physmem.perBankWrBursts::4 137623 # Per bank write bursts -system.physmem.perBankWrBursts::5 144276 # Per bank write bursts -system.physmem.perBankWrBursts::6 136529 # Per bank write bursts -system.physmem.perBankWrBursts::7 140386 # Per bank write bursts -system.physmem.perBankWrBursts::8 138327 # Per bank write bursts -system.physmem.perBankWrBursts::9 145050 # Per bank write bursts -system.physmem.perBankWrBursts::10 137213 # Per bank write bursts -system.physmem.perBankWrBursts::11 144076 # Per bank write bursts -system.physmem.perBankWrBursts::12 138694 # Per bank write bursts -system.physmem.perBankWrBursts::13 142077 # Per bank write bursts -system.physmem.perBankWrBursts::14 140963 # Per bank write bursts -system.physmem.perBankWrBursts::15 139115 # Per bank write bursts +system.physmem.perBankRdBursts::0 112674 # Per bank write bursts +system.physmem.perBankRdBursts::1 120331 # Per bank write bursts +system.physmem.perBankRdBursts::2 120633 # Per bank write bursts +system.physmem.perBankRdBursts::3 114638 # Per bank write bursts +system.physmem.perBankRdBursts::4 113111 # Per bank write bursts +system.physmem.perBankRdBursts::5 123581 # Per bank write bursts +system.physmem.perBankRdBursts::6 115477 # Per bank write bursts +system.physmem.perBankRdBursts::7 120263 # Per bank write bursts +system.physmem.perBankRdBursts::8 112291 # Per bank write bursts +system.physmem.perBankRdBursts::9 145720 # Per bank write bursts +system.physmem.perBankRdBursts::10 114582 # Per bank write bursts +system.physmem.perBankRdBursts::11 120005 # Per bank write bursts +system.physmem.perBankRdBursts::12 112695 # Per bank write bursts +system.physmem.perBankRdBursts::13 118645 # Per bank write bursts +system.physmem.perBankRdBursts::14 113317 # Per bank write bursts +system.physmem.perBankRdBursts::15 117751 # Per bank write bursts +system.physmem.perBankWrBursts::0 133340 # Per bank write bursts +system.physmem.perBankWrBursts::1 139177 # Per bank write bursts +system.physmem.perBankWrBursts::2 138321 # Per bank write bursts +system.physmem.perBankWrBursts::3 137224 # Per bank write bursts +system.physmem.perBankWrBursts::4 136590 # Per bank write bursts +system.physmem.perBankWrBursts::5 143143 # Per bank write bursts +system.physmem.perBankWrBursts::6 136203 # Per bank write bursts +system.physmem.perBankWrBursts::7 139934 # Per bank write bursts +system.physmem.perBankWrBursts::8 134977 # Per bank write bursts +system.physmem.perBankWrBursts::9 143618 # Per bank write bursts +system.physmem.perBankWrBursts::10 135619 # Per bank write bursts +system.physmem.perBankWrBursts::11 140132 # Per bank write bursts +system.physmem.perBankWrBursts::12 134815 # Per bank write bursts +system.physmem.perBankWrBursts::13 138770 # Per bank write bursts +system.physmem.perBankWrBursts::14 136807 # Per bank write bursts +system.physmem.perBankWrBursts::15 138904 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 498 # Number of times write queue was full causing retry -system.physmem.totGap 51558696478500 # Total gap between requests +system.physmem.numWrRetry 518 # Number of times write queue was full causing retry +system.physmem.totGap 51558689064500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1913796 # Read request sizes (log2) +system.physmem.readPktSize::6 1875009 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2240512 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1142122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 697940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2207309 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1116053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 690517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23803 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,88 +160,88 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 36011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 84715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 118224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 127097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 131612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 133869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 139104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 141132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 137785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 140939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 143104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 134560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 133279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 134737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 146876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 129080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 132587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 28211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 83457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 116558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 125148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 129368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 131713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 136998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 138946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 135798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 138971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 141020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 132458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 131167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 132874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 144896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 126854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 129875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2565 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 2532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1973 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 1548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1141 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 951139 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.933676 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.585937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.458614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 376624 39.60% 39.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 238014 25.02% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 91172 9.59% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 53576 5.63% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 39458 4.15% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 27371 2.88% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21519 2.26% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17750 1.87% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 85655 9.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 951139 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 118362 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.342416 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 51.876252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 118357 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 1272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1209 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 930002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 282.376133 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.748609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.895017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 369309 39.71% 39.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 231862 24.93% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88277 9.49% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51814 5.57% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37452 4.03% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26213 2.82% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21092 2.27% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17823 1.92% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 86160 9.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 930002 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 116289 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.301748 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 52.348914 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 116283 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 118362 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 118362 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.931642 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.417353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.979781 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 114164 96.45% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 1862 1.57% 98.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 1234 1.04% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 621 0.52% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 196 0.17% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 102 0.09% 99.85% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 116289 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 116288 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.983653 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.436820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 18.158845 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 112077 96.38% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 1857 1.60% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 1248 1.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 622 0.53% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 199 0.17% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 102 0.09% 99.84% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-223 42 0.04% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-255 35 0.03% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-287 40 0.03% 99.94% # Writes before turning the bus around for reads @@ -259,68 +259,68 @@ system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Wr system.physmem.wrPerTurnAround::864-895 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::1024-1055 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 118362 # Writes before turning the bus around for reads -system.physmem.totQLat 71570448504 # Total ticks spent queuing -system.physmem.totMemAccLat 107839098504 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9671640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37000.16 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 116288 # Writes before turning the bus around for reads +system.physmem.totQLat 70130172482 # Total ticks spent queuing +system.physmem.totMemAccLat 105674809982 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9478570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36994.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55750.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 55744.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.74 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.69 # Average write queue length when enqueuing -system.physmem.readRowHits 1560611 # Number of row buffer hits during reads -system.physmem.writeRowHits 1663363 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.23 # Row buffer hit rate for writes -system.physmem.avgGap 12340030.64 # Average gap between requests -system.physmem.pageHitRate 77.22 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3363189900 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1787570235 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6802934880 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5821719840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 51899586960.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 51612190140 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3200334720 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 101759183310 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 76295730720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12252381205680 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12554961718635 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.508122 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51437094541003 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 5396479999 # Time in different power states -system.physmem_0.memoryStateTime::REF 22052840000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51015251458000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 198686963242 # Time in different power states -system.physmem_0.memoryStateTime::ACT 94153955748 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 223156166011 # Time in different power states -system.physmem_1.actEnergy 3427956840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1822002270 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7008167040 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5875188300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 53218604400.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 52383682290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3161186880 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 106497624090 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 77662512480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12248740584255 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12559836053265 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.602662 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51435493097538 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5216830750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22612324000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 50999709861500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 202245988185 # Time in different power states -system.physmem_1.memoryStateTime::ACT 95365744212 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 233547114353 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.06 # Average write queue length when enqueuing +system.physmem.readRowHits 1529656 # Number of row buffer hits during reads +system.physmem.writeRowHits 1643629 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.45 # Row buffer hit rate for writes +system.physmem.avgGap 12556375.83 # Average gap between requests +system.physmem.pageHitRate 77.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3321699360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1765517490 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6716655120 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5762509380 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 51680160480.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 50972480280 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3129835680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 101675150490 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 76210464000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12252798333465 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12554072367525 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.490909 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51438669732358 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5228340749 # Time in different power states +system.physmem_0.memoryStateTime::REF 21959504000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51017233392500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 198464631937 # Time in different power states +system.physmem_0.memoryStateTime::ACT 92832806893 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 222971707921 # Time in different power states +system.physmem_1.actEnergy 3318507780 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1763828715 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6818742840 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5761011240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 51892211280.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 51236173110 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3081583200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 102800614920 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 76208995200 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12252080918985 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12555002532930 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.508949 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51438215485769 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5081473992 # Time in different power states +system.physmem_1.memoryStateTime::REF 22049198000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51014315527500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 198460418659 # Time in different power states +system.physmem_1.memoryStateTime::ACT 93344226239 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 225439539610 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -337,30 +337,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 292003156 # Number of BP lookups -system.cpu.branchPred.condPredicted 199825428 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13707860 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 209782047 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131422635 # Number of BTB hits +system.cpu.branchPred.lookups 292068322 # Number of BP lookups +system.cpu.branchPred.condPredicted 199851600 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13713135 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 209724607 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131462172 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.647227 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37743675 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 403344 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 8164760 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6089475 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2075285 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 798713 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.683237 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37751449 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 403092 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 8173057 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6085508 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2087549 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 802881 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,90 +390,91 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 1433016 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1433016 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 32195 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277777 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 671696 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 761320 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2826.976830 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 21785.764506 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 754204 99.07% 99.07% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4652 0.61% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 981 0.13% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 445 0.06% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 347 0.05% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 34 0.00% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 244 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 36 0.00% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 13 0.00% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 353 0.05% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 1435892 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1435892 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 31985 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277981 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 675717 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 760175 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2830.191074 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 21829.241774 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 752984 99.05% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4669 0.61% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 1022 0.13% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 473 0.06% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 342 0.04% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.00% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 237 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 34 0.00% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 14 0.00% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 355 0.05% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::917504-983039 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 761320 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 803371 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 26077.733077 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21137.704877 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20668.738137 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-131071 799705 99.54% 99.54% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-262143 2825 0.35% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-393215 589 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-524287 118 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-655359 123 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-786431 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::786432-917503 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::1.17965e+06-1.31072e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 803371 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1075651264316 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.736998 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.521821 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1071482592816 99.61% 99.61% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2636080000 0.25% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 763976000 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 297116500 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 205516000 0.02% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 123566500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 47691000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 91565500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 3134000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 3000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1075651264316 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 277778 89.61% 89.61% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 32195 10.39% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 309973 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1433016 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::786432-851967 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 760175 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 806276 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26170.477603 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21293.851875 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20136.943306 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 787717 97.70% 97.70% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 14855 1.84% 99.54% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1801 0.22% 99.76% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 1099 0.14% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 441 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 139 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 81 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 59 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 68 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 806276 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1071348818020 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.742300 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.520529 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1067163432520 99.61% 99.61% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2639718000 0.25% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 767294500 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 303032500 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 205205000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 125461000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 48256000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 92861500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 3532500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 24500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1071348818020 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 277982 89.68% 89.68% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 31985 10.32% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 309967 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1435892 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1433016 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309973 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1435892 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309967 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309973 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1742989 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309967 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1745859 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 218874380 # DTB read hits -system.cpu.dtb.read_misses 1009020 # DTB read misses -system.cpu.dtb.write_hits 193682033 # DTB write hits -system.cpu.dtb.write_misses 423996 # DTB write misses +system.cpu.dtb.read_hits 219013119 # DTB read hits +system.cpu.dtb.read_misses 1011306 # DTB read misses +system.cpu.dtb.write_hits 193770026 # DTB write hits +system.cpu.dtb.write_misses 424586 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 89021 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 108 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 17262 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 88767 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 111 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 16184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 85593 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 219883400 # DTB read accesses -system.cpu.dtb.write_accesses 194106029 # DTB write accesses +system.cpu.dtb.perms_faults 85758 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 220024425 # DTB read accesses +system.cpu.dtb.write_accesses 194194612 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 412556413 # DTB hits -system.cpu.dtb.misses 1433016 # DTB misses -system.cpu.dtb.accesses 413989429 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 412783145 # DTB hits +system.cpu.dtb.misses 1435892 # DTB misses +system.cpu.dtb.accesses 414219037 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -503,947 +504,953 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 178466 # Table walker walks requested -system.cpu.itb.walker.walksLong 178466 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1508 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 129505 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 20095 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 158371 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1754.443680 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 17709.281636 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-65535 157140 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-131071 1047 0.66% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-196607 42 0.03% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-327679 14 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-393215 7 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::524288-589823 40 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::589824-655359 48 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 158371 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 151108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29265.005824 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23190.077140 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 30431.733671 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 145001 95.96% 95.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 5046 3.34% 99.30% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 391 0.26% 99.56% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 366 0.24% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 100 0.07% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 51 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 8 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 85 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 178617 # Table walker walks requested +system.cpu.itb.walker.walksLong 178617 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1509 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 129197 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 20173 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 158444 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1791.778168 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 17776.926489 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-65535 157195 99.21% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-131071 1061 0.67% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-196607 49 0.03% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-262143 23 0.01% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-393215 12 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-458751 2 0.00% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::524288-589823 45 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::589824-655359 46 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 158444 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 150879 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29477.399108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23380.752932 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 29925.423831 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 144789 95.96% 95.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 5035 3.34% 99.30% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 407 0.27% 99.57% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 355 0.24% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 85 0.06% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 65 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 23 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 82 0.05% 99.98% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::655360-720895 8 0.01% 99.98% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::720896-786431 24 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 151108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 912439402568 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.949255 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.219812 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 46367810152 5.08% 5.08% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 866006867916 94.91% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 63907500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 568000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 249000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 912439402568 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 129505 98.85% 98.85% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1508 1.15% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 131013 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 150879 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 908136653272 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.948518 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.221299 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 46816690152 5.16% 5.16% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 861256760620 94.84% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 62690500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 511000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 908136653272 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 129197 98.85% 98.85% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1509 1.15% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 130706 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178466 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 178466 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178617 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 178617 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 131013 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 131013 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 309479 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 465485773 # ITB inst hits -system.cpu.itb.inst_misses 178466 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130706 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 130706 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 309323 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 465622680 # ITB inst hits +system.cpu.itb.inst_misses 178617 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 62647 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 62354 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 443320 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 442443 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 465664239 # ITB inst accesses -system.cpu.itb.hits 465485773 # DTB hits -system.cpu.itb.misses 178466 # DTB misses -system.cpu.itb.accesses 465664239 # DTB accesses -system.cpu.numPwrStateTransitions 34324 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 17162 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 2940404395.507225 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 58760863847.973442 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7839 45.68% 45.68% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.12% 99.80% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 465801297 # ITB inst accesses +system.cpu.itb.hits 465622680 # DTB hits +system.cpu.itb.misses 178617 # DTB misses +system.cpu.itb.accesses 465801297 # DTB accesses +system.cpu.numPwrStateTransitions 34330 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 17165 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2940001446.310807 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 58531807829.842911 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7841 45.68% 45.68% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.11% 99.79% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988780801904 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 17162 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1095477627305 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50463220235695 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2190964579 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 17165 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1093565558075 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50465124825925 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2187140442 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 794033282 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1302230220 # Number of instructions fetch has processed -system.cpu.fetch.Branches 292003156 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 175255785 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1304336456 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29502488 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4651258 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26755 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11711903 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1225327 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 1089 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 465024484 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6899822 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 52313 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2130737314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.716190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.134027 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 793785781 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1302631708 # Number of instructions fetch has processed +system.cpu.fetch.Branches 292068322 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 175299129 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1300965183 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29519562 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4657753 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 25879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11707627 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1236073 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 927 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 465162073 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6904477 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 52597 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2127139004 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.717629 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.134701 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1403414987 65.87% 65.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 283475853 13.30% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 89003023 4.18% 83.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 354843451 16.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1399565872 65.80% 65.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 283601888 13.33% 79.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 89018844 4.18% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 354952400 16.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2130737314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133276 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.594364 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 615599644 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 888388322 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542818505 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73189293 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10741550 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41458105 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4067803 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1416661162 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 33069720 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10741550 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 678370602 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 94749069 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 569457122 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 557397759 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220021212 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1392357267 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 8139910 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7467928 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 990269 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1135391 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 140197147 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22858 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1342242693 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2216016664 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1651872272 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1433815 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1263306379 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78936311 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44081382 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39609601 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160762582 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 223936207 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 198122558 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12861166 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11120462 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1339067750 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44403277 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1369076757 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4228585 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 73934913 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42101353 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 368543 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2130737314 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.642537 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.913709 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2127139004 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133539 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.595587 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 615428593 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 884736584 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 543030027 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 73193860 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10749940 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41477613 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4067608 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1417243244 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 33090232 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10749940 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 678230325 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 91937865 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 569242294 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 557610269 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219368311 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1392930802 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 8136567 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7440637 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 990068 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1113298 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 139552598 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22837 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1342716381 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2216807318 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1652527627 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1431919 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1263732146 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78984232 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44095214 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39617186 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160769192 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 224047664 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 198221089 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12872997 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11132343 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1339626168 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 44413765 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1369656198 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4234304 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 74015451 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 42135581 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 368828 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2127139004 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.643896 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.914248 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1278640571 60.01% 60.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 452467629 21.24% 81.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 292658965 13.74% 94.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96618652 4.53% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10322243 0.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29254 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1274738634 59.93% 59.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 452592629 21.28% 81.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 292740987 13.76% 94.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96714663 4.55% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10322849 0.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29242 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2130737314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2127139004 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 74049078 33.84% 33.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90108 0.04% 33.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26756 0.01% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 482 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 59033401 26.97% 60.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 85651168 39.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 74109343 33.81% 33.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90161 0.04% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26765 0.01% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 458 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 59034015 26.93% 60.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 85210307 38.88% 99.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 64791 0.03% 99.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 640346 0.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 55 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 945875031 69.09% 69.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2941932 0.21% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 129428 0.01% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 946221695 69.08% 69.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2942835 0.21% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 130438 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 381 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 112221 0.01% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 112188 0.01% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 223931934 16.36% 85.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 196085738 14.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 223953856 16.35% 85.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 195515958 14.27% 99.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 118365 0.01% 99.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 660412 0.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1369076757 # Type of FU issued -system.cpu.iq.rate 0.624874 # Inst issue rate -system.cpu.iq.fu_busy_cnt 218850993 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.159853 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5089559021 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1456673430 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1346855595 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2411384 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 915419 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 886368 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1586411072 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1516623 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5720273 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1369656198 # Type of FU issued +system.cpu.iq.rate 0.626231 # Inst issue rate +system.cpu.iq.fu_busy_cnt 219176186 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.160023 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5087371498 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1457327579 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1347394357 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2490391 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 913879 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 884967 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1587235373 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1596980 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5732534 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17413416 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22608 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 184689 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8002869 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17426729 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22539 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 187787 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8018407 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3613750 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2051788 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3639533 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2053743 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10741550 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13180703 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5272349 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1383757283 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10749940 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12646274 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5267578 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1384326807 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 223936207 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 198122558 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39070088 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 183909 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4898355 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 184689 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4057329 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6115164 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10172493 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1355379185 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 218880930 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12294353 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 224047664 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 198221089 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39077844 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 183202 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4894696 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 187787 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4060868 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6118781 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10179649 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1355949241 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 219017773 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12300796 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 286256 # number of nop insts executed -system.cpu.iew.exec_refs 412572980 # number of memory reference insts executed -system.cpu.iew.exec_branches 257403074 # Number of branches executed -system.cpu.iew.exec_stores 193692050 # Number of stores executed -system.cpu.iew.exec_rate 0.618622 # Inst execution rate -system.cpu.iew.wb_sent 1348783541 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1347741963 # cumulative count of insts written-back -system.cpu.iew.wb_producers 576070929 # num instructions producing a value -system.cpu.iew.wb_consumers 948341211 # num instructions consuming a value -system.cpu.iew.wb_rate 0.615136 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.607451 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 63015193 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 44034734 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9698166 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2116507295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.618725 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.263721 # Number of insts commited each cycle +system.cpu.iew.exec_nop 286874 # number of nop insts executed +system.cpu.iew.exec_refs 412797364 # number of memory reference insts executed +system.cpu.iew.exec_branches 257488143 # Number of branches executed +system.cpu.iew.exec_stores 193779591 # Number of stores executed +system.cpu.iew.exec_rate 0.619964 # Inst execution rate +system.cpu.iew.wb_sent 1349320641 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1348279324 # cumulative count of insts written-back +system.cpu.iew.wb_producers 576318139 # num instructions producing a value +system.cpu.iew.wb_consumers 948680474 # num instructions consuming a value +system.cpu.iew.wb_rate 0.616458 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.607494 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 63090267 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 44044937 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9703294 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2112894773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.620014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.265043 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1435626131 67.83% 67.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 397528537 18.78% 86.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150810671 7.13% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44606790 2.11% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36101901 1.71% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18021060 0.85% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 11293216 0.53% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5858251 0.28% 99.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16660738 0.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1431908907 67.77% 67.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 397571073 18.82% 86.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150815124 7.14% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44594147 2.11% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36107553 1.71% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18031210 0.85% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 11307158 0.54% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5865302 0.28% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16694299 0.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2116507295 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1114173091 # Number of instructions committed -system.cpu.commit.committedOps 1309536110 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2112894773 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1114574366 # Number of instructions committed +system.cpu.commit.committedOps 1310024478 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 396642479 # Number of memory references committed -system.cpu.commit.loads 206522790 # Number of loads committed -system.cpu.commit.membars 9192719 # Number of memory barriers committed -system.cpu.commit.branches 249090207 # Number of branches committed -system.cpu.commit.fp_insts 874521 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1196753296 # Number of committed integer instructions. -system.cpu.commit.function_calls 31104441 # Number of function calls committed. +system.cpu.commit.refs 396823616 # Number of memory references committed +system.cpu.commit.loads 206620934 # Number of loads committed +system.cpu.commit.membars 9197183 # Number of memory barriers committed +system.cpu.commit.branches 249169048 # Number of branches committed +system.cpu.commit.fp_insts 873305 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1197213012 # Number of committed integer instructions. +system.cpu.commit.function_calls 31117535 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 910131481 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2552727 0.19% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 103687 0.01% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 910437285 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2553089 0.19% 69.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 104752 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 8 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 13 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 21 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 105694 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 105694 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 206522790 15.77% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 190119689 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 206508219 15.76% 85.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 189547828 14.47% 99.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 112715 0.01% 99.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 654854 0.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1309536110 # Class of committed instruction -system.cpu.commit.bw_lim_events 16660738 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3462896243 # The number of ROB reads -system.cpu.rob.rob_writes 2759222856 # The number of ROB writes -system.cpu.timesIdled 9103079 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 60227265 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100926431181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1114173091 # Number of Instructions Simulated -system.cpu.committedOps 1309536110 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.966449 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.966449 # CPI: Total CPI of All Threads -system.cpu.ipc 0.508531 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.508531 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1609897597 # number of integer regfile reads -system.cpu.int_regfile_writes 948614350 # number of integer regfile writes -system.cpu.fp_regfile_reads 1422281 # number of floating regfile reads -system.cpu.fp_regfile_writes 763660 # number of floating regfile writes -system.cpu.cc_regfile_reads 314738541 # number of cc regfile reads -system.cpu.cc_regfile_writes 315610902 # number of cc regfile writes -system.cpu.misc_regfile_reads 3478507383 # number of misc regfile reads -system.cpu.misc_regfile_writes 44953668 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 13773933 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.982218 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 363424605 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13774445 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.383974 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 1310024478 # Class of committed instruction +system.cpu.commit.bw_lim_events 16694299 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3459813368 # The number of ROB reads +system.cpu.rob.rob_writes 2760364536 # The number of ROB writes +system.cpu.timesIdled 9090851 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60001438 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100930240360 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1114574366 # Number of Instructions Simulated +system.cpu.committedOps 1310024478 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.962310 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.962310 # CPI: Total CPI of All Threads +system.cpu.ipc 0.509603 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.509603 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1610546046 # number of integer regfile reads +system.cpu.int_regfile_writes 949011498 # number of integer regfile writes +system.cpu.fp_regfile_reads 1420249 # number of floating regfile reads +system.cpu.fp_regfile_writes 762248 # number of floating regfile writes +system.cpu.cc_regfile_reads 314797086 # number of cc regfile reads +system.cpu.cc_regfile_writes 315669715 # number of cc regfile writes +system.cpu.misc_regfile_reads 3475493523 # number of misc regfile reads +system.cpu.misc_regfile_writes 44962873 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 13773422 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.982216 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 363599894 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13773934 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.397679 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.982218 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.982216 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1609792532 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1609792532 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 188105539 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 188105539 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164299305 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164299305 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 464298 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 464298 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 335039 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 335039 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4843113 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4843113 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5333928 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5333928 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 352739883 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 352739883 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 353204181 # number of overall hits -system.cpu.dcache.overall_hits::total 353204181 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12867394 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12867394 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18868212 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18868212 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2064415 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2064415 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1270711 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1270711 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 552556 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 552556 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1610515756 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1610515756 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 188193818 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 188193818 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164381838 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164381838 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 464944 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 464944 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 334105 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 334105 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4846159 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4846159 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5335614 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5335614 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 352909761 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 352909761 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 353374705 # number of overall hits +system.cpu.dcache.overall_hits::total 353374705 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12874356 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12874356 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18866989 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18866989 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2064832 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2064832 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1271634 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1271634 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 551153 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 551153 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 33006317 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 33006317 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 35070732 # number of overall misses -system.cpu.dcache.overall_misses::total 35070732 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 226129752000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 226129752000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113756894884 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1113756894884 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30103485720 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 30103485720 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9429427500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 9429427500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 286500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 286500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1369990132604 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1369990132604 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1369990132604 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1369990132604 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 200972933 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 200972933 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 183167517 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 183167517 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2528713 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2528713 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605750 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1605750 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5395669 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5395669 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5333936 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5333936 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385746200 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385746200 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 388274913 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 388274913 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064026 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.064026 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103011 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.103011 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816390 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.816390 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791350 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791350 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102407 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102407 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 33012979 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 33012979 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 35077811 # number of overall misses +system.cpu.dcache.overall_misses::total 35077811 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 223063102000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 223063102000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1108624638487 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1108624638487 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30055916196 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 30055916196 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9351183000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 9351183000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 285500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 285500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1361743656683 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1361743656683 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1361743656683 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1361743656683 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201068174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201068174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 183248827 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 183248827 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2529776 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2529776 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605739 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1605739 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5397312 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5397312 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5335622 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5335622 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 385922740 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385922740 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 388452516 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 388452516 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064030 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.064030 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102958 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.102958 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816211 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.816211 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791931 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791931 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102116 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102116 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.085565 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.085565 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.090324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.090324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17573.857768 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17573.857768 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59028.216075 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59028.216075 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23690.269243 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23690.269243 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.107428 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.107428 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35812.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35812.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41506.907075 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41506.907075 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39063.630967 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39063.630967 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29294390 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.085543 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.085543 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.090301 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.090301 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17326.156120 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17326.156120 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58760.019338 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58760.019338 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23635.665762 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23635.665762 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16966.582782 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16966.582782 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35687.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35687.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41248.736041 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41248.736041 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38820.656645 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38820.656645 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28867036 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2113869 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2109714 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.858186 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.682914 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 10422476 # number of writebacks -system.cpu.dcache.writebacks::total 10422476 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5755479 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5755479 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15769683 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15769683 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6881 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 6881 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 266620 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 266620 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21532043 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21532043 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21532043 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21532043 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111915 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7111915 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3098529 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3098529 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2057605 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2057605 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263830 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1263830 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 285936 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 285936 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 10417036 # number of writebacks +system.cpu.dcache.writebacks::total 10417036 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5763320 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5763320 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15767233 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15767233 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7067 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7067 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 267203 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 267203 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 21537620 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21537620 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21537620 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21537620 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111036 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7111036 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3099756 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3099756 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2058030 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2058030 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1264567 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1264567 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283950 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 283950 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 11474274 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 11474274 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 13531879 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 13531879 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 11475359 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 11475359 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 13533389 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 13533389 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 120215948500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 120215948500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164231979720 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 164231979720 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 35080858000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 35080858000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28539216720 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28539216720 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4259524000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4259524000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 278500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 278500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312987144940 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 312987144940 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 348068002940 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 348068002940 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225685500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225685500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225685500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225685500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035387 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035387 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 117823858000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 117823858000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163535842014 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 163535842014 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 34754745000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 34754745000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28487682196 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28487682196 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4220692000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4220692000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 309847382210 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 309847382210 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 344602127210 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 344602127210 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225657500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225657500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225657500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225657500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035366 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035366 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016916 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813697 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813697 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787065 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787065 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052994 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052994 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813523 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813523 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787530 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787530 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052610 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052610 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029746 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029746 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034851 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034851 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16903.456875 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16903.456875 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53003.208852 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53003.208852 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17049.364674 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17049.364674 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22581.531314 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22581.531314 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14896.774103 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14896.774103 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34812.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34812.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27277.293966 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27277.293966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25722.074735 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25722.074735 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184782.307373 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184782.307373 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92376.073893 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92376.073893 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16962264 # number of replacements -system.cpu.icache.tags.tagsinuse 511.953467 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 447249112 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16962776 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.366505 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029735 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029735 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034839 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034839 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.155043 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.155043 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52757.649961 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52757.649961 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16887.385024 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16887.385024 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22527.617909 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22527.617909 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14864.208487 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14864.208487 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34687.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34687.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27001.105779 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27001.105779 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25463.106633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25463.106633 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184781.476315 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184781.476315 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.658432 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.658432 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 16948036 # number of replacements +system.cpu.icache.tags.tagsinuse 511.953468 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 447400638 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16948548 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.397579 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 13767456500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.953467 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.953468 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 481966186 # Number of tag accesses -system.cpu.icache.tags.data_accesses 481966186 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 447249112 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 447249112 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 447249112 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 447249112 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 447249112 # number of overall hits -system.cpu.icache.overall_hits::total 447249112 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17754074 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17754074 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17754074 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17754074 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17754074 # number of overall misses -system.cpu.icache.overall_misses::total 17754074 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 238230546873 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 238230546873 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 238230546873 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 238230546873 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 238230546873 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 238230546873 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465003186 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465003186 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465003186 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465003186 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465003186 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465003186 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038181 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.038181 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.038181 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.038181 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.038181 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.038181 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13418.359463 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13418.359463 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13418.359463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13418.359463 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 22063 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 482089545 # Number of tag accesses +system.cpu.icache.tags.data_accesses 482089545 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 447400638 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 447400638 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 447400638 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 447400638 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 447400638 # number of overall hits +system.cpu.icache.overall_hits::total 447400638 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17740135 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17740135 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17740135 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17740135 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17740135 # number of overall misses +system.cpu.icache.overall_misses::total 17740135 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 237745686369 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 237745686369 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 237745686369 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 237745686369 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 237745686369 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 237745686369 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465140773 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465140773 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465140773 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465140773 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465140773 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465140773 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038139 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.038139 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.038139 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.038139 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.038139 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.038139 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13401.571429 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13401.571429 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13401.571429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13401.571429 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 22866 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1484 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1431 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.867251 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.979036 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16962264 # number of writebacks -system.cpu.icache.writebacks::total 16962264 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791074 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 791074 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 791074 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 791074 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 791074 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 791074 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16963000 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16963000 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16963000 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16963000 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16963000 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16963000 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 16948036 # number of writebacks +system.cpu.icache.writebacks::total 16948036 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791363 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 791363 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 791363 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 791363 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 791363 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 791363 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16948772 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16948772 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16948772 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16948772 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16948772 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16948772 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 214024505887 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 214024505887 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 214024505887 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 214024505887 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 214024505887 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 214024505887 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 213645244880 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 213645244880 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 213645244880 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 213645244880 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 213645244880 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 213645244880 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1752662500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1752662500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1752662500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 1752662500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036479 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.036479 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.036479 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12617.137646 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12617.137646 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12617.137646 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12617.137646 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12617.137646 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12617.137646 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036438 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.036438 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.036438 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12605.352463 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12605.352463 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12605.352463 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12605.352463 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12605.352463 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12605.352463 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82307.809712 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82307.809712 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2409655 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65438.820576 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 59303582 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2471799 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.992073 # Average number of references to valid blocks. +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 2368264 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65438.912903 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 59342443 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2431405 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.406647 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 2677802000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9434.053113 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 385.411867 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 416.493163 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6670.865899 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48531.996533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.143952 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005881 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101789 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.740539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 284 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61860 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 284 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1041 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5649 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54812 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.943909 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 508249108 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 508249108 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1295823 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 305430 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1601253 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 10422476 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 10422476 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 16959660 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 16959660 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 39331 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 39331 # number of UpgradeReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 9464.122529 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 393.883765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 433.035779 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6680.528058 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48467.342772 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.144411 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006010 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006608 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101937 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.739553 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998519 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 252 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62889 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 248 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1015 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5647 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55838 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959610 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 508088213 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 508088213 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1306072 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 309439 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1615511 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 10417036 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 10417036 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 16945412 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 16945412 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 39342 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 39342 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1728598 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1728598 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16865372 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16865372 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8990828 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 8990828 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 668361 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 668361 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 1295823 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 305430 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 16865372 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 10719426 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 29186051 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 1295823 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 305430 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 16865372 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 10719426 # number of overall hits -system.cpu.l2cache.overall_hits::total 29186051 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10808 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8922 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 19730 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4027 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4027 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 1735264 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1735264 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16852583 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 16852583 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 9020162 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 9020162 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 672287 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 672287 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 1306072 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 309439 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 16852583 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 10755426 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 29223520 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 1306072 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 309439 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 16852583 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 10755426 # number of overall hits +system.cpu.l2cache.overall_hits::total 29223520 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10647 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8959 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 19606 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4043 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4043 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1343031 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1343031 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 97409 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 97409 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 448173 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 448173 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 595469 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 595469 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 10808 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 8922 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 97409 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1791204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1908343 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 10808 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 8922 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 97409 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1791204 # number of overall misses -system.cpu.l2cache.overall_misses::total 1908343 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1486458000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 980532000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2466990000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73290500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 73290500 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 192000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 192000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 140749219500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 140749219500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10783493000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 10783493000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49949086500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 49949086500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 569000 # number of InvalidateReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::total 569000 # number of InvalidateReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1486458000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 980532000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10783493000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 190698306000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 203948789000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1486458000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 980532000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10783493000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 190698306000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 203948789000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1306631 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 314352 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1620983 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 10422476 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 10422476 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 16959660 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 16959660 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43358 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 43358 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 1337553 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1337553 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 95970 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 95970 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 416410 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 416410 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 592280 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 592280 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 10647 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 8959 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 95970 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1753963 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1869539 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 10647 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 8959 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 95970 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1753963 # number of overall misses +system.cpu.l2cache.overall_misses::total 1869539 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1464838500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 979350000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2444188500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73726500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 73726500 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 191000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 191000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 139978365500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 139978365500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10559308500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 10559308500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 46880784000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 46880784000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 453500 # number of InvalidateReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::total 453500 # number of InvalidateReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1464838500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 979350000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10559308500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 186859149500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 199862646500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1464838500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 979350000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10559308500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 186859149500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 199862646500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1316719 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 318398 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1635117 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 10417036 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 10417036 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 16945412 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 16945412 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43385 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 43385 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 8 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3071629 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3071629 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16962781 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 16962781 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9439001 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 9439001 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263830 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1263830 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1306631 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 314352 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 16962781 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 12510630 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 31094394 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1306631 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 314352 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16962781 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 12510630 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 31094394 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008272 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028382 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.012172 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.092878 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.092878 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3072817 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3072817 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16948553 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 16948553 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9436572 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 9436572 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1264567 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1264567 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1316719 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 318398 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 16948553 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 12509389 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 31093059 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1316719 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 318398 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 16948553 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 12509389 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 31093059 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008086 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028138 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.011991 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093189 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093189 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437237 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.437237 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005743 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005743 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.047481 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.047481 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.471162 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.471162 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008272 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028382 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005743 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.143175 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.061373 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008272 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028382 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005743 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.143175 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.061373 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137533.123612 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 109900.470746 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 125037.506336 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18199.776509 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18199.776509 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 48000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 48000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104799.680350 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104799.680350 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110703.251240 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110703.251240 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 111450.458863 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 111450.458863 # average ReadSharedReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.955549 # average InvalidateReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.955549 # average InvalidateReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137533.123612 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 109900.470746 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110703.251240 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106463.756222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 106872.186499 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137533.123612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 109900.470746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110703.251240 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106463.756222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 106872.186499 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435286 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.435286 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005662 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005662 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044127 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044127 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.468366 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.468366 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008086 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028138 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005662 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.140212 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060127 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008086 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028138 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005662 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.140212 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060127 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137582.276698 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 109314.655654 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 124665.332041 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18235.592382 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18235.592382 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 47750 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 47750 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104652.574889 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104652.574889 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110027.180369 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110027.180369 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112583.232871 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112583.232871 # average ReadSharedReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.765685 # average InvalidateReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.765685 # average InvalidateReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137582.276698 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 109314.655654 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110027.180369 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106535.399835 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 106904.775188 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137582.276698 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 109314.655654 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110027.180369 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106535.399835 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 106904.775188 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 2133882 # number of writebacks -system.cpu.l2cache.writebacks::total 2133882 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 2100679 # number of writebacks +system.cpu.l2cache.writebacks::total 2100679 # number of writebacks system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10808 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8921 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 19729 # number of ReadReq MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4027 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4027 # number of UpgradeReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10647 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 19606 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4043 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4043 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1343031 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1343031 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 97409 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 97409 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 448152 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 448152 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 595469 # number of InvalidateReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::total 595469 # number of InvalidateReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10808 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8921 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 97409 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1791183 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1908321 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10808 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8921 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 97409 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1791183 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1908321 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1337553 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1337553 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 95970 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 95970 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 416389 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 416389 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 592280 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 592280 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10647 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 95970 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1753942 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1869518 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10647 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 95970 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1753942 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1869518 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54986 # number of ReadReq MSHR uncacheable @@ -1452,156 +1459,156 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88689 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 891304000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2269682000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76822000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76822000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 182500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 182500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127318887048 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127318887048 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9809383542 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9809383542 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 45465885070 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 45465885070 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12316948002 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12316948002 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 891304000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9809383542 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 172784772118 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 184863837660 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 891304000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9809383542 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 172784772118 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 184863837660 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 889760000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2248128500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77144500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77144500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 181500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 181500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126602809555 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126602809555 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9599588543 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9599588543 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42714761570 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42714761570 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12256085002 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12256085002 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 889760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9599588543 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169317571125 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 181165288168 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 889760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9599588543 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169317571125 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 181165288168 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1486487500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804372500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290860000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804371500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290859000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1486487500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804372500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290860000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012171 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804371500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290859000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.092878 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.092878 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093189 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093189 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437237 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437237 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.047479 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.047479 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.471162 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.471162 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.061372 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.061372 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115042.931725 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19076.732059 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19076.732059 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45625 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45625 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94799.663632 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94799.663632 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100703.051484 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100703.051484 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101451.929412 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101451.929412 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20684.448732 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20684.448732 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435286 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435286 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005662 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044125 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044125 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.468366 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.468366 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060127 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060127 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 114665.332041 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19081.004205 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19081.004205 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94652.555491 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94652.555491 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100026.972418 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100026.972418 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102583.789605 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102583.789605 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20693.059030 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20693.059030 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.469429 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.842324 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.439748 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.824137 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.675421 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.038077 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 62444778 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 31707340 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2080 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2080 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.660583 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.026802 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 62411777 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31689071 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2067 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2067 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 2265526 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28668320 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 2264077 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28650207 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 12556358 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16962264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3627230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43361 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 12517715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16948036 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3623971 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43388 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43369 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3071629 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3071629 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16963000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1296315 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1263830 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50930633 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41545171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 782892 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3048631 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 96307327 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171543584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467959922 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2514816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10453048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3652471370 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 3035082 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 141349672 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 35524572 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.026277 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.159958 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 43396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3072817 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3072817 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16948772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9438927 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1295442 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1264567 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50887949 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41543699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 787064 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3057144 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 96275856 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169722400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467531890 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2547184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10533752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3650335226 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2976479 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 139099568 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 35465406 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.159793 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 34591090 97.37% 97.37% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 933482 2.63% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 34535454 97.38% 97.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 929952 2.62% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 35524572 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 59309730487 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 35465406 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 59274617984 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1500879 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1490379 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25476019939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25454807175 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19475244130 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19473878402 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 468898263 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 469039231 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1742663628 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1741050209 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40311 # Transaction distribution -system.iobus.trans_dist::ReadResp 40311 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40296 # Transaction distribution +system.iobus.trans_dist::ReadResp 40296 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1618,11 +1625,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353734 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1637,12 +1644,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41893500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41892500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1664,75 +1671,75 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25183500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25201500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36499000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36497000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569168088 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569294464 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147710000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115471 # number of replacements -system.iocache.tags.tagsinuse 10.450359 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115456 # number of replacements +system.iocache.tags.tagsinuse 10.450363 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13091904207000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.527977 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.922382 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220499 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432649 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.528284 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.922079 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220518 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432630 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653148 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039767 # Number of tag accesses -system.iocache.tags.data_accesses 1039767 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039632 # Number of tag accesses +system.iocache.tags.data_accesses 1039632 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115490 # number of demand (read+write) misses -system.iocache.demand_misses::total 115530 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115475 # number of demand (read+write) misses +system.iocache.demand_misses::total 115515 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115490 # number of overall misses -system.iocache.overall_misses::total 115530 # number of overall misses +system.iocache.overall_misses::realview.ide 115475 # number of overall misses +system.iocache.overall_misses::total 115515 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1926111562 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1931197062 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1862993006 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1868078506 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13315765026 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13315765026 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13281113958 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13281113958 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15241876588 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15247313088 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15144106964 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15149543464 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15241876588 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15247313088 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15144106964 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15149543464 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115490 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115530 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115475 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115515 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115490 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115530 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115475 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115515 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1747,52 +1754,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 218231.538862 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217894.286585 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 211439.451368 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 211130.030063 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124838.418079 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 124838.418079 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124513.556195 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 124513.556195 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131977.088964 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131147.846288 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131977.088964 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 47583 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131147.846288 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 44063 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3458 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.760266 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.567884 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115490 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115530 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115475 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115515 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115490 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115530 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115475 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115515 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1484811562 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1488047062 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1422443006 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1425678506 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7975666597 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7975666597 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7941073224 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7941073224 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9460478159 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9463914659 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9363516230 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9366952730 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9460478159 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9463914659 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9363516230 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9366952730 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1807,94 +1814,94 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168231.538862 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 167894.286585 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 161439.451368 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 161130.030063 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74773.743690 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74773.743690 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74449.422711 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74449.422711 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 5147706 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2561464 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 5064341 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2518493 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2998 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54986 # Transaction distribution -system.membus.trans_dist::ReadResp 629139 # Transaction distribution +system.membus.trans_dist::ReadResp 595799 # Transaction distribution system.membus.trans_dist::WriteReq 33703 # Transaction distribution system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::WritebackDirty 2240512 # Transaction distribution -system.membus.trans_dist::CleanEvict 283345 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution +system.membus.trans_dist::WritebackDirty 2207309 # Transaction distribution +system.membus.trans_dist::CleanEvict 275154 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4609 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 1342476 # Transaction distribution -system.membus.trans_dist::ReadExResp 1342476 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 574153 # Transaction distribution -system.membus.trans_dist::InvalidateReq 702122 # Transaction distribution +system.membus.trans_dist::ReadExReq 1336997 # Transaction distribution +system.membus.trans_dist::ReadExResp 1336997 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 540813 # Transaction distribution +system.membus.trans_dist::InvalidateReq 698937 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6871030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7000692 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237690 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237690 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7238382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6748871 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6878533 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237677 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237677 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7116210 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258984332 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 259154386 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7252416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 266406802 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2841 # Total snoops (count) -system.membus.snoopTraffic 181312 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2712040 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013104 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.113719 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254375884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254545938 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7253504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 261799442 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2809 # Total snoops (count) +system.membus.snoopTraffic 179264 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2670049 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012702 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.111987 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2676502 98.69% 98.69% # Request fanout histogram -system.membus.snoop_fanout::1 35538 1.31% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2636133 98.73% 98.73% # Request fanout histogram +system.membus.snoop_fanout::1 33916 1.27% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2712040 # Request fanout histogram -system.membus.reqLayer0.occupancy 104012000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2670049 # Request fanout histogram +system.membus.reqLayer0.occupancy 104027000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5608000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5600000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14521699612 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14297533259 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10216122095 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10011316944 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44869281 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44794763 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1937,30 +1944,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 17162 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 17165 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 6d4993075..e4db2f557 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.296282 # Nu sim_ticks 47296281748500 # Number of ticks simulated final_tick 47296281748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 890958 # Simulator instruction rate (inst/s) -host_op_rate 1048084 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43128593002 # Simulator tick rate (ticks/s) -host_mem_usage 697472 # Number of bytes of host memory used -host_seconds 1096.63 # Real time elapsed on the host +host_inst_rate 1698090 # Simulator instruction rate (inst/s) +host_op_rate 1997558 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 82199406118 # Simulator tick rate (ticks/s) +host_mem_usage 696116 # Number of bytes of host memory used +host_seconds 575.38 # Real time elapsed on the host sim_insts 977055082 # Number of instructions simulated sim_ops 1149364510 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -300,34 +300,38 @@ system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Cl system.cpu0.op_class::IntAlu 404699186 69.29% 69.29% # Class of executed instruction system.cpu0.op_class::IntMult 1236587 0.21% 69.50% # Class of executed instruction system.cpu0.op_class::IntDiv 60193 0.01% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatAdd 8 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCmp 13 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCvt 21 0.00% 69.51% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 69.51% # Class of executed instruction system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 72938 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::FloatMisc 72938 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::MemRead 92545018 15.84% 85.36% # Class of executed instruction -system.cpu0.op_class::MemWrite 85482625 14.64% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 92483705 15.83% 85.35% # Class of executed instruction +system.cpu0.op_class::MemWrite 85092334 14.57% 99.92% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 61313 0.01% 99.93% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 390291 0.07% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 584096590 # Class of executed instruction @@ -859,7 +863,9 @@ system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Cl system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatMisc 36628 0.01% 69.52% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction @@ -877,12 +883,14 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 36628 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::MemRead 90755131 16.04% 85.56% # Class of executed instruction -system.cpu1.op_class::MemWrite 81710125 14.44% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 90705162 16.03% 85.55% # Class of executed instruction +system.cpu1.op_class::MemWrite 81422056 14.39% 99.94% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 49969 0.01% 99.95% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 288069 0.05% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 565908654 # Class of executed instruction diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 8ece6948a..62bebe0c3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167268500 # Number of ticks simulated final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 937025 # Simulator instruction rate (inst/s) -host_op_rate 1101207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48760450215 # Simulator tick rate (ticks/s) -host_mem_usage 680056 # Number of bytes of host memory used -host_seconds 1048.21 # Real time elapsed on the host +host_inst_rate 1788186 # Simulator instruction rate (inst/s) +host_op_rate 2101506 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93052770956 # Simulator tick rate (ticks/s) +host_mem_usage 679348 # Number of bytes of host memory used +host_seconds 549.27 # Real time elapsed on the host sim_insts 982198023 # Number of instructions simulated sim_ops 1154295627 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -270,34 +270,38 @@ system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Cl system.cpu.op_class::IntAlu 800829443 69.34% 69.34% # Class of executed instruction system.cpu.op_class::IntMult 2354388 0.20% 69.54% # Class of executed instruction system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatCvt 21 0.00% 69.55% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction +system.cpu.op_class::FloatMisc 107822 0.01% 69.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::MemRead 183711282 15.91% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 167826773 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 183598958 15.90% 85.46% # Class of executed instruction +system.cpu.op_class::MemWrite 167165612 14.47% 99.93% # Class of executed instruction +system.cpu.op_class::FloatMemRead 112324 0.01% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 661161 0.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1154930294 # Class of executed instruction diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 68cea9e8f..fcaa09afa 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.405013 # Nu sim_ticks 47405012960500 # Number of ticks simulated final_tick 47405012960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 480061 # Simulator instruction rate (inst/s) -host_op_rate 564722 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25874318289 # Simulator tick rate (ticks/s) -host_mem_usage 758156 # Number of bytes of host memory used -host_seconds 1832.13 # Real time elapsed on the host +host_inst_rate 1080699 # Simulator instruction rate (inst/s) +host_op_rate 1271286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58247547339 # Simulator tick rate (ticks/s) +host_mem_usage 759864 # Number of bytes of host memory used +host_seconds 813.85 # Real time elapsed on the host sim_insts 879531552 # Number of instructions simulated sim_ops 1034641707 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -638,30 +638,34 @@ system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Cl system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 69.58% # Class of executed instruction system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 44848 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::FloatMisc 44848 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.59% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::MemRead 86844124 15.95% 85.53% # Class of executed instruction -system.cpu0.op_class::MemWrite 78780788 14.47% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 86795135 15.94% 85.53% # Class of executed instruction +system.cpu0.op_class::MemWrite 78444196 14.40% 99.93% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 48989 0.01% 99.94% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 336592 0.06% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 544601223 # Class of executed instruction @@ -1637,34 +1641,38 @@ system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Cl system.cpu1.op_class::IntAlu 338840052 69.06% 69.06% # Class of executed instruction system.cpu1.op_class::IntMult 1031473 0.21% 69.27% # Class of executed instruction system.cpu1.op_class::IntDiv 58381 0.01% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 8 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatCmp 13 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatCvt 21 0.00% 69.28% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 69.28% # Class of executed instruction system.cpu1.op_class::FloatDiv 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 67037 0.01% 69.30% # Class of executed instruction +system.cpu1.op_class::FloatMisc 67037 0.01% 69.30% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.30% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::MemRead 78882725 16.08% 85.37% # Class of executed instruction -system.cpu1.op_class::MemWrite 71756042 14.63% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 78824615 16.07% 85.36% # Class of executed instruction +system.cpu1.op_class::MemWrite 71413356 14.56% 99.92% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 58110 0.01% 99.93% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 342686 0.07% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 490635753 # Class of executed instruction diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 39817260d..c8de2f883 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.821889 # Nu sim_ticks 51821888787500 # Number of ticks simulated final_tick 51821888787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 515124 # Simulator instruction rate (inst/s) -host_op_rate 605315 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31054928912 # Simulator tick rate (ticks/s) -host_mem_usage 676612 # Number of bytes of host memory used -host_seconds 1668.72 # Real time elapsed on the host +host_inst_rate 1225071 # Simulator instruction rate (inst/s) +host_op_rate 1439562 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73854998542 # Simulator tick rate (ticks/s) +host_mem_usage 679352 # Number of bytes of host memory used +host_seconds 701.67 # Real time elapsed on the host sim_insts 859596485 # Number of instructions simulated sim_ops 1010098639 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -600,34 +600,38 @@ system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Cl system.cpu.op_class::IntAlu 699904687 69.25% 69.25% # Class of executed instruction system.cpu.op_class::IntMult 2167959 0.21% 69.47% # Class of executed instruction system.cpu.op_class::IntDiv 97409 0.01% 69.48% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 21 0.00% 69.48% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 69.48% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 111537 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::FloatMisc 111537 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::MemRead 161593947 15.99% 85.48% # Class of executed instruction -system.cpu.op_class::MemWrite 146796321 14.52% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 161481542 15.98% 85.46% # Class of executed instruction +system.cpu.op_class::MemWrite 146123455 14.46% 99.92% # Class of executed instruction +system.cpu.op_class::FloatMemRead 112405 0.01% 99.93% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 672866 0.07% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1010671903 # Class of executed instruction diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 38958d98d..0c54e3227 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.062553 # Nu sim_ticks 62552970500 # Number of ticks simulated final_tick 62552970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185964 # Simulator instruction rate (inst/s) -host_op_rate 186891 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 128391357 # Simulator tick rate (ticks/s) -host_mem_usage 403424 # Number of bytes of host memory used -host_seconds 487.21 # Real time elapsed on the host +host_inst_rate 423901 # Simulator instruction rate (inst/s) +host_op_rate 426012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 292664487 # Simulator tick rate (ticks/s) +host_mem_usage 404124 # Number of bytes of host memory used +host_seconds 213.74 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -415,7 +415,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction @@ -437,8 +439,10 @@ system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction -system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction -system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction +system.cpu.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 3b8f7cb56..4f68c8fbf 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.058675 # Nu sim_ticks 58675371500 # Number of ticks simulated final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111966 # Simulator instruction rate (inst/s) -host_op_rate 112523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72520515 # Simulator tick rate (ticks/s) -host_mem_usage 490592 # Number of bytes of host memory used -host_seconds 809.09 # Real time elapsed on the host +host_inst_rate 241655 # Simulator instruction rate (inst/s) +host_op_rate 242858 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 156520643 # Simulator tick rate (ticks/s) +host_mem_usage 492304 # Number of bytes of host memory used +host_seconds 374.87 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -515,7 +515,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available @@ -537,8 +539,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9615894 47.83% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702925 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9615891 47.83% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702910 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -549,7 +553,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued @@ -571,22 +577,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337772 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047242 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337764 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047220 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued system.cpu.iq.rate 0.863794 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20102375 # FU busy when requested +system.cpu.iq.fu_busy_cnt 20102384 # FU busy when requested system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 467 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 238 # Number of floating point alu accesses +system.cpu.iq.fp_alu_accesses 247 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed @@ -665,7 +673,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction @@ -687,8 +697,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b27dfcb1b..ff7ca3031 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361613 # Nu sim_ticks 361613361500 # Number of ticks simulated final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1370596 # Simulator instruction rate (inst/s) -host_op_rate 1370653 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2032709522 # Simulator tick rate (ticks/s) -host_mem_usage 385816 # Number of bytes of host memory used -host_seconds 177.90 # Real time elapsed on the host +host_inst_rate 1844871 # Simulator instruction rate (inst/s) +host_op_rate 1844948 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2736100211 # Simulator tick rate (ticks/s) +host_mem_usage 385448 # Number of bytes of host memory used +host_seconds 132.16 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -65,7 +65,9 @@ system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Cl system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction @@ -87,8 +89,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction -system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction +system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index dac7009e5..48f2e7ba9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.066079 # Nu sim_ticks 66079350000 # Number of ticks simulated final_tick 66079350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104457 # Simulator instruction rate (inst/s) -host_op_rate 183932 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43689609 # Simulator tick rate (ticks/s) -host_mem_usage 414668 # Number of bytes of host memory used -host_seconds 1512.47 # Real time elapsed on the host +host_inst_rate 185548 # Simulator instruction rate (inst/s) +host_op_rate 326721 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77606283 # Simulator tick rate (ticks/s) +host_mem_usage 417148 # Number of bytes of host memory used +host_seconds 851.47 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,7 +403,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available @@ -425,8 +427,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3544036 86.42% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 190508 4.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3544032 86.41% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 189377 4.62% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 6 0.00% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1660 0.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued @@ -437,7 +441,9 @@ system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 57.24% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.24% # Type of FU issued @@ -459,22 +465,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.24% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101489755 31.85% 89.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34771062 10.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101489286 31.85% 89.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34764932 10.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 469 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 6130 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 318634973 # Type of FU issued system.cpu.iq.rate 2.411003 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4100758 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012870 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 773602517 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 4101289 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012871 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 773603045 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 412934380 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 314305089 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 19287 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 19290 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 34996 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4478 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 322693854 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8537 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 322694382 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8540 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57471685 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 22103872 # Number of loads squashed @@ -553,7 +561,9 @@ system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction @@ -575,8 +585,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 90779371 32.63% 88.70% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 31439738 11.30% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 14 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 683cfaa02..141b0c04b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.366229 # Nu sim_ticks 366229314500 # Number of ticks simulated final_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 561124 # Simulator instruction rate (inst/s) -host_op_rate 988050 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1300728257 # Simulator tick rate (ticks/s) -host_mem_usage 412916 # Number of bytes of host memory used -host_seconds 281.56 # Real time elapsed on the host +host_inst_rate 1002365 # Simulator instruction rate (inst/s) +host_op_rate 1765004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2323557450 # Simulator tick rate (ticks/s) +host_mem_usage 412036 # Number of bytes of host memory used +host_seconds 157.62 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -78,7 +78,9 @@ system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Cl system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction @@ -100,8 +102,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction -system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction +system.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index ddf2151ed..61f620036 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.422343 # Nu sim_ticks 422342506500 # Number of ticks simulated final_tick 422342506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 265332 # Simulator instruction rate (inst/s) -host_op_rate 265332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 183135937 # Simulator tick rate (ticks/s) -host_mem_usage 256400 # Number of bytes of host memory used -host_seconds 2306.17 # Real time elapsed on the host +host_inst_rate 474436 # Simulator instruction rate (inst/s) +host_op_rate 474436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 327462122 # Simulator tick rate (ticks/s) +host_mem_usage 257604 # Number of bytes of host memory used +host_seconds 1289.74 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -356,7 +356,9 @@ system.cpu.op_class_0::FloatAdd 144588 0.02% 66.64% # Cl system.cpu.op_class_0::FloatCmp 3 0.00% 66.64% # Class of committed instruction system.cpu.op_class_0::FloatCvt 369991 0.06% 66.70% # Class of committed instruction system.cpu.op_class_0::FloatMult 2 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::FloatDiv 3790 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.70% # Class of committed instruction @@ -378,8 +380,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.70% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::MemRead 146565535 23.95% 90.65% # Class of committed instruction -system.cpu.op_class_0::MemWrite 57220983 9.35% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 146469180 23.94% 90.63% # Class of committed instruction +system.cpu.op_class_0::MemWrite 57213427 9.35% 99.98% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 96355 0.02% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 7556 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 611901617 # Class of committed instruction diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 3968e09e7..3b6bf0c6f 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.368600 # Nu sim_ticks 368600034500 # Number of ticks simulated final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189198 # Simulator instruction rate (inst/s) -host_op_rate 204927 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137665575 # Simulator tick rate (ticks/s) -host_mem_usage 274600 # Number of bytes of host memory used -host_seconds 2677.50 # Real time elapsed on the host +host_inst_rate 368828 # Simulator instruction rate (inst/s) +host_op_rate 399489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 268368313 # Simulator tick rate (ticks/s) +host_mem_usage 276836 # Number of bytes of host memory used +host_seconds 1373.49 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -442,7 +442,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction @@ -465,7 +467,9 @@ system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Cl system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction -system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemWrite 56860206 10.36% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 48fa8fd80..36fb98963 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.236034 # Nu sim_ticks 236034256000 # Number of ticks simulated final_tick 236034256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147811 # Simulator instruction rate (inst/s) -host_op_rate 160132 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69053974 # Simulator tick rate (ticks/s) -host_mem_usage 301356 # Number of bytes of host memory used -host_seconds 3418.11 # Real time elapsed on the host +host_inst_rate 253188 # Simulator instruction rate (inst/s) +host_op_rate 274292 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118283576 # Simulator tick rate (ticks/s) +host_mem_usage 302048 # Number of bytes of host memory used +host_seconds 1995.49 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -531,7 +531,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.13% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.13% # attempts to use FU when none available @@ -553,8 +555,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.13% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44305814 32.74% 85.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19132145 14.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44305802 32.74% 85.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19132129 14.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 12 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -565,7 +569,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued @@ -587,22 +593,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133573210 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62394989 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133573188 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62394973 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 22 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 608905066 # Type of FU issued system.cpu.iq.rate 1.289866 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135340476 # FU busy when requested +system.cpu.iq.fu_busy_cnt 135340482 # FU busy when requested system.cpu.iq.fu_busy_rate 0.222269 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 1829844132 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 788130713 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 594185364 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 106 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 112 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 88 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 744245476 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 66 # Number of floating point alu accesses +system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 7285563 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 26474758 # Number of loads squashed @@ -681,7 +689,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction @@ -704,7 +714,9 @@ system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 56860204 10.36% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 6a67fce1b..15befb0d8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279361 # Nu sim_ticks 279360903000 # Number of ticks simulated final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1206466 # Simulator instruction rate (inst/s) -host_op_rate 1306763 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 665324846 # Simulator tick rate (ticks/s) -host_mem_usage 263448 # Number of bytes of host memory used -host_seconds 419.89 # Real time elapsed on the host +host_inst_rate 2213544 # Simulator instruction rate (inst/s) +host_op_rate 2397561 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1220693561 # Simulator tick rate (ticks/s) +host_mem_usage 263256 # Number of bytes of host memory used +host_seconds 228.85 # Real time elapsed on the host sim_insts 506578818 # Number of instructions simulated sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Cl system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction @@ -216,7 +218,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 9780dac13..dc3d7ebff 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.708700 # Nu sim_ticks 708700329500 # Number of ticks simulated final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 820539 # Simulator instruction rate (inst/s) -host_op_rate 888607 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1151553403 # Simulator tick rate (ticks/s) -host_mem_usage 275232 # Number of bytes of host memory used -host_seconds 615.43 # Real time elapsed on the host +host_inst_rate 1580290 # Simulator instruction rate (inst/s) +host_op_rate 1711383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2217795996 # Simulator tick rate (ticks/s) +host_mem_usage 275040 # Number of bytes of host memory used +host_seconds 319.55 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -194,7 +194,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Cl system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction @@ -217,7 +219,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 97084638c..32b980d52 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.487015 # Nu sim_ticks 487015166000 # Number of ticks simulated final_tick 487015166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125191 # Simulator instruction rate (inst/s) -host_op_rate 231667 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73737953 # Simulator tick rate (ticks/s) -host_mem_usage 321616 # Number of bytes of host memory used -host_seconds 6604.67 # Real time elapsed on the host +host_inst_rate 149671 # Simulator instruction rate (inst/s) +host_op_rate 276966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88156571 # Simulator tick rate (ticks/s) +host_mem_usage 323840 # Number of bytes of host memory used +host_seconds 5524.43 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -404,37 +404,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 973823159 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11212757 43.22% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11924633 45.96% 89.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2807188 10.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11212757 43.19% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11924633 45.93% 89.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2727831 10.51% 99.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 98893 0.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2915020 0.15% 0.15% # Type of FU issued @@ -445,7 +449,9 @@ system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued @@ -467,22 +473,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471201648 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186365855 9.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471201643 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 185912277 9.30% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 5 0.00% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 453578 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 1999301644 # Type of FU issued system.cpu.iq.rate 2.052607 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25944578 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012977 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5000714674 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 25964114 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012987 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5000734134 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 3305993539 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1923953649 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1300906 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 1300982 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4091270 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 238195 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021778795 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 552407 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 2021798255 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 552483 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 179914916 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 224265796 # Number of loads squashed @@ -561,7 +569,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction @@ -585,6 +595,8 @@ system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 76b9b35da..e99a80294 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885773 # Nu sim_ticks 885772926000 # Number of ticks simulated final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 861241 # Simulator instruction rate (inst/s) -host_op_rate 1593729 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 922618164 # Simulator tick rate (ticks/s) -host_mem_usage 273768 # Number of bytes of host memory used -host_seconds 960.06 # Real time elapsed on the host +host_inst_rate 1551014 # Simulator instruction rate (inst/s) +host_op_rate 2870153 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1661547121 # Simulator tick rate (ticks/s) +host_mem_usage 272636 # Number of bytes of host memory used +host_seconds 533.10 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -77,7 +77,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Cl system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction @@ -101,6 +103,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 9b8e6bb2d..4f486e613 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.650924 # Nu sim_ticks 1650923912500 # Number of ticks simulated final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 598809 # Simulator instruction rate (inst/s) -host_op_rate 1108098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1195612149 # Simulator tick rate (ticks/s) -host_mem_usage 285816 # Number of bytes of host memory used -host_seconds 1380.82 # Real time elapsed on the host +host_inst_rate 1073233 # Simulator instruction rate (inst/s) +host_op_rate 1986019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2142868820 # Simulator tick rate (ticks/s) +host_mem_usage 285448 # Number of bytes of host memory used +host_seconds 770.43 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -78,7 +78,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Cl system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction @@ -102,6 +104,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index e0c918d80..2ec97b33e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.233641 # Nu sim_ticks 233641094500 # Number of ticks simulated final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 295188 # Simulator instruction rate (inst/s) -host_op_rate 295188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172997788 # Simulator tick rate (ticks/s) -host_mem_usage 258004 # Number of bytes of host memory used -host_seconds 1350.54 # Real time elapsed on the host +host_inst_rate 449379 # Simulator instruction rate (inst/s) +host_op_rate 449379 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 263362780 # Simulator tick rate (ticks/s) +host_mem_usage 260228 # Number of bytes of host memory used +host_seconds 887.15 # Real time elapsed on the host sim_insts 398664651 # Number of instructions simulated sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -327,7 +327,9 @@ system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Cl system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction @@ -349,8 +351,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::MemRead 94754510 23.77% 81.56% # Class of committed instruction -system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 46072315 11.56% 69.35% # Class of committed instruction +system.cpu.op_class_0::MemWrite 30396984 7.62% 76.97% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 48682195 12.21% 89.18% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 43123780 10.82% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 1a8043b05..54dc9e079 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.064255 # Nu sim_ticks 64255452000 # Number of ticks simulated final_tick 64255452000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260947 # Simulator instruction rate (inst/s) -host_op_rate 260947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44644346 # Simulator tick rate (ticks/s) -host_mem_usage 259540 # Number of bytes of host memory used -host_seconds 1439.27 # Real time elapsed on the host +host_inst_rate 443081 # Simulator instruction rate (inst/s) +host_op_rate 443081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75804731 # Simulator tick rate (ticks/s) +host_mem_usage 261252 # Number of bytes of host memory used +host_seconds 847.64 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -402,37 +402,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 128152674 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 253970 1.40% 1.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 1.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 138834 0.77% 2.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 79013 0.44% 2.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3594 0.02% 2.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3443745 19.00% 21.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1647907 9.09% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8047413 44.40% 75.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4509145 24.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 253970 1.29% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 138834 0.71% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 79013 0.40% 2.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3594 0.02% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3443745 17.54% 19.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1647907 8.39% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3789083 19.30% 47.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1973005 10.05% 57.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 5150981 26.24% 83.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3150937 16.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued @@ -443,7 +447,9 @@ system.cpu.iq.FU_type_0::FloatAdd 36418443 9.36% 47.68% # Ty system.cpu.iq.FU_type_0::FloatCmp 7355119 1.89% 49.57% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 2800065 0.72% 50.29% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 16556449 4.25% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 1584163 0.41% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued @@ -465,22 +471,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99502948 25.57% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 75842088 19.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 48929897 12.57% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 31583157 8.11% 75.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 50573051 12.99% 88.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 44258931 11.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 389210637 # Type of FU issued system.cpu.iq.rate 3.028619 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18123623 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.046565 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 592644502 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 19631071 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.050438 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 593561800 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 242185048 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 227933309 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 332249256 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 332839406 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 166679024 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 158288157 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 234729597 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172571082 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 235646895 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 173161232 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 19364531 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 4980212 # Number of loads squashed @@ -559,7 +567,9 @@ system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Cl system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction @@ -581,8 +591,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.79% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 94754486 23.77% 81.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 73520728 18.44% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 46072297 11.56% 69.35% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 30396955 7.62% 76.97% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 48682189 12.21% 89.18% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 43123773 10.82% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 33645e09f..6d86d3450 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567393 # Nu sim_ticks 567392530500 # Number of ticks simulated final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 646502 # Simulator instruction rate (inst/s) -host_op_rate 646502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 920122456 # Simulator tick rate (ticks/s) -host_mem_usage 259072 # Number of bytes of host memory used -host_seconds 616.65 # Real time elapsed on the host +host_inst_rate 1833225 # Simulator instruction rate (inst/s) +host_op_rate 1833225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2609105944 # Simulator tick rate (ticks/s) +host_mem_usage 258692 # Number of bytes of host memory used +host_seconds 217.47 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -97,7 +97,9 @@ system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Cl system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 57.40% # Class of executed instruction system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction @@ -119,8 +121,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::MemRead 94754511 23.77% 81.56% # Class of executed instruction -system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 46072316 11.56% 69.35% # Class of executed instruction +system.cpu.op_class::MemWrite 30396985 7.62% 76.97% # Class of executed instruction +system.cpu.op_class::FloatMemRead 48682195 12.21% 89.18% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 43123780 10.82% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index c3dd06017..d7f32d52d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.225207 # Nu sim_ticks 225206521000 # Number of ticks simulated final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132189 # Simulator instruction rate (inst/s) -host_op_rate 158707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 109031633 # Simulator tick rate (ticks/s) -host_mem_usage 278744 # Number of bytes of host memory used -host_seconds 2065.52 # Real time elapsed on the host +host_inst_rate 284094 # Simulator instruction rate (inst/s) +host_op_rate 341086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 234325505 # Simulator tick rate (ticks/s) +host_mem_usage 279956 # Number of bytes of host memory used +host_seconds 961.08 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -415,7 +415,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction @@ -437,8 +439,10 @@ system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Cl system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction -system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Class of committed instruction -system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 44185174 13.48% 62.20% # Class of committed instruction +system.cpu.op_class_0::MemWrite 55008381 16.78% 78.98% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 9802024db..fc2854304 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.122178 # Number of seconds simulated -sim_ticks 122177531500 # Number of ticks simulated -final_tick 122177531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.124291 # Number of seconds simulated +sim_ticks 124290972500 # Number of ticks simulated +final_tick 124290972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120262 # Simulator instruction rate (inst/s) -host_op_rate 144388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53814187 # Simulator tick rate (ticks/s) -host_mem_usage 292180 # Number of bytes of host memory used -host_seconds 2270.36 # Real time elapsed on the host +host_inst_rate 226846 # Simulator instruction rate (inst/s) +host_op_rate 272354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103264191 # Simulator tick rate (ticks/s) +host_mem_usage 292872 # Number of bytes of host memory used +host_seconds 1203.62 # Real time elapsed on the host sim_insts 273037218 # Number of instructions simulated sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1888192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14650048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169280 # Number of bytes read from this memory -system.physmem.bytes_read::total 16707520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1888192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1888192 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2645 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261055 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15454495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 119907874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1385525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136747893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15454495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15454495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15454495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 119907874 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1385525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 136747893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261056 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1883840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14654016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 168640 # Number of bytes read from this memory +system.physmem.bytes_read::total 16706496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1883840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1883840 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228969 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2635 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261039 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15156692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117900888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1356816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134414396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15156692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15156692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15156692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117900888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1356816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134414396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261040 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261056 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261040 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16707584 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16706560 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16707584 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16706560 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 1259 # Per bank write bursts -system.physmem.perBankRdBursts::1 69992 # Per bank write bursts -system.physmem.perBankRdBursts::2 1296 # Per bank write bursts -system.physmem.perBankRdBursts::3 10759 # Per bank write bursts +system.physmem.perBankRdBursts::1 69986 # Per bank write bursts +system.physmem.perBankRdBursts::2 1297 # Per bank write bursts +system.physmem.perBankRdBursts::3 10756 # Per bank write bursts system.physmem.perBankRdBursts::4 42908 # Per bank write bursts -system.physmem.perBankRdBursts::5 121819 # Per bank write bursts -system.physmem.perBankRdBursts::6 160 # Per bank write bursts -system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::5 121816 # Per bank write bursts +system.physmem.perBankRdBursts::6 153 # Per bank write bursts +system.physmem.perBankRdBursts::7 261 # Per bank write bursts system.physmem.perBankRdBursts::8 228 # Per bank write bursts system.physmem.perBankRdBursts::9 562 # Per bank write bursts -system.physmem.perBankRdBursts::10 7776 # Per bank write bursts +system.physmem.perBankRdBursts::10 7773 # Per bank write bursts system.physmem.perBankRdBursts::11 812 # Per bank write bursts system.physmem.perBankRdBursts::12 1213 # Per bank write bursts system.physmem.perBankRdBursts::13 743 # Per bank write bursts system.physmem.perBankRdBursts::14 662 # Per bank write bursts -system.physmem.perBankRdBursts::15 610 # Per bank write bursts +system.physmem.perBankRdBursts::15 611 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 122177522000 # Total gap between requests +system.physmem.totGap 124290963000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261056 # Read request sizes (log2) +system.physmem.readPktSize::6 261040 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,20 +95,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43333 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 177 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -191,96 +191,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 248.480388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.727737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 204.056429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18253 27.15% 27.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21438 31.89% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11486 17.08% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6691 9.95% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4636 6.90% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2199 3.27% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1378 2.05% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 426 0.63% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 722 1.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67229 # Bytes accessed per row activation -system.physmem.totQLat 4621160381 # Total ticks spent queuing -system.physmem.totMemAccLat 9515960381 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 17701.80 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.854084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.733686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.637928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18270 26.89% 26.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22179 32.64% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11425 16.82% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6866 10.11% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4751 6.99% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2068 3.04% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1319 1.94% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 392 0.58% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 673 0.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67943 # Bytes accessed per row activation +system.physmem.totQLat 4615275409 # Total ticks spent queuing +system.physmem.totMemAccLat 9509775409 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17680.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36451.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 136.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36430.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 136.75 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.41 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.07 # Data bus utilization in percentage -system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.05 # Data bus utilization in percentage +system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193817 # Number of row buffer hits during reads +system.physmem.readRowHits 193087 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.97 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 468012.69 # Average gap between requests -system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 445443180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 236747280 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1773933000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 476137.61 # Average gap between requests +system.physmem.pageHitRate 73.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 450177000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 239263365 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1773833040 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9531222480.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4632019500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 224464800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 45099806190 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3562907040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 919525950 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 66426265230 # Total energy per rank (pJ) -system.physmem_0.averagePower 543.686420 # Core power per rank (mW) -system.physmem_0.totalIdleTime 111434381144 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 154081000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4033332000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 3253133750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 9278182481 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6555604606 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 98903197663 # Time in different power states -system.physmem_1.actEnergy 34636140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 18382980 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 89999700 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9685497120.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4649003790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 227628000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 45880019340 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3639028320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 957591945 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 67502066010 # Total energy per rank (pJ) +system.physmem_0.averagePower 543.097094 # Core power per rank (mW) +system.physmem_0.totalIdleTime 113501776163 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 155671000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4098592000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 3412225500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 9476337397 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6534800587 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 100613346016 # Time in different power states +system.physmem_1.actEnergy 35000280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 18576525 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 89985420 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3038165520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 716380560 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 121415040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10108537890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3723173760 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 21583783695 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 39434924925 # Total energy per rank (pJ) -system.physmem_1.averagePower 322.767403 # Core power per rank (mW) -system.physmem_1.totalIdleTime 120289757500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 194586000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1289158000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 88425719250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 9695988513 # Time in different power states -system.physmem_1.memoryStateTime::ACT 404030000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22168049737 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35971486 # Number of BP lookups -system.cpu.branchPred.condPredicted 19267078 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984296 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17894197 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923261 # Number of BTB hits +system.physmem_1.refreshEnergy 3070126800.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 722159790 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 122839680 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10172185800 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3790789440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 22016840895 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 40039093920 # Total energy per rank (pJ) +system.physmem_1.averagePower 322.140000 # Core power per rank (mW) +system.physmem_1.totalIdleTime 122386077248 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 197400000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1302732000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 90206777750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 9871788058 # Time in different power states +system.physmem_1.memoryStateTime::ACT 404763252 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22307511440 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35978086 # Number of BP lookups +system.cpu.branchPred.condPredicted 19268966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984583 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17896722 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13923101 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.808806 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6951889 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517219 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43864 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128904 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 77.796934 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6952398 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4419 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2517542 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473672 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43870 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 129186 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,234 +401,242 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 244355064 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 248581946 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12854090 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309386185 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35971486 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348505 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 227028352 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1990311 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1601 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3162 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82203694 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34298 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 240882453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.544883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12982171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309515100 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35978086 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23349171 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 231243677 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1995433 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 3229 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82227465 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34636 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 245228486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.518257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300334 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 80675861 33.49% 33.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40201773 16.69% 50.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28081031 11.66% 61.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91923788 38.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 84781187 34.57% 34.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40505386 16.52% 51.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28011183 11.42% 62.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91930730 37.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 240882453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.147210 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.266134 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 26812973 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 90710528 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 98252382 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 24245286 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 861284 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6686689 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134210 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348538542 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3411137 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 861284 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43083632 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37000044 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 289266 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 105269732 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54378495 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344597413 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1451618 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7112089 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 85489 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7460814 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27903739 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3277402 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394869828 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2218091968 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335911643 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192912802 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 245228486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144733 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.245123 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27310570 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94773867 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 97190577 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 25089647 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 863825 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6682147 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134191 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348416966 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3358743 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 863825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44033987 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38819082 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 289712 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104520763 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56701117 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344543720 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1460141 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7869954 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94767 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 8436803 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 28433094 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3429388 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394731046 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217541719 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335903437 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192790757 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22639780 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11574 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57375410 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89984183 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84392474 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977179 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1898949 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343275804 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22622 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339466020 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 967573 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15486826 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 37253539 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 502 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 240882453 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.409260 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.140571 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22500998 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11600 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11566 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 59469204 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89978957 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84398693 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2368147 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1979963 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343241150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22616 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339372334 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 953627 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15452166 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36722458 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 245228486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.383903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.138993 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 60724616 25.21% 25.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76160793 31.62% 56.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59430978 24.67% 81.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34569007 14.35% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9283720 3.85% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 678664 0.28% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34675 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64185587 26.17% 26.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 77296840 31.52% 57.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59648022 24.32% 82.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34412911 14.03% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 8897509 3.63% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 775021 0.32% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12596 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 240882453 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 245228486 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9218221 7.75% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7322 0.01% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 238834 0.20% 7.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 138891 0.12% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 70679 0.06% 8.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68365 0.06% 8.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 640804 0.54% 8.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 296732 0.25% 8.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 541759 0.46% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51504063 43.31% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56187426 47.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8796506 6.82% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7321 0.01% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 160578 0.12% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 165226 0.13% 7.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 81752 0.06% 7.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 59978 0.05% 7.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 823294 0.64% 7.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 313002 0.24% 8.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 382743 0.30% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27474499 21.29% 29.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41314471 32.01% 61.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 30691566 23.78% 85.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 18785214 14.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108184064 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148340 0.63% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792701 2.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8634973 2.54% 37.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3210554 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20863316 6.15% 44.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7179113 2.11% 46.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141894 2.10% 48.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 90024187 26.52% 75.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 83518595 24.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108168622 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148105 0.63% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6799290 2.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8596304 2.53% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3207462 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592646 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20838335 6.14% 44.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175285 2.11% 46.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140600 2.10% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 46512146 13.71% 62.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 55971174 16.49% 79.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 43494368 12.82% 91.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 27552700 8.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339466020 # Type of FU issued -system.cpu.iq.rate 1.389233 # Inst issue rate -system.cpu.iq.fu_busy_cnt 118913096 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.350295 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756328552 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235151256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219171646 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283366610 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123646075 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116917582 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 293624810 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 164754306 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5408815 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339372334 # Type of FU issued +system.cpu.iq.rate 1.365233 # Inst issue rate +system.cpu.iq.fu_busy_cnt 129056150 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.380279 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 765892553 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235176629 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219155615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 288090378 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123554179 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116971321 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 298827775 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 169600709 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5587408 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4251908 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7378 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2016857 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4246682 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7095 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14879 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2023076 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 126936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 613330 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 158632 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 537261 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 861284 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1350225 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1508994 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343299844 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 863825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1349614 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1747627 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343265167 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89984183 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84392474 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11589 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7652 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1502014 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 438026 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454508 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892534 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337437017 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89435625 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2029003 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89978957 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84398693 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11583 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6712 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1741146 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14879 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 437892 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454499 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892391 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337381646 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89446380 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1990688 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1418 # number of nop insts executed -system.cpu.iew.exec_refs 172563316 # number of memory reference insts executed -system.cpu.iew.exec_branches 31556143 # Number of branches executed -system.cpu.iew.exec_stores 83127691 # Number of stores executed -system.cpu.iew.exec_rate 1.380929 # Inst execution rate -system.cpu.iew.wb_sent 336235772 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336089228 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151786231 # num instructions producing a value -system.cpu.iew.wb_consumers 263562514 # num instructions consuming a value -system.cpu.iew.wb_rate 1.375413 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575902 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14164375 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1401 # number of nop insts executed +system.cpu.iew.exec_refs 172578078 # number of memory reference insts executed +system.cpu.iew.exec_branches 31542222 # Number of branches executed +system.cpu.iew.exec_stores 83131698 # Number of stores executed +system.cpu.iew.exec_rate 1.357225 # Inst execution rate +system.cpu.iew.wb_sent 336270787 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336126936 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153093104 # num instructions producing a value +system.cpu.iew.wb_consumers 267318257 # num instructions consuming a value +system.cpu.iew.wb_rate 1.352178 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572700 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14160521 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850425 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 238692959 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.373364 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.035708 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 850692 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 243036852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.044097 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 107534765 45.05% 45.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 67583251 28.31% 73.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20880103 8.75% 82.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13256001 5.55% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8658859 3.63% 91.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4515867 1.89% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3014415 1.26% 94.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2598093 1.09% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10651605 4.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 113296519 46.62% 46.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 65998128 27.16% 73.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 21346559 8.78% 82.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13163754 5.42% 87.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8182652 3.37% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4361649 1.79% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2983865 1.23% 94.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2442147 1.00% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11261579 4.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 238692959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 243036852 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037830 # Number of instructions committed system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -647,7 +655,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction @@ -669,560 +679,563 @@ system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 44185201 13.48% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 55008399 16.78% 78.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 10651605 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 570015418 # The number of ROB reads -system.cpu.rob.rob_writes 686144847 # The number of ROB writes -system.cpu.timesIdled 39403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3472611 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 11261579 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 573745483 # The number of ROB reads +system.cpu.rob.rob_writes 686139464 # The number of ROB writes +system.cpu.timesIdled 39266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3353460 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037218 # Number of Instructions Simulated system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.894951 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.894951 # CPI: Total CPI of All Threads -system.cpu.ipc 1.117379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.117379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325163205 # number of integer regfile reads -system.cpu.int_regfile_writes 134094196 # number of integer regfile writes -system.cpu.fp_regfile_reads 186638267 # number of floating regfile reads -system.cpu.fp_regfile_writes 131663703 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279409265 # number of cc regfile reads -system.cpu.cc_regfile_writes 80058845 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056731782 # number of misc regfile reads +system.cpu.cpi 0.910432 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.910432 # CPI: Total CPI of All Threads +system.cpu.ipc 1.098379 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.098379 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325197340 # number of integer regfile reads +system.cpu.int_regfile_writes 134110925 # number of integer regfile writes +system.cpu.fp_regfile_reads 186451715 # number of floating regfile reads +system.cpu.fp_regfile_writes 131763174 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279529156 # number of cc regfile reads +system.cpu.cc_regfile_writes 79965327 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056169060 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542799 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.841241 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 162053309 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543311 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 105.003664 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542798 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.843941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161960642 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543310 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 104.943687 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 91635000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.841241 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999690 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333480485 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333480485 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81040424 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81040424 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921391 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921391 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69631 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69631 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 333233788 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333233788 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 80947765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 80947765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921307 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921307 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69703 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69703 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161961815 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161961815 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 162031446 # number of overall hits -system.cpu.dcache.overall_hits::total 162031446 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2784008 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2784008 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131308 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131308 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161869072 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161869072 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161938775 # number of overall hits +system.cpu.dcache.overall_hits::total 161938775 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2753247 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2753247 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131392 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131392 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3915316 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3915316 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3915334 # number of overall misses -system.cpu.dcache.overall_misses::total 3915334 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47872980500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47872980500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9172353414 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9172353414 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3884639 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3884639 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3884657 # number of overall misses +system.cpu.dcache.overall_misses::total 3884657 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47533202500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47533202500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9194702918 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9194702918 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 57045333914 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 57045333914 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 57045333914 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 57045333914 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83824432 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83824432 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 56727905418 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 56727905418 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 56727905418 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 56727905418 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83701012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83701012 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69649 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69649 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69721 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69721 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165877131 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165877131 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165946780 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165946780 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033212 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165753711 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165753711 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165823432 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165823432 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032894 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032894 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013789 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013789 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.705077 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.705077 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8107.742024 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8107.742024 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023436 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023436 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023426 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023426 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17264.416342 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17264.416342 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8126.894054 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8126.894054 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14569.790513 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14569.790513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14569.723532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14569.723532 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14603.134401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14603.134401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14603.066736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14603.066736 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1090477 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1098365 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136210 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136254 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.005851 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542799 # number of writebacks -system.cpu.dcache.writebacks::total 1542799 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461435 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1461435 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910564 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910564 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 8.061158 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542798 # number of writebacks +system.cpu.dcache.writebacks::total 1542798 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1430654 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1430654 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910668 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910668 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2371999 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2371999 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2371999 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2371999 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322573 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322573 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220744 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220744 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2341322 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2341322 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2341322 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2341322 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322593 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322593 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220724 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220724 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 1543317 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1543317 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1543328 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1543328 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27142024000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27142024000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845028694 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845028694 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27108294500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27108294500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845527195 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845527195 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1269000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1269000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28987052694 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28987052694 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28988321694 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28988321694 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015778 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015778 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28953821695 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28953821695 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28955090695 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28955090695 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015801 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015801 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20522.136774 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20522.136774 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8358.228056 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8358.228056 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009311 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009311 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009307 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009307 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20496.323888 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20496.323888 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8361.243884 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8361.243884 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115363.636364 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115363.636364 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18782.306353 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18782.306353 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18782.994732 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18782.994732 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 725588 # number of replacements -system.cpu.icache.tags.tagsinuse 511.809147 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81470653 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726100 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.203075 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 346654500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.809147 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999627 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999627 # Average percentage of cache occupancy +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18760.774160 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18760.774160 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18761.462693 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18761.462693 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 726144 # number of replacements +system.cpu.icache.tags.tagsinuse 511.811939 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81493663 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726656 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.148889 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 348619500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.811939 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999633 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999633 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165133459 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165133459 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81470653 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81470653 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81470653 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81470653 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81470653 # number of overall hits -system.cpu.icache.overall_hits::total 81470653 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 733019 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 733019 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 733019 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 733019 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 733019 # number of overall misses -system.cpu.icache.overall_misses::total 733019 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8417582442 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8417582442 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8417582442 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8417582442 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8417582442 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8417582442 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82203672 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82203672 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82203672 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82203672 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82203672 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82203672 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008917 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008917 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008917 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008917 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008917 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.443733 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11483.443733 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.443733 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11483.443733 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.443733 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11483.443733 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 142274 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165181558 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165181558 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81493663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81493663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81493663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81493663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81493663 # number of overall hits +system.cpu.icache.overall_hits::total 81493663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 733780 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 733780 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 733780 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 733780 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 733780 # number of overall misses +system.cpu.icache.overall_misses::total 733780 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8421387941 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8421387941 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8421387941 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8421387941 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8421387941 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8421387941 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82227443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82227443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82227443 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82227443 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82227443 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82227443 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008924 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008924 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008924 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008924 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008924 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008924 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11476.720463 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11476.720463 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11476.720463 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11476.720463 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11476.720463 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11476.720463 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 139290 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4376 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4412 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.512340 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.570716 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 725588 # number of writebacks -system.cpu.icache.writebacks::total 725588 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6903 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 6903 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 6903 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 6903 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 6903 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 6903 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726116 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726116 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726116 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726116 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726116 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726116 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7892899950 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 7892899950 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7892899950 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 7892899950 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7892899950 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 7892899950 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008833 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008833 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008833 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10870.026208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10870.026208 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10870.026208 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10870.026208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10870.026208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10870.026208 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 404432 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 404544 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue +system.cpu.icache.writebacks::writebacks 726144 # number of writebacks +system.cpu.icache.writebacks::total 726144 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7107 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7107 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7107 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7107 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7107 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7107 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726673 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 726673 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 726673 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 726673 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 726673 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 726673 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7893866450 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7893866450 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7893866450 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7893866450 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7893866450 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7893866450 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008837 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008837 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008837 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10863.024290 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10863.024290 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10863.024290 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10863.024290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10863.024290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10863.024290 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 402240 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 402337 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 88 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28328 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 28103 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5246.342429 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1813751 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 6313 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 287.304134 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5253.910549 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1811940 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6312 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 287.062738 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5152.962075 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 93.380354 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.314512 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005699 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.320211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 192 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6121 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 5156.372421 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 97.538128 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.314720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005953 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.320673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 189 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 103 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 554 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1140 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011719 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373596 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 70548166 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 70548166 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 968244 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 968244 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1045693 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1045693 # number of WritebackClean hits +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 101 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 737 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 554 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4127 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011536 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373718 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 70566797 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 70566797 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 968251 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 968251 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1046259 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1046259 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 219960 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 219960 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696520 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 696520 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094361 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1094361 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 696520 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1314321 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2010841 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 696520 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1314321 # number of overall hits -system.cpu.l2cache.overall_hits::total 2010841 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 779 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 779 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29515 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 29515 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228211 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 228211 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 29515 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 228990 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 258505 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 29515 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 228990 # number of overall misses -system.cpu.l2cache.overall_misses::total 258505 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 43000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 43000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70551500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 70551500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2627115000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2627115000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18006396500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18006396500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2627115000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18076948000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20704063000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2627115000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18076948000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20704063000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 968244 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 968244 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1045693 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1045693 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 220739 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 220739 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726035 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 726035 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322572 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1322572 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 726035 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1543311 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2269346 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 726035 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1543311 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2269346 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.941176 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.941176 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003529 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003529 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040652 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040652 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172551 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172551 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040652 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.148376 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.113912 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040652 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148376 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.113912 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2687.500000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2687.500000 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90566.752246 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90566.752246 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89009.486702 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89009.486702 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78902.403916 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78902.403916 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89009.486702 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78942.084807 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80091.537881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89009.486702 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78942.084807 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80091.537881 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 219940 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 219940 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 697144 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 697144 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094316 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1094316 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 697144 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1314256 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2011400 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 697144 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1314256 # number of overall hits +system.cpu.l2cache.overall_hits::total 2011400 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 790 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 790 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29447 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 29447 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228264 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 228264 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 29447 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 229054 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 258501 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 29447 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 229054 # number of overall misses +system.cpu.l2cache.overall_misses::total 258501 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 42000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 42000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71200500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 71200500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2623850500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2623850500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17976905500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17976905500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2623850500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 18048106000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20671956500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2623850500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 18048106000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20671956500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 968251 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 968251 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1046259 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1046259 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 220730 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 220730 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726591 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 726591 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322580 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1322580 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 726591 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1543310 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2269901 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 726591 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1543310 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2269901 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.944444 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.944444 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003579 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003579 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040528 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040528 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172590 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172590 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040528 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148417 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.113882 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040528 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148417 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.113882 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2470.588235 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2470.588235 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90127.215190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90127.215190 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89104.170204 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89104.170204 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78754.886885 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78754.886885 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89104.170204 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78794.109686 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79968.574590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89104.170204 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78794.109686 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79968.574590 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 49 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 49 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 83 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 85 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 83 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 94 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54467 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 54467 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 730 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 730 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29504 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29504 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228177 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228177 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 29504 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 228907 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 258411 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 29504 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 228907 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54467 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 312878 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 206471258 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 206471258 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 251000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 251000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64550000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64550000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2449507500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2449507500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16634852500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16634852500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2449507500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16699402500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19148910000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2449507500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16699402500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 206471258 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19355381258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 85 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 96 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54078 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 54078 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 739 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 739 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29436 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29436 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228230 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228230 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 29436 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 228969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 258405 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 29436 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 228969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54078 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 312483 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 206290287 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 206290287 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 263000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 263000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65107500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65107500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2446651000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2446651000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16605070000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16605070000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2446651000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16670177500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19116828500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2446651000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16670177500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 206290287 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19323118787 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040637 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172525 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172525 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.113870 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.944444 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.944444 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040512 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172564 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172564 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148362 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113840 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148362 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.137871 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3790.758771 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88424.657534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88424.657534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83022.895201 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83022.895201 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72903.283416 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72903.283416 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74102.534335 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61862.391277 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4537831 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268421 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51822 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51821 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137664 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3814.680406 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3814.680406 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15470.588235 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15470.588235 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88102.165088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88102.165088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83117.645060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83117.645060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72755.860316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72755.860316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83117.645060 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72805.390686 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73980.102939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83117.645060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72805.390686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3814.680406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61837.344070 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4538943 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268977 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254452 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51443 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51442 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2048687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300143 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322572 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177738 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6807193 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92903808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290414848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55922 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2325285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131736 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338205 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2049252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968251 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55450 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726673 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179407 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629454 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6808861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92974976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197510912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290485888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55532 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5248 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2325451 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131557 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338010 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2018962 86.83% 86.83% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 306322 13.17% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2019523 86.84% 86.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305927 13.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2325285 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4537302500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2325451 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4538413500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1089460423 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1090077361 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2314997455 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2314996455 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261072 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 253753 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 261057 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253739 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260325 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 730 # Transaction distribution -system.membus.trans_dist::ReadExResp 730 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260326 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522127 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522127 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16707520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260300 # Transaction distribution +system.membus.trans_dist::UpgradeReq 17 # Transaction distribution +system.membus.trans_dist::ReadExReq 739 # Transaction distribution +system.membus.trans_dist::ReadExResp 739 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260301 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522096 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522096 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16706496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16706496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261072 # Request fanout histogram +system.membus.snoop_fanout::samples 261057 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261072 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261057 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261072 # Request fanout histogram -system.membus.reqLayer0.occupancy 329884354 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 261057 # Request fanout histogram +system.membus.reqLayer0.occupancy 317283410 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1377672131 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1389540628 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index ec456bd8f..a62595a11 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 781022 # Simulator instruction rate (inst/s) -host_op_rate 937704 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 577011080 # Simulator tick rate (ticks/s) -host_mem_usage 268872 # Number of bytes of host memory used -host_seconds 349.59 # Real time elapsed on the host +host_inst_rate 1476968 # Simulator instruction rate (inst/s) +host_op_rate 1773264 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1091168515 # Simulator tick rate (ticks/s) +host_mem_usage 268416 # Number of bytes of host memory used +host_seconds 184.86 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Cl system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction @@ -215,8 +217,10 @@ system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Cl system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction -system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 44185161 13.48% 62.20% # Class of executed instruction +system.cpu.op_class::MemWrite 55008376 16.78% 78.98% # Class of executed instruction +system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812145 # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 81799693e..42d337cb5 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517298 # Nu sim_ticks 517297855500 # Number of ticks simulated final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 565388 # Simulator instruction rate (inst/s) -host_op_rate 678769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1072356714 # Simulator tick rate (ticks/s) -host_mem_usage 278352 # Number of bytes of host memory used -host_seconds 482.39 # Real time elapsed on the host +host_inst_rate 1075622 # Simulator instruction rate (inst/s) +host_op_rate 1291325 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2040106124 # Simulator tick rate (ticks/s) +host_mem_usage 278152 # Number of bytes of host memory used +host_seconds 253.56 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -187,7 +187,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Cl system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction @@ -209,8 +211,10 @@ system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Cl system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 44185174 13.48% 62.20% # Class of executed instruction +system.cpu.op_class::MemWrite 55008381 16.78% 78.98% # Class of executed instruction +system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 40d44c1cb..42592acc9 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.521167 # Nu sim_ticks 521167228000 # Number of ticks simulated final_tick 521167228000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 258077 # Simulator instruction rate (inst/s) -host_op_rate 258077 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 144813393 # Simulator tick rate (ticks/s) -host_mem_usage 260992 # Number of bytes of host memory used -host_seconds 3598.89 # Real time elapsed on the host +host_inst_rate 492017 # Simulator instruction rate (inst/s) +host_op_rate 492017 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 276083455 # Simulator tick rate (ticks/s) +host_mem_usage 263220 # Number of bytes of host memory used +host_seconds 1887.72 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -351,7 +351,9 @@ system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Cl system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction @@ -373,8 +375,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::MemRead 237705247 25.59% 89.42% # Class of committed instruction -system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 228135214 24.56% 88.39% # Class of committed instruction +system.cpu.op_class_0::MemWrite 94471145 10.17% 98.56% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 9570033 1.03% 99.59% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 3836926 0.41% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 928789150 # Class of committed instruction diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index d1e4abf0c..b479c4175 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.180965 # Nu sim_ticks 180964610500 # Number of ticks simulated final_tick 180964610500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216717 # Simulator instruction rate (inst/s) -host_op_rate 216717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46556270 # Simulator tick rate (ticks/s) -host_mem_usage 262532 # Number of bytes of host memory used -host_seconds 3887.01 # Real time elapsed on the host +host_inst_rate 431391 # Simulator instruction rate (inst/s) +host_op_rate 431391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92673550 # Simulator tick rate (ticks/s) +host_mem_usage 265016 # Number of bytes of host memory used +host_seconds 1952.71 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -429,37 +429,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 361665180 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3586644 19.39% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11792491 63.74% 83.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3122167 16.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3586644 18.56% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11632892 60.20% 78.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3008624 15.57% 94.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 913480 4.73% 99.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 182872 0.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued @@ -470,7 +474,9 @@ system.cpu.iq.FU_type_0::FloatAdd 13297886 1.53% 59.47% # Ty system.cpu.iq.FU_type_0::FloatCmp 3826557 0.44% 59.91% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 3339806 0.38% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.30% # Type of FU issued @@ -492,22 +498,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 244265808 28.02% 88.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 101807385 11.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 234518362 26.91% 87.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 97834915 11.22% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 9747446 1.12% 99.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 3972470 0.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 871651299 # Type of FU issued system.cpu.iq.rate 2.408347 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18501302 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021226 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2054197029 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 19324512 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2054837876 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 876768256 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 835988686 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 69282679 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 69465042 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36778231 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 34166819 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 855053167 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 35098158 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 855694014 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 35280521 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 65597237 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 7548743 # Number of loads squashed @@ -586,7 +594,9 @@ system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Cl system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction @@ -608,8 +618,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 237510597 25.58% 89.41% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 227943648 24.55% 88.38% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 94464282 10.17% 98.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 9566949 1.03% 99.59% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 3836918 0.41% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index efcf10ec9..fdd12f539 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.464395 # Nu sim_ticks 464394627000 # Number of ticks simulated final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1533629 # Simulator instruction rate (inst/s) -host_op_rate 1533629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 766980884 # Simulator tick rate (ticks/s) -host_mem_usage 251816 # Number of bytes of host memory used -host_seconds 605.48 # Real time elapsed on the host +host_inst_rate 2996785 # Simulator instruction rate (inst/s) +host_op_rate 2996785 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1498717563 # Simulator tick rate (ticks/s) +host_mem_usage 251436 # Number of bytes of host memory used +host_seconds 309.86 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -103,7 +103,9 @@ system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Cl system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction @@ -125,8 +127,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction -system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction +system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction +system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 7031d8335..b41b24d8c 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.288611 # Nu sim_ticks 1288611150500 # Number of ticks simulated final_tick 1288611150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1122029 # Simulator instruction rate (inst/s) -host_op_rate 1122029 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1557051854 # Simulator tick rate (ticks/s) -host_mem_usage 262324 # Number of bytes of host memory used -host_seconds 827.60 # Real time elapsed on the host +host_inst_rate 2016883 # Simulator instruction rate (inst/s) +host_op_rate 2016883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2798849858 # Simulator tick rate (ticks/s) +host_mem_usage 261432 # Number of bytes of host memory used +host_seconds 460.41 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,7 +104,9 @@ system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Cl system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction @@ -126,8 +128,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction -system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction +system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction +system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index d38edd9f8..7545f6451 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525654 # Nu sim_ticks 525654485500 # Number of ticks simulated final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 213828 # Simulator instruction rate (inst/s) -host_op_rate 263250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 175444467 # Simulator tick rate (ticks/s) -host_mem_usage 278324 # Number of bytes of host memory used -host_seconds 2996.13 # Real time elapsed on the host +host_inst_rate 282925 # Simulator instruction rate (inst/s) +host_op_rate 348318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 232138645 # Simulator tick rate (ticks/s) +host_mem_usage 279272 # Number of bytes of host memory used +host_seconds 2264.40 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -437,7 +437,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction @@ -459,8 +461,10 @@ system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction -system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction -system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction +system.cpu.op_class_0::MemWrite 125149823 15.87% 98.62% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 0a89473ad..8f8bc9d4d 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.339013 # Nu sim_ticks 339012932000 # Number of ticks simulated final_tick 339012932000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140345 # Simulator instruction rate (inst/s) -host_op_rate 172783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74266222 # Simulator tick rate (ticks/s) -host_mem_usage 275384 # Number of bytes of host memory used -host_seconds 4564.83 # Real time elapsed on the host +host_inst_rate 218277 # Simulator instruction rate (inst/s) +host_op_rate 268728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115505586 # Simulator tick rate (ticks/s) +host_mem_usage 277356 # Number of bytes of host memory used +host_seconds 2935.04 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -538,37 +538,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 677553693 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66603323 24.62% 24.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 134116736 49.58% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69116750 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66603323 23.99% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18142 0.01% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.23% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 133475448 48.09% 72.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 66440411 23.94% 96.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 5100435 1.84% 98.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 5300037 1.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -579,7 +583,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued @@ -601,22 +607,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 266665907 31.01% 81.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 157233466 18.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 259646740 30.19% 80.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 153401509 17.84% 98.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 7019167 0.82% 99.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 860030622 # Type of FU issued system.cpu.iq.rate 1.268433 # Inst issue rate -system.cpu.iq.fu_busy_cnt 270491840 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2619781164 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 277574685 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.322750 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2622330507 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 980332291 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 820083655 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 57542493 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 62075995 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 24878671 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1098501615 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 32020847 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 1101050958 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36554349 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 13986301 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 19641213 # Number of loads squashed @@ -695,7 +703,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction @@ -717,8 +727,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 125149822 15.87% 98.62% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index e76db2752..a0c974f67 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778500 # Number of ticks simulated final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 969638 # Simulator instruction rate (inst/s) -host_op_rate 1193752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 598936996 # Simulator tick rate (ticks/s) -host_mem_usage 268708 # Number of bytes of host memory used -host_seconds 660.72 # Real time elapsed on the host +host_inst_rate 1825974 # Simulator instruction rate (inst/s) +host_op_rate 2248015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1127888505 # Simulator tick rate (ticks/s) +host_mem_usage 268260 # Number of bytes of host memory used +host_seconds 350.86 # Real time elapsed on the host sim_insts 640654411 # Number of instructions simulated sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Cl system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction @@ -215,8 +217,10 @@ system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction -system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction +system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction +system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index c71a30606..8c0d9c5fc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.046047 # Nu sim_ticks 1046047111500 # Number of ticks simulated final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 666714 # Simulator instruction rate (inst/s) -host_op_rate 819099 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1090788712 # Simulator tick rate (ticks/s) -host_mem_usage 278188 # Number of bytes of host memory used -host_seconds 958.98 # Real time elapsed on the host +host_inst_rate 1255251 # Simulator instruction rate (inst/s) +host_op_rate 1542152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2053674689 # Simulator tick rate (ticks/s) +host_mem_usage 277480 # Number of bytes of host memory used +host_seconds 509.35 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -194,7 +194,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Cl system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction @@ -216,8 +218,10 @@ system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction -system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction +system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction +system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 4a990b700..0d9a67eb8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061709 # Nu sim_ticks 61709224000 # Number of ticks simulated final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 242211 # Simulator instruction rate (inst/s) -host_op_rate 242211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 169006859 # Simulator tick rate (ticks/s) -host_mem_usage 262168 # Number of bytes of host memory used -host_seconds 365.13 # Real time elapsed on the host +host_inst_rate 484192 # Simulator instruction rate (inst/s) +host_op_rate 484192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 337853764 # Simulator tick rate (ticks/s) +host_mem_usage 263376 # Number of bytes of host memory used +host_seconds 182.65 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -353,7 +353,9 @@ system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Cl system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.40% # Class of committed instruction system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.44% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction @@ -375,8 +377,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::MemRead 20366786 23.03% 83.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 20366476 23.03% 83.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 14619024 16.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 310 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 6ed69f426..53a1c5599 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022820 # Nu sim_ticks 22819771500 # Number of ticks simulated final_tick 22819771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186519 # Simulator instruction rate (inst/s) -host_op_rate 186519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53476835 # Simulator tick rate (ticks/s) -host_mem_usage 263708 # Number of bytes of host memory used -host_seconds 426.72 # Real time elapsed on the host +host_inst_rate 390933 # Simulator instruction rate (inst/s) +host_op_rate 390933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 112084385 # Simulator tick rate (ticks/s) +host_mem_usage 265424 # Number of bytes of host memory used +host_seconds 203.59 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -438,7 +438,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available @@ -460,8 +462,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168337 46.29% 55.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1114013 44.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1168317 46.29% 55.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1113838 44.13% 99.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 25 0.00% 99.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 417 0.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -472,7 +476,9 @@ system.cpu.iq.FU_type_0::FloatAdd 121159 0.14% 55.92% # Ty system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 120693 0.14% 56.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 56.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 39087 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -494,22 +500,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22887844 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15994084 18.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22887385 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15970151 18.03% 99.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 459 0.00% 99.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 23933 0.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 88573949 # Type of FU issued system.cpu.iq.rate 1.940728 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2523813 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028494 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223970382 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 2524060 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028497 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223970516 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 101417859 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 86818116 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611328 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 611441 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 420538 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 299902 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90791946 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305816 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 90792080 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305929 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1674439 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 2855253 # Number of loads squashed @@ -588,7 +596,9 @@ system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Cl system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.46% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction @@ -610,8 +620,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 20276638 22.95% 83.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 20276331 22.95% 83.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 14611772 16.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 307 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index feef465f0..d9533629f 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.060131 # Nu sim_ticks 60130734500 # Number of ticks simulated final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142105 # Simulator instruction rate (inst/s) -host_op_rate 181732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120494644 # Simulator tick rate (ticks/s) -host_mem_usage 279144 # Number of bytes of host memory used -host_seconds 499.03 # Real time elapsed on the host +host_inst_rate 310652 # Simulator instruction rate (inst/s) +host_op_rate 397278 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 263409545 # Simulator tick rate (ticks/s) +host_mem_usage 281384 # Number of bytes of host memory used +host_seconds 228.28 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -441,7 +441,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction @@ -463,8 +465,10 @@ system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction -system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction -system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20555707 22.67% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6270a4a24..da2276c3c 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.037982 # Nu sim_ticks 37982056000 # Number of ticks simulated final_tick 37982056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105525 # Simulator instruction rate (inst/s) -host_op_rate 134954 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56525025 # Simulator tick rate (ticks/s) -host_mem_usage 282344 # Number of bytes of host memory used -host_seconds 671.95 # Real time elapsed on the host +host_inst_rate 220867 # Simulator instruction rate (inst/s) +host_op_rate 282464 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118308818 # Simulator tick rate (ticks/s) +host_mem_usage 284316 # Number of bytes of host memory used +host_seconds 321.04 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -527,7 +527,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.63% # attempts to use FU when none available @@ -549,8 +551,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11088474 37.25% 59.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11940322 40.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11088448 37.25% 59.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11940306 40.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 30 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -561,7 +565,9 @@ system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.28% # Type of FU issued @@ -583,22 +589,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23958877 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21133721 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23958815 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21133689 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 62 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 94484787 # Type of FU issued system.cpu.iq.rate 1.243808 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29765517 # FU busy when requested +system.cpu.iq.fu_busy_cnt 29765526 # FU busy when requested system.cpu.iq.fu_busy_rate 0.315030 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 291599265 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 104199326 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 93203450 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 335 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 124250121 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 183 # Number of floating point alu accesses +system.cpu.iq.fp_alu_accesses 192 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1368397 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1289383 # Number of loads squashed @@ -677,7 +685,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction @@ -699,8 +709,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20555706 22.67% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 5d202194f..d9427be27 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.241902 # Nu sim_ticks 1241902335500 # Number of ticks simulated final_tick 1241902335500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311711 # Simulator instruction rate (inst/s) -host_op_rate 311711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 211957790 # Simulator tick rate (ticks/s) -host_mem_usage 254092 # Number of bytes of host memory used -host_seconds 5859.20 # Real time elapsed on the host +host_inst_rate 473348 # Simulator instruction rate (inst/s) +host_op_rate 473348 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 321867657 # Simulator tick rate (ticks/s) +host_mem_usage 255296 # Number of bytes of host memory used +host_seconds 3858.43 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -366,7 +366,9 @@ system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Cl system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction @@ -388,8 +390,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::MemRead 449492741 24.61% 91.11% # Class of committed instruction -system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 449492662 24.61% 91.11% # Class of committed instruction +system.cpu.op_class_0::MemWrite 162429751 8.89% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 79 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 55 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1826378509 # Class of committed instruction diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index d6615dc1b..6249c394a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.684200 # Nu sim_ticks 684199968000 # Number of ticks simulated final_tick 684199968000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 209715 # Simulator instruction rate (inst/s) -host_op_rate 209715 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82651888 # Simulator tick rate (ticks/s) -host_mem_usage 254604 # Number of bytes of host memory used -host_seconds 8278.09 # Real time elapsed on the host +host_inst_rate 295566 # Simulator instruction rate (inst/s) +host_op_rate 295566 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 116486932 # Simulator tick rate (ticks/s) +host_mem_usage 257340 # Number of bytes of host memory used +host_seconds 5873.62 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -449,7 +449,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.86% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.86% # attempts to use FU when none available @@ -471,8 +473,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.86% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18955564 51.66% 87.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4577828 12.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18955559 51.65% 87.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4574949 12.47% 99.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 21 0.00% 99.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 8342 0.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -483,7 +487,9 @@ system.cpu.iq.FU_type_0::FloatAdd 895059 0.03% 65.56% # Ty system.cpu.iq.FU_type_0::FloatCmp 21 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued @@ -505,22 +511,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 671607156 25.63% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230690638 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 671606942 25.63% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230625627 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 214 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 65011 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 2620166340 # Type of FU issued system.cpu.iq.rate 1.914766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36691137 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014003 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6644947058 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 36696616 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014005 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6644950011 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 4031627633 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 2518705843 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1938210 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 1940736 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 1246935 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 885827 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2655891113 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 966364 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 2655894066 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 968890 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69399237 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 272696697 # Number of loads squashed @@ -599,7 +607,9 @@ system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Cl system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction @@ -621,8 +631,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 444595584 24.43% 91.17% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 160728448 8.83% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 79 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 54 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 5f8a25a7f..9f7e15391 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1729437 # Simulator instruction rate (inst/s) -host_op_rate 1729437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 867853739 # Simulator tick rate (ticks/s) -host_mem_usage 243124 # Number of bytes of host memory used -host_seconds 1052.24 # Real time elapsed on the host +host_inst_rate 3052391 # Simulator instruction rate (inst/s) +host_op_rate 3052390 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1531729085 # Simulator tick rate (ticks/s) +host_mem_usage 242484 # Number of bytes of host memory used +host_seconds 596.18 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -103,7 +103,9 @@ system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Cl system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction @@ -125,8 +127,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction -system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction +system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 622e92943..6af37cfb2 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.639614 # Nu sim_ticks 2639613874500 # Number of ticks simulated final_tick 2639613874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1111155 # Simulator instruction rate (inst/s) -host_op_rate 1111155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1611744129 # Simulator tick rate (ticks/s) -host_mem_usage 254908 # Number of bytes of host memory used -host_seconds 1637.74 # Real time elapsed on the host +host_inst_rate 2013574 # Simulator instruction rate (inst/s) +host_op_rate 2013574 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2920714569 # Simulator tick rate (ticks/s) +host_mem_usage 253500 # Number of bytes of host memory used +host_seconds 903.76 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,7 +104,9 @@ system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Cl system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction @@ -126,8 +128,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction -system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction +system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 16fb45e1d..20e951f6a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.150226 # Nu sim_ticks 1150225722500 # Number of ticks simulated final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 267770 # Simulator instruction rate (inst/s) -host_op_rate 288482 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 199406485 # Simulator tick rate (ticks/s) -host_mem_usage 271372 # Number of bytes of host memory used -host_seconds 5768.25 # Real time elapsed on the host +host_inst_rate 386915 # Simulator instruction rate (inst/s) +host_op_rate 416843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 288133243 # Simulator tick rate (ticks/s) +host_mem_usage 273608 # Number of bytes of host memory used +host_seconds 3991.99 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -448,7 +448,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction @@ -470,8 +472,10 @@ system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction -system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction +system.cpu.op_class_0::MemWrite 174847022 10.51% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index ea5c16164..3e40b495b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.787742 # Nu sim_ticks 787742202500 # Number of ticks simulated final_tick 787742202500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201500 # Simulator instruction rate (inst/s) -host_op_rate 217086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 102767126 # Simulator tick rate (ticks/s) -host_mem_usage 327820 # Number of bytes of host memory used -host_seconds 7665.31 # Real time elapsed on the host +host_inst_rate 267668 # Simulator instruction rate (inst/s) +host_op_rate 288372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 136513298 # Simulator tick rate (ticks/s) +host_mem_usage 329792 # Number of bytes of host memory used +host_seconds 5770.44 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -539,7 +539,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available @@ -561,8 +563,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191460462 47.22% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47920671 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191460455 47.22% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47920650 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -573,7 +577,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued @@ -595,22 +601,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532139540 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186322827 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532139508 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186322803 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 32 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 1857513748 # Type of FU issued system.cpu.iq.rate 1.179011 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405481908 # FU busy when requested +system.cpu.iq.fu_busy_cnt 405481927 # FU busy when requested system.cpu.iq.fu_busy_rate 0.218293 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5709408399 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 5709408400 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2231939413 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1805717250 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 255 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262995523 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 2262995524 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 151 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 17822173 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 84257734 # Number of loads squashed @@ -689,7 +697,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction @@ -711,8 +721,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 174847021 10.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index ddb5178a1..4d1539e1f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1176831 # Simulator instruction rate (inst/s) -host_op_rate 1267857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 633929666 # Simulator tick rate (ticks/s) -host_mem_usage 260476 # Number of bytes of host memory used -host_seconds 1312.48 # Real time elapsed on the host +host_inst_rate 2178592 # Simulator instruction rate (inst/s) +host_op_rate 2347103 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1173553065 # Simulator tick rate (ticks/s) +host_mem_usage 260024 # Number of bytes of host memory used +host_seconds 708.97 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Cl system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction @@ -215,8 +217,10 @@ system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction -system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 02e32a48c..11abffe81 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.379922 # Nu sim_ticks 2379921906500 # Number of ticks simulated final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 802178 # Simulator instruction rate (inst/s) -host_op_rate 864460 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1240688848 # Simulator tick rate (ticks/s) -host_mem_usage 272000 # Number of bytes of host memory used -host_seconds 1918.23 # Real time elapsed on the host +host_inst_rate 1526036 # Simulator instruction rate (inst/s) +host_op_rate 1644518 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2360243305 # Simulator tick rate (ticks/s) +host_mem_usage 271808 # Number of bytes of host memory used +host_seconds 1008.34 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -194,7 +194,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Cl system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction @@ -216,8 +218,10 @@ system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction -system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index e4956c5fa..86df30690 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 913315 # Simulator instruction rate (inst/s) -host_op_rate 1423027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 864105629 # Simulator tick rate (ticks/s) -host_mem_usage 264708 # Number of bytes of host memory used -host_seconds 3293.59 # Real time elapsed on the host +host_inst_rate 1654731 # Simulator instruction rate (inst/s) +host_op_rate 2578221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1565575242 # Simulator tick rate (ticks/s) +host_mem_usage 262288 # Number of bytes of host memory used +host_seconds 1817.87 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -77,7 +77,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Cl system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction @@ -101,6 +103,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 3b577baaf..037ceb011 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.898831 # Nu sim_ticks 5898831348500 # Number of ticks simulated final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 637466 # Simulator instruction rate (inst/s) -host_op_rate 993229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1250066735 # Simulator tick rate (ticks/s) -host_mem_usage 275724 # Number of bytes of host memory used -host_seconds 4718.81 # Real time elapsed on the host +host_inst_rate 1175665 # Simulator instruction rate (inst/s) +host_op_rate 1831792 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2305472192 # Simulator tick rate (ticks/s) +host_mem_usage 275096 # Number of bytes of host memory used +host_seconds 2558.62 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -78,7 +78,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Cl system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction @@ -102,6 +104,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 2c8dfca63..40657583a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053438 # Nu sim_ticks 53437621500 # Number of ticks simulated final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 247892 # Simulator instruction rate (inst/s) -host_op_rate 247892 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 144138078 # Simulator tick rate (ticks/s) -host_mem_usage 256712 # Number of bytes of host memory used -host_seconds 370.74 # Real time elapsed on the host +host_inst_rate 468238 # Simulator instruction rate (inst/s) +host_op_rate 468238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272260061 # Simulator tick rate (ticks/s) +host_mem_usage 257916 # Number of bytes of host memory used +host_seconds 196.27 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -327,7 +327,9 @@ system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Cl system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction @@ -349,8 +351,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::MemRead 19996208 21.76% 92.93% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 19433628 21.15% 92.31% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6424338 6.99% 99.30% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 76788 0.08% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91903089 # Class of committed instruction diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 2ed297d74..bb93c695e 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.021955 # Nu sim_ticks 21954917500 # Number of ticks simulated final_tick 21954917500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181107 # Simulator instruction rate (inst/s) -host_op_rate 181107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47234568 # Simulator tick rate (ticks/s) -host_mem_usage 257228 # Number of bytes of host memory used -host_seconds 464.81 # Real time elapsed on the host +host_inst_rate 353144 # Simulator instruction rate (inst/s) +host_op_rate 353144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92103562 # Simulator tick rate (ticks/s) +host_mem_usage 259964 # Number of bytes of host memory used +host_seconds 238.37 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -401,37 +401,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 43616730 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 484010 20.16% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34926 1.45% 21.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12192 0.51% 22.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1012503 42.17% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 694860 28.94% 93.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 162157 6.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 484010 20.07% 20.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34926 1.45% 21.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12192 0.51% 22.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1012503 41.99% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 682717 28.32% 92.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160804 6.67% 99.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 21053 0.87% 99.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 2406 0.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued @@ -442,7 +446,9 @@ system.cpu.iq.FU_type_0::FloatAdd 2847523 2.85% 64.15% # Ty system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 2443321 2.45% 66.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 314198 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.03% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued @@ -464,22 +470,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24854622 24.91% 92.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7268455 7.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24115562 24.17% 91.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7190219 7.21% 99.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 739060 0.74% 99.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 78236 0.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 99762246 # Type of FU issued system.cpu.iq.rate 2.271979 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2401186 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024069 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229973015 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 2411149 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024169 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229977416 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 129921960 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 89757276 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15688832 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 15694394 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 9653681 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 7189481 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93781523 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8381902 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 93785924 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8387464 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1923320 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 6908286 # Number of loads squashed @@ -558,7 +566,9 @@ system.cpu.commit.op_class_0::FloatAdd 2732553 2.97% 67.37% # Cl system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction @@ -580,8 +590,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 19996198 21.76% 92.93% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 19433618 21.15% 92.31% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6424318 6.99% 99.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 76785 0.08% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 26e7200e9..f4cf26547 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.132539 # Nu sim_ticks 132538562500 # Number of ticks simulated final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171463 # Simulator instruction rate (inst/s) -host_op_rate 180750 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131881088 # Simulator tick rate (ticks/s) -host_mem_usage 273644 # Number of bytes of host memory used -host_seconds 1004.99 # Real time elapsed on the host +host_inst_rate 360845 # Simulator instruction rate (inst/s) +host_op_rate 380389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 277544932 # Simulator tick rate (ticks/s) +host_mem_usage 274852 # Number of bytes of host memory used +host_seconds 477.54 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -415,7 +415,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction @@ -437,8 +439,10 @@ system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Cl system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction -system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction -system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction +system.cpu.op_class_0::MemWrite 12498389 6.88% 99.62% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 04ea23c2f..17a991711 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.086053 # Number of seconds simulated -sim_ticks 86053034000 # Number of ticks simulated -final_tick 86053034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.086155 # Number of seconds simulated +sim_ticks 86154694000 # Number of ticks simulated +final_tick 86154694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114393 # Simulator instruction rate (inst/s) -host_op_rate 120589 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57131119 # Simulator tick rate (ticks/s) -host_mem_usage 270696 # Number of bytes of host memory used -host_seconds 1506.24 # Real time elapsed on the host +host_inst_rate 235949 # Simulator instruction rate (inst/s) +host_op_rate 248729 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 117978801 # Simulator tick rate (ticks/s) +host_mem_usage 272668 # Number of bytes of host memory used +host_seconds 730.26 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 652224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 193472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 70848 # Number of bytes read from this memory -system.physmem.bytes_read::total 916544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 652224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 652224 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 10191 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1107 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14321 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 7579326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2248288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 823306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10650920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7579326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7579326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7579326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2248288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 823306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10650920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 14321 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 652480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 193344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory +system.physmem.bytes_read::total 916864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 652480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 652480 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7573354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2244149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 824563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10642067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7573354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7573354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7573354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2244149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 824563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10642067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14326 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 14321 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14326 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 916544 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 916864 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 916544 # Total read bytes from the system interface side +system.physmem.bytesReadSys 916864 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1378 # Per bank write bursts -system.physmem.perBankRdBursts::1 501 # Per bank write bursts -system.physmem.perBankRdBursts::2 5089 # Per bank write bursts -system.physmem.perBankRdBursts::3 804 # Per bank write bursts -system.physmem.perBankRdBursts::4 2285 # Per bank write bursts +system.physmem.perBankRdBursts::0 1380 # Per bank write bursts +system.physmem.perBankRdBursts::1 498 # Per bank write bursts +system.physmem.perBankRdBursts::2 5094 # Per bank write bursts +system.physmem.perBankRdBursts::3 810 # Per bank write bursts +system.physmem.perBankRdBursts::4 2279 # Per bank write bursts system.physmem.perBankRdBursts::5 424 # Per bank write bursts system.physmem.perBankRdBursts::6 384 # Per bank write bursts system.physmem.perBankRdBursts::7 628 # Per bank write bursts system.physmem.perBankRdBursts::8 270 # Per bank write bursts system.physmem.perBankRdBursts::9 231 # Per bank write bursts -system.physmem.perBankRdBursts::10 354 # Per bank write bursts -system.physmem.perBankRdBursts::11 348 # Per bank write bursts -system.physmem.perBankRdBursts::12 321 # Per bank write bursts +system.physmem.perBankRdBursts::10 355 # Per bank write bursts +system.physmem.perBankRdBursts::11 347 # Per bank write bursts +system.physmem.perBankRdBursts::12 322 # Per bank write bursts system.physmem.perBankRdBursts::13 267 # Per bank write bursts system.physmem.perBankRdBursts::14 240 # Per bank write bursts system.physmem.perBankRdBursts::15 797 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 86052975500 # Total gap between requests +system.physmem.totGap 86154635500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 14321 # Read request sizes (log2) +system.physmem.readPktSize::6 14326 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,15 +95,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see @@ -191,29 +191,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8480 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 108.022642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 86.441459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 123.287712 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5899 69.56% 69.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 2101 24.78% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 209 2.46% 96.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 89 1.05% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 41 0.48% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 0.42% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15 0.18% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13 0.15% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 77 0.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8480 # Bytes accessed per row activation -system.physmem.totQLat 1499260235 # Total ticks spent queuing -system.physmem.totMemAccLat 1767778985 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 71605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 104689.63 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 8486 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.983974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.597492 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 122.302837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5884 69.34% 69.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2105 24.81% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 256 3.02% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 62 0.73% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 39 0.46% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 0.44% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 16 0.19% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9 0.11% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 78 0.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8486 # Bytes accessed per row activation +system.physmem.totQLat 1505073312 # Total ticks spent queuing +system.physmem.totMemAccLat 1773685812 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 105058.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 123439.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 10.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 123808.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.64 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 10.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.08 # Data bus utilization in percentage @@ -221,66 +221,66 @@ system.physmem.busUtilRead 0.08 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5837 # Number of row buffer hits during reads +system.physmem.readRowHits 5836 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.76 # Row buffer hit rate for reads +system.physmem.readRowHitRate 40.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6008866.39 # Average gap between requests -system.physmem.pageHitRate 40.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 82060020 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6013865.38 # Average gap between requests +system.physmem.pageHitRate 40.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 51536520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 27380925 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 82088580 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5180800560.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1120628550 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 275264640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12259963560 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8345872320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 9276913815 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 36622770765 # Total energy per rank (pJ) -system.physmem_0.averagePower 425.583720 # Core power per rank (mW) -system.physmem_0.totalIdleTime 82871785017 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 531109000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2203210000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34253599252 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21734056085 # Time in different power states -system.physmem_0.memoryStateTime::ACT 445220983 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 26885838680 # Time in different power states -system.physmem_1.actEnergy 9017820 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4789290 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20191920 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 5189405520.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1121826120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 276469440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12277996650 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8345487360 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9295531755 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 36669774810 # Total energy per rank (pJ) +system.physmem_0.averagePower 425.627121 # Core power per rank (mW) +system.physmem_0.totalIdleTime 82968376764 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 533443000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2206916000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34311542002 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21733088112 # Time in different power states +system.physmem_0.memoryStateTime::ACT 444281236 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 26925423650 # Time in different power states +system.physmem_1.actEnergy 9082080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4823445 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20199060 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 882623040.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 198112620 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 50847360 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1971627720 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1393669440 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18810725700 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23341907430 # Total energy per rank (pJ) -system.physmem_1.averagePower 271.250252 # Core power per rank (mW) -system.physmem_1.totalIdleTime 85485463257 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 101360000 # Time in different power states -system.physmem_1.memoryStateTime::REF 375610000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 77532398500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3629358146 # Time in different power states -system.physmem_1.memoryStateTime::ACT 90573993 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 4323733361 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85625838 # Number of BP lookups -system.cpu.branchPred.condPredicted 68176243 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5935432 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39943176 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38184524 # Number of BTB hits +system.physmem_1.refreshEnergy 885081600.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 198834810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 51009600 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1986610170 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1389476160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18829930140 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23375329815 # Total energy per rank (pJ) +system.physmem_1.averagePower 271.318119 # Core power per rank (mW) +system.physmem_1.totalIdleTime 85585158757 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 101660000 # Time in different power states +system.physmem_1.memoryStateTime::REF 376638000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 77610163250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3618418671 # Time in different power states +system.physmem_1.memoryStateTime::ACT 91210493 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 4356603586 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85641138 # Number of BP lookups +system.cpu.branchPred.condPredicted 68185958 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5937589 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39953535 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38189781 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.597115 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683485 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81916 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681521 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653387 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 28134 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40344 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.585487 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3685328 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81910 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681706 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 653811 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 27895 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40302 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,137 +401,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 172106069 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 172309389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5685351 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347171735 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85625838 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42521396 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158200265 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11884759 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 4307 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78326471 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18089 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169836333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.138878 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.056220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5689865 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347272234 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85641138 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42528920 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158389740 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11889123 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingQuiesceStallCycles 80 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 4192 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78352490 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18126 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 170032695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.057606 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18169241 10.70% 10.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30071574 17.71% 28.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31598899 18.61% 47.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 89996619 52.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18322538 10.78% 10.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30071394 17.69% 28.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31619936 18.60% 47.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90018827 52.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169836333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.497518 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.017196 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17522714 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17948295 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121866676 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6730979 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5767669 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11064280 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189793 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 304996623 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27241409 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5767669 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37489750 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8834769 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 601523 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108355832 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8786790 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277419061 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13180458 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3061814 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 846087 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2626546 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 39334 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 27085 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481448286 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187772528 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296460965 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3003847 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 170032695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.497020 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.015399 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17554898 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18106153 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121828666 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6773205 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5769773 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11065170 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189895 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 305047176 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27240886 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5769773 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37541623 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8963730 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 601187 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108324902 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8831480 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277455959 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13183896 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3097230 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842604 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2610060 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 40707 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26842 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481461567 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1187957820 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296507996 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005110 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188471357 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23624 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13352846 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33915531 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14406995 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2538352 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1801972 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263797881 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45980 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214410891 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5187410 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82207907 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216953193 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 764 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169836333 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.262456 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.019138 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 188484638 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23626 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23627 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13450862 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33923289 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14424821 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2554501 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1823311 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263831896 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45982 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214447255 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5189742 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82241924 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 216953797 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 766 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 170032695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.261212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018500 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 53122752 31.28% 31.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 35940807 21.16% 52.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65514665 38.58% 91.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13639448 8.03% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571104 0.93% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47348 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 209 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53222567 31.30% 31.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36044522 21.20% 52.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65538005 38.54% 91.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13630055 8.02% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1551450 0.91% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45818 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 278 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169836333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 170032695 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35657368 66.16% 66.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153250 0.28% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35732 0.07% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 954 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34277 0.06% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14055726 26.08% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3956441 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35671912 66.13% 66.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153261 0.28% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35713 0.07% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 264 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 557 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 40113 0.07% 66.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 13911271 25.79% 92.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3849843 7.14% 99.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 142059 0.26% 99.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 136275 0.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 166991462 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919191 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167013253 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919503 0.43% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued @@ -544,91 +550,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33016 0.02% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 165181 0.08% 78.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245709 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460330 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206622 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245720 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460387 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206623 0.10% 78.86% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31869240 14.86% 93.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13372180 6.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31297547 14.59% 93.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13233764 6.17% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 576685 0.27% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 147618 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214410891 # Type of FU issued -system.cpu.iq.rate 1.245807 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53895257 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251364 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653788467 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344049655 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204252570 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952315 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2009022 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 214447255 # Type of FU issued +system.cpu.iq.rate 1.244548 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53942541 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251542 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654066032 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344116098 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204293302 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3993456 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2010644 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1806352 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266172688 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133460 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1598637 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 266215456 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2174340 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1590107 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6019387 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7380 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7051 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1762361 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6027145 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7088 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1780187 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25560 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 770 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25576 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 767 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5767669 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5624657 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 173600 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263863986 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5769773 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5628686 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 175497 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263897928 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33915531 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14406995 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23572 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 166551 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7051 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3148917 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246700 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6395617 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207126816 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30634090 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7284075 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33923289 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14424821 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23574 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3848 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 168493 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7088 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3148569 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6396009 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207164807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30640004 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7282448 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20125 # number of nop insts executed -system.cpu.iew.exec_refs 43772682 # number of memory reference insts executed -system.cpu.iew.exec_branches 44853086 # Number of branches executed -system.cpu.iew.exec_stores 13138592 # Number of stores executed -system.cpu.iew.exec_rate 1.203484 # Inst execution rate -system.cpu.iew.wb_sent 206368979 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206058922 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129395738 # num instructions producing a value -system.cpu.iew.wb_consumers 221650226 # num instructions consuming a value -system.cpu.iew.wb_rate 1.197279 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583783 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68671574 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20050 # number of nop insts executed +system.cpu.iew.exec_refs 43787631 # number of memory reference insts executed +system.cpu.iew.exec_branches 44861497 # Number of branches executed +system.cpu.iew.exec_stores 13147627 # Number of stores executed +system.cpu.iew.exec_rate 1.202284 # Inst execution rate +system.cpu.iew.wb_sent 206408899 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206099654 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129383753 # num instructions producing a value +system.cpu.iew.wb_consumers 221651913 # num instructions consuming a value +system.cpu.iew.wb_rate 1.196102 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583725 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68705367 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5760722 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158539716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.145772 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.650496 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5762801 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158729167 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.144404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.650562 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73944910 46.64% 46.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41143540 25.95% 72.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22534900 14.21% 86.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9516225 6.00% 92.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3553894 2.24% 95.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2144247 1.35% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1327660 0.84% 97.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1009164 0.64% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3365176 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 74124112 46.70% 46.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41154034 25.93% 72.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22561648 14.21% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9505511 5.99% 92.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3552884 2.24% 95.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2129952 1.34% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1300201 0.82% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1012623 0.64% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3388202 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158539716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158729167 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -647,7 +655,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction @@ -669,40 +679,42 @@ system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 12498388 6.88% 99.62% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3365176 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 405491255 # The number of ROB reads -system.cpu.rob.rob_writes 511954468 # The number of ROB writes -system.cpu.timesIdled 10012 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2269736 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3388202 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 405691473 # The number of ROB reads +system.cpu.rob.rob_writes 512028923 # The number of ROB writes +system.cpu.timesIdled 10004 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2276694 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.998857 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.998857 # CPI: Total CPI of All Threads -system.cpu.ipc 1.001144 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.001144 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218726711 # number of integer regfile reads -system.cpu.int_regfile_writes 114168819 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904003 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441695 # number of floating regfile writes -system.cpu.cc_regfile_reads 708199076 # number of cc regfile reads -system.cpu.cc_regfile_writes 229511616 # number of cc regfile writes -system.cpu.misc_regfile_reads 57440558 # number of misc regfile reads +system.cpu.cpi 1.000037 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.000037 # CPI: Total CPI of All Threads +system.cpu.ipc 0.999963 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.999963 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218765999 # number of integer regfile reads +system.cpu.int_regfile_writes 114196362 # number of integer regfile writes +system.cpu.fp_regfile_reads 2903942 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441736 # number of floating regfile writes +system.cpu.cc_regfile_reads 708332294 # number of cc regfile reads +system.cpu.cc_regfile_writes 229516818 # number of cc regfile writes +system.cpu.misc_regfile_reads 57457287 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72579 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.404028 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41032024 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73091 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.382715 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 516933500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.404028 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998836 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998836 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72598 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.401142 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41046057 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73110 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.428765 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 556160500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.401142 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998830 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998830 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id @@ -710,47 +722,47 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82362375 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82362375 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28645802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28645802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341304 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341304 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82390572 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82390572 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28659846 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28659846 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341293 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341293 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40987106 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40987106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40987470 # number of overall hits -system.cpu.dcache.overall_hits::total 40987470 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89259 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89259 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22983 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22983 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 41001139 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41001139 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41001503 # number of overall hits +system.cpu.dcache.overall_hits::total 41001503 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89304 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89304 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22994 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22994 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112242 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112242 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112358 # number of overall misses -system.cpu.dcache.overall_misses::total 112358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1986737500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1986737500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 247540999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 247540999 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2234278499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2234278499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2234278499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2234278499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28735061 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28735061 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 112298 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112298 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112414 # number of overall misses +system.cpu.dcache.overall_misses::total 112414 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1992894500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1992894500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 247642499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 247642499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2317500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2317500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2240536999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2240536999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2240536999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2240536999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28749150 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28749150 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) @@ -759,14 +771,14 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41099348 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41099348 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41099828 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41099828 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41113437 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41113437 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41113917 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41113917 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001859 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001859 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses @@ -775,282 +787,282 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22258.119629 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22258.119629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10770.613018 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10770.613018 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19905.904198 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19905.904198 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19885.353059 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19885.353059 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22315.848114 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22315.848114 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10769.874706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10769.874706 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8913.461538 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8913.461538 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19951.708837 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19951.708837 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19931.120670 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19931.120670 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11288 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11146 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 867 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 13.049711 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72579 # number of writebacks -system.cpu.dcache.writebacks::total 72579 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24837 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24837 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14427 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14427 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 12.855825 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72598 # number of writebacks +system.cpu.dcache.writebacks::total 72598 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24877 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24877 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14424 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14424 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39264 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39264 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39264 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39264 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64422 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64422 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8556 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8556 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 39301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64427 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64427 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8570 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8570 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 72978 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 72978 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73091 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73091 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1062843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1062843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87501999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 87501999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 72997 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72997 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73110 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73110 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1062486000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1062486000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88387499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 88387499 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 969000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 969000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1150345499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1150345499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1151314499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1151314499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1150873499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1150873499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1151842499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1151842499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002241 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002241 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16498.145044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16498.145044 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10226.975105 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10226.975105 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16491.315753 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16491.315753 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10313.593816 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10313.593816 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8575.221239 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8575.221239 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15762.907986 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15762.907986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15751.795693 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15751.795693 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 53612 # number of replacements -system.cpu.icache.tags.tagsinuse 510.587809 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78268729 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54124 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1446.100233 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 85282294500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.587809 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997242 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997242 # Average percentage of cache occupancy +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15766.038317 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15766.038317 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15754.924073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15754.924073 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 53656 # number of replacements +system.cpu.icache.tags.tagsinuse 510.578461 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78294727 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54168 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1445.405535 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 85384212500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.578461 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997224 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997224 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156706996 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156706996 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78268729 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78268729 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78268729 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78268729 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78268729 # number of overall hits -system.cpu.icache.overall_hits::total 78268729 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57707 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57707 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57707 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57707 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57707 # number of overall misses -system.cpu.icache.overall_misses::total 57707 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2245995927 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2245995927 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2245995927 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2245995927 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2245995927 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2245995927 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78326436 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78326436 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78326436 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78326436 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78326436 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78326436 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 156759076 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156759076 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 78294727 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78294727 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78294727 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78294727 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78294727 # number of overall hits +system.cpu.icache.overall_hits::total 78294727 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57727 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57727 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57727 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57727 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57727 # number of overall misses +system.cpu.icache.overall_misses::total 57727 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2248583426 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2248583426 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2248583426 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2248583426 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2248583426 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2248583426 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78352454 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78352454 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78352454 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78352454 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78352454 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78352454 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000737 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000737 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000737 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000737 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000737 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000737 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38920.684267 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38920.684267 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38920.684267 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38920.684267 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38920.684267 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38920.684267 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 93822 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38952.022901 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38952.022901 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38952.022901 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38952.022901 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38952.022901 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38952.022901 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 93736 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 55 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3270 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3241 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.691743 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.921938 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 27.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 53612 # number of writebacks -system.cpu.icache.writebacks::total 53612 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3582 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3582 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3582 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3582 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3582 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3582 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54125 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54125 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54125 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54125 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54125 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54125 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2049967950 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2049967950 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2049967950 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2049967950 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2049967950 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2049967950 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 53656 # number of writebacks +system.cpu.icache.writebacks::total 53656 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3558 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3558 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3558 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3558 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3558 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3558 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54169 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54169 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54169 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54169 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54169 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54169 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2054126952 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2054126952 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2054126952 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2054126952 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2054126952 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2054126952 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37874.696536 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37874.696536 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37874.696536 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37874.696536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37874.696536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37874.696536 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9207 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9207 # number of prefetch candidates identified +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37920.710222 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37920.710222 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37920.710222 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37920.710222 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37920.710222 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37920.710222 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 9281 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9281 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1345 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 1351 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1792.687270 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99060 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2834 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 34.954128 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1796.196657 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99029 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2833 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 34.955524 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1727.437863 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 65.249406 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.105434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003983 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.109417 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 128 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 1727.103732 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 69.092925 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.105414 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004217 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.109631 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 127 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 54 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 60 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 957 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007812 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 958 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007751 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4003735 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4003735 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 64697 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 64697 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 51019 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 51019 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8384 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8384 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43929 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 43929 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61675 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 61675 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 43929 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 70059 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 113988 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 43929 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 70059 # number of overall hits -system.cpu.l2cache.overall_hits::total 113988 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 239 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 239 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10196 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10196 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2793 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2793 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10196 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3032 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 13228 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10196 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3032 # number of overall misses -system.cpu.l2cache.overall_misses::total 13228 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 20303000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 20303000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1707637000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1707637000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 558453500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 558453500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1707637000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 578756500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2286393500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1707637000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 578756500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2286393500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 64697 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 64697 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 51019 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 51019 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 8623 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 8623 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54125 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 54125 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64468 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 64468 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 54125 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 73091 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 127216 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 54125 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 73091 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 127216 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.027717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188379 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188379 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043324 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043324 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188379 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.041483 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103981 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188379 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.041483 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103981 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84949.790795 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84949.790795 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167481.071008 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167481.071008 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199947.547440 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199947.547440 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167481.071008 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 190882.750660 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 172844.987904 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167481.071008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 190882.750660 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 172844.987904 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 4005715 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4005715 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 64715 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 64715 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 51058 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 51058 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8400 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8400 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43969 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 43969 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61680 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 61680 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 43969 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 70080 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 114049 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 43969 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 70080 # number of overall hits +system.cpu.l2cache.overall_hits::total 114049 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 236 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 236 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10200 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 10200 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2794 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2794 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10200 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3030 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 13230 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10200 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3030 # number of overall misses +system.cpu.l2cache.overall_misses::total 13230 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 21058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 21058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1711516500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1711516500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 557966500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 557966500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1711516500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 579024500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2290541000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1711516500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 579024500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2290541000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 64715 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 64715 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 51058 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 51058 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 8636 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 8636 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54169 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 54169 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64474 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 64474 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 54169 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 73110 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 127279 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 54169 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 73110 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 127279 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027327 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.027327 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188300 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188300 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043335 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043335 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188300 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.041444 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103945 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188300 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.041444 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103945 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89228.813559 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89228.813559 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167795.735294 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167795.735294 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199701.682176 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199701.682176 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167795.735294 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 191097.194719 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 173132.350718 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167795.735294 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 191097.194719 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 173132.350718 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1069,136 +1081,136 @@ system.cpu.l2cache.demand_mshr_hits::total 14 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2057 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 2057 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 238 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 238 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10191 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10191 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2785 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2785 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10191 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3023 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 13214 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10191 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3023 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2057 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15271 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 97518621 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 97518621 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 18660000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 18660000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1645631000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1645631000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 541204500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 541204500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1645631000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 559864500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2205495500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1645631000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 559864500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 97518621 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2303014121 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2053 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 2053 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10195 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10195 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2786 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2786 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10195 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3021 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 13216 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10195 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3021 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2053 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15269 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 99413611 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 99413611 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 19424000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 19424000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1649486500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1649486500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 540711500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 540711500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1649486500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 560135500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2209622000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1649486500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 560135500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 99413611 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2309035611 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188286 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043200 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043200 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041359 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103871 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041359 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027212 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027212 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188207 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188207 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043211 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043211 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188207 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041321 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103835 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188207 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041321 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.120040 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47408.177443 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78403.361345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78403.361345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161478.853891 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161478.853891 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194328.366248 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194328.366248 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161478.853891 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185201.620906 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166905.970940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161478.853891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185201.620906 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 150809.647109 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253407 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126211 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10475 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 949 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.119965 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 48423.580614 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 48423.580614 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82655.319149 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82655.319149 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161793.673369 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161793.673369 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194081.658291 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194081.658291 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161793.673369 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185413.935783 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167192.947942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161793.673369 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185413.935783 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 48423.580614 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151223.761281 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253533 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126274 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10481 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 943 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 942 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64697 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61494 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2394 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54125 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64468 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380622 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6895104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9322880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16217984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2394 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 118642 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54169 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64474 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161993 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218818 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380811 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6900736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9325312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16226048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2391 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 129610 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.088311 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283775 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 129670 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.088263 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283705 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118165 91.17% 91.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11444 8.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118226 91.17% 91.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11443 8.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 129610 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252894500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 129670 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 253020500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81192487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81260982 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109641490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109669990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 14321 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 10482 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 14326 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10488 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 14082 # Transaction distribution -system.membus.trans_dist::ReadExReq 238 # Transaction distribution -system.membus.trans_dist::ReadExResp 238 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 14083 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28641 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28641 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 916480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14090 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14091 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28651 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 916800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 14321 # Request fanout histogram +system.membus.snoop_fanout::samples 14326 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 14321 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14326 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 14321 # Request fanout histogram -system.membus.reqLayer0.occupancy 18093154 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14326 # Request fanout histogram +system.membus.reqLayer0.occupancy 18054137 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 77218560 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77252283 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index f0c12dca0..ed017dd04 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103189 # Nu sim_ticks 103189362000 # Number of ticks simulated final_tick 103189362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73255 # Simulator instruction rate (inst/s) -host_op_rate 122783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57235650 # Simulator tick rate (ticks/s) -host_mem_usage 306480 # Number of bytes of host memory used -host_seconds 1802.89 # Real time elapsed on the host +host_inst_rate 113263 # Simulator instruction rate (inst/s) +host_op_rate 189839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88494148 # Simulator tick rate (ticks/s) +host_mem_usage 308956 # Number of bytes of host memory used +host_seconds 1166.06 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -373,37 +373,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 206138472 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 759085 19.35% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2731626 69.64% 88.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 432034 11.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 759085 19.25% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2706167 68.61% 87.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 429953 10.90% 98.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 45275 1.15% 99.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3569 0.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1211760 0.36% 0.36% # Type of FU issued @@ -414,7 +418,9 @@ system.cpu.iq.FU_type_0::FloatAdd 1809637 0.53% 67.20% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued @@ -436,22 +442,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 84315938 24.93% 92.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26623181 7.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 82580981 24.41% 91.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26493050 7.83% 99.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 1734957 0.51% 99.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 130131 0.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 338268196 # Type of FU issued system.cpu.iq.rate 1.639065 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3922745 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011597 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 879521716 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 3944049 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011660 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 879529534 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 744046350 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 315909602 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8181525 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 8195011 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 15431147 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 3556535 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 336873543 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4105638 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 336881361 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4119124 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 18155877 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 72027242 # Number of loads squashed @@ -530,7 +538,9 @@ system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction @@ -552,8 +562,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 55945136 25.27% 90.41% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20410230 9.22% 99.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 704451 0.32% 99.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 273aa022a..d2533b8b8 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.869358 # Nu sim_ticks 1869357999000 # Number of ticks simulated final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1685575 # Simulator instruction rate (inst/s) -host_op_rate 1685575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48476092750 # Simulator tick rate (ticks/s) -host_mem_usage 336716 # Number of bytes of host memory used -host_seconds 38.56 # Real time elapsed on the host +host_inst_rate 3011659 # Simulator instruction rate (inst/s) +host_op_rate 3011657 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 86613414800 # Simulator tick rate (ticks/s) +host_mem_usage 336084 # Number of bytes of host memory used +host_seconds 21.58 # Real time elapsed on the host sim_insts 64999904 # Number of instructions simulated sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -217,7 +217,9 @@ system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Cl system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction @@ -239,8 +241,10 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7945590 16.06% 89.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::MemRead 7859946 15.88% 88.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 4676411 9.45% 98.30% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 85644 0.17% 98.47% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 81881 0.17% 98.63% # Class of executed instruction system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 49485886 # Class of executed instruction @@ -514,7 +518,9 @@ system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Cl system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 64.73% # Class of executed instruction system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction +system.cpu1.op_class::FloatMisc 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction @@ -536,8 +542,10 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction -system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction +system.cpu1.op_class::MemRead 2842559 18.31% 83.05% # Class of executed instruction +system.cpu1.op_class::MemWrite 2023248 13.03% 96.08% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 94457 0.61% 96.69% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 90649 0.58% 97.27% # Class of executed instruction system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 15525875 # Class of executed instruction diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index ac4b28ba6..5eba6ea99 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332003500 # Number of ticks simulated final_tick 1829332003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1751464 # Simulator instruction rate (inst/s) -host_op_rate 1751464 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53365900898 # Simulator tick rate (ticks/s) -host_mem_usage 334408 # Number of bytes of host memory used -host_seconds 34.28 # Real time elapsed on the host +host_inst_rate 2980615 # Simulator instruction rate (inst/s) +host_op_rate 2980613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90817249233 # Simulator tick rate (ticks/s) +host_mem_usage 334036 # Number of bytes of host memory used +host_seconds 20.14 # Real time elapsed on the host sim_insts 60038469 # Number of instructions simulated sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -202,7 +202,9 @@ system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Cl system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 71.18% # Class of executed instruction system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction @@ -224,8 +226,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction -system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction +system.cpu.op_class::MemRead 9830448 16.37% 87.56% # Class of executed instruction +system.cpu.op_class::MemWrite 6236007 10.38% 97.95% # Class of executed instruction +system.cpu.op_class::FloatMemRead 144629 0.24% 98.19% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 138108 0.23% 98.42% # Class of executed instruction system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 60050307 # Class of executed instruction diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index de3485335..1bc6ab18a 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.966742 # Nu sim_ticks 1966741627000 # Number of ticks simulated final_tick 1966741627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 801704 # Simulator instruction rate (inst/s) -host_op_rate 801704 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25865455419 # Simulator tick rate (ticks/s) -host_mem_usage 334360 # Number of bytes of host memory used -host_seconds 76.04 # Real time elapsed on the host +host_inst_rate 1743154 # Simulator instruction rate (inst/s) +host_op_rate 1743154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56239519255 # Simulator tick rate (ticks/s) +host_mem_usage 337608 # Number of bytes of host memory used +host_seconds 34.97 # Real time elapsed on the host sim_insts 60959478 # Number of instructions simulated sim_ops 60959478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -490,7 +490,9 @@ system.cpu0.op_class::FloatAdd 26676 0.06% 71.66% # Cl system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::FloatDiv 1883 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::FloatSqrt 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::SimdAdd 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::SimdAddAcc 0 0.00% 71.66% # Class of executed instruction @@ -512,8 +514,10 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.66% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::MemRead 7680863 16.10% 87.77% # Class of executed instruction -system.cpu0.op_class::MemWrite 5099104 10.69% 98.46% # Class of executed instruction +system.cpu0.op_class::MemRead 7588274 15.91% 87.57% # Class of executed instruction +system.cpu0.op_class::MemWrite 5010180 10.50% 98.08% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 92589 0.19% 98.27% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 88924 0.19% 98.46% # Class of executed instruction system.cpu0.op_class::IprAccess 735804 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 47699751 # Class of executed instruction @@ -905,7 +909,9 @@ system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Cl system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction system.cpu1.op_class::FloatDiv 1759 0.01% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatMisc 0 0.00% 64.94% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 64.94% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 64.94% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 64.94% # Class of executed instruction @@ -927,8 +933,10 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.94% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 64.94% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.94% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::MemRead 2529811 19.06% 84.00% # Class of executed instruction -system.cpu1.op_class::MemWrite 1759476 13.26% 97.25% # Class of executed instruction +system.cpu1.op_class::MemRead 2447876 18.44% 83.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 1681278 12.67% 96.05% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction system.cpu1.op_class::IprAccess 364369 2.75% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 13271624 # Class of executed instruction diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index e8b92466f..d65bd28a8 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.926421 # Nu sim_ticks 1926421414000 # Number of ticks simulated final_tick 1926421414000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 779030 # Simulator instruction rate (inst/s) -host_op_rate 779030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26705916367 # Simulator tick rate (ticks/s) -host_mem_usage 331544 # Number of bytes of host memory used -host_seconds 72.13 # Real time elapsed on the host +host_inst_rate 1670874 # Simulator instruction rate (inst/s) +host_op_rate 1670873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57279188873 # Simulator tick rate (ticks/s) +host_mem_usage 333776 # Number of bytes of host memory used +host_seconds 33.63 # Real time elapsed on the host sim_insts 56195014 # Number of instructions simulated sim_ops 56195014 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -474,7 +474,9 @@ system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Cl system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction @@ -496,8 +498,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9330523 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6379338 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::MemRead 9185894 16.34% 86.70% # Class of executed instruction +system.cpu.op_class::MemWrite 6241230 11.10% 97.80% # Class of executed instruction +system.cpu.op_class::FloatMemRead 144629 0.26% 98.06% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 138108 0.25% 98.30% # Class of executed instruction system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 56206855 # Class of executed instruction diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 9c9dc0805..812c8a1b2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802883 # Nu sim_ticks 2802883274000 # Number of ticks simulated final_tick 2802883274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 787866 # Simulator instruction rate (inst/s) -host_op_rate 960003 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15041277607 # Simulator tick rate (ticks/s) -host_mem_usage 600036 # Number of bytes of host memory used -host_seconds 186.35 # Real time elapsed on the host +host_inst_rate 1537557 # Simulator instruction rate (inst/s) +host_op_rate 1873488 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29353729253 # Simulator tick rate (ticks/s) +host_mem_usage 598048 # Number of bytes of host memory used +host_seconds 95.49 # Real time elapsed on the host sim_insts 146815798 # Number of instructions simulated sim_ops 178892721 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -283,7 +283,9 @@ system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Cl system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction @@ -305,8 +307,10 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20595754 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17275036 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20593498 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17267541 14.77% 99.99% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 116874608 # Class of executed instruction @@ -815,7 +819,9 @@ system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Cl system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::FloatMisc 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction @@ -837,8 +843,10 @@ system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12287954 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7735598 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12287438 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7734322 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 516 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 1276 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 65451587 # Class of executed instruction diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index cc1e1b968..e1c368a8b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854715000 # Number of ticks simulated final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 812904 # Simulator instruction rate (inst/s) -host_op_rate 989581 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15850589349 # Simulator tick rate (ticks/s) -host_mem_usage 583016 # Number of bytes of host memory used -host_seconds 175.63 # Real time elapsed on the host +host_inst_rate 1570014 # Simulator instruction rate (inst/s) +host_op_rate 1911240 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30613244357 # Simulator tick rate (ticks/s) +host_mem_usage 581428 # Number of bytes of host memory used +host_seconds 90.94 # Real time elapsed on the host sim_insts 142771202 # Number of instructions simulated sim_ops 173801044 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -265,7 +265,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Cl system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction @@ -287,8 +289,10 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855508 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083002 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31852800 17.97% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24074230 13.58% 99.99% # Class of executed instruction +system.cpu.op_class::FloatMemRead 2708 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 8772 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 177217860 # Class of executed instruction diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index bd324667f..4b2087469 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.870823 # Nu sim_ticks 2870822663000 # Number of ticks simulated final_tick 2870822663000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 442891 # Simulator instruction rate (inst/s) -host_op_rate 535691 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9664154143 # Simulator tick rate (ticks/s) -host_mem_usage 616988 # Number of bytes of host memory used -host_seconds 297.06 # Real time elapsed on the host +host_inst_rate 1048966 # Simulator instruction rate (inst/s) +host_op_rate 1268757 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22889064818 # Simulator tick rate (ticks/s) +host_mem_usage 618276 # Number of bytes of host memory used +host_seconds 125.42 # Real time elapsed on the host sim_insts 131564747 # Number of instructions simulated sim_ops 159131669 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -598,7 +598,9 @@ system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Cl system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction @@ -620,8 +622,10 @@ system.cpu0.op_class::SimdFloatMisc 8149 0.01% 68.53% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::MemRead 25408167 17.75% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 19633320 13.72% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 25405911 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19625890 13.71% 99.99% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 7430 0.01% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 143146475 # Class of executed instruction @@ -1551,7 +1555,9 @@ system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Cl system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatMisc 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction @@ -1573,8 +1579,10 @@ system.cpu1.op_class::SimdFloatMisc 3315 0.02% 62.20% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::MemRead 4054552 20.17% 82.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 3542729 17.62% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 4054036 20.17% 82.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 3541453 17.62% 99.99% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 516 0.00% 99.99% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 20100990 # Class of executed instruction diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index aaea4a10c..954602a38 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.905298 # Nu sim_ticks 2905297782500 # Number of ticks simulated final_tick 2905297782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 483331 # Simulator instruction rate (inst/s) -host_op_rate 582745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12486239543 # Simulator tick rate (ticks/s) -host_mem_usage 580500 # Number of bytes of host memory used -host_seconds 232.68 # Real time elapsed on the host +host_inst_rate 1078702 # Simulator instruction rate (inst/s) +host_op_rate 1300576 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27866902585 # Simulator tick rate (ticks/s) +host_mem_usage 582552 # Number of bytes of host memory used +host_seconds 104.26 # Real time elapsed on the host sim_insts 112461365 # Number of instructions simulated sim_ops 135593151 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -567,7 +567,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Cl system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction @@ -589,8 +591,10 @@ system.cpu.op_class::SimdFloatMisc 8431 0.01% 67.27% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu.op_class::MemRead 24842315 17.91% 85.18% # Class of executed instruction -system.cpu.op_class::MemWrite 20563755 14.82% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24839607 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20555241 14.82% 99.99% # Class of executed instruction +system.cpu.op_class::FloatMemRead 2708 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 8514 0.01% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 138713890 # Class of executed instruction diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index e660dd01c..ceada1391 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu sim_ticks 200409271000 # Number of ticks simulated final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 11448115 # Simulator instruction rate (inst/s) -host_op_rate 11448111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4380279881 # Simulator tick rate (ticks/s) -host_mem_usage 499724 # Number of bytes of host memory used -host_seconds 45.75 # Real time elapsed on the host +host_inst_rate 19542475 # Simulator instruction rate (inst/s) +host_op_rate 19542467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7477344580 # Simulator tick rate (ticks/s) +host_mem_usage 503180 # Number of bytes of host memory used +host_seconds 26.80 # Real time elapsed on the host sim_insts 523780905 # Number of instructions simulated sim_ops 523780905 # Number of ops (including micro ops) simulated drivesys.voltage_domain.voltage 1 # Voltage in Volts @@ -178,7 +178,9 @@ drivesys.cpu.op_class::FloatAdd 141 0.00% 63.95% # Cl drivesys.cpu.op_class::FloatCmp 0 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::FloatCvt 0 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::FloatMult 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::FloatMultAcc 0 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::FloatDiv 23 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::FloatMisc 0 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::FloatSqrt 0 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::SimdAdd 0 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.95% # Class of executed instruction @@ -200,8 +202,10 @@ drivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.95% # Cl drivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::MemRead 4026028 21.13% 85.08% # Class of executed instruction -drivesys.cpu.op_class::MemWrite 2085021 10.94% 96.02% # Class of executed instruction +drivesys.cpu.op_class::MemRead 4025389 21.13% 85.08% # Class of executed instruction +drivesys.cpu.op_class::MemWrite 2084412 10.94% 96.02% # Class of executed instruction +drivesys.cpu.op_class::FloatMemRead 639 0.00% 96.02% # Class of executed instruction +drivesys.cpu.op_class::FloatMemWrite 609 0.00% 96.02% # Class of executed instruction drivesys.cpu.op_class::IprAccess 757336 3.98% 100.00% # Class of executed instruction drivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction drivesys.cpu.op_class::total 19051393 # Class of executed instruction @@ -532,7 +536,9 @@ testsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Cl testsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::FloatMultAcc 0 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::FloatDiv 922 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::FloatMisc 0 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction @@ -554,8 +560,10 @@ testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Cl testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::MemRead 4230485 20.88% 84.48% # Class of executed instruction -testsys.cpu.op_class::MemWrite 2319388 11.45% 95.93% # Class of executed instruction +testsys.cpu.op_class::MemRead 4224290 20.85% 84.45% # Class of executed instruction +testsys.cpu.op_class::MemWrite 2313781 11.42% 95.87% # Class of executed instruction +testsys.cpu.op_class::FloatMemRead 6195 0.03% 95.90% # Class of executed instruction +testsys.cpu.op_class::FloatMemWrite 5607 0.03% 95.93% # Class of executed instruction testsys.cpu.op_class::IprAccess 824126 4.07% 100.00% # Class of executed instruction testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction testsys.cpu.op_class::total 20261020 # Class of executed instruction @@ -721,11 +729,11 @@ sim_seconds 0.000407 # Nu sim_ticks 407341500 # Number of ticks simulated final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 5887840528 # Simulator instruction rate (inst/s) -host_op_rate 5886957075 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4576964640 # Simulator tick rate (ticks/s) -host_mem_usage 499724 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 9980587708 # Simulator instruction rate (inst/s) +host_op_rate 9978728931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7757989630 # Simulator tick rate (ticks/s) +host_mem_usage 503180 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 523853183 # Number of instructions simulated sim_ops 523853183 # Number of ops (including micro ops) simulated drivesys.voltage_domain.voltage 1 # Voltage in Volts @@ -874,7 +882,9 @@ drivesys.cpu.op_class::FloatAdd 0 0.00% 63.60% # Cl drivesys.cpu.op_class::FloatCmp 0 0.00% 63.60% # Class of executed instruction drivesys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction drivesys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::FloatMultAcc 0 0.00% 63.60% # Class of executed instruction drivesys.cpu.op_class::FloatDiv 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::FloatMisc 0 0.00% 63.60% # Class of executed instruction drivesys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction drivesys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction drivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction @@ -898,6 +908,8 @@ drivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Cl drivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction drivesys.cpu.op_class::MemRead 7678 21.24% 84.84% # Class of executed instruction drivesys.cpu.op_class::MemWrite 3936 10.89% 95.73% # Class of executed instruction +drivesys.cpu.op_class::FloatMemRead 0 0.00% 95.73% # Class of executed instruction +drivesys.cpu.op_class::FloatMemWrite 0 0.00% 95.73% # Class of executed instruction drivesys.cpu.op_class::IprAccess 1545 4.27% 100.00% # Class of executed instruction drivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction drivesys.cpu.op_class::total 36152 # Class of executed instruction @@ -1179,7 +1191,9 @@ testsys.cpu.op_class::FloatAdd 0 0.00% 63.58% # Cl testsys.cpu.op_class::FloatCmp 0 0.00% 63.58% # Class of executed instruction testsys.cpu.op_class::FloatCvt 0 0.00% 63.58% # Class of executed instruction testsys.cpu.op_class::FloatMult 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::FloatMultAcc 0 0.00% 63.58% # Class of executed instruction testsys.cpu.op_class::FloatDiv 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::FloatMisc 0 0.00% 63.58% # Class of executed instruction testsys.cpu.op_class::FloatSqrt 0 0.00% 63.58% # Class of executed instruction testsys.cpu.op_class::SimdAdd 0 0.00% 63.58% # Class of executed instruction testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.58% # Class of executed instruction @@ -1203,6 +1217,8 @@ testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.58% # Cl testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.58% # Class of executed instruction testsys.cpu.op_class::MemRead 7674 21.24% 84.82% # Class of executed instruction testsys.cpu.op_class::MemWrite 3938 10.90% 95.72% # Class of executed instruction +testsys.cpu.op_class::FloatMemRead 0 0.00% 95.72% # Class of executed instruction +testsys.cpu.op_class::FloatMemWrite 0 0.00% 95.72% # Class of executed instruction testsys.cpu.op_class::IprAccess 1545 4.28% 100.00% # Class of executed instruction testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction testsys.cpu.op_class::total 36126 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 6227dc2b6..e5561895a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 41083000 # Number of ticks simulated final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172605 # Simulator instruction rate (inst/s) -host_op_rate 172547 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1105034404 # Simulator tick rate (ticks/s) -host_mem_usage 251288 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 217103 # Simulator instruction rate (inst/s) +host_op_rate 217013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1389706699 # Simulator tick rate (ticks/s) +host_mem_usage 253264 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -327,7 +327,9 @@ system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.88% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 67.88% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 67.88% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 67.88% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 67.88% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction @@ -349,8 +351,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::MemRead 1192 18.59% 86.46% # Class of committed instruction -system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 1191 18.57% 86.45% # Class of committed instruction +system.cpu.op_class_0::MemWrite 861 13.43% 99.88% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 6413 # Class of committed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 518b46438..6cc52ba2c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 23776000 # Number of ticks simulated final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93889 # Simulator instruction rate (inst/s) -host_op_rate 93856 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 349385939 # Simulator tick rate (ticks/s) -host_mem_usage 252568 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 139405 # Simulator instruction rate (inst/s) +host_op_rate 139373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 518883929 # Simulator tick rate (ticks/s) +host_mem_usage 254032 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -407,7 +407,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 14.89% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available @@ -430,7 +432,9 @@ system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # at system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 37 26.24% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36 25.53% 99.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1 0.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued @@ -441,7 +445,9 @@ system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued @@ -463,8 +469,10 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2475 22.97% 89.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1111 10.31% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2474 22.96% 89.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 10.24% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 10776 # Type of FU issued @@ -557,7 +565,9 @@ system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction @@ -579,8 +589,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6402 # Class of committed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index f237b4325..a3ed3546f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3214500 # Number of ticks simulated final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 280584 # Simulator instruction rate (inst/s) -host_op_rate 280421 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140703848 # Simulator tick rate (ticks/s) -host_mem_usage 242116 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 1072411 # Simulator instruction rate (inst/s) +host_op_rate 1070683 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 536687952 # Simulator tick rate (ticks/s) +host_mem_usage 241476 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -103,7 +103,9 @@ system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Cl system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction @@ -125,8 +127,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction +system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction +system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 66e7aabe9..b35897ba6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000129 # Nu sim_ticks 129075 # Number of ticks simulated final_tick 129075 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 59192 # Simulator instruction rate (inst/s) -host_op_rate 59185 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1192972 # Simulator tick rate (ticks/s) -host_mem_usage 410988 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 77143 # Simulator instruction rate (inst/s) +host_op_rate 77134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1554751 # Simulator tick rate (ticks/s) +host_mem_usage 412952 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -344,7 +344,9 @@ system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Cl system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction @@ -366,8 +368,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction +system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction +system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 0d7120e11..82e5081b6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000116 # Nu sim_ticks 115948 # Number of ticks simulated final_tick 115948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 62775 # Simulator instruction rate (inst/s) -host_op_rate 62768 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1136521 # Simulator tick rate (ticks/s) -host_mem_usage 416956 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 73551 # Simulator instruction rate (inst/s) +host_op_rate 73543 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1331606 # Simulator tick rate (ticks/s) +host_mem_usage 419184 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -344,7 +344,9 @@ system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Cl system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction @@ -366,8 +368,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction +system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction +system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index b89069f53..5c18a3fa2 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000114 # Nu sim_ticks 113952 # Number of ticks simulated final_tick 113952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 64476 # Simulator instruction rate (inst/s) -host_op_rate 64460 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1146955 # Simulator tick rate (ticks/s) -host_mem_usage 412808 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 100852 # Simulator instruction rate (inst/s) +host_op_rate 100836 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1794284 # Simulator tick rate (ticks/s) +host_mem_usage 414264 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -341,7 +341,9 @@ system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Cl system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction @@ -363,8 +365,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction +system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction +system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 56d6a64b0..cdf9185d7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000093 # Nu sim_ticks 93323 # Number of ticks simulated final_tick 93323 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 48908 # Simulator instruction rate (inst/s) -host_op_rate 48899 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 712591 # Simulator tick rate (ticks/s) -host_mem_usage 412484 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 111182 # Simulator instruction rate (inst/s) +host_op_rate 111161 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1619882 # Simulator tick rate (ticks/s) +host_mem_usage 412912 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -343,7 +343,9 @@ system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Cl system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction @@ -365,8 +367,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction +system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction +system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 06dea8ad2..70a6e8611 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000112 # Nu sim_ticks 112490 # Number of ticks simulated final_tick 112490 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 94486 # Simulator instruction rate (inst/s) -host_op_rate 94411 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1658372 # Simulator tick rate (ticks/s) -host_mem_usage 414356 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 109209 # Simulator instruction rate (inst/s) +host_op_rate 109187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1917933 # Simulator tick rate (ticks/s) +host_mem_usage 416076 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -345,7 +345,9 @@ system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Cl system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction @@ -367,8 +369,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction +system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction +system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index ffd6a3082..b5443e567 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu sim_ticks 36128500 # Number of ticks simulated final_tick 36128500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 310790 # Simulator instruction rate (inst/s) -host_op_rate 310669 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1752338800 # Simulator tick rate (ticks/s) -host_mem_usage 252108 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 739000 # Simulator instruction rate (inst/s) +host_op_rate 738191 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4160971439 # Simulator tick rate (ticks/s) +host_mem_usage 251728 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -97,7 +97,9 @@ system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Cl system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction @@ -119,8 +121,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction +system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction +system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index a6e87b576..23238c1fc 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000022 # Nu sim_ticks 22083000 # Number of ticks simulated final_tick 22083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143746 # Simulator instruction rate (inst/s) -host_op_rate 143654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1226490189 # Simulator tick rate (ticks/s) -host_mem_usage 251004 # Number of bytes of host memory used +host_inst_rate 166693 # Simulator instruction rate (inst/s) +host_op_rate 166561 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1421880228 # Simulator tick rate (ticks/s) +host_mem_usage 251952 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated @@ -327,7 +327,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 72.26% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 72.26% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 72.26% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 72.26% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 72.26% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 72.26% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 72.26% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 72.26% # Class of committed instruction @@ -350,7 +352,9 @@ system.cpu.op_class_0::SimdFloatMult 0 0.00% 72.26% # Cl system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 72.26% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 72.26% # Class of committed instruction system.cpu.op_class_0::MemRead 419 16.21% 88.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemWrite 292 11.30% 99.77% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 99.77% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 6 0.23% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 2585 # Class of committed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index cecea8f6e..ed65513bb 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000013 # Nu sim_ticks 13358500 # Number of ticks simulated final_tick 13358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53089 # Simulator instruction rate (inst/s) -host_op_rate 53060 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 296795260 # Simulator tick rate (ticks/s) -host_mem_usage 251260 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 102485 # Simulator instruction rate (inst/s) +host_op_rate 102439 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 573050673 # Simulator tick rate (ticks/s) +host_mem_usage 252720 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -399,37 +399,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 7018 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 10.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 30 50.00% 60.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 24 40.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 30 49.18% 59.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 24 39.34% 98.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1 1.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -440,7 +444,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.01% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.01% # Type of FU issued @@ -463,20 +469,22 @@ system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.01% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 745 20.01% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 372 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 366 9.83% 99.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 6 0.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 3724 # Type of FU issued system.cpu.iq.rate 0.139382 # Inst issue rate -system.cpu.iq.fu_busy_cnt 60 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016112 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14532 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 61 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016380 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14533 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 6293 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3394 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3777 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3778 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -556,7 +564,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 72.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 72.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction @@ -579,7 +589,9 @@ system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 288 11.18% 99.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 6 0.23% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 74510a8b2..b12c3ecf5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120967 # Simulator instruction rate (inst/s) -host_op_rate 120887 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60829891 # Simulator tick rate (ticks/s) -host_mem_usage 241828 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 601225 # Simulator instruction rate (inst/s) +host_op_rate 599847 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 301371607 # Simulator tick rate (ticks/s) +host_mem_usage 241196 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -103,7 +103,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Cl system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction @@ -126,7 +128,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index d4dee56c3..28d393468 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000049 # Nu sim_ticks 48659 # Number of ticks simulated final_tick 48659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 43978 # Simulator instruction rate (inst/s) -host_op_rate 43962 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 829814 # Simulator tick rate (ticks/s) -host_mem_usage 410700 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 67712 # Simulator instruction rate (inst/s) +host_op_rate 67695 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1277923 # Simulator tick rate (ticks/s) +host_mem_usage 411644 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -338,7 +338,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Cl system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction @@ -361,7 +363,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 9bed4b569..9060cd787 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000044 # Nu sim_ticks 44230 # Number of ticks simulated final_tick 44230 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 44627 # Simulator instruction rate (inst/s) -host_op_rate 44610 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 765394 # Simulator tick rate (ticks/s) -host_mem_usage 414624 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 73967 # Simulator instruction rate (inst/s) +host_op_rate 73941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1268663 # Simulator tick rate (ticks/s) +host_mem_usage 415828 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -338,7 +338,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Cl system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction @@ -361,7 +363,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 0254766b0..7864412c9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000043 # Nu sim_ticks 42756 # Number of ticks simulated final_tick 42756 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 50628 # Simulator instruction rate (inst/s) -host_op_rate 50604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 839232 # Simulator tick rate (ticks/s) -host_mem_usage 411504 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 103649 # Simulator instruction rate (inst/s) +host_op_rate 103608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1718399 # Simulator tick rate (ticks/s) +host_mem_usage 412956 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -338,7 +338,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Cl system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction @@ -361,7 +363,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 4d9201d35..af200054c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000035 # Nu sim_ticks 35056 # Number of ticks simulated final_tick 35056 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 50934 # Simulator instruction rate (inst/s) -host_op_rate 50910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 692254 # Simulator tick rate (ticks/s) -host_mem_usage 411180 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 89727 # Simulator instruction rate (inst/s) +host_op_rate 89697 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1219820 # Simulator tick rate (ticks/s) +host_mem_usage 412632 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -338,7 +338,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Cl system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction @@ -361,7 +363,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 535942f10..38f9f0d34 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000044 # Nu sim_ticks 43520 # Number of ticks simulated final_tick 43520 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 93431 # Simulator instruction rate (inst/s) -host_op_rate 93392 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1576605 # Simulator tick rate (ticks/s) -host_mem_usage 411000 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 112756 # Simulator instruction rate (inst/s) +host_op_rate 112704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1902499 # Simulator tick rate (ticks/s) +host_mem_usage 412460 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -343,7 +343,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Cl system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction @@ -366,7 +368,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index f7ca8186a..55cc07d2c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu sim_ticks 18484500 # Number of ticks simulated final_tick 18484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121029 # Simulator instruction rate (inst/s) -host_op_rate 120936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 866943608 # Simulator tick rate (ticks/s) -host_mem_usage 250796 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 287292 # Simulator instruction rate (inst/s) +host_op_rate 286342 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2049000197 # Simulator tick rate (ticks/s) +host_mem_usage 250420 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -97,7 +97,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Cl system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction @@ -120,7 +122,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 48cd9ae26..4822d2cee 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000033 # Nu sim_ticks 32719500 # Number of ticks simulated final_tick 32719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127457 # Simulator instruction rate (inst/s) -host_op_rate 149152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 904929733 # Simulator tick rate (ticks/s) -host_mem_usage 267332 # Number of bytes of host memory used +host_inst_rate 128948 # Simulator instruction rate (inst/s) +host_op_rate 150916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 915725978 # Simulator tick rate (ticks/s) +host_mem_usage 269308 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated @@ -415,7 +415,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction @@ -438,7 +440,9 @@ system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Cl system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction -system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemWrite 922 17.10% 99.70% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 5391 # Class of committed instruction diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index bf47005a8..5d8a28b22 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu sim_ticks 18422500 # Number of ticks simulated final_tick 18422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65137 # Simulator instruction rate (inst/s) -host_op_rate 76274 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 261240377 # Simulator tick rate (ticks/s) -host_mem_usage 268360 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 76941 # Simulator instruction rate (inst/s) +host_op_rate 90095 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 308579581 # Simulator tick rate (ticks/s) +host_mem_usage 270584 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -613,37 +613,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 13535 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 6.12% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 66 44.90% 51.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 72 48.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 6.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 66 44.00% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62 41.33% 91.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 91.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 13 8.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -654,7 +658,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued @@ -677,21 +683,23 @@ system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 1876 23.17% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1187 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1154 14.25% 99.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 33 0.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8096 # Type of FU issued system.cpu.iq.rate 0.219725 # Inst issue rate -system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018157 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_cnt 150 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018528 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 29820 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14935 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 7404 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 8200 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses +system.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1170 # Number of loads squashed @@ -770,7 +778,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction @@ -793,7 +803,9 @@ system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 867d50715..613bc274a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20299000 # Number of ticks simulated final_tick 20299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44590 # Simulator instruction rate (inst/s) -host_op_rate 52212 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197038809 # Simulator tick rate (ticks/s) -host_mem_usage 265156 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 98455 # Simulator instruction rate (inst/s) +host_op_rate 115276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 434998330 # Simulator tick rate (ticks/s) +host_mem_usage 266116 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -489,37 +489,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 15916 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 416 28.85% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 475 32.94% 61.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 551 38.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 416 28.75% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 475 32.83% 61.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 539 37.25% 98.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 17 1.17% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -530,7 +534,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.78% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.78% # Type of FU issued @@ -553,21 +559,23 @@ system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Ty system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 1605 22.21% 85.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1082 14.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1066 14.75% 99.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 7228 # Type of FU issued system.cpu.iq.rate 0.178034 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199502 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_cnt 1447 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.200194 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 31952 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 11715 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 6617 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 8642 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses +system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed @@ -646,7 +654,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction @@ -669,7 +679,9 @@ system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 83c02dd61..d8c753698 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207093 # Simulator instruction rate (inst/s) -host_op_rate 242387 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 121392563 # Simulator tick rate (ticks/s) -host_mem_usage 259512 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 707147 # Simulator instruction rate (inst/s) +host_op_rate 826854 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 413753949 # Simulator tick rate (ticks/s) +host_mem_usage 259056 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -317,7 +317,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Cl system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction @@ -340,7 +342,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index b8117da74..0f68cb20c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 213878 # Simulator instruction rate (inst/s) -host_op_rate 250318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 125362190 # Simulator tick rate (ticks/s) -host_mem_usage 258232 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 709054 # Simulator instruction rate (inst/s) +host_op_rate 829008 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 414799236 # Simulator tick rate (ticks/s) +host_mem_usage 257780 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Cl system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction @@ -216,7 +218,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 6ed816eb8..9543604da 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000029 # Nu sim_ticks 28648500 # Number of ticks simulated final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192730 # Simulator instruction rate (inst/s) -host_op_rate 224907 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1208517164 # Simulator tick rate (ticks/s) -host_mem_usage 267456 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 484095 # Simulator instruction rate (inst/s) +host_op_rate 564461 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3030833923 # Simulator tick rate (ticks/s) +host_mem_usage 267516 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -187,7 +187,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Cl system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction @@ -210,7 +212,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index fb05a48a7..10245d965 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24405000 # Number of ticks simulated final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101939 # Simulator instruction rate (inst/s) -host_op_rate 101907 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 497362491 # Simulator tick rate (ticks/s) -host_mem_usage 250452 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 123007 # Simulator instruction rate (inst/s) +host_op_rate 122970 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 600170719 # Simulator tick rate (ticks/s) +host_mem_usage 251144 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -392,7 +392,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available @@ -416,6 +418,8 @@ system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # at system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 117 65.00% 68.33% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 57 31.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -426,7 +430,9 @@ system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.90% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.90% # Type of FU issued @@ -450,6 +456,8 @@ system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.90% # T system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.90% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 2274 28.01% 86.91% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8119 # Type of FU issued @@ -542,7 +550,9 @@ system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.90% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.90% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.90% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.90% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.90% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.90% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.90% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.90% # Class of committed instruction @@ -566,6 +576,8 @@ system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5640 # Class of committed instruction diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index fd6e40c23..d8c0265b8 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2820500 # Number of ticks simulated final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 280567 # Simulator instruction rate (inst/s) -host_op_rate 280375 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140096420 # Simulator tick rate (ticks/s) -host_mem_usage 239748 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 973752 # Simulator instruction rate (inst/s) +host_op_rate 969638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 482917179 # Simulator tick rate (ticks/s) +host_mem_usage 239104 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -89,7 +89,9 @@ system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Cl system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction @@ -113,6 +115,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index d2ad37c0f..b83fdc852 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000106 # Nu sim_ticks 106125 # Number of ticks simulated final_tick 106125 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 64036 # Simulator instruction rate (inst/s) -host_op_rate 64023 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1204237 # Simulator tick rate (ticks/s) -host_mem_usage 413260 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 110492 # Simulator instruction rate (inst/s) +host_op_rate 110472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2077956 # Simulator tick rate (ticks/s) +host_mem_usage 415232 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -332,7 +332,9 @@ system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Cl system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction @@ -356,6 +358,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 657853e9f..06655105e 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000034 # Nu sim_ticks 34362500 # Number of ticks simulated final_tick 34362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 251821 # Simulator instruction rate (inst/s) -host_op_rate 251667 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1532173253 # Simulator tick rate (ticks/s) -host_mem_usage 250252 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 587904 # Simulator instruction rate (inst/s) +host_op_rate 587165 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3572983060 # Simulator tick rate (ticks/s) +host_mem_usage 249352 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -83,7 +83,9 @@ system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Cl system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction @@ -107,6 +109,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index cfc1cce24..fbc31e89b 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21268000 # Number of ticks simulated final_tick 21268000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112778 # Simulator instruction rate (inst/s) -host_op_rate 112739 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 413846380 # Simulator tick rate (ticks/s) -host_mem_usage 248372 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 133148 # Simulator instruction rate (inst/s) +host_op_rate 133114 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 488684971 # Simulator tick rate (ticks/s) +host_mem_usage 249832 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -386,37 +386,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 12418 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12 6.32% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 88 46.32% 52.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 90 47.37% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 12 6.06% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 88 44.44% 50.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 87 43.94% 94.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 11 5.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -427,7 +431,9 @@ system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.81% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.81% # Type of FU issued @@ -449,22 +455,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.81% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1813 20.58% 83.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1463 16.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1439 16.34% 99.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 2 0.02% 99.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 24 0.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8808 # Type of FU issued system.cpu.iq.rate 0.207067 # Inst issue rate -system.cpu.iq.fu_busy_cnt 190 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021571 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30215 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 198 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022480 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30218 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14647 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8115 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8964 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 8967 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 39 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 976 # Number of loads squashed @@ -543,7 +551,9 @@ system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction @@ -565,8 +575,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 960 16.57% 81.92% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 1027 17.73% 99.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 19 0.33% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 55872626c..78aa3bef2 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 247008 # Simulator instruction rate (inst/s) -host_op_rate 246868 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 123347407 # Simulator tick rate (ticks/s) -host_mem_usage 238692 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 1025115 # Simulator instruction rate (inst/s) +host_op_rate 1023244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 510651564 # Simulator tick rate (ticks/s) +host_mem_usage 238048 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -89,7 +89,9 @@ system.cpu.op_class::FloatAdd 2 0.03% 65.35% # Cl system.cpu.op_class::FloatCmp 0 0.00% 65.35% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.35% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 65.35% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 65.35% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 65.35% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 65.35% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 65.35% # Class of executed instruction @@ -111,8 +113,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 65.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 65.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::MemRead 961 16.59% 81.94% # Class of executed instruction -system.cpu.op_class::MemWrite 1046 18.06% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 960 16.57% 81.93% # Class of executed instruction +system.cpu.op_class::MemWrite 1027 17.73% 99.65% # Class of executed instruction +system.cpu.op_class::FloatMemRead 1 0.02% 99.67% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 19 0.33% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5793 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 7638ef846..f9e1e99fd 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 238347 # Simulator instruction rate (inst/s) -host_op_rate 238214 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120430561 # Simulator tick rate (ticks/s) -host_mem_usage 240180 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 818529 # Simulator instruction rate (inst/s) +host_op_rate 815458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 411063520 # Simulator tick rate (ticks/s) +host_mem_usage 239556 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -71,7 +71,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Cl system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction @@ -95,6 +97,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index a1c151f90..c1f6ae8aa 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu sim_ticks 86746 # Number of ticks simulated final_tick 86746 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 61570 # Simulator instruction rate (inst/s) -host_op_rate 61552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1002076 # Simulator tick rate (ticks/s) -host_mem_usage 413704 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 115505 # Simulator instruction rate (inst/s) +host_op_rate 115448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1879120 # Simulator tick rate (ticks/s) +host_mem_usage 414144 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -312,7 +312,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Cl system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction @@ -336,6 +338,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 9112c70f3..0b31a1b60 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu sim_ticks 30915500 # Number of ticks simulated final_tick 30915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184246 # Simulator instruction rate (inst/s) -host_op_rate 184150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1068222426 # Simulator tick rate (ticks/s) -host_mem_usage 250688 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 536275 # Simulator instruction rate (inst/s) +host_op_rate 534981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3098223884 # Simulator tick rate (ticks/s) +host_mem_usage 250312 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -65,7 +65,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Cl system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction @@ -89,6 +91,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index d0952668c..7984b1b75 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 22466500 # Number of ticks simulated final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32079 # Simulator instruction rate (inst/s) -host_op_rate 58113 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 133941475 # Simulator tick rate (ticks/s) -host_mem_usage 269032 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 70304 # Simulator instruction rate (inst/s) +host_op_rate 127350 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 293494415 # Simulator tick rate (ticks/s) +host_mem_usage 271256 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -377,7 +377,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.93% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.93% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.93% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.93% # attempts to use FU when none available @@ -401,6 +403,8 @@ system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.93% # at system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.93% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 41 14.70% 94.62% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 15 5.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued @@ -411,7 +415,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.02% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.02% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.02% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.02% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 80.02% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.02% # Type of FU issued @@ -434,7 +440,9 @@ system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.02% # Ty system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.02% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 2258 12.47% 92.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1361 7.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1357 7.49% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 4 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 18112 # Type of FU issued @@ -527,7 +535,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction @@ -551,6 +561,8 @@ system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index f34005614..0cb308579 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127315 # Simulator instruction rate (inst/s) -host_op_rate 230565 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132772406 # Simulator tick rate (ticks/s) -host_mem_usage 258816 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 340881 # Simulator instruction rate (inst/s) +host_op_rate 616836 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 354943212 # Simulator tick rate (ticks/s) +host_mem_usage 258192 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -77,7 +77,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Cl system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction @@ -101,6 +103,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 61c4aeeab..c59c92e77 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000092 # Nu sim_ticks 91859 # Number of ticks simulated final_tick 91859 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 42401 # Simulator instruction rate (inst/s) -host_op_rate 76797 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 723555 # Simulator tick rate (ticks/s) -host_mem_usage 431840 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 91408 # Simulator instruction rate (inst/s) +host_op_rate 165563 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1559913 # Simulator tick rate (ticks/s) +host_mem_usage 432272 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -319,7 +319,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Cl system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction @@ -343,6 +345,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index afc430970..e95224dac 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu sim_ticks 31247500 # Number of ticks simulated final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85405 # Simulator instruction rate (inst/s) -host_op_rate 154687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 495766938 # Simulator tick rate (ticks/s) -host_mem_usage 269328 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 377585 # Simulator instruction rate (inst/s) +host_op_rate 682900 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2185869298 # Simulator tick rate (ticks/s) +host_mem_usage 268708 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -71,7 +71,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Cl system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction @@ -95,6 +97,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index 0fd976f9c..b7214d7d7 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu sim_ticks 26661500 # Number of ticks simulated final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67147 # Simulator instruction rate (inst/s) -host_op_rate 67138 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140157650 # Simulator tick rate (ticks/s) -host_mem_usage 253164 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 139098 # Simulator instruction rate (inst/s) +host_op_rate 139080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 290337480 # Simulator tick rate (ticks/s) +host_mem_usage 255644 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 12770 # Number of instructions simulated sim_ops 12770 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -404,37 +404,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 26300 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 29 9.70% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191 63.88% 73.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79 26.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29 9.67% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191 63.67% 73.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 25.67% 99.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3 1.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued @@ -445,7 +449,9 @@ system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.09% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued @@ -467,8 +473,10 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2015 22.62% 88.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1006 11.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2014 22.60% 88.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 999 11.21% 99.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 7 0.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8910 # Type of FU issued @@ -480,7 +488,9 @@ system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Ty system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMultAcc 0 0.00% 65.99% # Type of FU issued system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMisc 0 0.00% 65.99% # Type of FU issued system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued @@ -502,27 +512,29 @@ system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Ty system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2411 23.21% 89.21% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1121 10.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2410 23.20% 89.20% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1114 10.73% 99.92% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMemRead 1 0.01% 99.93% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::total 10386 # Type of FU issued system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued system.cpu.iq.rate 0.361863 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 151 # FU busy when requested +system.cpu.iq.fu_busy_cnt::0 152 # FU busy when requested system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 299 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.007825 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.007877 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.015495 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.015547 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 65200 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 17504 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 43 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 19569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses +system.cpu.iq.fp_alu_accesses 23 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 740 # Number of loads squashed @@ -655,7 +667,9 @@ system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction @@ -677,8 +691,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6402 # Class of committed instruction @@ -690,7 +706,9 @@ system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Cl system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::FloatMisc 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction @@ -712,8 +730,10 @@ system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::MemRead 1185 18.51% 86.49% # Class of committed instruction -system.cpu.commit.op_class_1::MemWrite 865 13.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_1::MemRead 1184 18.49% 86.47% # Class of committed instruction +system.cpu.commit.op_class_1::MemWrite 858 13.40% 99.88% # Class of committed instruction +system.cpu.commit.op_class_1::FloatMemRead 1 0.02% 99.89% # Class of committed instruction +system.cpu.commit.op_class_1::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6402 # Class of committed instruction diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 24ae64048..c02cfcc5d 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu sim_ticks 29908500 # Number of ticks simulated final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58398 # Simulator instruction rate (inst/s) -host_op_rate 58392 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120966219 # Simulator tick rate (ticks/s) -host_mem_usage 251080 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 90593 # Simulator instruction rate (inst/s) +host_op_rate 90586 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187662601 # Simulator tick rate (ticks/s) +host_mem_usage 251772 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -370,7 +370,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.07% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.07% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.07% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.07% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.07% # attempts to use FU when none available @@ -394,6 +396,8 @@ system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.07% # at system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.07% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 53 17.15% 70.23% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 92 29.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -404,7 +408,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.29% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.29% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.29% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.29% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.29% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.29% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.29% # Type of FU issued @@ -428,6 +434,8 @@ system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.29% # T system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.29% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 4185 16.72% 90.01% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 2501 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 25032 # Type of FU issued @@ -520,7 +528,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 75.77% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 75.77% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction @@ -544,6 +554,8 @@ system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 3be5d7ce8..9445c1e91 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110250 # Simulator instruction rate (inst/s) -host_op_rate 110244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55345027 # Simulator tick rate (ticks/s) -host_mem_usage 240104 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 446852 # Simulator instruction rate (inst/s) +host_op_rate 446721 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 224213840 # Simulator tick rate (ticks/s) +host_mem_usage 239476 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -73,7 +73,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Cl system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction @@ -97,6 +99,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 387eea7ee..b91f75440 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000045 # Nu sim_ticks 44698500 # Number of ticks simulated final_tick 44698500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128576 # Simulator instruction rate (inst/s) -host_op_rate 128568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 379003891 # Simulator tick rate (ticks/s) -host_mem_usage 250608 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 357665 # Simulator instruction rate (inst/s) +host_op_rate 357507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1053539740 # Simulator tick rate (ticks/s) +host_mem_usage 250236 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -65,7 +65,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Cl system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction @@ -89,6 +91,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt index 090f011e7..db5d6bd9b 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000461 # Nu sim_ticks 461109000 # Number of ticks simulated final_tick 461109000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212686 # Simulator instruction rate (inst/s) -host_op_rate 212584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15184120914 # Simulator tick rate (ticks/s) -host_mem_usage 634004 # Number of bytes of host memory used +host_inst_rate 260049 # Simulator instruction rate (inst/s) +host_op_rate 259797 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18548021181 # Simulator tick rate (ticks/s) +host_mem_usage 634440 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated @@ -347,7 +347,9 @@ system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Cl system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction @@ -369,8 +371,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 1196 18.51% 86.55% # Class of executed instruction +system.cpu.op_class::MemWrite 861 13.32% 99.88% # Class of executed instruction +system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 47755a477..e2e78f729 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000065 # Nu sim_ticks 64758000 # Number of ticks simulated final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 560678 # Simulator instruction rate (inst/s) -host_op_rate 559951 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5612828222 # Simulator tick rate (ticks/s) -host_mem_usage 638096 # Number of bytes of host memory used +host_inst_rate 610635 # Simulator instruction rate (inst/s) +host_op_rate 610062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6117087273 # Simulator tick rate (ticks/s) +host_mem_usage 638532 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated @@ -326,7 +326,9 @@ system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Cl system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction @@ -348,8 +350,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 1196 18.51% 86.55% # Class of executed instruction +system.cpu.op_class::MemWrite 861 13.32% 99.88% # Class of executed instruction +system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index afb55617d..e93677565 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000372 # Nu sim_ticks 372284000 # Number of ticks simulated final_tick 372284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131983 # Simulator instruction rate (inst/s) -host_op_rate 152589 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9840410910 # Simulator tick rate (ticks/s) -host_mem_usage 650048 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 264702 # Simulator instruction rate (inst/s) +host_op_rate 305997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19731375693 # Simulator tick rate (ticks/s) +host_mem_usage 650740 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -437,7 +437,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Cl system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction @@ -460,7 +462,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction -system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 934 16.02% 99.73% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.73% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 3eb7c70d8..d277e8b47 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu sim_ticks 52453000 # Number of ticks simulated final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 234245 # Simulator instruction rate (inst/s) -host_op_rate 270642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2457731659 # Simulator tick rate (ticks/s) -host_mem_usage 654144 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 494492 # Simulator instruction rate (inst/s) +host_op_rate 571324 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5188174566 # Simulator tick rate (ticks/s) +host_mem_usage 654324 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -416,7 +416,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Cl system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction @@ -439,7 +441,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction -system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 934 16.02% 99.73% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 99.73% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt index b290494a3..bec900094 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000423 # Nu sim_ticks 423127000 # Number of ticks simulated final_tick 423127000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243919 # Simulator instruction rate (inst/s) -host_op_rate 243782 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18277293383 # Simulator tick rate (ticks/s) -host_mem_usage 631884 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 225323 # Simulator instruction rate (inst/s) +host_op_rate 225118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16871799532 # Simulator tick rate (ticks/s) +host_mem_usage 632064 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -333,7 +333,9 @@ system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Cl system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction @@ -357,6 +359,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 3bd6c6ff6..c7fcf57ee 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000062 # Nu sim_ticks 62333000 # Number of ticks simulated final_tick 62333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 499257 # Simulator instruction rate (inst/s) -host_op_rate 498740 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5505866075 # Simulator tick rate (ticks/s) -host_mem_usage 635976 # Number of bytes of host memory used +host_inst_rate 472885 # Simulator instruction rate (inst/s) +host_op_rate 471880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5205204018 # Simulator tick rate (ticks/s) +host_mem_usage 636424 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated @@ -313,7 +313,9 @@ system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Cl system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction @@ -337,6 +339,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index ba7428ffa..ef64cb9b2 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000380 # Nu sim_ticks 380341000 # Number of ticks simulated final_tick 380341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148243 # Simulator instruction rate (inst/s) -host_op_rate 148143 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10150108269 # Simulator tick rate (ticks/s) -host_mem_usage 632328 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 290732 # Simulator instruction rate (inst/s) +host_op_rate 290372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19883940078 # Simulator tick rate (ticks/s) +host_mem_usage 632768 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -316,7 +316,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Cl system.cpu.op_class::FloatCmp 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% # Class of executed instruction @@ -340,6 +342,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 898894976..e9aaf12b4 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000057 # Nu sim_ticks 56511000 # Number of ticks simulated final_tick 56511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 292382 # Simulator instruction rate (inst/s) -host_op_rate 292023 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2971184542 # Simulator tick rate (ticks/s) -host_mem_usage 636424 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 572788 # Simulator instruction rate (inst/s) +host_op_rate 572177 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5822018151 # Simulator tick rate (ticks/s) +host_mem_usage 636864 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -294,7 +294,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Cl system.cpu.op_class::FloatCmp 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% # Class of executed instruction @@ -318,6 +320,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index d3b77ec90..e2f01a250 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000508 # Nu sim_ticks 507841000 # Number of ticks simulated final_tick 507841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96340 # Simulator instruction rate (inst/s) -host_op_rate 173892 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8558810197 # Simulator tick rate (ticks/s) -host_mem_usage 650468 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 118772 # Simulator instruction rate (inst/s) +host_op_rate 214398 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10553661963 # Simulator tick rate (ticks/s) +host_mem_usage 651408 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -324,7 +324,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Cl system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction @@ -348,6 +350,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index bf9b895e3..20642e324 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000059 # Nu sim_ticks 58513000 # Number of ticks simulated final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 325988 # Simulator instruction rate (inst/s) -host_op_rate 588251 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3335289412 # Simulator tick rate (ticks/s) -host_mem_usage 654560 # Number of bytes of host memory used +host_inst_rate 297973 # Simulator instruction rate (inst/s) +host_op_rate 537391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3045372421 # Simulator tick rate (ticks/s) +host_mem_usage 656016 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated @@ -301,7 +301,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Cl system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction @@ -325,6 +327,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt index be5cb8048..738fdd2f1 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000668 # Nu sim_ticks 668137500 # Number of ticks simulated final_tick 668137500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112893 # Simulator instruction rate (inst/s) -host_op_rate 232149 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1126339333 # Simulator tick rate (ticks/s) -host_mem_usage 1312868 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host +host_inst_rate 245703 # Simulator instruction rate (inst/s) +host_op_rate 505252 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2451366703 # Simulator tick rate (ticks/s) +host_mem_usage 1323744 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 66963 # Number of instructions simulated sim_ops 137705 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -430,7 +430,9 @@ system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Cl system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 80.25% # Class of executed instruction system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 80.25% # Class of executed instruction system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction @@ -452,8 +454,10 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction -system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction -system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16382 11.90% 92.15% # Class of executed instruction +system.cpu0.op_class::MemWrite 10514 7.64% 99.78% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 302 0.22% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 137705 # Class of executed instruction diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 96e0c0f43..60be1d71b 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000500 # Number of ticks simulated final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1173010 # Simulator instruction rate (inst/s) -host_op_rate 1178851 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 700951539 # Simulator tick rate (ticks/s) -host_mem_usage 393548 # Number of bytes of host memory used -host_seconds 77.24 # Real time elapsed on the host +host_inst_rate 2113722 # Simulator instruction rate (inst/s) +host_op_rate 2124249 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1263089948 # Simulator tick rate (ticks/s) +host_mem_usage 393096 # Number of bytes of host memory used +host_seconds 42.86 # Real time elapsed on the host sim_insts 90602408 # Number of instructions simulated sim_ops 91053639 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Cl system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction @@ -215,8 +217,10 @@ system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 22475905 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744822 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 6 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 699231bfd..e4e6e6d7c 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147164 # Nu sim_ticks 147164058500 # Number of ticks simulated final_tick 147164058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 748296 # Simulator instruction rate (inst/s) -host_op_rate 752015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1215788381 # Simulator tick rate (ticks/s) -host_mem_usage 404056 # Number of bytes of host memory used -host_seconds 121.04 # Real time elapsed on the host +host_inst_rate 1482184 # Simulator instruction rate (inst/s) +host_op_rate 1489549 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2408165715 # Simulator tick rate (ticks/s) +host_mem_usage 404112 # Number of bytes of host memory used +host_seconds 61.11 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -187,7 +187,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Cl system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction @@ -209,8 +211,10 @@ system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 22475905 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744822 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 6 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 878a32205..424dd4571 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu sim_ticks 122215823500 # Number of ticks simulated final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2878876 # Simulator instruction rate (inst/s) -host_op_rate 2878995 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1443018123 # Simulator tick rate (ticks/s) -host_mem_usage 374552 # Number of bytes of host memory used -host_seconds 84.69 # Real time elapsed on the host +host_inst_rate 2760120 # Simulator instruction rate (inst/s) +host_op_rate 2760234 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1383492525 # Simulator tick rate (ticks/s) +host_mem_usage 373928 # Number of bytes of host memory used +host_seconds 88.34 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -73,7 +73,9 @@ system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Cl system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction @@ -95,8 +97,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction -system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction +system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index f30c65448..3e6cfcc08 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1086071 # Simulator instruction rate (inst/s) -host_op_rate 1912397 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1161424459 # Simulator tick rate (ticks/s) -host_mem_usage 401896 # Number of bytes of host memory used -host_seconds 145.47 # Real time elapsed on the host +host_inst_rate 1482871 # Simulator instruction rate (inst/s) +host_op_rate 2611098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1585754680 # Simulator tick rate (ticks/s) +host_mem_usage 400496 # Number of bytes of host memory used +host_seconds 106.54 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -77,7 +77,9 @@ system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Cl system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction @@ -99,8 +101,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction -system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction +system.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index cd3aa922b..79bf3fe5b 100644 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1644868 # Simulator instruction rate (inst/s) -host_op_rate 1644867 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 822434164 # Simulator tick rate (ticks/s) -host_mem_usage 249080 # Number of bytes of host memory used -host_seconds 242.37 # Real time elapsed on the host +host_inst_rate 2875345 # Simulator instruction rate (inst/s) +host_op_rate 2875345 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1437672996 # Simulator tick rate (ticks/s) +host_mem_usage 248448 # Number of bytes of host memory used +host_seconds 138.65 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -103,7 +103,9 @@ system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Cl system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 57.40% # Class of executed instruction system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction @@ -125,8 +127,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::MemRead 94754510 23.77% 81.56% # Class of executed instruction -system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 46072315 11.56% 69.35% # Class of executed instruction +system.cpu.op_class::MemWrite 30396984 7.62% 76.97% # Class of executed instruction +system.cpu.op_class::FloatMemRead 48682195 12.21% 89.18% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 43123780 10.82% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664651 # Class of executed instruction diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index d8e803150..f26d1562f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000125 # Nu sim_ticks 124830000 # Number of ticks simulated final_tick 124830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147575 # Simulator instruction rate (inst/s) -host_op_rate 147575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15906234 # Simulator tick rate (ticks/s) -host_mem_usage 266768 # Number of bytes of host memory used -host_seconds 7.85 # Real time elapsed on the host +host_inst_rate 284956 # Simulator instruction rate (inst/s) +host_op_rate 284955 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30713692 # Simulator tick rate (ticks/s) +host_mem_usage 268476 # Number of bytes of host memory used +host_seconds 4.06 # Real time elapsed on the host sim_insts 1158143 # Number of instructions simulated sim_ops 1158143 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -404,7 +404,9 @@ system.cpu0.iq.fu_full::FloatAdd 0 0.00% 39.09% # at system.cpu0.iq.fu_full::FloatCmp 0 0.00% 39.09% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCvt 0 0.00% 39.09% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMult 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 39.09% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatDiv 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 39.09% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 39.09% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAdd 0 0.00% 39.09% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 39.09% # attempts to use FU when none available @@ -428,6 +430,8 @@ system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.09% # at system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 39.09% # attempts to use FU when none available system.cpu0.iq.fu_full::MemRead 77 23.33% 62.42% # attempts to use FU when none available system.cpu0.iq.fu_full::MemWrite 124 37.58% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -438,7 +442,9 @@ system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Ty system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.23% # Type of FU issued @@ -462,6 +468,8 @@ system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::MemRead 177454 38.45% 80.68% # Type of FU issued system.cpu0.iq.FU_type_0::MemWrite 89178 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::total 461556 # Type of FU issued @@ -554,7 +562,9 @@ system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Cl system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.97% # Class of committed instruction @@ -578,6 +588,8 @@ system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.9 system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::MemRead 175137 32.63% 83.60% # Class of committed instruction system.cpu0.commit.op_class_0::MemWrite 88033 16.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::total 536742 # Class of committed instruction @@ -932,7 +944,9 @@ system.cpu1.iq.fu_full::FloatAdd 0 0.00% 40.04% # at system.cpu1.iq.fu_full::FloatCmp 0 0.00% 40.04% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCvt 0 0.00% 40.04% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMult 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 40.04% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatDiv 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 40.04% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 40.04% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAdd 0 0.00% 40.04% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 40.04% # attempts to use FU when none available @@ -956,6 +970,8 @@ system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.04% # at system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 40.04% # attempts to use FU when none available system.cpu1.iq.fu_full::MemRead 60 12.58% 52.62% # attempts to use FU when none available system.cpu1.iq.fu_full::MemWrite 226 47.38% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -966,7 +982,9 @@ system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.99% # Ty system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.99% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.99% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 47.99% # Type of FU issued system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 47.99% # Type of FU issued system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.99% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.99% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.99% # Type of FU issued @@ -990,6 +1008,8 @@ system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.99% # system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.99% # Type of FU issued system.cpu1.iq.FU_type_0::MemRead 103154 35.70% 83.69% # Type of FU issued system.cpu1.iq.FU_type_0::MemWrite 47124 16.31% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::total 288968 # Type of FU issued @@ -1082,7 +1102,9 @@ system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.57% # Cl system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.57% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.57% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 54.57% # Class of committed instruction system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 54.57% # Class of committed instruction system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.57% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.57% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.57% # Class of committed instruction @@ -1106,6 +1128,8 @@ system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.5 system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.57% # Class of committed instruction system.cpu1.commit.op_class_0::MemRead 100003 31.22% 85.78% # Class of committed instruction system.cpu1.commit.op_class_0::MemWrite 45541 14.22% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::total 320342 # Class of committed instruction @@ -1456,7 +1480,9 @@ system.cpu2.iq.fu_full::FloatAdd 0 0.00% 44.96% # at system.cpu2.iq.fu_full::FloatCmp 0 0.00% 44.96% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatCvt 0 0.00% 44.96% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatMult 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 44.96% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatDiv 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMisc 0 0.00% 44.96% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 44.96% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAdd 0 0.00% 44.96% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 44.96% # attempts to use FU when none available @@ -1480,6 +1506,8 @@ system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.96% # at system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 44.96% # attempts to use FU when none available system.cpu2.iq.fu_full::MemRead 58 11.24% 56.20% # attempts to use FU when none available system.cpu2.iq.fu_full::MemWrite 226 43.80% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -1490,7 +1518,9 @@ system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.16% # Ty system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.16% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.16% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 50.16% # Type of FU issued system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 50.16% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.16% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.16% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.16% # Type of FU issued @@ -1514,6 +1544,8 @@ system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.16% # system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.16% # Type of FU issued system.cpu2.iq.FU_type_0::MemRead 81333 35.58% 85.74% # Type of FU issued system.cpu2.iq.FU_type_0::MemWrite 32584 14.26% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::total 228568 # Type of FU issued @@ -1606,7 +1638,9 @@ system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Cl system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 55.92% # Class of committed instruction system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 55.92% # Class of committed instruction system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction @@ -1630,6 +1664,8 @@ system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.9 system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction system.cpu2.commit.op_class_0::MemRead 77871 31.55% 87.47% # Class of committed instruction system.cpu2.commit.op_class_0::MemWrite 30919 12.53% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::total 246824 # Class of committed instruction @@ -1981,7 +2017,9 @@ system.cpu3.iq.fu_full::FloatAdd 0 0.00% 41.42% # at system.cpu3.iq.fu_full::FloatCmp 0 0.00% 41.42% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatCvt 0 0.00% 41.42% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatMult 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 41.42% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatDiv 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMisc 0 0.00% 41.42% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 41.42% # attempts to use FU when none available system.cpu3.iq.fu_full::SimdAdd 0 0.00% 41.42% # attempts to use FU when none available system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 41.42% # attempts to use FU when none available @@ -2005,6 +2043,8 @@ system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.42% # at system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 41.42% # attempts to use FU when none available system.cpu3.iq.fu_full::MemRead 48 10.04% 51.46% # attempts to use FU when none available system.cpu3.iq.fu_full::MemWrite 232 48.54% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -2015,7 +2055,9 @@ system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Ty system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 48.80% # Type of FU issued system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 48.80% # Type of FU issued system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued @@ -2039,6 +2081,8 @@ system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued system.cpu3.iq.FU_type_0::MemRead 93130 35.81% 84.60% # Type of FU issued system.cpu3.iq.FU_type_0::MemWrite 40048 15.40% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::total 260097 # Type of FU issued @@ -2131,7 +2175,9 @@ system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.12% # Cl system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.12% # Class of committed instruction system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.12% # Class of committed instruction system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 55.12% # Class of committed instruction system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 55.12% # Class of committed instruction system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.12% # Class of committed instruction system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.12% # Class of committed instruction system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.12% # Class of committed instruction @@ -2155,6 +2201,8 @@ system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.1 system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.12% # Class of committed instruction system.cpu3.commit.op_class_0::MemRead 89736 31.43% 86.55% # Class of committed instruction system.cpu3.commit.op_class_0::MemWrite 38400 13.45% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::total 285532 # Class of committed instruction diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index fb2ceaeb2..fe9ceb9c1 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428563 # Simulator instruction rate (inst/s) -host_op_rate 428559 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55493138 # Simulator tick rate (ticks/s) -host_mem_usage 263740 # Number of bytes of host memory used -host_seconds 1.58 # Real time elapsed on the host +host_inst_rate 1262575 # Simulator instruction rate (inst/s) +host_op_rate 1262551 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163483418 # Simulator tick rate (ticks/s) +host_mem_usage 263368 # Number of bytes of host memory used +host_seconds 0.54 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,7 +95,9 @@ system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Cl system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 52.97% # Class of executed instruction system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 52.97% # Class of executed instruction system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction @@ -119,6 +121,8 @@ system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Cl system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 175388 # Class of executed instruction @@ -268,7 +272,9 @@ system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Cl system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction @@ -292,6 +298,8 @@ system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Cl system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 167432 # Class of executed instruction @@ -438,7 +446,9 @@ system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Cl system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction @@ -462,6 +472,8 @@ system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Cl system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction +system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::total 167367 # Class of executed instruction @@ -609,7 +621,9 @@ system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Cl system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatMultAcc 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatMisc 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction @@ -633,6 +647,8 @@ system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Cl system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction +system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::total 167304 # Class of executed instruction diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index c1353f29d..e24c67483 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000263 # Nu sim_ticks 263409500 # Number of ticks simulated final_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 389943 # Simulator instruction rate (inst/s) -host_op_rate 389940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 154718592 # Simulator tick rate (ticks/s) -host_mem_usage 263736 # Number of bytes of host memory used -host_seconds 1.70 # Real time elapsed on the host +host_inst_rate 919692 # Simulator instruction rate (inst/s) +host_op_rate 919679 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 364903746 # Simulator tick rate (ticks/s) +host_mem_usage 263368 # Number of bytes of host memory used +host_seconds 0.72 # Real time elapsed on the host sim_insts 663871 # Number of instructions simulated sim_ops 663871 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,7 +95,9 @@ system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Cl system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction @@ -119,6 +121,8 @@ system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Cl system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::MemRead 48981 30.94% 84.23% # Class of executed instruction system.cpu0.op_class::MemWrite 24959 15.77% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 158306 # Class of executed instruction @@ -364,7 +368,9 @@ system.cpu1.op_class::FloatAdd 0 0.00% 59.26% # Cl system.cpu1.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 59.26% # Class of executed instruction system.cpu1.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::FloatMisc 0 0.00% 59.26% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction @@ -388,6 +394,8 @@ system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Cl system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction system.cpu1.op_class::MemRead 55710 32.89% 92.15% # Class of executed instruction system.cpu1.op_class::MemWrite 13289 7.85% 100.00% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 169372 # Class of executed instruction @@ -632,7 +640,9 @@ system.cpu2.op_class::FloatAdd 0 0.00% 59.45% # Cl system.cpu2.op_class::FloatCmp 0 0.00% 59.45% # Class of executed instruction system.cpu2.op_class::FloatCvt 0 0.00% 59.45% # Class of executed instruction system.cpu2.op_class::FloatMult 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::FloatMultAcc 0 0.00% 59.45% # Class of executed instruction system.cpu2.op_class::FloatDiv 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::FloatMisc 0 0.00% 59.45% # Class of executed instruction system.cpu2.op_class::FloatSqrt 0 0.00% 59.45% # Class of executed instruction system.cpu2.op_class::SimdAdd 0 0.00% 59.45% # Class of executed instruction system.cpu2.op_class::SimdAddAcc 0 0.00% 59.45% # Class of executed instruction @@ -656,6 +666,8 @@ system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.45% # Cl system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.45% # Class of executed instruction system.cpu2.op_class::MemRead 53070 31.98% 91.44% # Class of executed instruction system.cpu2.op_class::MemWrite 14205 8.56% 100.00% # Class of executed instruction +system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::total 165924 # Class of executed instruction @@ -900,7 +912,9 @@ system.cpu3.op_class::FloatAdd 0 0.00% 59.20% # Cl system.cpu3.op_class::FloatCmp 0 0.00% 59.20% # Class of executed instruction system.cpu3.op_class::FloatCvt 0 0.00% 59.20% # Class of executed instruction system.cpu3.op_class::FloatMult 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::FloatMultAcc 0 0.00% 59.20% # Class of executed instruction system.cpu3.op_class::FloatDiv 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::FloatMisc 0 0.00% 59.20% # Class of executed instruction system.cpu3.op_class::FloatSqrt 0 0.00% 59.20% # Class of executed instruction system.cpu3.op_class::SimdAdd 0 0.00% 59.20% # Class of executed instruction system.cpu3.op_class::SimdAddAcc 0 0.00% 59.20% # Class of executed instruction @@ -924,6 +938,8 @@ system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.20% # Cl system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.20% # Class of executed instruction system.cpu3.op_class::MemRead 57167 33.54% 92.75% # Class of executed instruction system.cpu3.op_class::MemWrite 12359 7.25% 100.00% # Class of executed instruction +system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::total 170427 # Class of executed instruction diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 9ca521f76..4f8d8987a 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1734998 # Simulator instruction rate (inst/s) -host_op_rate 1734998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 868493662 # Simulator tick rate (ticks/s) -host_mem_usage 251200 # Number of bytes of host memory used -host_seconds 50.92 # Real time elapsed on the host +host_inst_rate 2866684 # Simulator instruction rate (inst/s) +host_op_rate 2866683 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1434985124 # Simulator tick rate (ticks/s) +host_mem_usage 250568 # Number of bytes of host memory used +host_seconds 30.82 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -103,7 +103,9 @@ system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Cl system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.40% # Class of executed instruction system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.44% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction @@ -125,8 +127,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 20366476 23.03% 83.47% # Class of executed instruction +system.cpu.op_class::MemWrite 14619024 16.53% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 310 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 1605 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 39b06f58a..d5c3e5af1 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.134921 # Nu sim_ticks 134921160500 # Number of ticks simulated final_tick 134921160500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1080841 # Simulator instruction rate (inst/s) -host_op_rate 1080841 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1650749081 # Simulator tick rate (ticks/s) -host_mem_usage 262472 # Number of bytes of host memory used -host_seconds 81.73 # Real time elapsed on the host +host_inst_rate 1865262 # Simulator instruction rate (inst/s) +host_op_rate 1865262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2848781352 # Simulator tick rate (ticks/s) +host_mem_usage 261840 # Number of bytes of host memory used +host_seconds 47.36 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,7 +104,9 @@ system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Cl system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.40% # Class of executed instruction system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.44% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction @@ -126,8 +128,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 20366476 23.03% 83.47% # Class of executed instruction +system.cpu.op_class::MemWrite 14619024 16.53% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 310 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 1605 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 0dedef5a8..8cea01eaa 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960022500 # Number of ticks simulated final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 970522 # Simulator instruction rate (inst/s) -host_op_rate 1241163 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 670069309 # Simulator tick rate (ticks/s) -host_mem_usage 268760 # Number of bytes of host memory used -host_seconds 73.07 # Real time elapsed on the host +host_inst_rate 1769120 # Simulator instruction rate (inst/s) +host_op_rate 2262458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1221438298 # Simulator tick rate (ticks/s) +host_mem_usage 267796 # Number of bytes of host memory used +host_seconds 40.08 # Real time elapsed on the host sim_insts 70913204 # Number of instructions simulated sim_ops 90688159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Cl system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction @@ -215,8 +217,10 @@ system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction +system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690106 # Class of executed instruction diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 992da2d61..ae3fac096 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.128202 # Nu sim_ticks 128202163500 # Number of ticks simulated final_tick 128202163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 621865 # Simulator instruction rate (inst/s) -host_op_rate 793946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1132872219 # Simulator tick rate (ticks/s) -host_mem_usage 278756 # Number of bytes of host memory used -host_seconds 113.17 # Real time elapsed on the host +host_inst_rate 1220543 # Simulator instruction rate (inst/s) +host_op_rate 1558290 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2223504943 # Simulator tick rate (ticks/s) +host_mem_usage 279580 # Number of bytes of host memory used +host_seconds 57.66 # Real time elapsed on the host sim_insts 70373651 # Number of instructions simulated sim_ops 89847385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -194,7 +194,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Cl system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction @@ -216,8 +218,10 @@ system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction +system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690106 # Class of executed instruction diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 3cc7eb188..6cb5528ee 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu sim_ticks 68148677000 # Number of ticks simulated final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2595314 # Simulator instruction rate (inst/s) -host_op_rate 2628918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1315986019 # Simulator tick rate (ticks/s) -host_mem_usage 250608 # Number of bytes of host memory used -host_seconds 51.79 # Real time elapsed on the host +host_inst_rate 2768800 # Simulator instruction rate (inst/s) +host_op_rate 2804650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1403953412 # Simulator tick rate (ticks/s) +host_mem_usage 249976 # Number of bytes of host memory used +host_seconds 48.54 # Real time elapsed on the host sim_insts 134398959 # Number of instructions simulated sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -73,7 +73,9 @@ system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Cl system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction @@ -95,8 +97,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 37046611 27.18% 84.49% # Class of executed instruction +system.cpu.op_class::MemWrite 19133112 14.04% 98.53% # Class of executed instruction +system.cpu.op_class::FloatMemRead 250107 0.18% 98.72% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293808 # Class of executed instruction diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 03cf29f2f..109903b56 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.203261 # Nu sim_ticks 203260902500 # Number of ticks simulated final_tick 203260902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1624841 # Simulator instruction rate (inst/s) -host_op_rate 1645879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2457359114 # Simulator tick rate (ticks/s) -host_mem_usage 261872 # Number of bytes of host memory used -host_seconds 82.72 # Real time elapsed on the host +host_inst_rate 1825324 # Simulator instruction rate (inst/s) +host_op_rate 1848958 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2760562270 # Simulator tick rate (ticks/s) +host_mem_usage 261500 # Number of bytes of host memory used +host_seconds 73.63 # Real time elapsed on the host sim_insts 134398959 # Number of instructions simulated sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -72,7 +72,9 @@ system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Cl system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction @@ -94,8 +96,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 37046611 27.18% 84.49% # Class of executed instruction +system.cpu.op_class::MemWrite 19133112 14.04% 98.53% # Class of executed instruction +system.cpu.op_class::FloatMemRead 250107 0.18% 98.72% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293808 # Class of executed instruction diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 3247793b8..8f24d441f 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1661672 # Simulator instruction rate (inst/s) -host_op_rate 1661672 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 830836471 # Simulator tick rate (ticks/s) -host_mem_usage 246768 # Number of bytes of host memory used -host_seconds 55.31 # Real time elapsed on the host +host_inst_rate 3055578 # Simulator instruction rate (inst/s) +host_op_rate 3055577 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1527789176 # Simulator tick rate (ticks/s) +host_mem_usage 246136 # Number of bytes of host memory used +host_seconds 30.08 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -103,7 +103,9 @@ system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Cl system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 71.17% # Class of executed instruction system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction @@ -125,8 +127,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction -system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 19433628 21.15% 92.31% # Class of executed instruction +system.cpu.op_class::MemWrite 6424338 6.99% 99.30% # Class of executed instruction +system.cpu.op_class::FloatMemRead 562580 0.61% 99.92% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 76788 0.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 2c1174f11..9a7bbe1ce 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118768 # Nu sim_ticks 118767526500 # Number of ticks simulated final_tick 118767526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1126977 # Simulator instruction rate (inst/s) -host_op_rate 1126976 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1456406210 # Simulator tick rate (ticks/s) -host_mem_usage 256508 # Number of bytes of host memory used -host_seconds 81.55 # Real time elapsed on the host +host_inst_rate 2099166 # Simulator instruction rate (inst/s) +host_op_rate 2099165 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2712778064 # Simulator tick rate (ticks/s) +host_mem_usage 256380 # Number of bytes of host memory used +host_seconds 43.78 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -97,7 +97,9 @@ system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Cl system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 71.17% # Class of executed instruction system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction @@ -119,8 +121,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction -system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 19433628 21.15% 92.31% # Class of executed instruction +system.cpu.op_class::MemWrite 6424338 6.99% 99.30% # Class of executed instruction +system.cpu.op_class::FloatMemRead 562580 0.61% 99.92% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 76788 0.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 1b2962550..04adafc72 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491500 # Number of ticks simulated final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1084851 # Simulator instruction rate (inst/s) -host_op_rate 1143608 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 627025223 # Simulator tick rate (ticks/s) -host_mem_usage 263772 # Number of bytes of host memory used -host_seconds 158.84 # Real time elapsed on the host +host_inst_rate 2182343 # Simulator instruction rate (inst/s) +host_op_rate 2300541 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1261356268 # Simulator tick rate (ticks/s) +host_mem_usage 263320 # Number of bytes of host memory used +host_seconds 78.96 # Real time elapsed on the host sim_insts 172317410 # Number of instructions simulated sim_ops 181650342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Cl system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction @@ -215,8 +217,10 @@ system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Cl system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction -system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction -system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 27348059 15.06% 92.74% # Class of executed instruction +system.cpu.op_class::MemWrite 12498389 6.88% 99.62% # Class of executed instruction +system.cpu.op_class::FloatMemRead 548085 0.30% 99.92% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 146246 0.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 21be26077..c0d3d2f4a 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230201 # Nu sim_ticks 230201146500 # Number of ticks simulated final_tick 230201146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 826360 # Simulator instruction rate (inst/s) -host_op_rate 871192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1106995865 # Simulator tick rate (ticks/s) -host_mem_usage 273252 # Number of bytes of host memory used -host_seconds 207.95 # Real time elapsed on the host +host_inst_rate 1601768 # Simulator instruction rate (inst/s) +host_op_rate 1688668 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2145736650 # Simulator tick rate (ticks/s) +host_mem_usage 273052 # Number of bytes of host memory used +host_seconds 107.28 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -187,7 +187,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Cl system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction @@ -209,8 +211,10 @@ system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Cl system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction -system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction -system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 27348059 15.06% 92.74% # Class of executed instruction +system.cpu.op_class::MemWrite 12498389 6.88% 99.62% # Class of executed instruction +system.cpu.op_class::FloatMemRead 548085 0.30% 99.92% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 146246 0.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index d03b1694b..289ea550d 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2512744 # Simulator instruction rate (inst/s) -host_op_rate 2512747 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1256380653 # Simulator tick rate (ticks/s) -host_mem_usage 246048 # Number of bytes of host memory used -host_seconds 76.99 # Real time elapsed on the host +host_inst_rate 2624723 # Simulator instruction rate (inst/s) +host_op_rate 2624726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1312370434 # Simulator tick rate (ticks/s) +host_mem_usage 246444 # Number of bytes of host memory used +host_seconds 73.70 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -73,7 +73,9 @@ system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Cl system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction @@ -95,8 +97,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction -system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 56837780 29.38% 89.71% # Class of executed instruction +system.cpu.op_class::MemWrite 18800854 9.72% 99.43% # Class of executed instruction +system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 5920b739e..c6c812ce5 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.270605 # Nu sim_ticks 270604702500 # Number of ticks simulated final_tick 270604702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1707855 # Simulator instruction rate (inst/s) -host_op_rate 1707857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2389075229 # Simulator tick rate (ticks/s) -host_mem_usage 256284 # Number of bytes of host memory used -host_seconds 113.27 # Real time elapsed on the host +host_inst_rate 1830893 # Simulator instruction rate (inst/s) +host_op_rate 1830895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2561189341 # Simulator tick rate (ticks/s) +host_mem_usage 255916 # Number of bytes of host memory used +host_seconds 105.66 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -65,7 +65,9 @@ system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Cl system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction @@ -87,8 +89,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction -system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 56837780 29.38% 89.71% # Class of executed instruction +system.cpu.op_class::MemWrite 18800854 9.72% 99.43% # Class of executed instruction +system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 24b1a8bcb..b7cc9a760 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1175193 # Simulator instruction rate (inst/s) -host_op_rate 1969730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1169160517 # Simulator tick rate (ticks/s) -host_mem_usage 289616 # Number of bytes of host memory used -host_seconds 112.38 # Real time elapsed on the host +host_inst_rate 1535006 # Simulator instruction rate (inst/s) +host_op_rate 2572810 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1527126307 # Simulator tick rate (ticks/s) +host_mem_usage 288212 # Number of bytes of host memory used +host_seconds 86.04 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -77,7 +77,9 @@ system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Cl system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction @@ -99,8 +101,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction -system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 55945136 25.27% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 20410230 9.22% 99.63% # Class of executed instruction +system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 180cfa389..cb7e359a9 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250992 # Nu sim_ticks 250991873500 # Number of ticks simulated final_tick 250991873500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1054537 # Simulator instruction rate (inst/s) -host_op_rate 1767501 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2004072574 # Simulator tick rate (ticks/s) -host_mem_usage 299608 # Number of bytes of host memory used -host_seconds 125.24 # Real time elapsed on the host +host_inst_rate 1067110 # Simulator instruction rate (inst/s) +host_op_rate 1788574 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2027966293 # Simulator tick rate (ticks/s) +host_mem_usage 298984 # Number of bytes of host memory used +host_seconds 123.77 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -71,7 +71,9 @@ system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Cl system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction @@ -93,8 +95,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction -system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 55945136 25.27% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 20410230 9.22% 99.63% # Class of executed instruction +system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction |