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authorGabe Black <gblack@eecs.umich.edu>2006-10-18 20:48:08 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-18 20:48:08 -0400
commit849d5e2efb24c177bb15a6c4d2c5e3a6a8dba349 (patch)
tree4928410991b057906056a4d897f66c3aabf6de67
parent94926a72e91bf8af1870ae439ca4a91135427269 (diff)
downloadgem5-849d5e2efb24c177bb15a6c4d2c5e3a6a8dba349.tar.xz
Fixed a compiler error, disassembly output, and corrected the address calculation.
--HG-- extra : convert_revision : d34b3c0443064addb6f454ac70fbaeda0678e329
-rw-r--r--src/arch/sparc/isa/formats/blockmem.isa12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/sparc/isa/formats/blockmem.isa b/src/arch/sparc/isa/formats/blockmem.isa
index a273f07e3..4a2a14a15 100644
--- a/src/arch/sparc/isa/formats/blockmem.isa
+++ b/src/arch/sparc/isa/formats/blockmem.isa
@@ -105,11 +105,11 @@ output decoder {{
printMnemonic(response, mnemonic);
if(save)
{
- printReg(response, _srcRegIdx[0]);
+ printReg(response, _srcRegIdx[1]);
ccprintf(response, ", ");
}
ccprintf(response, "[ ");
- printReg(response, _srcRegIdx[!save ? 0 : 1]);
+ printReg(response, _srcRegIdx[0]);
if(imm >= 0)
ccprintf(response, " + 0x%x ]", imm);
else
@@ -282,8 +282,8 @@ def template MicroLoadExecute {{
}};
def template MicroStoreExecute {{
- Fault %(class_name)s_%(micro_pc)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
+ Fault %(class_name)s::%(class_name)s_%(micro_pc)s::execute(
+ %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t write_result = 0;
@@ -323,8 +323,8 @@ let {{
if(EA & 0x3f)
return new MemAddressNotAligned;
'''
- addrCalcReg = 'EA = Rs1 + Rs2 + offset * 8;'
- addrCalcImm = 'EA = Rs1 + imm + offset * 8;'
+ addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
+ addrCalcImm = 'EA = Rs1 + imm + offset;'
iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags)
iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags)
header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm)