diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-23 04:49:48 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-23 04:49:48 -0400 |
| commit | a4329af937870e832caf3fc34e2ca448f2322ecc (patch) | |
| tree | 75f99dc15123d371a4d55f693b0d3044721bc7b3 | |
| parent | 69e82539fd81299751e1000c0dac49f2eddbbdb6 (diff) | |
| download | gem5-a4329af937870e832caf3fc34e2ca448f2322ecc.tar.xz | |
stats: Update stats for DMA port send
This patch updates the stats after removing the zero-time send used in
the DMA port.
5 files changed, 3987 insertions, 3991 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 156205699..955cfdbb2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534230 # Number of seconds simulated -sim_ticks 2534229746000 # Number of ticks simulated -final_tick 2534229746000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534173 # Number of seconds simulated +sim_ticks 2534173219000 # Number of ticks simulated +final_tick 2534173219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65745 # Simulator instruction rate (inst/s) -host_op_rate 84567 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2749446134 # Simulator tick rate (ticks/s) -host_mem_usage 380664 # Number of bytes of host memory used -host_seconds 921.72 # Real time elapsed on the host -sim_insts 60598794 # Number of instructions simulated -sim_ops 77947430 # Number of ops (including micro ops) simulated +host_inst_rate 58476 # Simulator instruction rate (inst/s) +host_op_rate 75217 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2445371941 # Simulator tick rate (ticks/s) +host_mem_usage 386340 # Number of bytes of host memory used +host_seconds 1036.31 # Real time elapsed on the host +sim_insts 60599410 # Number of instructions simulated +sim_ops 77948210 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095568 # Number of bytes read from this memory -system.physmem.bytes_read::total 129434640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 798080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9096016 # Number of bytes read from this memory +system.physmem.bytes_read::total 129435344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142152 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096882 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12470 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142159 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096893 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47169229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1313 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47170281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1389 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51074548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493383 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683517 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47169229 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51075966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314927 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314927 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493669 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190160 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683829 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47170281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1389 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4779219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53758065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4779503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53759795 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -69,26 +69,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15049421 # DTB read hits -system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11294481 # DTB write hits +system.cpu.checker.dtb.read_hits 15049590 # DTB read hits +system.cpu.checker.dtb.read_misses 7303 # DTB read misses +system.cpu.checker.dtb.write_hits 11294593 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15056723 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296670 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056893 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296782 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26343902 # DTB hits -system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26353393 # DTB accesses -system.cpu.checker.itb.inst_hits 61777557 # ITB inst hits +system.cpu.checker.dtb.hits 26344183 # DTB hits +system.cpu.checker.dtb.misses 9492 # DTB misses +system.cpu.checker.dtb.accesses 26353675 # DTB accesses +system.cpu.checker.itb.inst_hits 61778177 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -105,36 +105,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61782028 # ITB inst accesses -system.cpu.checker.itb.hits 61777557 # DTB hits +system.cpu.checker.itb.inst_accesses 61782648 # ITB inst accesses +system.cpu.checker.itb.hits 61778177 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61782028 # DTB accesses -system.cpu.checker.numCycles 78238000 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61782648 # DTB accesses +system.cpu.checker.numCycles 78238784 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51729015 # DTB read hits -system.cpu.dtb.read_misses 77642 # DTB read misses -system.cpu.dtb.write_hits 11810988 # DTB write hits -system.cpu.dtb.write_misses 17459 # DTB write misses +system.cpu.dtb.read_hits 51719750 # DTB read hits +system.cpu.dtb.read_misses 77229 # DTB read misses +system.cpu.dtb.write_hits 11809411 # DTB write hits +system.cpu.dtb.write_misses 17373 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7775 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2642 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7767 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2639 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51806657 # DTB read accesses -system.cpu.dtb.write_accesses 11828447 # DTB write accesses +system.cpu.dtb.perms_faults 1315 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51796979 # DTB read accesses +system.cpu.dtb.write_accesses 11826784 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63540003 # DTB hits -system.cpu.dtb.misses 95101 # DTB misses -system.cpu.dtb.accesses 63635104 # DTB accesses -system.cpu.itb.inst_hits 13083995 # ITB inst hits -system.cpu.itb.inst_misses 12083 # ITB inst misses +system.cpu.dtb.hits 63529161 # DTB hits +system.cpu.dtb.misses 94602 # DTB misses +system.cpu.dtb.accesses 63623763 # DTB accesses +system.cpu.itb.inst_hits 13045523 # ITB inst hits +system.cpu.itb.inst_misses 12142 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -143,121 +143,121 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5178 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5168 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3112 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3109 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13096078 # ITB inst accesses -system.cpu.itb.hits 13083995 # DTB hits -system.cpu.itb.misses 12083 # DTB misses -system.cpu.itb.accesses 13096078 # DTB accesses -system.cpu.numCycles 475967538 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13057665 # ITB inst accesses +system.cpu.itb.hits 13045523 # DTB hits +system.cpu.itb.misses 12142 # DTB misses +system.cpu.itb.accesses 13057665 # DTB accesses +system.cpu.numCycles 475815628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15172784 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12163693 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783478 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10392072 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8320250 # Number of BTB hits +system.cpu.BPredUnit.lookups 15155227 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12146705 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783529 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10394615 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8308125 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454874 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82640 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31374160 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 100930999 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15172784 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9775124 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22189039 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5936170 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 131560 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 97680943 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 99805 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208737 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 364 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13080141 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1016234 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6355 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155765235 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.799529 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.166844 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454278 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82490 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31347726 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 100822937 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15155227 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9762403 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22167713 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5923551 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 130252 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97680521 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2843 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 98238 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209120 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13041690 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1002552 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6432 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155704074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.799073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.166371 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133592933 85.77% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382764 0.89% 86.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755577 1.13% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2658359 1.71% 89.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2327487 1.49% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1136384 0.73% 91.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2915896 1.87% 93.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 784165 0.50% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9211670 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133553129 85.77% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1381799 0.89% 86.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1755926 1.13% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2652519 1.70% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2328486 1.50% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1136180 0.73% 91.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2905092 1.87% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 785179 0.50% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9205764 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155765235 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031878 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.212054 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33515539 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 97301422 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20013824 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1028268 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3906182 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2022458 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174763 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 117645711 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 578390 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3906182 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35614317 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37590587 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53594123 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18875472 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6184554 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110140296 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21341 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015182 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4143290 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 32170 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 114983026 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 504387694 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 504296628 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91066 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78733405 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36249620 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 891466 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797109 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12509806 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21006076 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13841580 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1961226 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2453000 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 100941360 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2057614 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126221061 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189445 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24437015 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65086313 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 513058 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155765235 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.810329 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523325 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155704074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031851 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.211895 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33480524 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97304946 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19992509 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1030333 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3895762 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2022425 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174533 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 117498058 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 576273 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3895762 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35565671 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37584641 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53601603 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18869314 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6187083 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110088875 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21357 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1014287 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4146063 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32391 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 114923514 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 504161217 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 504070393 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78734130 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36189383 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 892416 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 798033 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12508562 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20972747 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13834973 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1961849 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2465756 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 100830951 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2058696 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126177528 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189533 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24329335 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 64639752 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514100 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155704074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.810368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523012 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 110569920 70.98% 70.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13988875 8.98% 79.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7307591 4.69% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6076063 3.90% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12752921 8.19% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2780626 1.79% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1679008 1.08% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 481895 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128336 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 110503842 70.97% 70.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14006844 9.00% 79.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7305691 4.69% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6085046 3.91% 88.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12721239 8.17% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2798387 1.80% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1680857 1.08% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 475213 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126955 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155765235 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155704074 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57759 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57592 0.65% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available @@ -286,13 +286,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370724 94.64% 95.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 416242 4.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370496 94.62% 95.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 418270 4.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59912166 47.47% 47.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95497 0.08% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59895243 47.47% 47.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95317 0.08% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued @@ -305,11 +305,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 7 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued @@ -318,363 +318,363 @@ system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53392141 42.30% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12455427 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53367566 42.30% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12453578 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126221061 # Type of FU issued -system.cpu.iq.rate 0.265188 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8844727 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070073 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417312910 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127452442 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87180232 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23310 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12552 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134689743 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12379 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 626582 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126177528 # Type of FU issued +system.cpu.iq.rate 0.265182 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8846360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070110 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417165828 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127235505 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87177257 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23405 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134647760 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12462 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624931 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5289586 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7312 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30140 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2042757 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5256081 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7285 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30200 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2036035 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34106883 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1034668 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34106907 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1030049 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3906182 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28670725 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 450645 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103223935 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 233802 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21006076 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13841580 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1466072 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114504 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3680 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30140 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 409816 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293009 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 702825 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122971529 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52416599 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3249532 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3895762 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28674144 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 449674 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103114750 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 233495 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20972747 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13834973 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466916 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113563 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3765 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30200 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409921 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 292907 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 702828 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122963273 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52407414 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3214255 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224961 # number of nop insts executed -system.cpu.iew.exec_refs 64739842 # number of memory reference insts executed -system.cpu.iew.exec_branches 11733959 # Number of branches executed -system.cpu.iew.exec_stores 12323243 # Number of stores executed -system.cpu.iew.exec_rate 0.258361 # Inst execution rate -system.cpu.iew.wb_sent 121621677 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87190526 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47712664 # num instructions producing a value -system.cpu.iew.wb_consumers 88871095 # num instructions consuming a value +system.cpu.iew.exec_nop 225103 # number of nop insts executed +system.cpu.iew.exec_refs 64729141 # number of memory reference insts executed +system.cpu.iew.exec_branches 11726228 # Number of branches executed +system.cpu.iew.exec_stores 12321727 # Number of stores executed +system.cpu.iew.exec_rate 0.258426 # Inst execution rate +system.cpu.iew.wb_sent 121618308 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87187548 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47710631 # num instructions producing a value +system.cpu.iew.wb_consumers 88857501 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.183186 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536875 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183238 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24296365 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544556 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 611758 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151941485 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.513999 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.495079 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24186815 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544596 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612016 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151890748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.495245 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 124150656 81.71% 81.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13572481 8.93% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3978264 2.62% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2132059 1.40% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949397 1.28% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 999089 0.66% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1584839 1.04% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727042 0.48% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2847658 1.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 124092082 81.70% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13579714 8.94% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3980091 2.62% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2134436 1.41% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949184 1.28% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1000796 0.66% 96.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1579621 1.04% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 721647 0.48% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2853177 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151941485 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60749175 # Number of instructions committed -system.cpu.commit.committedOps 78097811 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151890748 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60749791 # Number of instructions committed +system.cpu.commit.committedOps 78098591 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27515313 # Number of memory references committed -system.cpu.commit.loads 15716490 # Number of loads committed -system.cpu.commit.membars 413125 # Number of memory barriers committed -system.cpu.commit.branches 10023277 # Number of branches committed +system.cpu.commit.refs 27515604 # Number of memory references committed +system.cpu.commit.loads 15716666 # Number of loads committed +system.cpu.commit.membars 413138 # Number of memory barriers committed +system.cpu.commit.branches 10023383 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69136099 # Number of committed integer instructions. -system.cpu.commit.function_calls 996018 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2847658 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69136784 # Number of committed integer instructions. +system.cpu.commit.function_calls 996034 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2853177 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 249572720 # The number of ROB reads -system.cpu.rob.rob_writes 208783952 # The number of ROB writes -system.cpu.timesIdled 1774345 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320202303 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592403923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60598794 # Number of Instructions Simulated -system.cpu.committedOps 77947430 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60598794 # Number of Instructions Simulated -system.cpu.cpi 7.854406 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.854406 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556725628 # number of integer regfile reads -system.cpu.int_regfile_writes 89967061 # number of integer regfile writes -system.cpu.fp_regfile_reads 8371 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 133111894 # number of misc regfile reads -system.cpu.misc_regfile_writes 912902 # number of misc regfile writes -system.cpu.icache.replacements 989535 # number of replacements -system.cpu.icache.tagsinuse 511.594104 # Cycle average of tags in use -system.cpu.icache.total_refs 12006884 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990047 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.127590 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 249407638 # The number of ROB reads +system.cpu.rob.rob_writes 208557399 # The number of ROB writes +system.cpu.timesIdled 1773714 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320111554 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592442776 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60599410 # Number of Instructions Simulated +system.cpu.committedOps 77948210 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60599410 # Number of Instructions Simulated +system.cpu.cpi 7.851819 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.851819 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127359 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127359 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556670721 # number of integer regfile reads +system.cpu.int_regfile_writes 89963166 # number of integer regfile writes +system.cpu.fp_regfile_reads 8373 # number of floating regfile reads +system.cpu.fp_regfile_writes 2910 # number of floating regfile writes +system.cpu.misc_regfile_reads 132949410 # number of misc regfile reads +system.cpu.misc_regfile_writes 912934 # number of misc regfile writes +system.cpu.icache.replacements 989799 # number of replacements +system.cpu.icache.tagsinuse 511.593898 # Cycle average of tags in use +system.cpu.icache.total_refs 11967809 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990311 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.084900 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.594104 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.593898 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12006884 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12006884 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12006884 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12006884 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12006884 # number of overall hits -system.cpu.icache.overall_hits::total 12006884 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1073125 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1073125 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1073125 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1073125 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1073125 # number of overall misses -system.cpu.icache.overall_misses::total 1073125 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14103457490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14103457490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14103457490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14103457490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14103457490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14103457490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13080009 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13080009 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13080009 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13080009 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13080009 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13080009 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082043 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082043 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082043 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082043 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082043 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082043 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13142.418162 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13142.418162 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13142.418162 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13142.418162 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4497 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11967809 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11967809 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11967809 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11967809 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11967809 # number of overall hits +system.cpu.icache.overall_hits::total 11967809 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1073749 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1073749 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1073749 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1073749 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1073749 # number of overall misses +system.cpu.icache.overall_misses::total 1073749 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14109467991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14109467991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14109467991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14109467991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14109467991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14109467991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13041558 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13041558 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13041558 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13041558 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13041558 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13041558 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082333 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082333 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082333 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082333 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082333 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082333 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13140.378236 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13140.378236 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13140.378236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13140.378236 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4599 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 306 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.244068 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.029412 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83043 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 83043 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 83043 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 83043 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 83043 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 83043 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990082 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 990082 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 990082 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 990082 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 990082 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 990082 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11447874492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11447874492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11447874492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11447874492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11447874492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11447874492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83395 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 83395 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 83395 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 83395 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 83395 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 83395 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990354 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 990354 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 990354 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 990354 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 990354 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 990354 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11451236993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11451236993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11451236993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11451236993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11451236993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11451236993 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7934000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7934000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075694 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075694 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075694 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.551882 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.551882 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075938 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075938 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075938 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.771487 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.771487 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645234 # number of replacements -system.cpu.dcache.tagsinuse 511.991712 # Cycle average of tags in use -system.cpu.dcache.total_refs 21791132 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645746 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.745671 # Average number of references to valid blocks. +system.cpu.dcache.replacements 645297 # number of replacements +system.cpu.dcache.tagsinuse 511.991711 # Cycle average of tags in use +system.cpu.dcache.total_refs 21788102 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645809 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.737687 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.991711 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13929737 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13929737 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7288383 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7288383 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 284164 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 284164 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21218120 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21218120 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21218120 # number of overall hits -system.cpu.dcache.overall_hits::total 21218120 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 727325 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 727325 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962578 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13599 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3689903 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3689903 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3689903 # number of overall misses -system.cpu.dcache.overall_misses::total 3689903 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441506500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9441506500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104195765238 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104195765238 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181224000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 181224000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 305500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113637271738 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113637271738 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113637271738 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113637271738 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14657062 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14657062 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250961 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250961 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297763 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297763 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285742 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285742 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24908023 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24908023 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24908023 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24908023 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049623 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049623 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289005 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289005 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045671 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045671 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000049 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000049 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148141 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148141 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148141 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12981.138418 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12981.138418 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35170.640313 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35170.640313 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.273991 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.273991 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21821.428571 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21821.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30796.818165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30796.818165 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25623 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15683 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2532 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.119668 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.211470 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13926305 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13926305 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7288115 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7288115 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284783 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284783 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21214420 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21214420 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21214420 # number of overall hits +system.cpu.dcache.overall_hits::total 21214420 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 727409 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 727409 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962946 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962946 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13565 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13565 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3690355 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3690355 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3690355 # number of overall misses +system.cpu.dcache.overall_misses::total 3690355 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441109500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9441109500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104189875245 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104189875245 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180817000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180817000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 318500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 318500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113630984745 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113630984745 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113630984745 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113630984745 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14653714 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14653714 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10251061 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10251061 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 298348 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 298348 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285754 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285754 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24904775 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24904775 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24904775 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24904775 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049640 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049640 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289038 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289038 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045467 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045467 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000052 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000052 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148179 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148179 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148179 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148179 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12979.093605 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12979.093605 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35164.284211 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35164.284211 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13329.671950 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13329.671950 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21233.333333 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21233.333333 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30791.342498 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30791.342498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30791.342498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30791.342498 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25421 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15604 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2521 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.083697 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.948905 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609265 # number of writebacks -system.cpu.dcache.writebacks::total 609265 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339927 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 339927 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713517 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713517 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1356 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1356 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3053444 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3053444 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3053444 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3053444 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387398 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387398 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249061 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249061 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12243 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12243 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636459 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636459 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636459 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636459 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4758834000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4758834000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8540298916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8540298916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141913000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141913000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13299132916 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13299132916 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13299132916 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13299132916 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407357500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407357500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42045203371 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42045203371 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224452560871 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224452560871 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024296 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024296 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041117 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041117 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000049 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000049 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025552 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025552 # 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number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199342581499 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199347873499 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000621 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015539 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986806 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986806 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090316 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198964561499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198969853499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000664 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012480 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026703 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015554 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985873 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985873 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540999 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540999 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000664 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000086 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012480 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222789 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.090365 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000664 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000086 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012480 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222789 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.090365 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.817791 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40457.094439 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40770.241468 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.942407 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.942407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41044.839598 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40459.418744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40773.060165 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40005.288298 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40005.288298 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40255.737727 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40255.737727 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40261.502586 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40261.502586 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -959,16 +959,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307562103462 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307562103462 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1202929249396 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1202929249396 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88032 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88035 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 820ef6b3e..6d0b522dc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.004001 # Number of seconds simulated -sim_ticks 1004001369000 # Number of ticks simulated -final_tick 1004001369000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603785 # Number of seconds simulated +sim_ticks 2603784540500 # Number of ticks simulated +final_tick 2603784540500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89245 # Simulator instruction rate (inst/s) -host_op_rate 114826 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1450204701 # Simulator tick rate (ticks/s) -host_mem_usage 385792 # Number of bytes of host memory used -host_seconds 692.32 # Real time elapsed on the host -sim_insts 61785538 # Number of instructions simulated -sim_ops 79495701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 44040192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory +host_inst_rate 66983 # Simulator instruction rate (inst/s) +host_op_rate 86203 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2766471262 # Simulator tick rate (ticks/s) +host_mem_usage 391460 # Number of bytes of host memory used +host_seconds 941.19 # Real time elapsed on the host +sim_insts 63043892 # Number of instructions simulated +sim_ops 81133946 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 411712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4381300 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 403392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5239536 # Number of bytes read from this memory -system.physmem.bytes_read::total 54478052 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 411712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 403392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4277248 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 398208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4365108 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 424768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5242032 # Number of bytes read from this memory +system.physmem.bytes_read::total 131542884 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 398208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 424768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4259200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7304336 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 5505024 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7288336 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6433 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68530 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81894 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5668214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66832 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6222 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6637 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81933 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15301920 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66550 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43864673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 410071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4363839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 401784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5218654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54260934 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 410071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 401784 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 811855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4260201 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 16932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2998092 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7275225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4260201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43864673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 410071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4380771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 401784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 8216746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 61536159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823834 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46513268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 152934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1676447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 163135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2013236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50519881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 152934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 163135 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316069 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1635773 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6529 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1156830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2799132 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1635773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46513268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 152934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1682976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 163135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3170066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53319012 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -75,246 +75,246 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 64 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 382 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 446 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 64 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 382 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 446 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 64 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 382 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 446 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72797 # number of replacements -system.l2c.tagsinuse 53893.248657 # Cycle average of tags in use -system.l2c.total_refs 1879341 # Total number of references to valid blocks. -system.l2c.sampled_refs 137955 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.622855 # Average number of references to valid blocks. +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 147 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015058 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036687 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010605 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030007 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016763 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.845822 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.849705 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.847496 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.788093 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.775885 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.094283 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000383 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015058 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245668 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010605 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241609 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.094283 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40125 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40414.404184 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40401.462226 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40752.249330 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40018.602104 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.352120 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40025.227139 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40032.668693 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40071.411028 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.293283 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41479.108882 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40522.584254 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40955.438773 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41147.266459 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40415.399240 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40309.523810 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40988.091626 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40406.314468 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40738.817362 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40030.815252 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.056416 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40039.134560 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40039.048656 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40026.172297 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40033.496723 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41457.990366 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40504.355392 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40934.944357 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40125 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41383.664371 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40513.611874 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40924.743030 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41147.266459 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41363.480232 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40309.523810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40988.091626 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40496.981989 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40904.983621 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40125 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41383.664371 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40513.611874 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40924.743030 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41147.266459 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41363.480232 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40309.523810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40988.091626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40496.981989 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40904.983621 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -507,27 +507,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8992964 # DTB read hits -system.cpu0.dtb.read_misses 35495 # DTB read misses -system.cpu0.dtb.write_hits 5204763 # DTB write hits -system.cpu0.dtb.write_misses 6364 # DTB write misses +system.cpu0.dtb.read_hits 9065848 # DTB read hits +system.cpu0.dtb.read_misses 36360 # DTB read misses +system.cpu0.dtb.write_hits 5285915 # DTB write hits +system.cpu0.dtb.write_misses 6625 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2149 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1250 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 357 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2165 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 342 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 536 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9028459 # DTB read accesses -system.cpu0.dtb.write_accesses 5211127 # DTB write accesses +system.cpu0.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9102208 # DTB read accesses +system.cpu0.dtb.write_accesses 5292540 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14197727 # DTB hits -system.cpu0.dtb.misses 41859 # DTB misses -system.cpu0.dtb.accesses 14239586 # DTB accesses -system.cpu0.itb.inst_hits 4345219 # ITB inst hits -system.cpu0.itb.inst_misses 5468 # ITB inst misses +system.cpu0.dtb.hits 14351763 # DTB hits +system.cpu0.dtb.misses 42985 # DTB misses +system.cpu0.dtb.accesses 14394748 # DTB accesses +system.cpu0.itb.inst_hits 4413372 # ITB inst hits +system.cpu0.itb.inst_misses 5476 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -536,538 +536,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1393 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1660 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1472 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4350687 # ITB inst accesses -system.cpu0.itb.hits 4345219 # DTB hits -system.cpu0.itb.misses 5468 # DTB misses -system.cpu0.itb.accesses 4350687 # DTB accesses -system.cpu0.numCycles 69454344 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4418848 # ITB inst accesses +system.cpu0.itb.hits 4413372 # DTB hits +system.cpu0.itb.misses 5476 # DTB misses +system.cpu0.itb.accesses 4418848 # DTB accesses +system.cpu0.numCycles 70012496 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6140299 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4680843 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 325697 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3967848 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3011514 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6217398 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4733750 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 327130 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 4014715 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3051469 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 689087 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 31971 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 11903950 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32719278 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6140299 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3700601 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7697719 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1567081 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 66811 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21663795 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4784 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 55267 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 90495 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4343360 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 170443 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2579 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 42607741 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.991445 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.370542 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 700588 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31775 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12151517 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 33217564 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6217398 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3752057 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7806548 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1581421 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 67728 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 22157211 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 54633 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 92488 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4411708 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 171100 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2593 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 43471985 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.986228 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.366083 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34918154 81.95% 81.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 615023 1.44% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 811777 1.91% 85.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 689946 1.62% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 788421 1.85% 88.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 570027 1.34% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 709248 1.66% 91.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 365635 0.86% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3139510 7.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35673429 82.06% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 623255 1.43% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 822107 1.89% 85.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 699884 1.61% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 794381 1.83% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 577438 1.33% 90.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 719535 1.66% 91.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 371399 0.85% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3190557 7.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 42607741 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088408 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471090 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12410407 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21637687 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6924723 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 574768 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1060156 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 960041 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 65781 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40808812 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 215037 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1060156 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12993427 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5870248 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13615125 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6864393 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2204392 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39624437 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2198 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 433654 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1244123 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 41 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39987634 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 178950817 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 178916692 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34125 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31114791 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8872842 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 451750 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 410482 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5405254 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7790925 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5788375 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1121917 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1222446 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37402937 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 939151 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37702557 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87742 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6716452 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14173286 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 260083 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 42607741 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.884876 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.498206 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 43471985 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088804 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.474452 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12679354 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 22114744 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7023055 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 583785 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1071047 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 976895 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 65884 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 41430285 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 215511 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1071047 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13270486 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5876098 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14061413 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6963478 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2229463 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 40231881 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2342 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 440788 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1249784 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 63 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40621534 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 181781749 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 181747462 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34287 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31667723 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8953810 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 461246 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 417498 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5499956 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7912486 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5888217 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1140849 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1237786 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37992607 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 949484 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 38225982 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 89034 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6781394 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14357702 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 260797 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 43471985 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.879325 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.495049 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27166804 63.76% 63.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5957097 13.98% 77.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3214078 7.54% 85.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2477962 5.82% 91.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2111115 4.95% 96.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 940986 2.21% 98.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 497762 1.17% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 188040 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53897 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27798434 63.95% 63.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6055917 13.93% 77.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3289826 7.57% 85.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2491193 5.73% 91.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2118698 4.87% 96.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 969648 2.23% 98.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 500024 1.15% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 192302 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 55943 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 42607741 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 43471985 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 24897 2.34% 2.34% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 455 0.04% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841667 79.11% 81.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 196890 18.51% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25214 2.35% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 458 0.04% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 837969 78.03% 80.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 210208 19.58% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22610692 59.97% 60.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48707 0.13% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 696 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9470500 25.12% 85.36% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5519656 14.64% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22961950 60.07% 60.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 49879 0.13% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 12 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9545903 24.97% 85.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5615312 14.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37702557 # Type of FU issued -system.cpu0.iq.rate 0.542839 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1063909 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028218 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 119197860 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45066260 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34725350 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8284 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4664 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3878 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38709880 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4307 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 311315 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 38225982 # Type of FU issued +system.cpu0.iq.rate 0.545988 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1073849 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028092 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 121121114 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45731569 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35283041 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8365 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4658 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3880 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 39243245 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4372 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 321528 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1483597 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3551 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13024 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 603760 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1492825 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3508 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13401 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 615446 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2189792 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149535 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5390 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1060156 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4217100 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98020 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38461133 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 95338 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7790925 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5788375 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 610075 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39436 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2994 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13024 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 172050 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 129143 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 301193 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37281122 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9309198 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 421435 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1071047 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4218607 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98464 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 39061403 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 95550 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7912486 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5888217 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 616723 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40108 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2851 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13401 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 172679 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 129654 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 302333 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37800204 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9383648 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 425778 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119045 # number of nop insts executed -system.cpu0.iew.exec_refs 14772448 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4922535 # Number of branches executed -system.cpu0.iew.exec_stores 5463250 # Number of stores executed -system.cpu0.iew.exec_rate 0.536772 # Inst execution rate -system.cpu0.iew.wb_sent 37065432 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34729228 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18441672 # num instructions producing a value -system.cpu0.iew.wb_consumers 35371865 # num instructions consuming a value +system.cpu0.iew.exec_nop 119312 # number of nop insts executed +system.cpu0.iew.exec_refs 14941647 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4991029 # Number of branches executed +system.cpu0.iew.exec_stores 5557999 # Number of stores executed +system.cpu0.iew.exec_rate 0.539907 # Inst execution rate +system.cpu0.iew.wb_sent 37583639 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35286921 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18740450 # num instructions producing a value +system.cpu0.iew.wb_consumers 35992151 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.500030 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.521366 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.504009 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520682 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6577828 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 679068 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 261125 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 41583448 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.756316 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.712971 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6642216 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 688687 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 262418 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 42437322 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.753690 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.709171 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29716852 71.46% 71.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5893148 14.17% 85.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1935709 4.65% 90.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 983715 2.37% 92.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 787040 1.89% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 514741 1.24% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 394337 0.95% 96.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 216625 0.52% 97.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1141281 2.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 30360862 71.54% 71.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5984991 14.10% 85.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1981270 4.67% 90.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1011467 2.38% 92.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 801137 1.89% 94.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 524678 1.24% 95.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395620 0.93% 96.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 217374 0.51% 97.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1159923 2.73% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 41583448 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23837222 # Number of instructions committed -system.cpu0.commit.committedOps 31450221 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 42437322 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24255943 # Number of instructions committed +system.cpu0.commit.committedOps 31984592 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11491943 # Number of memory references committed -system.cpu0.commit.loads 6307328 # Number of loads committed -system.cpu0.commit.membars 231960 # Number of memory barriers committed -system.cpu0.commit.branches 4279027 # Number of branches committed +system.cpu0.commit.refs 11692432 # Number of memory references committed +system.cpu0.commit.loads 6419661 # Number of loads committed +system.cpu0.commit.membars 234476 # Number of memory barriers committed +system.cpu0.commit.branches 4345348 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27769802 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489719 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1141281 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28253924 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499843 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1159923 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 77601886 # The number of ROB reads -system.cpu0.rob.rob_writes 77118702 # The number of ROB writes -system.cpu0.timesIdled 360842 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26846603 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 1938505291 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23756480 # Number of Instructions Simulated -system.cpu0.committedOps 31369479 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23756480 # Number of Instructions Simulated -system.cpu0.cpi 2.923596 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.923596 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.342045 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.342045 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 173851540 # number of integer regfile reads -system.cpu0.int_regfile_writes 34503400 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3265 # number of floating regfile reads -system.cpu0.fp_regfile_writes 914 # number of floating regfile writes -system.cpu0.misc_regfile_reads 46745590 # number of misc regfile reads -system.cpu0.misc_regfile_writes 520572 # number of misc regfile writes -system.cpu0.icache.replacements 396597 # number of replacements -system.cpu0.icache.tagsinuse 510.934010 # Cycle average of tags in use -system.cpu0.icache.total_refs 3914161 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 397109 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.856641 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 79019948 # The number of ROB reads +system.cpu0.rob.rob_writes 78326882 # The number of ROB writes +system.cpu0.timesIdled 363516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26540511 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5137512787 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24175201 # Number of Instructions Simulated +system.cpu0.committedOps 31903850 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24175201 # Number of Instructions Simulated +system.cpu0.cpi 2.896046 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.896046 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.345298 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.345298 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 176381452 # number of integer regfile reads +system.cpu0.int_regfile_writes 35063385 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3376 # number of floating regfile reads +system.cpu0.fp_regfile_writes 954 # number of floating regfile writes +system.cpu0.misc_regfile_reads 47472836 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527620 # number of misc regfile writes +system.cpu0.icache.replacements 404634 # number of replacements +system.cpu0.icache.tagsinuse 511.577738 # Cycle average of tags in use +system.cpu0.icache.total_refs 3973841 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 405146 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.808417 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 7097415000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.934010 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.997918 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.997918 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3914161 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3914161 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3914161 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3914161 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3914161 # number of overall hits -system.cpu0.icache.overall_hits::total 3914161 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 429060 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 429060 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 429060 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 429060 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 429060 # number of overall misses -system.cpu0.icache.overall_misses::total 429060 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5859924996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5859924996 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5859924996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5859924996 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5859924996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5859924996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4343221 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4343221 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4343221 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4343221 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4343221 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4343221 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.098788 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.098788 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.098788 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.098788 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.098788 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.098788 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13657.588673 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.588673 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13657.588673 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13657.588673 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13657.588673 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13657.588673 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2603 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 511.577738 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3973841 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3973841 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3973841 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3973841 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3973841 # number of overall hits +system.cpu0.icache.overall_hits::total 3973841 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 437728 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 437728 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 437728 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 437728 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 437728 # number of overall misses +system.cpu0.icache.overall_misses::total 437728 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5954762997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5954762997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5954762997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5954762997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5954762997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5954762997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4411569 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4411569 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4411569 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4411569 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4411569 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4411569 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099223 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.099223 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099223 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.099223 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099223 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.099223 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13603.797328 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13603.797328 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13603.797328 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13603.797328 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13603.797328 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13603.797328 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2654 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.133721 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.430556 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31940 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31940 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31940 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31940 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31940 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31940 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 397120 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 397120 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 397120 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 397120 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 397120 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 397120 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4781055496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4781055496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4781055496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4781055496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4781055496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4781055496 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32567 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 32567 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 32567 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 32567 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 32567 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 32567 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405161 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 405161 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 405161 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 405161 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 405161 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 405161 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4858454497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4858454497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4858454497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4858454497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4858454497 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4858454497 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8271000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8271000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8271000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 8271000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091434 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.091434 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.091434 # 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mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091841 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.091841 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11991.416985 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11991.416985 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11991.416985 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # 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Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.672384 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 50121000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 460.505640 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.899425 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.899425 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5832717 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5832717 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3162819 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3162819 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174349 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174349 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171411 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178875 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 178875 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10966722 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10966722 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10966722 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10966722 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062572 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062572 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333397 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333397 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048095 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048095 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.041727 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.041727 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179742 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.179742 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179742 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.179742 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13820.410506 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13820.410506 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40802.535154 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40802.535154 # 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number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 95 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.293103 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 38.347368 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 476.472696 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.930611 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.930611 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5934886 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5934886 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3237835 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3237835 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174610 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174610 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171576 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171576 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9172721 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9172721 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9172721 # number of overall hits +system.cpu0.dcache.overall_hits::total 9172721 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 390009 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 390009 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1580289 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1580289 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7755 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7755 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1970298 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1970298 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1970298 # number of overall misses +system.cpu0.dcache.overall_misses::total 1970298 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5381478000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5381478000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 64293852363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 64293852363 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88752000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88752000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 73359500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 73359500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 69675330363 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 69675330363 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 69675330363 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 69675330363 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6324895 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6324895 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818124 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4818124 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183513 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183513 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179331 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 179331 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11143019 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11143019 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11143019 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11143019 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.061663 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.061663 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327988 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.327988 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048514 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048514 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043244 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043244 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.176819 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.176819 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.176819 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.176819 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13798.343115 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13798.343115 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40684.869896 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40684.869896 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.774570 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.774570 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9459.638943 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9459.638943 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35362.838699 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35362.838699 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35362.838699 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35362.838699 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7486 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3477 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 556 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 90 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.464029 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 38.633333 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256563 # number of writebacks -system.cpu0.dcache.writebacks::total 256563 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201019 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 201019 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451459 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1451459 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 444 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 444 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1652478 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1652478 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1652478 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1652478 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188305 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188305 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130403 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130403 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8365 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8365 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7460 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7460 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318708 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318708 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318708 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318708 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2330576500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2330576500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4457768490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4457768490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67402500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67402500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50994500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50994500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6788344990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6788344990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6788344990 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6788344990 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13509879500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13509879500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1216585395 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1216585395 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14726464895 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14726464895 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030264 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030264 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027484 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027484 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045671 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045671 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.041705 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.041705 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029061 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029061 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029061 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029061 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12376.604445 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12376.604445 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34184.554727 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34184.554727 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8057.680813 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8057.680813 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6835.723861 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6835.723861 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21299.575128 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21299.575128 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21299.575128 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21299.575128 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255914 # number of writebacks +system.cpu0.dcache.writebacks::total 255914 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200897 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 200897 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449259 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1449259 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 477 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 477 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1650156 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1650156 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1650156 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1650156 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189112 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189112 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131030 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131030 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8426 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8426 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7752 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7752 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320142 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320142 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320142 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320142 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2327531500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2327531500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4469430491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4469430491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67004000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67004000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 57855500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 57855500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6796961991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6796961991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6796961991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6796961991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13432598000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13432598000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1289898395 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1289898395 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14722496395 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14722496395 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029900 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029900 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027195 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027195 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045915 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045915 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043227 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043227 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028730 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028730 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028730 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028730 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12307.688037 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12307.688037 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34109.978562 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34109.978562 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7952.053169 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.053169 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7463.299794 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7463.299794 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21231.084928 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21231.084928 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21231.084928 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21231.084928 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1077,27 +1077,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43128318 # DTB read hits -system.cpu1.dtb.read_misses 43709 # DTB read misses -system.cpu1.dtb.write_hits 6848528 # DTB write hits -system.cpu1.dtb.write_misses 11704 # DTB write misses +system.cpu1.dtb.read_hits 43411799 # DTB read hits +system.cpu1.dtb.read_misses 44882 # DTB read misses +system.cpu1.dtb.write_hits 7014123 # DTB write hits +system.cpu1.dtb.write_misses 11858 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3032 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 376 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2347 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3336 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 317 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 614 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43172027 # DTB read accesses -system.cpu1.dtb.write_accesses 6860232 # DTB write accesses +system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43456681 # DTB read accesses +system.cpu1.dtb.write_accesses 7025981 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49976846 # DTB hits -system.cpu1.dtb.misses 55413 # DTB misses -system.cpu1.dtb.accesses 50032259 # DTB accesses -system.cpu1.itb.inst_hits 9000425 # ITB inst hits -system.cpu1.itb.inst_misses 6008 # ITB inst misses +system.cpu1.dtb.hits 50425922 # DTB hits +system.cpu1.dtb.misses 56740 # DTB misses +system.cpu1.dtb.accesses 50482662 # DTB accesses +system.cpu1.itb.inst_hits 9129638 # ITB inst hits +system.cpu1.itb.inst_misses 6055 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1106,122 +1106,122 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1553 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1576 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1639 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1653 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9006433 # ITB inst accesses -system.cpu1.itb.hits 9000425 # DTB hits -system.cpu1.itb.misses 6008 # DTB misses -system.cpu1.itb.accesses 9006433 # DTB accesses -system.cpu1.numCycles 411196854 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9135693 # ITB inst accesses +system.cpu1.itb.hits 9129638 # DTB hits +system.cpu1.itb.misses 6055 # DTB misses +system.cpu1.itb.accesses 9135693 # DTB accesses +system.cpu1.numCycles 413048277 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9419862 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7750034 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 456519 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6563236 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5515830 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9610060 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7888453 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 467347 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6680212 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5602853 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 808543 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 49558 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 20407169 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 70137907 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9419862 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6324373 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14954252 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4469714 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 69962 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78537497 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4608 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 48031 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 137349 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 105 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8998373 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 846947 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3472 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 117207584 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.722166 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.072596 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 834872 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 50683 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 20902821 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 71155819 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9610060 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6437725 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 15200148 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4519747 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 75962 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 79085155 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 48956 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 142448 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9127576 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 837727 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3443 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 118542872 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.725366 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076680 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 102261187 87.25% 87.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 819653 0.70% 87.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 985556 0.84% 88.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2033886 1.74% 90.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1605966 1.37% 91.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 588504 0.50% 92.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2242580 1.91% 94.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 432923 0.37% 94.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6237329 5.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 103350754 87.18% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 840912 0.71% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1013712 0.86% 88.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2056350 1.73% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1628340 1.37% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 605586 0.51% 92.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2262195 1.91% 94.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 445115 0.38% 94.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6339908 5.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 117207584 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022908 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.170570 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 22086254 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78170196 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13474165 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 527031 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2949938 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1142917 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 100567 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 79224649 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 333390 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2949938 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 23604711 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32726720 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41122515 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12389079 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4414621 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 72870010 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19270 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 676690 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3162757 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33999 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 77285870 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 335898709 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 335839792 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58917 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49079142 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28206728 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 460869 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 403889 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7994466 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13706939 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8341114 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1036889 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1489334 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 65799753 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1184242 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 90434427 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 105475 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18495331 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52692216 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 284904 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 117207584 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.771575 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.509324 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 118542872 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.023266 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.172270 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 22607772 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78712094 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13698658 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 543937 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2980411 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1178240 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102814 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 80488884 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 342985 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2980411 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 24131061 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32829819 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41497762 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12625753 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4478066 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 74194515 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19311 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 694411 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3187694 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 34028 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 78612274 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 341980095 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 341920829 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50181552 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28430722 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 479709 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 419295 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8182404 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13956070 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8535310 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1073815 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1496663 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 66987245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1207542 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 91662010 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 107326 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18596353 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52788554 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 287891 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 118542872 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.773239 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.509704 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 86216438 73.56% 73.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8629120 7.36% 80.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4443515 3.79% 84.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3900369 3.33% 88.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10705508 9.13% 97.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1918417 1.64% 98.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1028985 0.88% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 292713 0.25% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 72519 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 87045508 73.43% 73.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8827320 7.45% 80.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4565356 3.85% 84.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3971386 3.35% 88.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10748062 9.07% 97.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1958505 1.65% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1059536 0.89% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 289761 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 77438 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 117207584 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 118542872 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 27077 0.34% 0.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 994 0.01% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 27804 0.35% 0.35% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 991 0.01% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available @@ -1249,399 +1249,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7551420 96.03% 96.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 284170 3.61% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7575099 95.91% 96.28% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 294066 3.72% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313737 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 38536009 42.61% 42.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59463 0.07% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 3 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1448 0.00% 43.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.03% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44313821 49.00% 92.03% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7209923 7.97% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 39285679 42.86% 43.20% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61425 0.07% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.27% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44600762 48.66% 91.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7398685 8.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 90434427 # Type of FU issued -system.cpu1.iq.rate 0.219930 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7863661 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.086954 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 306085964 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 85487883 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54343960 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14808 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8052 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6813 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 97976579 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7772 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 344186 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 91662010 # Type of FU issued +system.cpu1.iq.rate 0.221916 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7897960 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.086164 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 309913949 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 86800137 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 55536555 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14796 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 99238492 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7741 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 357612 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3955729 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4256 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17131 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1493245 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3966417 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4317 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17649 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1516764 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31918877 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1021818 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31964885 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1028430 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2949938 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24820563 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 368762 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 67089139 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 132396 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13706939 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8341114 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 882128 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65563 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3455 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17131 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 238596 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 168339 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 406935 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87595702 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43496570 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2838725 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2980411 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24884610 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 372296 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 68300564 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 134907 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13956070 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8535310 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 896808 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 67508 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3396 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17649 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 244559 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 171299 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 415858 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 88842251 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43794323 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2819759 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105144 # number of nop insts executed -system.cpu1.iew.exec_refs 50630638 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7094868 # Number of branches executed -system.cpu1.iew.exec_stores 7134068 # Number of stores executed -system.cpu1.iew.exec_rate 0.213026 # Inst execution rate -system.cpu1.iew.wb_sent 86451134 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54350773 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30183399 # num instructions producing a value -system.cpu1.iew.wb_consumers 53726330 # num instructions consuming a value +system.cpu1.iew.exec_nop 105777 # number of nop insts executed +system.cpu1.iew.exec_refs 51113945 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7256967 # Number of branches executed +system.cpu1.iew.exec_stores 7319622 # Number of stores executed +system.cpu1.iew.exec_rate 0.215089 # Inst execution rate +system.cpu1.iew.wb_sent 87693649 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 55543356 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30809625 # num instructions producing a value +system.cpu1.iew.wb_consumers 54951337 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.132177 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.561799 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.134472 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560671 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 18453809 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899338 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 357846 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 114304625 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.421644 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.382099 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 18558974 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 919651 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 366370 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 115610884 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.426428 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.387814 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 97479553 85.28% 85.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8276936 7.24% 92.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2163829 1.89% 94.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1249082 1.09% 95.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1246649 1.09% 96.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 573488 0.50% 97.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1001794 0.88% 97.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 527131 0.46% 98.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1786163 1.56% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 98380656 85.10% 85.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8456019 7.31% 92.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2240447 1.94% 94.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1287846 1.11% 95.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1284560 1.11% 96.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 584416 0.51% 97.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1022455 0.88% 97.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 531646 0.46% 98.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1822839 1.58% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 114304625 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38098697 # Number of instructions committed -system.cpu1.commit.committedOps 48195861 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 115610884 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38938330 # Number of instructions committed +system.cpu1.commit.committedOps 49299735 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16599079 # Number of memory references committed -system.cpu1.commit.loads 9751210 # Number of loads committed -system.cpu1.commit.membars 196398 # Number of memory barriers committed -system.cpu1.commit.branches 5978782 # Number of branches committed +system.cpu1.commit.refs 17008199 # Number of memory references committed +system.cpu1.commit.loads 9989653 # Number of loads committed +system.cpu1.commit.membars 202304 # Number of memory barriers committed +system.cpu1.commit.branches 6136573 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42713997 # Number of committed integer instructions. -system.cpu1.commit.function_calls 536442 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1786163 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43691789 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556207 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1822839 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 178079063 # The number of ROB reads -system.cpu1.rob.rob_writes 136331127 # The number of ROB writes -system.cpu1.timesIdled 1409981 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 293989270 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1596154251 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38029058 # Number of Instructions Simulated -system.cpu1.committedOps 48126222 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38029058 # Number of Instructions Simulated -system.cpu1.cpi 10.812702 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.812702 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092484 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092484 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391789649 # number of integer regfile reads -system.cpu1.int_regfile_writes 57184516 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4895 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes -system.cpu1.misc_regfile_reads 89371872 # number of misc regfile reads -system.cpu1.misc_regfile_writes 414539 # number of misc regfile writes -system.cpu1.icache.replacements 604043 # number of replacements -system.cpu1.icache.tagsinuse 477.396851 # Cycle average of tags in use -system.cpu1.icache.total_refs 8346622 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 604555 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.806224 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 180532357 # The number of ROB reads +system.cpu1.rob.rob_writes 138785705 # The number of ROB writes +system.cpu1.timesIdled 1423841 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294505405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4793867333 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38868691 # Number of Instructions Simulated +system.cpu1.committedOps 49230096 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38868691 # Number of Instructions Simulated +system.cpu1.cpi 10.626761 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.626761 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.094102 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.094102 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 397649399 # number of integer regfile reads +system.cpu1.int_regfile_writes 58356680 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4927 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes +system.cpu1.misc_regfile_reads 90861332 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429704 # number of misc regfile writes +system.cpu1.icache.replacements 621691 # number of replacements +system.cpu1.icache.tagsinuse 498.705536 # Cycle average of tags in use +system.cpu1.icache.total_refs 8457096 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 622203 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.592181 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74944474500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 477.396851 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.932416 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.932416 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8346622 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8346622 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8346622 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8346622 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8346622 # number of overall hits -system.cpu1.icache.overall_hits::total 8346622 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 651698 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 651698 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 651698 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 651698 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 651698 # number of overall misses -system.cpu1.icache.overall_misses::total 651698 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8706583495 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8706583495 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8706583495 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8706583495 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8706583495 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8706583495 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8998320 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8998320 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8998320 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8998320 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8998320 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8998320 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072424 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.072424 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072424 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.072424 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072424 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.072424 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13359.843816 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13359.843816 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13359.843816 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13359.843816 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13359.843816 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13359.843816 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1860 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 498.705536 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974034 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974034 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8457096 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8457096 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8457096 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8457096 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8457096 # number of overall hits +system.cpu1.icache.overall_hits::total 8457096 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 670427 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 670427 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 670427 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 670427 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 670427 # number of overall misses +system.cpu1.icache.overall_misses::total 670427 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8963788993 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8963788993 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8963788993 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8963788993 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8963788993 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8963788993 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9127523 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9127523 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9127523 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9127523 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9127523 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9127523 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073451 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.073451 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073451 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.073451 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073451 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.073451 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13370.268490 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13370.268490 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13370.268490 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13370.268490 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13370.268490 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13370.268490 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 164 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.341463 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.184211 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47118 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 47118 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 47118 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 47118 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 47118 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 47118 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 604580 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 604580 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 604580 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 604580 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 604580 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 604580 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7117577996 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7117577996 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7117577996 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7117577996 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7117577996 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7117577996 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48189 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 48189 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 48189 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 48189 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 48189 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 48189 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622238 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 622238 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 622238 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 622238 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 622238 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 622238 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328903994 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328903994 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328903994 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7328903994 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328903994 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7328903994 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3208500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3208500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3208500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3208500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067188 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067188 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.067188 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11772.764557 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11772.764557 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11772.764557 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068172 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.068172 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.068172 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11778.297041 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11778.297041 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11778.297041 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 360631 # number of replacements -system.cpu1.dcache.tagsinuse 472.241123 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12789913 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 361011 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.428042 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 363699 # number of replacements +system.cpu1.dcache.tagsinuse 487.062362 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13149394 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 364069 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.117862 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 71012585000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 472.241123 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.922346 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.922346 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8401496 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8401496 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4150430 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4150430 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 102060 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 102060 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 98301 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 98301 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12551926 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12551926 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12551926 # number of overall hits -system.cpu1.dcache.overall_hits::total 12551926 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 394540 # 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number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5828870500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56343693023 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 56343693023 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129108000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129108000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 64979500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 64979500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 62172563523 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 62172563523 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 62172563523 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 62172563523 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8796036 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8796036 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5701491 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5701491 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116114 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 116114 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108883 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 108883 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14497527 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14497527 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14497527 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14497527 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044854 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.044854 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272045 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.272045 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121036 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121036 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097187 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097187 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134202 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134202 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134202 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134202 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.839154 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.839154 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36325.904025 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 36325.904025 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9186.566102 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9186.566102 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6140.568891 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6140.568891 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31955.454136 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 31955.454136 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31955.454136 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 31955.454136 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 23777 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 10847 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3216 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.393346 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 66.956790 # average number of cycles each access was blocked +system.cpu1.dcache.occ_blocks::cpu1.data 487.062362 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951294 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951294 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8615849 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8615849 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4289025 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4289025 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104659 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 104659 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100738 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 100738 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12904874 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12904874 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12904874 # number of overall hits +system.cpu1.dcache.overall_hits::total 12904874 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 398775 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 398775 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1559814 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1559814 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14251 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14251 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10935 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10935 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1958589 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1958589 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1958589 # number of overall misses +system.cpu1.dcache.overall_misses::total 1958589 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5911762000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5911762000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56390406018 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 56390406018 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131021000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131021000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 76240500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 76240500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 62302168018 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 62302168018 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 62302168018 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 62302168018 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9014624 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9014624 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848839 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5848839 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 118910 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 118910 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111673 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 111673 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14863463 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14863463 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14863463 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14863463 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044236 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044236 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.266688 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.266688 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119847 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119847 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131772 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.131772 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131772 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.131772 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14824.805968 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14824.805968 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36152.006597 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 36152.006597 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9193.810961 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9193.810961 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6972.153635 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6972.153635 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31809.720170 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 31809.720170 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31809.720170 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 31809.720170 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 24015 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 11108 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3240 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.412037 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 66.119048 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 325044 # number of writebacks -system.cpu1.dcache.writebacks::total 325044 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 165979 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 165979 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1389692 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1389692 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1430 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1430 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1555671 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1555671 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1555671 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1555671 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228561 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228561 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161369 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161369 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12624 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12624 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10579 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10579 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389930 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389930 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389930 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389930 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2788566500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2788566500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5142243728 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5142243728 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88146000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88146000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43823500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43823500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7930810228 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7930810228 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7930810228 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7930810228 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168983572500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168983572500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40847570579 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40847570579 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 209831143079 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 209831143079 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025985 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025985 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028303 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028303 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108721 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108721 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097159 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097159 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026896 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026896 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026896 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026896 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12200.535087 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12200.535087 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31866.366700 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31866.366700 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6982.414449 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6982.414449 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4142.499291 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4142.499291 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20339.061442 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20339.061442 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20339.061442 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20339.061442 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 328533 # number of writebacks +system.cpu1.dcache.writebacks::total 328533 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 166830 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 166830 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1397003 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1397003 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1431 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1431 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1563833 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1563833 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1563833 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1563833 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231945 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231945 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162811 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162811 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12820 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12820 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10928 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10928 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394756 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394756 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394756 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394756 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2840785000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2840785000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5178833227 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5178833227 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89705500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89705500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 54384500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 54384500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8019618227 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8019618227 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8019618227 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8019618227 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169259240500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169259240500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40718348836 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40718348836 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 209977589336 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 209977589336 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025730 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025730 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027836 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027836 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107813 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107813 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097857 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097857 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026559 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026559 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026559 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026559 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12247.666473 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12247.666473 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31808.865660 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31808.865660 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6997.308892 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6997.308892 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4976.619693 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4976.619693 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20315.380202 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20315.380202 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20315.380202 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20315.380202 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1663,18 +1659,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479854932995 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 479854932995 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479854932995 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 479854932995 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1218779341193 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1218779341193 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43104 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43799 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 52217 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53911 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 9bc6eb181..c4b901e8a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534230 # Number of seconds simulated -sim_ticks 2534229746000 # Number of ticks simulated -final_tick 2534229746000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534173 # Number of seconds simulated +sim_ticks 2534173219000 # Number of ticks simulated +final_tick 2534173219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72788 # Simulator instruction rate (inst/s) -host_op_rate 93626 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3043970352 # Simulator tick rate (ticks/s) -host_mem_usage 380668 # Number of bytes of host memory used -host_seconds 832.54 # Real time elapsed on the host -sim_insts 60598794 # Number of instructions simulated -sim_ops 77947430 # Number of ops (including micro ops) simulated +host_inst_rate 83771 # Simulator instruction rate (inst/s) +host_op_rate 107754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3503174864 # Simulator tick rate (ticks/s) +host_mem_usage 385312 # Number of bytes of host memory used +host_seconds 723.39 # Real time elapsed on the host +sim_insts 60599410 # Number of instructions simulated +sim_ops 77948210 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095568 # Number of bytes read from this memory -system.physmem.bytes_read::total 129434640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 798080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9096016 # Number of bytes read from this memory +system.physmem.bytes_read::total 129435344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142152 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096882 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12470 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142159 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096893 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47169229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1313 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47170281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1389 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51074548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493383 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683517 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47169229 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51075966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314927 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314927 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493669 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190160 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683829 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47170281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1389 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4779219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53758065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4779503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53759795 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -69,27 +69,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51729015 # DTB read hits -system.cpu.dtb.read_misses 77642 # DTB read misses -system.cpu.dtb.write_hits 11810988 # DTB write hits -system.cpu.dtb.write_misses 17459 # DTB write misses +system.cpu.dtb.read_hits 51719750 # DTB read hits +system.cpu.dtb.read_misses 77229 # DTB read misses +system.cpu.dtb.write_hits 11809411 # DTB write hits +system.cpu.dtb.write_misses 17373 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2642 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4263 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2639 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51806657 # DTB read accesses -system.cpu.dtb.write_accesses 11828447 # DTB write accesses +system.cpu.dtb.perms_faults 1315 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51796979 # DTB read accesses +system.cpu.dtb.write_accesses 11826784 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63540003 # DTB hits -system.cpu.dtb.misses 95101 # DTB misses -system.cpu.dtb.accesses 63635104 # DTB accesses -system.cpu.itb.inst_hits 13083995 # ITB inst hits -system.cpu.itb.inst_misses 12083 # ITB inst misses +system.cpu.dtb.hits 63529161 # DTB hits +system.cpu.dtb.misses 94602 # DTB misses +system.cpu.dtb.accesses 63623763 # DTB accesses +system.cpu.itb.inst_hits 13045523 # ITB inst hits +system.cpu.itb.inst_misses 12142 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -98,121 +98,121 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2591 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2586 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3112 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3109 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13096078 # ITB inst accesses -system.cpu.itb.hits 13083995 # DTB hits -system.cpu.itb.misses 12083 # DTB misses -system.cpu.itb.accesses 13096078 # DTB accesses -system.cpu.numCycles 475967538 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13057665 # ITB inst accesses +system.cpu.itb.hits 13045523 # DTB hits +system.cpu.itb.misses 12142 # DTB misses +system.cpu.itb.accesses 13057665 # DTB accesses +system.cpu.numCycles 475815628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15172784 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12163693 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783478 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10392072 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8320250 # Number of BTB hits +system.cpu.BPredUnit.lookups 15155227 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12146705 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783529 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10394615 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8308125 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454874 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82640 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31374160 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 100930999 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15172784 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9775124 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22189039 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5936170 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 131560 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 97680943 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 99805 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208737 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 364 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13080141 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1016234 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6355 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155765235 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.799529 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.166844 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454278 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82490 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31347726 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 100822937 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15155227 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9762403 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22167713 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5923551 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 130252 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97680521 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2843 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 98238 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209120 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13041690 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1002552 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6432 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155704074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.799073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.166371 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133592933 85.77% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382764 0.89% 86.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755577 1.13% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2658359 1.71% 89.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2327487 1.49% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1136384 0.73% 91.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2915896 1.87% 93.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 784165 0.50% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9211670 5.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133553129 85.77% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1381799 0.89% 86.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1755926 1.13% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2652519 1.70% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2328486 1.50% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1136180 0.73% 91.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2905092 1.87% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 785179 0.50% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9205764 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155765235 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031878 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.212054 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33515539 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 97301422 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20013824 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1028268 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3906182 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2022458 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174763 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 117645711 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 578390 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3906182 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35614317 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37590587 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53594123 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18875472 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6184554 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110140296 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21341 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015182 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4143290 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 32170 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 114983026 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 504387694 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 504296628 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91066 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78733405 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36249620 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 891466 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797109 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12509806 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21006076 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13841580 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1961226 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2453000 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 100941360 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2057614 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126221061 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189445 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24437015 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65086313 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 513058 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155765235 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.810329 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523325 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155704074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031851 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.211895 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33480524 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97304946 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19992509 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1030333 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3895762 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2022425 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174533 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 117498058 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 576273 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3895762 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35565671 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37584641 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53601603 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18869314 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6187083 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110088875 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21357 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1014287 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4146063 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32391 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 114923514 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 504161217 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 504070393 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78734130 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36189383 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 892416 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 798033 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12508562 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20972747 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13834973 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1961849 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2465756 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 100830951 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2058696 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126177528 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189533 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24329335 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 64639752 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514100 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155704074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.810368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523012 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 110569920 70.98% 70.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13988875 8.98% 79.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7307591 4.69% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6076063 3.90% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12752921 8.19% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2780626 1.79% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1679008 1.08% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 481895 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128336 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 110503842 70.97% 70.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14006844 9.00% 79.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7305691 4.69% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6085046 3.91% 88.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12721239 8.17% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2798387 1.80% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1680857 1.08% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 475213 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126955 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155765235 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155704074 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57759 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57592 0.65% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available @@ -241,13 +241,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370724 94.64% 95.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 416242 4.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370496 94.62% 95.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 418270 4.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59912166 47.47% 47.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95497 0.08% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59895243 47.47% 47.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95317 0.08% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued @@ -260,11 +260,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 7 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued @@ -273,363 +273,363 @@ system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Ty system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53392141 42.30% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12455427 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53367566 42.30% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12453578 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126221061 # Type of FU issued -system.cpu.iq.rate 0.265188 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8844727 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070073 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417312910 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127452442 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87180232 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23310 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12552 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134689743 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12379 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 626582 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126177528 # Type of FU issued +system.cpu.iq.rate 0.265182 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8846360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070110 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417165828 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127235505 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87177257 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23405 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134647760 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12462 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624931 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5289586 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7312 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30140 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2042757 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5256081 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7285 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30200 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2036035 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34106883 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1034668 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34106907 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1030049 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3906182 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28670725 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 450645 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103223935 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 233802 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21006076 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13841580 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1466072 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114504 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3680 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30140 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 409816 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293009 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 702825 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122971529 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52416599 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3249532 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3895762 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28674144 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 449674 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103114750 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 233495 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20972747 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13834973 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466916 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113563 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3765 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30200 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409921 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 292907 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 702828 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122963273 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52407414 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3214255 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224961 # number of nop insts executed -system.cpu.iew.exec_refs 64739842 # number of memory reference insts executed -system.cpu.iew.exec_branches 11733959 # Number of branches executed -system.cpu.iew.exec_stores 12323243 # Number of stores executed -system.cpu.iew.exec_rate 0.258361 # Inst execution rate -system.cpu.iew.wb_sent 121621677 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87190526 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47712664 # num instructions producing a value -system.cpu.iew.wb_consumers 88871095 # num instructions consuming a value +system.cpu.iew.exec_nop 225103 # number of nop insts executed +system.cpu.iew.exec_refs 64729141 # number of memory reference insts executed +system.cpu.iew.exec_branches 11726228 # Number of branches executed +system.cpu.iew.exec_stores 12321727 # Number of stores executed +system.cpu.iew.exec_rate 0.258426 # Inst execution rate +system.cpu.iew.wb_sent 121618308 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87187548 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47710631 # num instructions producing a value +system.cpu.iew.wb_consumers 88857501 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.183186 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536875 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183238 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24296365 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544556 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 611758 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151941485 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.513999 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.495079 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24186815 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544596 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612016 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151890748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.495245 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 124150656 81.71% 81.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13572481 8.93% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3978264 2.62% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2132059 1.40% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949397 1.28% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 999089 0.66% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1584839 1.04% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727042 0.48% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2847658 1.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 124092082 81.70% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13579714 8.94% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3980091 2.62% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2134436 1.41% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949184 1.28% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1000796 0.66% 96.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1579621 1.04% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 721647 0.48% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2853177 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151941485 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60749175 # Number of instructions committed -system.cpu.commit.committedOps 78097811 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151890748 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60749791 # Number of instructions committed +system.cpu.commit.committedOps 78098591 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27515313 # Number of memory references committed -system.cpu.commit.loads 15716490 # Number of loads committed -system.cpu.commit.membars 413125 # Number of memory barriers committed -system.cpu.commit.branches 10023277 # Number of branches committed +system.cpu.commit.refs 27515604 # Number of memory references committed +system.cpu.commit.loads 15716666 # Number of loads committed +system.cpu.commit.membars 413138 # Number of memory barriers committed +system.cpu.commit.branches 10023383 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69136099 # Number of committed integer instructions. -system.cpu.commit.function_calls 996018 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2847658 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69136784 # Number of committed integer instructions. +system.cpu.commit.function_calls 996034 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2853177 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 249572720 # The number of ROB reads -system.cpu.rob.rob_writes 208783952 # The number of ROB writes -system.cpu.timesIdled 1774345 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320202303 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592403923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60598794 # Number of Instructions Simulated -system.cpu.committedOps 77947430 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60598794 # Number of Instructions Simulated -system.cpu.cpi 7.854406 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.854406 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556725625 # number of integer regfile reads -system.cpu.int_regfile_writes 89967060 # number of integer regfile writes -system.cpu.fp_regfile_reads 8371 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 133111894 # number of misc regfile reads -system.cpu.misc_regfile_writes 912902 # number of misc regfile writes -system.cpu.icache.replacements 989535 # number of replacements -system.cpu.icache.tagsinuse 511.594104 # Cycle average of tags in use -system.cpu.icache.total_refs 12006884 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990047 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.127590 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 249407638 # The number of ROB reads +system.cpu.rob.rob_writes 208557399 # The number of ROB writes +system.cpu.timesIdled 1773714 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320111554 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592442776 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60599410 # Number of Instructions Simulated +system.cpu.committedOps 77948210 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60599410 # Number of Instructions Simulated +system.cpu.cpi 7.851819 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.851819 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127359 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127359 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556670718 # number of integer regfile reads +system.cpu.int_regfile_writes 89963165 # number of integer regfile writes +system.cpu.fp_regfile_reads 8373 # number of floating regfile reads +system.cpu.fp_regfile_writes 2910 # number of floating regfile writes +system.cpu.misc_regfile_reads 132949410 # number of misc regfile reads +system.cpu.misc_regfile_writes 912934 # number of misc regfile writes +system.cpu.icache.replacements 989799 # number of replacements +system.cpu.icache.tagsinuse 511.593898 # Cycle average of tags in use +system.cpu.icache.total_refs 11967809 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990311 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.084900 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.594104 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.593898 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12006884 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12006884 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12006884 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12006884 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12006884 # number of overall hits -system.cpu.icache.overall_hits::total 12006884 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1073125 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1073125 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1073125 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1073125 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1073125 # number of overall misses -system.cpu.icache.overall_misses::total 1073125 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14103457490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14103457490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14103457490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14103457490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14103457490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14103457490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13080009 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13080009 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13080009 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13080009 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13080009 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13080009 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082043 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082043 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082043 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082043 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082043 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082043 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13142.418162 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13142.418162 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13142.418162 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13142.418162 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13142.418162 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4497 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11967809 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11967809 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11967809 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11967809 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11967809 # number of overall hits +system.cpu.icache.overall_hits::total 11967809 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1073749 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1073749 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1073749 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1073749 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1073749 # number of overall misses +system.cpu.icache.overall_misses::total 1073749 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14109467991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14109467991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14109467991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14109467991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14109467991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14109467991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13041558 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13041558 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13041558 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13041558 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13041558 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13041558 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082333 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082333 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082333 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082333 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082333 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082333 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13140.378236 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13140.378236 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13140.378236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13140.378236 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4599 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 306 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.244068 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.029412 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83043 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 83043 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 83043 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 83043 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 83043 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 83043 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990082 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 990082 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 990082 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 990082 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 990082 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 990082 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11447874492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11447874492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11447874492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11447874492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11447874492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11447874492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83395 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 83395 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 83395 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 83395 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 83395 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 83395 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990354 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 990354 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 990354 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 990354 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 990354 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 990354 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11451236993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11451236993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11451236993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11451236993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11451236993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11451236993 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7934000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7934000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7934000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075694 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075694 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075694 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075694 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.551882 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.551882 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.551882 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.551882 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075938 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075938 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075938 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075938 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.771487 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.771487 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.771487 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.771487 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645234 # number of replacements -system.cpu.dcache.tagsinuse 511.991712 # Cycle average of tags in use -system.cpu.dcache.total_refs 21791132 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645746 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.745671 # Average number of references to valid blocks. +system.cpu.dcache.replacements 645297 # number of replacements +system.cpu.dcache.tagsinuse 511.991711 # Cycle average of tags in use +system.cpu.dcache.total_refs 21788102 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645809 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.737687 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.991711 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13929737 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13929737 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7288383 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7288383 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 284164 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 284164 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21218120 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21218120 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21218120 # number of overall hits -system.cpu.dcache.overall_hits::total 21218120 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 727325 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 727325 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962578 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13599 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3689903 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3689903 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3689903 # number of overall misses -system.cpu.dcache.overall_misses::total 3689903 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441506500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9441506500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104195765238 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104195765238 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181224000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 181224000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 305500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113637271738 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113637271738 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113637271738 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113637271738 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14657062 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14657062 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250961 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250961 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297763 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297763 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285742 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285742 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24908023 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24908023 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24908023 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24908023 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049623 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049623 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289005 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289005 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045671 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045671 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000049 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000049 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148141 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148141 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148141 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12981.138418 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12981.138418 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35170.640313 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35170.640313 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.273991 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.273991 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21821.428571 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21821.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30796.818165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30796.818165 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25623 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15683 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2532 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.119668 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.211470 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13926305 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13926305 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7288115 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7288115 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284783 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284783 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21214420 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21214420 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21214420 # number of overall hits +system.cpu.dcache.overall_hits::total 21214420 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 727409 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 727409 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962946 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962946 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13565 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13565 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3690355 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3690355 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3690355 # number of overall misses +system.cpu.dcache.overall_misses::total 3690355 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9441109500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9441109500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104189875245 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104189875245 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180817000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180817000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 318500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 318500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113630984745 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113630984745 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113630984745 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113630984745 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14653714 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14653714 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10251061 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10251061 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 298348 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 298348 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285754 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285754 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24904775 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24904775 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24904775 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24904775 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049640 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049640 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289038 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289038 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045467 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045467 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000052 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000052 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148179 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148179 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148179 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148179 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12979.093605 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12979.093605 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35164.284211 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35164.284211 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13329.671950 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13329.671950 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21233.333333 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21233.333333 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30791.342498 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30791.342498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30791.342498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30791.342498 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25421 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15604 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2521 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.083697 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.948905 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609265 # number of writebacks -system.cpu.dcache.writebacks::total 609265 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339927 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 339927 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713517 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713517 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1356 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1356 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3053444 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3053444 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3053444 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3053444 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387398 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387398 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249061 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249061 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12243 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12243 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636459 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636459 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636459 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636459 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4758834000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4758834000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8540298916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8540298916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141913000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141913000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13299132916 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13299132916 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13299132916 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13299132916 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407357500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407357500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42045203371 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42045203371 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224452560871 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224452560871 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024296 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024296 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041117 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041117 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000049 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000049 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025552 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12284.095426 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12284.095426 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.988862 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.988862 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11591.358327 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11591.358327 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19821.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19821.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609382 # number of writebacks +system.cpu.dcache.writebacks::total 609382 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339956 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 339956 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713832 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713832 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1350 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1350 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3053788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3053788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3053788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3053788 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387453 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387453 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249114 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249114 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12215 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12215 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636567 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636567 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636567 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636567 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4759977000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4759977000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8542104919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8542104919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141597500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141597500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 288500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 288500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13302081919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13302081919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13302081919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13302081919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356244500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356244500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41726674069 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41726674069 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224082918569 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224082918569 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026441 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026441 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024301 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024301 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040942 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040942 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000052 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025560 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025560 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025560 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025560 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12285.301701 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12285.301701 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.943235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.943235 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11592.099877 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11592.099877 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19233.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19233.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.593633 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.593633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.593633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.593633 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -637,149 +637,149 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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Cycle average of tags in use +system.cpu.l2cache.total_refs 1928116 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129809 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.853485 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498979146000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36881.759655 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 43.531667 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8182.264424 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6241.498349 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.562797 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000650 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40144.230769 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41042.817791 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40270.662422 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40331.664039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -914,16 +914,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307562103462 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307562103462 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1202929249396 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1202929249396 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88032 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88035 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 0a013f420..db4dfffca 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,320 +1,320 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.203695 # Number of seconds simulated -sim_ticks 1203694548000 # Number of ticks simulated -final_tick 1203694548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.203606 # Number of seconds simulated +sim_ticks 1203606499000 # Number of ticks simulated +final_tick 1203606499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 610810 # Simulator instruction rate (inst/s) -host_op_rate 778429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11963163223 # Simulator tick rate (ticks/s) -host_mem_usage 383784 # Number of bytes of host memory used -host_seconds 100.62 # Real time elapsed on the host -sim_insts 61457649 # Number of instructions simulated -sim_ops 78322983 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 418240 # Simulator instruction rate (inst/s) +host_op_rate 532998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8191230777 # Simulator tick rate (ticks/s) +host_mem_usage 386340 # Number of bytes of host memory used +host_seconds 146.94 # Real time elapsed on the host +sim_insts 61455549 # Number of instructions simulated +sim_ops 78317886 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 354404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 354084 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 364636 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5307760 # Number of bytes read from this memory -system.physmem.bytes_read::total 62191012 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 354404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 364636 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 364956 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5307824 # Number of bytes read from this memory +system.physmem.bytes_read::total 62191076 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 354084 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 364956 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4163840 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4163904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7191184 # Number of bytes written to this memory +system.physmem.bytes_written::total 7191248 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11751 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82960 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6655189 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65060 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82961 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6655190 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65061 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821896 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43120999 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821897 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43124154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 294430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3538482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 294186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3538741 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 302931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4409557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51666772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 294430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 302931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597361 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3459216 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14123 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2500920 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5974260 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3459216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43120999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 303219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4409933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51670605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 294186 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 303219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3459523 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2501103 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5974750 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3459523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43124154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 294430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3552606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 294186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3552865 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 302931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6910477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57641032 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 70187 # number of replacements -system.l2c.tagsinuse 53228.642974 # Cycle average of tags in use -system.l2c.total_refs 1643789 # Total number of references to valid blocks. -system.l2c.sampled_refs 135350 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.144728 # Average number of references to valid blocks. +system.physmem.bw_total::cpu1.inst 303219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6911036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57645355 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70188 # number of replacements +system.l2c.tagsinuse 53228.072476 # Cycle average of tags in use +system.l2c.total_refs 1643838 # Total number of references to valid blocks. +system.l2c.sampled_refs 135351 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.145001 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40454.040636 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40453.574010 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.003088 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3394.914064 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2735.381228 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.669984 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3118.851455 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3522.782116 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.617280 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.003089 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3394.604865 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2735.402876 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.669960 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3118.943835 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3522.873439 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.617273 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.051802 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.051798 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.047590 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.053753 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.812205 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.047591 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.053755 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.812196 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 278283 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 124654 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5208 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 278308 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 124645 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5210 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 576279 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 223386 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1213325 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571443 # number of Writeback hits -system.l2c.Writeback_hits::total 571443 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 576222 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223363 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1213263 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571562 # number of Writeback hits +system.l2c.Writeback_hits::total 571562 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 888 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1880 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 95 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 286 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 39230 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 70245 # number of ReadExReq hits +system.l2c.UpgradeReq_hits::cpu1.data 878 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1870 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 189 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 285 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 39231 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 70244 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024485 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018151 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801759 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.846817 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.825942 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.774232 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.803313 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784801 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610346 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528823 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.561684 # mshr miss rate for ReadExReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045926 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024492 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018152 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801719 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848254 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.826675 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.775268 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.801653 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784906 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610344 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528826 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.561686 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.109536 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.109541 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.109536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.109541 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40009.498417 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40089.798466 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40070.196166 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.606680 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40029.842942 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.831745 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40003.051908 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40020.615979 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40009.585810 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.813699 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40147.319169 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40087.526994 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40002.833333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40003.655492 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40008.626839 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40012.464971 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40013.447229 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40013.005494 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.299080 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40009.018041 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40004.805769 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.496176 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40004.762820 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.274170 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,9 +498,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 4800541 # DTB read hits +system.cpu0.dtb.read_hits 4800569 # DTB read hits system.cpu0.dtb.read_misses 2116 # DTB read misses -system.cpu0.dtb.write_hits 4101169 # DTB write hits +system.cpu0.dtb.write_hits 4101188 # DTB write hits system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -511,13 +511,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 4802657 # DTB read accesses -system.cpu0.dtb.write_accesses 4101574 # DTB write accesses +system.cpu0.dtb.read_accesses 4802685 # DTB read accesses +system.cpu0.dtb.write_accesses 4101593 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 8901710 # DTB hits +system.cpu0.dtb.hits 8901757 # DTB hits system.cpu0.dtb.misses 2521 # DTB misses -system.cpu0.dtb.accesses 8904231 # DTB accesses -system.cpu0.itb.inst_hits 19425295 # ITB inst hits +system.cpu0.dtb.accesses 8904278 # DTB accesses +system.cpu0.itb.inst_hits 19425317 # ITB inst hits system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 19426645 # ITB inst accesses -system.cpu0.itb.hits 19425295 # DTB hits +system.cpu0.itb.inst_accesses 19426667 # ITB inst accesses +system.cpu0.itb.hits 19425317 # DTB hits system.cpu0.itb.misses 1350 # DTB misses -system.cpu0.itb.accesses 19426645 # DTB accesses -system.cpu0.numCycles 2405961611 # number of cpu cycles simulated +system.cpu0.itb.accesses 19426667 # DTB accesses +system.cpu0.numCycles 2405785466 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 19048182 # Number of instructions committed -system.cpu0.committedOps 25051772 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 22684080 # Number of integer alu accesses +system.cpu0.committedInsts 19048205 # Number of instructions committed +system.cpu0.committedOps 25051835 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 22684157 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses -system.cpu0.num_func_calls 868675 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 2620305 # number of instructions that are conditional controls -system.cpu0.num_int_insts 22684080 # number of integer instructions +system.cpu0.num_func_calls 868672 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 2620308 # number of instructions that are conditional controls +system.cpu0.num_int_insts 22684157 # number of integer instructions system.cpu0.num_fp_insts 4364 # number of float instructions -system.cpu0.num_int_register_reads 128950966 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23731370 # number of times the integer registers were written +system.cpu0.num_int_register_reads 128951400 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23731440 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written -system.cpu0.num_mem_refs 9388163 # number of memory refs -system.cpu0.num_load_insts 5047859 # Number of load instructions -system.cpu0.num_store_insts 4340304 # Number of store instructions -system.cpu0.num_idle_cycles 2301502404.823749 # Number of idle cycles -system.cpu0.num_busy_cycles 104459206.176251 # Number of busy cycles -system.cpu0.not_idle_fraction 0.043417 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.956583 # Percentage of idle cycles +system.cpu0.num_mem_refs 9388218 # number of memory refs +system.cpu0.num_load_insts 5047895 # Number of load instructions +system.cpu0.num_store_insts 4340323 # Number of store instructions +system.cpu0.num_idle_cycles 2301327262.807119 # Number of idle cycles +system.cpu0.num_busy_cycles 104458203.192881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.043420 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.956580 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 34020 # number of quiesce instructions executed -system.cpu0.icache.replacements 283184 # number of replacements -system.cpu0.icache.tagsinuse 509.502628 # Cycle average of tags in use -system.cpu0.icache.total_refs 19141582 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 283696 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.472160 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 34019 # number of quiesce instructions executed +system.cpu0.icache.replacements 283204 # number of replacements +system.cpu0.icache.tagsinuse 509.502445 # Cycle average of tags in use +system.cpu0.icache.total_refs 19141584 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 283716 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.467411 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.502628 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 509.502445 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 19141582 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 19141582 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19141582 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 19141582 # 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number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 3929923500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 3929923500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425278 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 19425278 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19425278 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 19425278 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19425278 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 19425278 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014604 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014604 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014604 # 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miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.029464 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062733 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062733 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061308 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 8568408 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 8568408 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8568408 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 8568408 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031846 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031846 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029465 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.029465 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062741 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062741 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061268 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061268 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13596.209913 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13596.209913 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35907.261581 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35907.261581 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8916.687817 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8916.687817 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8618.227881 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8618.227881 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 23502.313804 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23502.313804 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13595.386359 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13595.386359 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35904.647703 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35904.647703 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8914.985408 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8914.985408 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8597.373895 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8597.373895 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23500.987024 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23500.987024 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,66 +737,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 204960 # number of writebacks -system.cpu0.dcache.writebacks::total 204960 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146461 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 146461 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116958 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 116958 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7880 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7880 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7695 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7695 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 263419 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 263419 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 263419 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 263419 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698392500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698392500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965725500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965725500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54503500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54503500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50946500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 205058 # number of writebacks +system.cpu0.dcache.writebacks::total 205058 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146457 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 146457 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116961 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 116961 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7881 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7881 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7690 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7690 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 263418 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 263418 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 263418 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 263418 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698225500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698225500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965521500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965521500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54497000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54497000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50753000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50753000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5664118000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5664118000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5664118000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5664118000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130688000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130688000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193496500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193496500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324184500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324184500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031847 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031847 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029464 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029464 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061292 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5663747000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5663747000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5663747000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5663747000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130745000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130745000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193494500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193494500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324239500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324239500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031846 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029465 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029465 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062741 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062741 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061252 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061252 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6916.687817 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6916.687817 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6620.727745 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6620.727745 # average StoreCondReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11595.386359 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11595.386359 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33904.647703 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33904.647703 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6914.985408 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6914.985408 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6599.869961 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6599.869961 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -806,26 +806,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10590618 # DTB read hits -system.cpu1.dtb.read_misses 5230 # DTB read misses -system.cpu1.dtb.write_hits 7384755 # DTB write hits -system.cpu1.dtb.write_misses 1835 # DTB write misses +system.cpu1.dtb.read_hits 10589201 # DTB read hits +system.cpu1.dtb.read_misses 5231 # DTB read misses +system.cpu1.dtb.write_hits 7383574 # DTB write hits +system.cpu1.dtb.write_misses 1834 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 193 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10595848 # DTB read accesses -system.cpu1.dtb.write_accesses 7386590 # DTB write accesses +system.cpu1.dtb.read_accesses 10594432 # DTB read accesses +system.cpu1.dtb.write_accesses 7385408 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17975373 # DTB hits +system.cpu1.dtb.hits 17972775 # DTB hits system.cpu1.dtb.misses 7065 # DTB misses -system.cpu1.dtb.accesses 17982438 # DTB accesses -system.cpu1.itb.inst_hits 43340388 # ITB inst hits +system.cpu1.dtb.accesses 17979840 # DTB accesses +system.cpu1.itb.inst_hits 43338256 # ITB inst hits system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -842,79 +842,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43343405 # ITB inst accesses -system.cpu1.itb.hits 43340388 # DTB hits +system.cpu1.itb.inst_accesses 43341273 # ITB inst accesses +system.cpu1.itb.hits 43338256 # DTB hits system.cpu1.itb.misses 3017 # DTB misses -system.cpu1.itb.accesses 43343405 # DTB accesses -system.cpu1.numCycles 2407389096 # number of cpu cycles simulated +system.cpu1.itb.accesses 43341273 # DTB accesses +system.cpu1.numCycles 2407212998 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 42409467 # Number of instructions committed -system.cpu1.committedOps 53271211 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 47739499 # Number of integer alu accesses +system.cpu1.committedInsts 42407344 # Number of instructions committed +system.cpu1.committedOps 53266051 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47734651 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses -system.cpu1.num_func_calls 1335008 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5483103 # number of instructions that are conditional controls -system.cpu1.num_int_insts 47739499 # number of integer instructions +system.cpu1.num_func_calls 1334953 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5482869 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47734651 # number of integer instructions system.cpu1.num_fp_insts 5457 # number of float instructions -system.cpu1.num_int_register_reads 274842107 # number of times the integer registers were read -system.cpu1.num_int_register_writes 51975033 # number of times the integer registers were written +system.cpu1.num_int_register_reads 274813771 # number of times the integer registers were read +system.cpu1.num_int_register_writes 51971016 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written -system.cpu1.num_mem_refs 18684058 # number of memory refs -system.cpu1.num_load_insts 11000639 # Number of load instructions -system.cpu1.num_store_insts 7683419 # Number of store instructions -system.cpu1.num_idle_cycles 1827105047.254482 # Number of idle cycles -system.cpu1.num_busy_cycles 580284048.745518 # Number of busy cycles -system.cpu1.not_idle_fraction 0.241043 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.758957 # Percentage of idle cycles +system.cpu1.num_mem_refs 18681443 # number of memory refs +system.cpu1.num_load_insts 10999206 # Number of load instructions +system.cpu1.num_store_insts 7682237 # Number of store instructions +system.cpu1.num_idle_cycles 1827286039.250482 # Number of idle cycles +system.cpu1.num_busy_cycles 579926958.749518 # Number of busy cycles +system.cpu1.not_idle_fraction 0.240912 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.759088 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 56706 # number of quiesce instructions executed -system.cpu1.icache.replacements 582628 # number of replacements -system.cpu1.icache.tagsinuse 479.068937 # Cycle average of tags in use -system.cpu1.icache.total_refs 42757244 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 583140 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 73.322434 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 56704 # number of quiesce instructions executed +system.cpu1.icache.replacements 582576 # number of replacements +system.cpu1.icache.tagsinuse 479.066528 # Cycle average of tags in use +system.cpu1.icache.total_refs 42755164 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 583088 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 73.325405 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.068937 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935682 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935682 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 42757244 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 42757244 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 42757244 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 42757244 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 42757244 # number of overall hits -system.cpu1.icache.overall_hits::total 42757244 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 583140 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 583140 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 583140 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 583140 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 583140 # 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average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13467.614981 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13467.614981 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 479.066528 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935677 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935677 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 42755164 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42755164 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42755164 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42755164 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42755164 # number of overall hits +system.cpu1.icache.overall_hits::total 42755164 # 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number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43338252 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43338252 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43338252 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43338252 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43338252 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43338252 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013454 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013454 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013454 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013454 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013454 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6687225000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6687225000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6687225000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 583088 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 583088 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 583088 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 583088 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 583088 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 583088 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6685829500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6685829500 # 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average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013454 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013454 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11466.244375 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 401361 # number of replacements -system.cpu1.dcache.tagsinuse 473.304740 # Cycle average of tags in use -system.cpu1.dcache.total_refs 15681919 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 401873 # 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average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20724.117785 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20724.117785 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 473.299929 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.924414 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.924414 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 9100620 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9100620 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6322619 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6322619 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111839 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 111839 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114463 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 114463 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15423239 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15423239 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15423239 # number of overall hits +system.cpu1.dcache.overall_hits::total 15423239 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 253127 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 253127 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 178055 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 178055 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13099 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13099 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10399 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10399 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 431182 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 431182 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 431182 # number of overall misses +system.cpu1.dcache.overall_misses::total 431182 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3277248500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3277248500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5648876500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5648876500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115793500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 115793500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63008000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 63008000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8926125000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8926125000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8926125000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8926125000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9353747 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9353747 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6500674 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6500674 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124938 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 124938 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124862 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 124862 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 15854421 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 15854421 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 15854421 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 15854421 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027062 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027062 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027390 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027390 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104844 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104844 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027196 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027196 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027196 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027196 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.052270 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.052270 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31725.458426 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31725.458426 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8839.873273 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8839.873273 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6059.044139 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6059.044139 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20701.525110 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20701.525110 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,66 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 366483 # number of writebacks -system.cpu1.dcache.writebacks::total 366483 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253200 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 253200 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178129 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 178129 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13100 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13100 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10399 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10399 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 431329 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 431329 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 431329 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 431329 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2771848500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2771848500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5304406500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5304406500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89559000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89559000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42226500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 366504 # number of writebacks +system.cpu1.dcache.writebacks::total 366504 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253127 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 253127 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178055 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 178055 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13099 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13099 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10394 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10394 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 431182 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 431182 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 431182 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 431182 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2770994500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2770994500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5292766500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5292766500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89595500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89595500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42224000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42224000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8076255000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8076255000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8076255000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8076255000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40377042500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40377042500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027397 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027397 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104839 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104839 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083274 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083274 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027201 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6836.564885 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6836.564885 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4060.630830 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8063761000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8063761000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8063761000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8063761000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170066366500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170066366500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40314514000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40314514000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210380880500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210380880500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027062 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027390 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027390 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104844 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104844 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083244 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083244 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027196 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027196 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.052270 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.052270 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29725.458426 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29725.458426 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6839.873273 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6839.873273 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4062.343660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4062.343660 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1126,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 567076826640 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 522347967555 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 522347967555 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 522347967555 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 522347967555 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index e07e69ea6..d1abeb8c8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.624688 # Number of seconds simulated -sim_ticks 2624688000000 # Number of ticks simulated -final_tick 2624688000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.624627 # Number of seconds simulated +sim_ticks 2624627401000 # Number of ticks simulated +final_tick 2624627401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 509092 # Simulator instruction rate (inst/s) -host_op_rate 647812 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22195691402 # Simulator tick rate (ticks/s) -host_mem_usage 379628 # Number of bytes of host memory used -host_seconds 118.25 # Real time elapsed on the host -sim_insts 60201138 # Number of instructions simulated -sim_ops 76605123 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory +host_inst_rate 463403 # Simulator instruction rate (inst/s) +host_op_rate 589674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20203281292 # Simulator tick rate (ticks/s) +host_mem_usage 381220 # Number of bytes of host memory used +host_seconds 129.91 # Real time elapsed on the host +sim_insts 60201162 # Number of instructions simulated +sim_ops 76605148 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 123834568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9049616 # Number of bytes read from this memory -system.physmem.bytes_read::total 134012208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9049808 # Number of bytes read from this memory +system.physmem.bytes_read::total 133590712 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3676928 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3677120 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693000 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6693192 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15479321 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141434 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690705 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57452 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 141437 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15637997 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57455 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811470 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47341343 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811473 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47181771 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 268917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3447883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51058338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 268917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1400901 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1149116 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550017 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1400901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47341343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 268924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3448035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50898925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 268924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1401006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1149143 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550149 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1401006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47181771 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53608356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 268924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4597178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53449074 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -69,26 +69,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996726 # DTB read hits -system.cpu.dtb.read_misses 7357 # DTB read misses -system.cpu.dtb.write_hits 11231612 # DTB write hits +system.cpu.dtb.read_hits 14996727 # DTB read hits +system.cpu.dtb.read_misses 7361 # DTB read misses +system.cpu.dtb.write_hits 11231610 # DTB write hits system.cpu.dtb.write_misses 2211 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3491 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15004083 # DTB read accesses -system.cpu.dtb.write_accesses 11233823 # DTB write accesses +system.cpu.dtb.read_accesses 15004088 # DTB read accesses +system.cpu.dtb.write_accesses 11233821 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26228338 # DTB hits -system.cpu.dtb.misses 9568 # DTB misses -system.cpu.dtb.accesses 26237906 # DTB accesses -system.cpu.itb.inst_hits 61495107 # ITB inst hits +system.cpu.dtb.hits 26228337 # DTB hits +system.cpu.dtb.misses 9572 # DTB misses +system.cpu.dtb.accesses 26237909 # DTB accesses +system.cpu.itb.inst_hits 61495131 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -105,79 +105,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61499578 # ITB inst accesses -system.cpu.itb.hits 61495107 # DTB hits +system.cpu.itb.inst_accesses 61499602 # ITB inst accesses +system.cpu.itb.hits 61495131 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61499578 # DTB accesses -system.cpu.numCycles 5249376000 # number of cpu cycles simulated +system.cpu.itb.accesses 61499602 # DTB accesses +system.cpu.numCycles 5249254802 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60201138 # Number of instructions committed -system.cpu.committedOps 76605123 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872510 # Number of integer alu accesses +system.cpu.committedInsts 60201162 # Number of instructions committed +system.cpu.committedOps 76605148 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872531 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139913 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948064 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872510 # number of integer instructions +system.cpu.num_func_calls 2139915 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948068 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872531 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read -system.cpu.num_int_register_writes 74180711 # number of times the integer registers were written +system.cpu.num_int_register_reads 394780405 # number of times the integer registers were read +system.cpu.num_int_register_writes 74180740 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27395681 # number of memory refs -system.cpu.num_load_insts 15660705 # Number of load instructions -system.cpu.num_store_insts 11734976 # Number of store instructions -system.cpu.num_idle_cycles 4573668198.612257 # Number of idle cycles -system.cpu.num_busy_cycles 675707801.387743 # Number of busy cycles -system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.871278 # Percentage of idle cycles +system.cpu.num_mem_refs 27395680 # number of memory refs +system.cpu.num_load_insts 15660706 # Number of load instructions +system.cpu.num_store_insts 11734974 # Number of store instructions +system.cpu.num_idle_cycles 4573851223.612257 # Number of idle cycles +system.cpu.num_busy_cycles 675403578.387743 # Number of busy cycles +system.cpu.not_idle_fraction 0.128667 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.871333 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.replacements 855878 # number of replacements -system.cpu.icache.tagsinuse 510.920723 # Cycle average of tags in use -system.cpu.icache.total_refs 60638717 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856390 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.807362 # Average number of references to valid blocks. +system.cpu.icache.replacements 855895 # number of replacements +system.cpu.icache.tagsinuse 510.920698 # Cycle average of tags in use +system.cpu.icache.total_refs 60638724 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856407 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.805965 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.920723 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.920698 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60638717 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60638717 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60638717 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60638717 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60638717 # number of overall hits -system.cpu.icache.overall_hits::total 60638717 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses -system.cpu.icache.overall_misses::total 856390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565531500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11565531500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11565531500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11565531500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11565531500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11565531500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61495107 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61495107 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61495107 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60638724 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60638724 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60638724 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60638724 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60638724 # number of overall hits +system.cpu.icache.overall_hits::total 60638724 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856407 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856407 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856407 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856407 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856407 # number of overall misses +system.cpu.icache.overall_misses::total 856407 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11564476500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11564476500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11564476500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11564476500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11564476500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11564476500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61495131 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61495131 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61495131 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61495131 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61495131 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61495131 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.981959 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13504.981959 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13504.981959 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13504.981959 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.481989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13503.481989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13503.481989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13503.481989 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,18 +186,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856390 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856390 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856390 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852751500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9852751500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852751500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9852751500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852751500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9852751500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856407 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856407 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856407 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856407 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856407 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856407 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9851662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9851662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851662500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9851662500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles @@ -208,90 +208,90 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.981959 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.981959 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.481989 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.481989 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627203 # number of replacements -system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use -system.cpu.dcache.total_refs 23656923 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627715 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.687363 # Average number of references to valid blocks. +system.cpu.dcache.replacements 627232 # number of replacements +system.cpu.dcache.tagsinuse 511.878513 # Cycle average of tags in use +system.cpu.dcache.total_refs 23656893 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627744 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.685574 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.878513 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13196260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13196266 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13196266 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973744 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973744 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236294 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236294 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23170043 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23170043 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23170043 # number of overall hits -system.cpu.dcache.overall_hits::total 23170043 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368704 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368704 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619214 # number of overall misses -system.cpu.dcache.overall_misses::total 619214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201105500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5201105500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8977284500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8977284500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14178390000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14178390000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14178390000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14178390000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10224293 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 23170010 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23170010 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23170010 # number of overall hits +system.cpu.dcache.overall_hits::total 23170010 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368699 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368699 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250547 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250547 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11397 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11397 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619246 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619246 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619246 # number of overall misses +system.cpu.dcache.overall_misses::total 619246 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5200667500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5200667500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8968842000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8968842000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154755000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 154755000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14169509500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14169509500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14169509500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14169509500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564965 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564965 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10224291 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10224291 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23789257 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23789257 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23789257 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23789257 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027181 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027181 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024501 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024501 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.452602 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.452602 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35836.032494 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35836.032494 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22897.398961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22897.398961 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 23789256 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23789256 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23789256 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23789256 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027180 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027180 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024505 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024505 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046013 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046013 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026030 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026030 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026030 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026030 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.455941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.455941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35797.044068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35797.044068 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.573309 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.573309 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22881.874893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22881.874893 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,54 +300,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks -system.cpu.dcache.writebacks::total 595968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368704 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368704 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619214 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619214 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619214 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619214 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463697500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463697500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8476264500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8476264500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131994000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131994000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939962000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12939962000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939962000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12939962000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162296000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162296000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387676000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387676000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223549972000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 223549972000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024501 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046025 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046025 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026029 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.452602 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.452602 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33836.032494 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33836.032494 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20897.398961 # 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