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authorGabe Black <gblack@eecs.umich.edu>2011-08-07 09:21:48 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-08-07 09:21:48 -0700
commit16882b04838c33e7de5456937b8b069547827b2a (patch)
tree52d9dadf5185a920a6fd1a1f3457180ba0086bc4
parent720c0be620bd3427b5222e437fc7a82cb3a9ad7f (diff)
downloadgem5-16882b04838c33e7de5456937b8b069547827b2a.tar.xz
Translation: Use a pointer type as the template argument.
This allows regular pointers and reference counted pointers without having to use any shim structures or other tricks.
-rw-r--r--src/cpu/base_dyn_inst.hh13
-rw-r--r--src/cpu/simple/timing.cc24
-rw-r--r--src/cpu/translation.hh8
3 files changed, 23 insertions, 22 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 18a178c4a..cb9294481 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -91,6 +91,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
// The DynInstPtr type.
typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
// The list of instructions iterator type.
typedef typename std::list<DynInstPtr>::iterator ListIt;
@@ -950,8 +951,8 @@ BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
new WholeTranslationState(req, NULL, res, mode);
// One translation if the request isn't split.
- DataTranslation<BaseDynInst<Impl> > *trans =
- new DataTranslation<BaseDynInst<Impl> >(this, state);
+ DataTranslation<BaseDynInstPtr> *trans =
+ new DataTranslation<BaseDynInstPtr>(this, state);
cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
if (!translationCompleted) {
// Save memory requests.
@@ -964,10 +965,10 @@ BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
// Two translations when the request is split.
- DataTranslation<BaseDynInst<Impl> > *stransLow =
- new DataTranslation<BaseDynInst<Impl> >(this, state, 0);
- DataTranslation<BaseDynInst<Impl> > *stransHigh =
- new DataTranslation<BaseDynInst<Impl> >(this, state, 1);
+ DataTranslation<BaseDynInstPtr> *stransLow =
+ new DataTranslation<BaseDynInstPtr>(this, state, 0);
+ DataTranslation<BaseDynInstPtr> *stransHigh =
+ new DataTranslation<BaseDynInstPtr>(this, state, 1);
cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 1c726ba57..e2151d974 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -461,18 +461,18 @@ TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
WholeTranslationState *state =
new WholeTranslationState(req, req1, req2, new uint8_t[size],
NULL, mode);
- DataTranslation<TimingSimpleCPU> *trans1 =
- new DataTranslation<TimingSimpleCPU>(this, state, 0);
- DataTranslation<TimingSimpleCPU> *trans2 =
- new DataTranslation<TimingSimpleCPU>(this, state, 1);
+ DataTranslation<TimingSimpleCPU *> *trans1 =
+ new DataTranslation<TimingSimpleCPU *>(this, state, 0);
+ DataTranslation<TimingSimpleCPU *> *trans2 =
+ new DataTranslation<TimingSimpleCPU *>(this, state, 1);
thread->dtb->translateTiming(req1, tc, trans1, mode);
thread->dtb->translateTiming(req2, tc, trans2, mode);
} else {
WholeTranslationState *state =
new WholeTranslationState(req, new uint8_t[size], NULL, mode);
- DataTranslation<TimingSimpleCPU> *translation
- = new DataTranslation<TimingSimpleCPU>(this, state);
+ DataTranslation<TimingSimpleCPU *> *translation
+ = new DataTranslation<TimingSimpleCPU *>(this, state);
thread->dtb->translateTiming(req, tc, translation, mode);
}
@@ -530,18 +530,18 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
WholeTranslationState *state =
new WholeTranslationState(req, req1, req2, newData, res, mode);
- DataTranslation<TimingSimpleCPU> *trans1 =
- new DataTranslation<TimingSimpleCPU>(this, state, 0);
- DataTranslation<TimingSimpleCPU> *trans2 =
- new DataTranslation<TimingSimpleCPU>(this, state, 1);
+ DataTranslation<TimingSimpleCPU *> *trans1 =
+ new DataTranslation<TimingSimpleCPU *>(this, state, 0);
+ DataTranslation<TimingSimpleCPU *> *trans2 =
+ new DataTranslation<TimingSimpleCPU *>(this, state, 1);
thread->dtb->translateTiming(req1, tc, trans1, mode);
thread->dtb->translateTiming(req2, tc, trans2, mode);
} else {
WholeTranslationState *state =
new WholeTranslationState(req, newData, res, mode);
- DataTranslation<TimingSimpleCPU> *translation =
- new DataTranslation<TimingSimpleCPU>(this, state);
+ DataTranslation<TimingSimpleCPU *> *translation =
+ new DataTranslation<TimingSimpleCPU *>(this, state);
thread->dtb->translateTiming(req, tc, translation, mode);
}
diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh
index 60953540f..b6bc2182c 100644
--- a/src/cpu/translation.hh
+++ b/src/cpu/translation.hh
@@ -214,21 +214,21 @@ class WholeTranslationState
* translation state class indicate that the whole translation is complete
* then the execution context is informed.
*/
-template <class ExecContext>
+template <class ExecContextPtr>
class DataTranslation : public BaseTLB::Translation
{
protected:
- ExecContext *xc;
+ ExecContextPtr xc;
WholeTranslationState *state;
int index;
public:
- DataTranslation(ExecContext *_xc, WholeTranslationState* _state)
+ DataTranslation(ExecContextPtr _xc, WholeTranslationState* _state)
: xc(_xc), state(_state), index(0)
{
}
- DataTranslation(ExecContext *_xc, WholeTranslationState* _state,
+ DataTranslation(ExecContextPtr _xc, WholeTranslationState* _state,
int _index)
: xc(_xc), state(_state), index(_index)
{