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authorAli Saidi <saidi@eecs.umich.edu>2007-11-01 17:30:50 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-11-01 17:30:50 -0400
commit333ac6cc3221d449801ecd75a3f846b98acd5786 (patch)
tree2e0e5a45e4ac85d4783e0b186435788a4695d3e6
parent4b49bd47f464fb3fe31a943b913edb565fa68423 (diff)
downloadgem5-333ac6cc3221d449801ecd75a3f846b98acd5786.tar.xz
DRAM: Make latency parameters be Param.Latency instead of ints.
--HG-- extra : convert_revision : 553b86cc4653da089d7aa0045a3f3bdcabf6c4d8
-rw-r--r--src/mem/PhysicalMemory.py12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mem/PhysicalMemory.py b/src/mem/PhysicalMemory.py
index 2ef3df7c1..99bd27f2b 100644
--- a/src/mem/PhysicalMemory.py
+++ b/src/mem/PhysicalMemory.py
@@ -46,12 +46,12 @@ class DRAMMemory(PhysicalMemory):
mem_actpolicy = Param.String("open", "Open/Close policy")
memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
bus_width = Param.Int(16, "")
- act_lat = Param.Int(2, "RAS to CAS delay")
- cas_lat = Param.Int(1, "CAS delay")
- war_lat = Param.Int(2, "write after read delay")
- pre_lat = Param.Int(2, "precharge delay")
- dpl_lat = Param.Int(2, "data in to precharge delay")
- trc_lat = Param.Int(6, "row cycle delay")
+ act_lat = Param.Latency("2ns", "RAS to CAS delay")
+ cas_lat = Param.Latency("1ns", "CAS delay")
+ war_lat = Param.Latency("2ns", "write after read delay")
+ pre_lat = Param.Latency("2ns", "precharge delay")
+ dpl_lat = Param.Latency("2ns", "data in to precharge delay")
+ trc_lat = Param.Latency("6ns", "row cycle delay")
num_banks = Param.Int(4, "Number of Banks")
num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")